W83176R-400

W83176R-400 W83176G-400 Winbond Current Mode Differential Buffer for PCI Express and SATA Date: May/16/2006 Revision: 0.6 W83176R-400/W83176G-400 CURRENT MODE DIFFERENTIAL BUFFER FOR PCI EXPRESS AND SATA W83176R-400/W83176G-400 Datasheet Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS 1 2 3 4 5 6 7 8 9 10 n.a. 7 05/11/04 05/16/06 0.5 0.6 n.a. n.a. First publish Add lead free part -I- Publication Release Date: May, 2006 Revision 0.6 W83176R-400/W83176G-400 CURRENT MODE DIFFERENTIAL BUFFER FOR PCI EXPRESS AND SATA Table of Content1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 1 BLOCK DIAGRAM ...................................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 3 5.1 5.2 6. 2 Clock Outputs ..............................................................................................................................3 Power Pins...................................................................................................................................3 Register 0: Control Register (Default: 07h) ................................................................................4 Register 1: Control Register (Default: FFh) ................................................................................4 Register 2: Control Register (Default: 00h) ................................................................................4 Register 3: Reserved Register (Default: 00h) ............................................................................5 Register 4: Winbond Chip ID – Project Code Register (Default: 11h).......................................5 Register 5: Test Register (Default: 00h) .....................................................................................5 Block Write protocol.....................................................................................................................6 Block Read protocol ....................................................................................................................6 Byte Write protocol ......................................................................................................................6 Byte Read protocol......................................................................................................................6 I C CONTROL AND STATUS REGISTERS............................................................................... 4 6.1 6.2 6.3 6.4 6.5 6.6 7. ACCESS INTERFACE ................................................................................................................ 6 7.1 7.2 7.3 7.4 8. 9. 10. ORDERING INFORMATION....................................................................................................... 7 HOW TO READ THE TOP MARKING........................................................................................ 7 PACKAGE DRAWING AND DIMENSIONS................................................................................ 8 - II - W83176R-400/W83176G-400 CURRENT MODE DIFFERENTIAL BUFFER FOR PCI EXPRESS AND SATA 1. GENERAL DESCRIPTION The W83176R-400 supports four current mode differential Clock pair’s buffer output companion devices to CK409 or CK410 clock generator. The W83176R-400 provides I2C serial bus interface to program the registers to enable or disable each clock outputs. The W83176R-400 accepts a reference clock as its input current mode differential pair’s clock. 2. PRODUCT FEATURES • • • • • • • • Four current mode differential clock pairs clock outputs Support zero delay buffer mode and normal buffer mode Supports two hardware output enable/disable pin Programmable PLL bandwidth Low Skew outputs (< 50ps) Low cycle to cycle jitter (