W83176R-733

W83176R-733 W83176G-733 Winbond Dual Bank DDR BUFFER For VIA CHIPSET Date: Mar/22/2006 Revision: 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET W83176R-733/W83176G-733 Data Sheet Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS 1 2 3 4 5 6 7 8 9 10 n.a. 3,4,5,8 09/09/03 12/18/03 03/22/2006 0.5 0.6 1.0 n.a. n.a. 1.0 All of the versions before 0.50 are for internal use. First published preliminary version. Correction IC version, correction description and default value Update on Web and add lead free part some Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -I- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET Table of Content1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 1 BLOCK DIAGRAM ...................................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 3 5.1 5.2 6. 7. Clock Function Pins..................................................................................................................3 Control Signal Pins...................................................................................................................3 POWER PINS ............................................................................................................................. 4 I2C CONTROL AND STATUS REGISTERS .............................................................................. 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 Register 0 ~ Register 5 RESERVED.......................................................................................4 Register 6: Output Control (1 = Enable, 0 = Disable) (Default: FFh)......................................4 Register 7: Output Control (1 = Enable, 0 = Disable) (Default: FFh)......................................4 REGISTER 8 ~ Register 17 RESERVED ...............................................................................5 Skew step reference Table ......................................................................................................5 Register 18: Skew Control (Default: 88h)................................................................................5 Register 19: Skew Control (Default: 80h)................................................................................5 Slew rate reference table .........................................................................................................6 Register 20: Skew & Slew Rate Control (Default: 8Ah) ..........................................................6 Register 21: Slew Rate Control (Default: AAh) .......................................................................6 Register 22: Slew Rate Control (Default: AAh) .......................................................................6 Register 23: Slew Rate Control (Default: AAh) .......................................................................7 Block Write Protocol .................................................................................................................8 Block Read Protocol.................................................................................................................8 Byte Write Protocol...................................................................................................................8 Byte Read Protocol ..................................................................................................................8 ABSOLUTE MAXIMUM RATINGS .........................................................................................9 AC CHARACTERISTICS.........................................................................................................9 DC CHARACTERISTICS ........................................................................................................9 8. ACCESS INTERFACE ................................................................................................................ 8 8.1 8.2 8.3 8.4 9. SPECIFICATIONS ...................................................................................................................... 9 9.1 9.2 9.3 10. 11. 12. ORDERING INFORMATION..................................................................................................... 10 HOW TO READ THE TOP MARKING...................................................................................... 10 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 11 - II - W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 1. GENERAL DESCRIPTION The W83176R-733 is a 2.5V Dual Bank D.D.R. Clock buffer designed for VIA system. W83176R-733 can support 4 D.D.R. DRAM DIMMs. The W83176R-733 provides I2C serial bus interface to program the registers to enable or disable each clock outputs. The W83176R-733 accepts a reference clock as its input and runs on 2.5V supply. 2. PRODUCT FEATURES • • • • • Low Skew outputs (< 100ps) Two Feedback pins for synchronous for each bank. Supports up to 4 D.D.R. DIMMs Supports PC3200 D.D.R. SDRAM I2C 2-Wire serial interface and supports Byte or Block Date RW • 48-pin SSOP package 3. PIN CONFIGURATION V D D 2. 5 G ND FB _O U T B B U F_ IN B D D RB T 0 D D RB C 0 D D RB T 1 D D RB C 1 G ND V D D 2. 5 D DR AT0 D DR AC 0 D DR AT1 D DR AC 1 G ND V D D 2. 5 FB _O U T A BU F_I N A D DR AT2 D DR AC 2 D DR AT3 D DR AC 3 V D D 2. 5 G ND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 V D D 2 .5 G ND O E _O D D * O E _E V E N * D D R BT 2 D D R BC 2 D D R BT 3 D D R BC 3 G ND V D D 2 .5 D DR AT4 D DR AC 4 D DR AT5 D DR AC 5 G ND V D D 2 .5 D D R BT 4 D D R BC 4 D D R BT 5 D D R BC 5 V D D 2 .5 G ND S DATA * S CL K * *: Internal pull-up resistor 120K to VDD -1- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 4. BLOCK DIAGRAM FB_OUTA DDRAT[5:0] DDRAC[5:0] FB_OUTB DDRBT[5:0] DDRBC[5:0] BUF_INA BUF_INB SCLK* SDATA* OE_ODD* OE_EVEN* Control Logic -2- W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 5. PIN DESCRIPTION BUFFER TYPE SYMBOL DESCRIPTION IN OUT I/OD * Input Output Bi-directional Pin, Open Drain Internal 120kΩ pull-up 5.1 Clock Function Pins PIN PIN NAME TYPE DESCRIPTION 　 18 　 BUF_INTA IN OUT OUT IN OUT OUT Bank A DDR Buffer True reference clock input. Bank A DDR Buffer clocks of differential pair outputs. Bank A DDR Buffer True Feedback output, dedicated for external feedback. Bank B DDR Buffer True reference clock input. Bank B DDR Buffer clocks of differential pair outputs. Bank B DDR Buffer True Feedback output, dedicated for external feedback. 　 36,35,38,37,2 　 DDRAT/C 1,22,20,19,14 [5:0] ,13,11,12 17 4 FB_OUTA 　 BUF_INTB 30,29,32,31,42,4 DDRBT/C [5:0] 1,44,43,7,8,5,6 3 FB_OUTB 5.2 Control Signal Pins PIN PIN NAME TYPE 2 DESCRIPTION 26 25 SDATA * SCLK * I/OD IN Serial data of I C 2-wire control interface Internal pull-up resistor 120K to VDD2.5 Serial clock of I2C 2-wire control interface Internal pull-up resistor 120K to VDD2.5 OE_EVEN=1 Enable, OE_EVEN=0 Disable, Even Buffer clock output pairs (DDR0, 2,4), Internal pull-up resistor 120K to VDD2.5 OE_ODD=1 Enable, OE_ODD=0 Disable, ODD Buffer clock output pairs (DDR1, 3, 5), Internal pull-up resistor 120K to VDD2.5 45 OE_EVEN* IN 46 OE_ODD* IN -3- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 6. POWER PINS PIN PIN NAME DESCRIPTION 2,9,15,24,27,34,40,47 1,10,16,23,28,33,39,48 GND VDD2.5 　 Ground Power Supply 2.5V 7. I2C CONTROL AND STATUS REGISTERS 7.1 7.2 BIT Register 0 ~ Register 5 RESERVED Register 6: Output Control (1 = Enable, 0 = Disable) (Default: FFh) PIN NO PWD DESCRIPTION 7 6 5 4 3 2 1 0 Reserved 17 36,35 38,37 21,22 20,19 13,14 11,12 1 1 1 1 1 1 1 1 Reserved FB_OUTA output control DDRA_T5/C5 output control DDRA_T4/C4 output control DDRA_T3/C3 output control DDRA_T2/C2 output control DDRA_T1/C1 output control DDRA_T0/C0 output control 7.3 Bit 7 6 5 4 3 2 1 0 Register 7: Output Control (1 = Enable, 0 = Disable) (Default: FFh) Pin No Reserved 3 30,29 32,31 42,41 44,43 7,8 5,6 PWD 1 1 1 1 1 1 1 1 Reserved FB_OUTB output control DDRB_T5/C5 output control DDRB_T4/C4 output control DDRB_T3/C3 output control DDRB_T2/C2 output control DDRB_T1/C1 output control DDRB_T0/C0 output control Description -4- W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 7.4 7.5 REGISTER 8 ~ Register 17 RESERVED Skew step reference Table SKEW/ DELAY TIME (PS) 000 001 010 011 100 101 110 111 0 250 500 750 1000 1250 1500 1750 7.6 BIT Register 18: Skew Control (Default: 88h) NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 Reserved DDRA_TSKEW DDRA_TSKEW DDRA_TSKEW Reserved DDRA_CSKEW DDRA_CSKEW DDRA_CSKEW 1 0 0 0 1 0 0 0 Reserved DDRA True clock outputs with FB_OUTA True clock SKEW control bits Reserved DDRA Complementary clock outputs with FB_OUTA True clock SKEW control bits 7.7 BIT Register 19: Skew Control (Default: 80h) NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 Reserved DDRB_CSKEW DDRB_CSKEW DDRB_CSKEW FAOUT_SKEW FAOUT_SKEW FBOUT_SKEW FBOUT_SKEW 1 0 0 0 0 0 0 0 Reserved DDRB Complementary clock outputs with FB_OUTB True clock SKEW control bits FB_OUTA, DDRA clock outputs with BUF_INA clock SKEW control bits FB_OUTB, DDRB clock outputs with BUF_INB clock SKEW control bits -5- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 7.8 Slew rate reference table SR STATUS 10/01 11 00 Normal (default) Strong Weak 7.9 BIT Register 20: Skew & Slew Rate Control (Default: 8Ah) NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 Reserved DDRB_TSKEW DDRB_TSKEW DDRB_TSKEW DDRAT/C0_SR DDRAT/C0_SR DDRAT/C1_SR DDRAT/C1_SR 1 0 0 0 1 0 1 0 Reserved DDRB True clock outputs with FB_OUTB True clock SKEW control bits DDRAT/C0 slew rate control bits DDRAT/C1 slew rate control bits 7.10 Register 21: Slew Rate Control (Default: AAh) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 DDRAT/C2_SR DDRAT/C2_SR DDRAT/C3_SR DDRAT/C3_SR DDRAT/C4_SR DDRAT/C4_SR DDRAT/C5_SR DDRAT/C5_SR 1 0 1 0 1 0 1 0 DDRAT/C2 slew rate control bits DDRAT/C3 slew rate control bits DDRAT/C4 slew rate control bits DDRAT/C5 slew rate control bits 7.11 Register 22: Slew Rate Control (Default: AAh) BIT NAME PWD DESCRIPTION 7 6 5 4 DDRBT/C0_SR DDRBT/C0_SR DDRBT/C1_SR DDRBT/C1_SR 1 0 1 0 DDRBT/C0 slew rate control bits DDRBT/C1 slew rate control bits -6- W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET Register 22: Slew Rate Control (Default: AAh), continued BIT NAME PWD DESCRIPTION 3 2 1 0 DDRBT/C2_SR DDRBT/C2_SR DDRBT/C3_SR DDRBT/C3_SR 1 0 1 0 DDRBT/C2 slew rate control bits DDRBT/C3 slew rate control bits 7.12 Register 23: Slew Rate Control (Default: AAh) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 DDRBT/C4_SR DDRBT/C4_SR DDRBT/C5_SR DDRBT/C5_SR FBOUT_SR FBOUT_SR FAOUT_SR FAOUT_SR 1 0 1 0 1 0 1 0 DDRBT/C4 slew rate control bits DDRBT/C5 slew rate control bits FB_OUTB slew rate control bits FB_OUTA slew rate control bits -7- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 8. ACCESS INTERFACE The W83176R-733 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83176R-733 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C write address is defined at 0xD4. The I2C read address is defined at 0xD5. 8.1 Block Write Protocol 8.2 Block Read Protocol ## In block mode, the command code must filled ‘00h’ 8.3 Byte Write Protocol 8.4 Byte Read Protocol -8- W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD2.5). PARAMETER RATING Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model) - 0.5 V to + 3.6 V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C 2000V 9.2 AC CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS VDD2.5 = 2.5V ± 5 %, TA = 0°C to +70°C, Test load = 10 pF Operating clock frequency Input Clock Duty Cycle Dynamic Supply Current Cycle to Cycle Jitter Output to Output Skew Output clock Rise time Output clock Fall time Output clock Duty Cycle Output differential-pair crossing voltage FIN Dtin Idd C-Cjitter Tskew Tor Tof Dtot Voc 100 45 200 55 200 200 100 950 950 55 (Vdd/2) + 0.2 MHz % mA ps ps ps ps % V 650 650 45 (Vdd/2) -0.2 Vdd/ 2 Fin=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz 9.3 DC CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS VDD2.5= 2.5V ± 5 %, TA = 0°C to +70°C SDATA, SCLK Input Low Voltage SDATA, SCLK Input High Voltage BUF_IN Input Voltage Low BUF_IN Input Voltage High Input Pin Capacitance Output Pin Capacitance Input Pin Inductance SVIL SVIH VIL VIH CIN COUT LIN 2.1 5 6 7 2.2 0.4 1.0 Vdc Vdc Vdc Vdc pF pF nH Fin=100 to 200Mhz Fin=100 to 200Mhz -9- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 10. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83176R-733 W83176G-733 48 PIN SSOP 48 PIN SSOP(Lead free part) Commercial, 0°C to +70°C Commercial, 0°C to +70°C 11. HOW TO READ THE TOP MARKING W83176R-733 28051234 342GAASA W83176G-733 28051234 342GAASA 1st line: Winbond logo and the type number: Normal:W83176R-733, Lead free part: W83176G-733 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G E D SA 342: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision SA: Internal use code All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 10 - W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 12. PACKAGE DRAWING AND DIMENSIONS .035 .045 .045 .055 0.40/0.50 DIA SYMBOL DIMENSION IN MM DIMENSION IN INCH E END VIEW HE A A1 A2 b c D HE E e L L1 Y θ MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0.13 0.25 0.005 0.720 0.400 0.292 0.020 0.024 18.2 18.42 18.54 9 10.16 10.31 10.41 7.42 0.51 0.61 7.52 0.64 0.81 1.40 7.59 0.76 1.02 0.08 8 MAX. 0.110 0.016 0.092 0.0135 0.010 TOP VIEW SEE DETAIL "A" c D θ A2 A Y SEATING PLANE e SIDE VIEW A1 0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 8 b PARTING LINE c 0 0 θ L L1 DETAIL"A" Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 11 - Publication Release Date: March, 2006 Revision 1.0