W83194AR-W

W83194AR-W 150MHZ CLOCK FOR WHITNEY CHIPSET 1.0 GENERAL DESCRIPTION The W83194AR-W is a Clock Synthesizer for Intel Whitney chipset. W83194AR-W provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 different frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194AR-W provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.5% and 0.75% center type spread spectrum to reduce EMI. The W83194AR-W accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES • • • • • • • • • • • • 2 CPU clocks 9 SDRAM clocks for 2 DIMMs 8 PCI synchronous clocks. Optional single or mixed supply: (VddR = VddP=VddS = Vdd48 = Vdd3 = 3.3V, VddA=VddC=2.5V) Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 150MHz I2C 2-Wire serial interface and I2C read back 0.5% and 0.75% center type spread spectrum Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) Two 48 MHz pins for USB 24 MHz for super I/O 48-pin SSOP package -1- Publication Release Date: May. 1999 Revision 0.50 W83194AR-W PRELIMINARY 3.0 PIN CONFIGURATION REFX2/*FS3 VddR Xin Xout Vss Vdd3 3V66-0 3V66-1 Vss3 PCICLK0/ *FS0 PCICLK1/ FS1# PCICLK2/*FS2 VssP PCICLK3/FS4# PCICLK4 VddP PCICLK5 PCICLK6 PCICLK7 Vss48 48MHz_0 48MHz_1 *SIO_SEL/24_48MHz Vdd48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VddLAPIC IOAPIC VddLCPU CPUCLK0 CPUCLK1 VssC VddS SDRAM 0 SDRAM 1 SDRAM 2 VssS SDRAM 3 SDRAM 4 SDRAM 5 VddS SDRAM 6 SDRAM 7 SDRAM 8 VssS PD# *SDCLK VddA VssA *SDATA -2- Publication Release Date: May. 1999 Revision 0.50 W83194AR-W PRELIMINARY 4.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250kΩ pull-up 4.1 Crystal I/O SYMBOL Xin Xout PIN 3 4 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. 4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs SYMBOL CPUCLK [0:1] PD# IOAPIC SDRAM [ 0:8] PIN 45,44 29 47 41,40, 39,37,36,35,33 ,32,31 10 I/O OUT IN OUT OUT FUNCTION Low skew (< 250ps) clock outputs for host frequencies such as CPU and Chipset. Power Down mode when driven low. Clock outputs synchronous with PCI clock and powered by VddA. SDRAM clock outputs. PCICLK0/ *FS0 I/O PCICLK1/ FS1# 11 I/O PCICLK2/ *FS2 12 I/O PCICLK3/ FS4# 14 I/O PCICLK [ 4:7 ] 3V66 [0:1] 15,17,18,19 7,8 OUT OUT 3.3V 33MHz PCI clock during normal operation. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. Latched input for FS4 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. 3.3V output clocks for the chipset. -3- Publication Release Date: May. 1999 Revision 0.50 W83194AR-W PRELIMINARY 4.3 I2C Control Interface SYMBOL *SDATA *SDCLK PIN 25 28 I/O I/O IN 2 FUNCTION Serial data of I C 2-wire control interface with internal pull-up resistor. Serial clock of I2C 2-wire control interface with internal pull-up resistor. 4.4 Fixed Frequency Outputs SYMBOL REFX2 / *FS3 PIN 3 I/O I/O FUNCTION 14.318MHz reference clock. This REF output is the stronger buffer for ISA bus loads. Halt PCICLK(0:4) clocks at logic 0 level, when input low (In mobile mode. MODE=0) *SIO_SEL/24_48MHz 23 I/O 24MHz or 48MHz output clock. Latched input for SIO_SEL at initial power up for the output frequency of 24MHz(HIGH) and 48MHz(LOW) clocks. 48MHz [0:1] 21,22 I/O 48MHz output for USB during normal operation. 4.5 Power Pins SYMBOL VddL Vdd48 Vdd3 VddP VddR VddS VddA Vss PIN 48 24 6 16 2 42,34 27 FUNCTION Power supply for CPU & IOAPIC, 2.5V or 3.3V. Power supply for 48MHz output,3.3V. Power supply for 3V_66 output, 3.3V. Power supply for PCICLK, 3.3V. Power supply for REFX2, 3.3V. Power supply for SDRAM[0:8], nominal 3.3V. Power for I2C CLK and DATA. 5,9,13,20,26,30,38, Circuit Ground. 43 -4- Publication Release Date: May. 1999 Revision 0.50 W83194AR-W PRELIMINARY 5.0 FREQUENCY SELECTION BY HARDWARE FS4 FS3 FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) 3V66(MHz) PCI (Mhz) = 3V66/2 IOAPIC (Mhz) = PCI/2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 83.3 90 75 150 138 95.25 129 124 119 114 110 105 66.8 100.2 133.6 125 90 113 150 138 95.25 129 124 119 114 110 105 100.2 100.2 100.2 133.3 125 127 130 72 140 136 145 155 121 117 112 107 66.8 100.2 100.9 133.3 125 127 130 108 140 136 145 155 121 117 112 107 100.2 100.2 100.9 83 60 75 75 69 63.5 86 83 80 76 73.3 70 66.8 66.8 66.7 66.7 83.33 84.67 86.67 72 70 68 73 78 81 78 75 71 66.8 66.8 67.3 41.7 30 37.7 37.5 34.6 31.75 43 41.4 39.8 38 36.7 35 33.4 33.3 33.6 33.3 41.67 42.34 43.33 36.1 35.1 33.9 36.3 38.8 40.5 38.9 37.3 35.7 33.4 33.4 33.6 20.85 15 18.85 18.75 17.3 15.88 21.5 20.7 19.9 19 18.35 17.5 16.7 16.7 16.8 16.7 20.83 21.17 21.67 18.05 17.55 16.95 18.15 19.4 20.25 19.45 18.65 17.85 16.7 16.7 16.8 133.6 133.6 66.7 33.3 16.7 -5- Publication Release Date: May. 1999 Revision 0.50 W83194AR-W PRELIMINARY 6.0 SERIAL CONTROL 0REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. Frequency Table Setting by I2C (SEL5 ~ SEL0) SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 83.3 90 75 150 138 95.25 SDRAM (MHz) 125 90 113 150 138 95.25 3V66 (MHz) 83 60 75 75 69 63.5 PCI (MHz) 41.7 30 37.7 37.5 34.6 31.75 IOAPIC (MHz) 20.85 15 18.85 18.75 17.3 15.88 129 124 119 114 110 105 66.8 100.2 133.6 133.3 129 124 119 114 110 105 100.2 100.2 100.2 133.3 86 83 80 76 73.3 70 66.8 66.8 43 41.4 39.8 38 36.7 35 33.4 33.3 21.5 20.7 19.9 19 18.35 17.5 16.7 16.7 66.7 66.7 33.6 33.3 16.8 16.7 125 127 130 72 140 136 145 155 121 117 112 107 66.8 100.2 100.9 133.3 125 127 130 108 140 136 145 155 121 117 112 107 100.2 100.2 100.9 133.3 83.33 84.67 86.67 72 70 68 73 78 81 78 75 71 66.8 66.8 67.3 66.7 41.67 42.34 43.33 36.1 35.1 33.9 36.3 38.8 40.5 38.9 37.3 35.7 33.4 33.4 33.6 33.3 20.83 21.17 21.67 18.05 17.55 16.95 18.15 19.4 20.25 19.45 18.65 17.85 16.7 16.7 16.8 16.7 -6- Publication Release Date: May. 1999 Revision 0.50 W83194AR-W PRELIMINARY SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 CPU (MHz) SDRAM (MHz) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 141 143 145 146 147 148 149 151 153 155 156 157 159 161 163 164 168 170 172 175 177 180 182 184 186 188 190 192 194 196 198 200 141 143 145 146 147 148 149 151 153 155 156 157 159 161 163 164 168 170 172 175 177 180 182 184 186 188 190 192 194 196 198 200 3V66 (MHz) 70.5 71.5 72.5 73 73.5 74 74.5 75.5 76.5 77.5 78 78.5 79.5 80.5 81.5 82 84 85 86 58.33 59 60 60.67 61.33 62 62.67 63.33 64 64.67 65.33 66 66.67 PCI (MHz) 35.25 35.75 36.25 36.5 36.75 37 37.25 37.75 38.25 38.75 39 39.25 39.75 40.25 40.75 41 42 42.5 43 29.17 29.5 30 30.33 30.67 31 31.33 31.67 32 32.33 32.67 33 33.33 IOAPIC (MHz) 17.63 17.88 18.13 18.25 18.38 18.5 18.63 18.88 19.13 19.38 19.5 19.63 19.88 20.13 20.38 20.5 21 21.25 21.5 14.58 14.75 15 15.17 15.33 15.5 15.67 15.83 16 16.17 16.33 16.5 16.67 -7- Publication Release Date: May. 1999 Revision 0.50 W83194AR-W PRELIMINARY 6.1 Register 0: Control Register Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 0 0 0 1 1 1 Pin 1 23 21,22 31 Reserved REF2X(Active / Inactive) Reserved Reserved Reserved 24_48MHz(Active / Inactive) 48MHz_0, 48MHz_1(Active / Inactive) SDRAM8(Active / Inactive) Description 6.2 Register 1 : SDRAM Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 32 33 35 36 37 39 40 41 SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive) Description 6.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 19 18 17 15 14 13 11 10 PCICLK7 (Active / Inactive) PCICLK6 (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK0 (Active / Inactive) Description -8- Publication Release Date: May. 1999 Revision 0.50 W83194AR-W PRELIMINARY 6.4 Register 3: CPU Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 1 0 1 1 1 0 Pin 8 7 47 44 43 Reserved 3V66_1(Active / Inactive) 3V66_0(Active / Inactive) Reserved IOAPIC(Active / Inactive) CPUCLK1 (Active / Inactive) CPUCLK0 (Active / Inactive) Reserved Description 6.5 Register 4: Control Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description SSEL3 (Frequency table selection by software via I2C ) SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit (1,2, 4:6) SSEL4 (Frequency table selection by software via I2C ) SSEL5 (Frequency table selection by software via I2C ) Reserved 6.6 Register 5: Control Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description 0 = ¡Ó0.5% Center type Spread Spectrum Modulation 1 = ¡Ó0.75% Center type Spread Spectrum Modulation Reserved Reserved Reserved Reserved Reserved 0 = Normal 1 = Spread Spectrum enabled Reserved -9- Publication Release Date: May. 1999 Revision 0.50 W83194AR-W PRELIMINARY 6.7 Register 6: Winbond Chip ID Register (Read Only) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 0 0 1 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description 6.8 Register 7: Winbond Chip ID Register (Read Only) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 1 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description - 10 - Publication Release Date: May. 1999 Revision 0.50 W83194AR-W PRELIMINARY 7.0 ORDERING INFORMATION Part Number W83194AR-W Package Type 48 PIN SSOP Production Flow Commercial, 0°C to +70°C 8.0 HOW TO READ THE TOP MARKING W83194AR-W 28051234 814GBB 1st line: Winbond logo and the type number: W83194AR-W 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR BB: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 11 - Publication Release Date: May. 1999 Revision 0.50 W83194AR-W PRELIMINARY 9.0 PACKAGE DRAWING AND DIMENSIONS Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 12 - Publication Release Date: May. 1999 Revision 0.50