W83194BR-372

W83194BR-372 WINBOND CLOCK GENERATOR FOR SIS 746/748 CHIPSETS -I- Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 2 BLOCK DIAGRAM ...................................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 3 5.1 5.2 5.3 5.4 5.5 5.6 6. 7. Crystal I/O .............................................................................................................................3 CPU, AGP, ZCLK and PCI, IOAPIC Clock Outputs............................................................3 Fixed Frequency Outputs.....................................................................................................4 I2C Control Interface .............................................................................................................4 Power Management Pins.....................................................................................................4 Power Pins............................................................................................................................4 FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 5 I2C CONTROL AND STATUS REGISTERS ............................................................................... 6 7.1 7.2 7.3 7.4 FFh) 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 Register 0: Frequency Select (Default = 40h) .....................................................................6 Register 1: CPU Clock (1 = Enable, 0 = Stopped) (Default: 68h).......................................6 Register 2: PCI Clock (1 = Enable, 0 = Stopped) (Default: FFh)........................................6 Register 3: AGP, 24_48MHz, 48MHz, REF Control (1 =Enable, 0 =Stopped) (Default: 7 Register 4: IOAPIC, ZCLK Control (1 = Enable, 0 = Stopped) (Default: F0h) ...................7 Register 5: 24_48MHz Control (Default: 88h) .....................................................................7 Register 6: M/N (Default: 90h) .............................................................................................8 Register 7: N (Default: BBh).................................................................................................8 Register 8: Winbond Chip ID (Default: 72h) (Read only)....................................................8 Register 9: Reserved (Default: 50h) (Read only) ................................................................9 Register 10: M/N Program (Default: 04h)............................................................................9 Register 11: Spread Spectrum Programming (Default: 0Eh) ...........................................10 Register 12: Divisor and Step-less Enable Control (Default: 88h)....................................10 Register 13: FIX Mode Control (Default: 0Fh)...................................................................12 Register 14: Fix Mode Control (Default: 2Ch) ...................................................................12 Register 15: Skew Control (Default: E4h)..........................................................................13 Block Write Protocol ...........................................................................................................14 Block Read Protocol...........................................................................................................14 - II - 8. ACCESS INTERFACE .............................................................................................................. 14 8.1 8.2 W83194BR-372 8.3 8.4 9. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10. 11. 12. 13. Byte Write Protocol.............................................................................................................14 Byte Read Protocol.............................................................................................................14 Absolute Maximum Ratings ...............................................................................................15 General Operating Characteristics ....................................................................................15 Skew Group Timing Clock .................................................................................................15 CPU (Open Drain) Electrical Characteristics.....................................................................16 AGP, ZCLK Electrical Characteristics................................................................................16 PCI Electrical Characteristics.............................................................................................16 24M, 48M Electrical Characteristics ..................................................................................17 REF Electrical Characteristics............................................................................................17 IOAPIC Electrical Characteristics ......................................................................................17 SPECIFICATIONS .................................................................................................................... 15 ORDERING INFORMATION..................................................................................................... 18 HOW TO READ THE TOP MARKING...................................................................................... 18 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 19 REVISION HISTORY ................................................................................................................ 20 - III - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 1. GENERAL DESCRIPTION The W83194BR-372 is a Clock Synthesizer for SIS 746/748 chipset. W83194BR-372 provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, PCI, and AGP clocks setting, support two ZCLK clock outputs; all clocks are externally selectable with smooth transitions. The W83194BR-372 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83194BR-372 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. 2. PRODUCT FEATURES • • • • • • • • • • • • • • • • • • 1 2.5V open drain Differential pairs clock outputs for CPU 1 2.5V open drain singled-ended clock output for chipset host bus. 2 3.3V ZCLK clock outputs 2 AGP clock outputs 8 PCI synchronous clocks 2 2.5V IOAPIC clock outputs 1 24_48Mhz clock output for super I/O. 1 48 MHz clock output for USB. 3 14.318MHz REF clock outputs. ZCLK/AGP/PCI clock out supports synchronous and asynchronous mode Smooth frequency switch with selections from 100 to 200MHz Step-less frequency programming I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% and +/- 0.25% center type spread spectrum Programmable S.S.T. scale to reduce EMI Programmable registers to enable/stop each output and select modes Programmable clock outputs Skew control 48-pin SSOP package -1- Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 3. PIN CONFIGURATION VDDREF FS0 &/REF0 FS1 &/REF1 REF2 GND XIN XOUT GND ZCLK0 ZCLK1 VDDZ PCI_STOP#* VDDPCI FS2 &/PCI_F0 FS3*/PCI_F1 PCI0 PCI1 GND VDDPCI PCI2 PCI3 PCI4 PCI5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDI IOAPIC1 IOAPIC0 GND CPU_STOP#* CPUT1 VDDCPU GND CPUT0 CPUC0 VDDCPU GND VDDA SCLK * SDATA* PD#* GND AGP_0 AGP_1 VDDAGP VDD48 48MHz 24_48MHz GND #: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND 4. BLOCK DIAGRAM PLL2 Divider 48MHz 24_48MHz 3 XIN XOUT XTAL OSC REF 0:2 PLL1 Spread Spectrum VCOCLK 2 CPUT0:1 CPUC0 ZCLK0:1 2 M/N/Ratio ROM 2 Divider 2 IOAPIC0:1 AGP 0:1 FS(0:3) Latch &POR 8 PCI_F0:1,P CI_0:5 PD#* PCI_STOP#* CPU_STOP#* Control Logic &Config Register SDATA* SCLK* I2C Interface -2- W83194BR-372 5. PIN DESCRIPTION BUFFER TYPE SYMBOL DESCRIPTION IN INtp120k INtd120k OUT OD # * & Input Latched input at power up, internal 120kΩ pull up. Latched input at power up, internal 120kΩ pull down. Output Open Drain Active Low Internal 120kΩ pull-up Internal 120 kΩ pull-down 5.1 Crystal I/O PIN PIN NAME TYPE DESCRIPTION 6 7 XIN XOUT IN OUT Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). 5.2 CPU, AGP, ZCLK and PCI, IOAPIC Clock Outputs PIN PIN NAME TYPE DESCRIPTION 40,39 43 31,30 9,10 14 CPUT0 CPUC0 CPUT1 AGP_0: 1 ZCLK0: 1 PCI_F0 FS2& PCI_F1 OD OD OUT OUT OUT INtd120k OUT INtp120k OUT OUT 2.5V open drain differential clock outputs for AMD K7 CPU 2.5V open drain singled –ended synchronize with CPUT0, For chipset host bus 3.3V AGP clock outputs. 3.3V ZCLK clock outputs, For MuTIOL bus. 3.3V PCI free running clock output. Latched input for FS2 at initial power up for H/W selecting the output frequency. This is internal 120K pull down. 3.3V PCI free running clock output. Latched input for FS3 at initial power up for H/W selecting the output frequency, This is internal 120K pull up. Low skew (< 250ps) PCI clock outputs. 2.5V IOAPIC outputs. 15 16, 17, 20, 21, 22, 23 47, 46 FS3* PCI [0:5] IOAPIC [0:1] -3- Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 5.3 Fixed Frequency Outputs PIN PIN NAME TYPE DESCRIPTION REF0 2 FS0& REF1 3 4 27 26 FS1& REF2 48MHz 24_48MHz OUT INtd120k OUT INtd120k OUT OUT OUT 14.318MHz output. Latched input for FS0 at initial power up for H/W selecting the output frequency. This is internal 120K pull down. 14.318MHz output. Latched input for FS1 at initial power up for H/W selecting the output frequency. This is internal 120K pull down. 14.318MHz output. 48MHz clock output for USB. 24MHz (default) or 48MHz clock output, it could be R/W by I2C control after power on reset period. Select by register 5 bit 7. 5.4 I2C Control Interface PIN PIN NAME TYPE 2 DESCRIPTION 34 35 SDATA* SCLK* I/OD IN Serial data of I C 2-wire control interface with internal pull-up resistor. Serial clock of I2C 2-wire control interface with internal pull-up resistor. 5.5 Power Management Pins PIN PIN NAME TYPE DESCRIPTION 33 12 44 PD#* PCI_STOP#* CPU_STOP#* INtp120k INtp120k INtp120k Power Down Function. This is power down pin, low active (PD#). Internal 120K pull up Active low, Stop all PCI clock output besides the free running clocks. Active low, Stop all CPU clock outputs. 5.6 Power Pins PIN PIN NAME TYPE DESCRIPTION 1 13,19 29 38,42 28 11 48 36 5, 8, 18, 24, 25, 32, 37, 41, 45 VDDREF VDDPCI VDDAGP VDDCPU VDD48 VDDZ VDDI VDDA GND PWR PWR PWR PWR PWR PWR PWR PWR PWR 3.3V power supply for REF. 3.3V power supply for PCI. 3.3V power supply for AGP. 2.5V power supply for CPU. 3.3V power supply for 48MHz. 3.3V power supply for ZCLK. 2.5V power supply for IOAPIC 3.3V power supply for Analog core logic. Ground pin -4- W83194BR-372 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3). FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHZ) 133.34 133.34 133.34 133.34 133.34 133.34 133.34 133.34 100.00 100.00 100.00 100.00 100.00 166.67 110.97 110.97 114.55 119.91 133.34 133.34 133.34 145.64 149.89 166.67 111.12 137.37 144.97 149.89 155.04 166.67 180.17 200.01 ZCLK (MHZ) 66.67 66.67 100.00 100.00 133.34 133.34 166.67 166.67 66.67 66.67 100.00 100.00 133.34 133.34 166.45 166.45 95.45 99.93 83.34 111.12 133.34 116.51 99.93 111.12 133.34 137.37 144.97 149.89 124.03 133.34 135.13 133.34 AGP (MHZ) 66.67 50.00 66.67 50.00 66.67 50.00 66.67 55.56 66.67 50.00 66.67 50.00 66.67 66.67 66.58 55.48 63.64 66.62 66.67 74.08 83.34 64.73 66.62 66.67 66.67 68.68 64.43 66.62 68.91 66.67 67.56 66.67 PCI (MHZ) 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.29 33.29 31.82 33.31 33.33 33.33 33.33 32.37 66.31 33.33 33.33 34.34 32.22 33.31 34.45 33.33 33.78 33.33 -5- Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 7. I2C CONTROL AND STATUS REGISTERS 7.1 Register 0: Frequency Select (Default = 40h) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 SSEL [4] SSEL [3] SSEL [2] SSEL [1] SSEL [0] EN_SSEL 0 1 0 0 0 0 Enable software table selection FS [4:0]. 0 = Hardware table setting (Jump mode). 1 = Software table setting through Bit7~3. (Jump less mode) Enable spread spectrum mode under clock output. 0 = Spread Spectrum mode disable 1 = Spread Spectrum mode enable Reserved Frequency selection by software via I2C 1 0 EN_SPSP Reserved 0 0 7.2 Register 1: CPU Clock (1 = Enable, 0 = Stopped) (Default: 68h) BIT PIN NO PWD DESCRIPTION 7 6 5 4 3 2 1 0 Tri-state 43 40,39 15 14 3 2 0 1 1 X X X X X Tri-state all output if set 1 CPUT1 output control CPUT0 / C0 output control Default: 0 (Read only) Power on latched value of FS3 pin. Default: 1 (Read only) Power on latched value of FS2 pin. Default: 0 (Read only) Power on latched value of FS1 pin. Default: 0 (Read only) Power on latched value of FS0 pin. Default: 0 (Read only) 7.3 Register 2: PCI Clock (1 = Enable, 0 = Stopped) (Default: FFh) BIT PIN NO PWD DESCRIPTION 7 6 5 4 3 2 1 0 15 14 23 22 21 20 17 16 1 1 1 1 1 1 1 1 PCI_F1 output control PCI_F0 output control PCI5 output control PCI4 output control PCI3 output control PCI2 output control PCI1 output control PCI0 output control -6- W83194BR-372 7.4 Register 3: AGP, 24_48MHz, 48MHz, REF Control (1 =Enable, 0 =Stopped) (Default: FFh) BIT PIN NO PWD DESCRIPTION 7 6 5 4 3 2 1 0 30 31 26 27 4 3 2 - 1 1 1 1 1 1 1 1 AGP_1 output control AGP_0 output control 24_48MHz output control 48MHz output control REF2 output control REF1 output control REF0 output control Reserved 7.5 Register 4: IOAPIC, ZCLK Control (1 = Enable, 0 = Stopped) (Default: F0h) BIT PIN NO PWD DESCRIPTION 7 6 5 4 3 2 1 0 47 46 10 9 SEL SEL SEL 1 1 1 1 0 0 0 0 IOAPIC1 output control IOAPIC0 output control ZCLK1 output control ZCLK0 output control Reserved Asynchronous ZCLK/AGP/PCI frequency table selection, SEL 001: 132 / 66 / 33M 011: 132 / 88 / 44M 101: 132 / 66 / 33M 111: 132 / 88 / 33M 010:132 / 75.43 / 37.7M 100:176 / 88 / 44M 110:132 / 75.43 / 33M 000: Clock from PLL1 7.6 Register 5: 24_48MHz Control (Default: 88h) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 SEL24_48 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 0 0 0 1 0 0 0 24 / 48 MHz output selection, 1: 24 MHz (Default), 0: 48 MHz. Reserved Reserved Reserved -7- Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 7.7 Register 6: M/N (Default: 90h) Bit 7 6 5 4 3 2 1 0 Name N M M>5> M M M M M PWD 1 0 0 1 0 0 0 0 Programmable M divisor DESCRIPTION Programmable N divisor value. Bit 7 ~0 are defined in the Register 7. 7.8 Register 7: N (Default: BBh) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 N N N N N N N N 1 0 1 1 1 0 1 1 Programmable N divisor bit 7 ~0. The bit 8 is defined in Register 6. 7.9 Register 8: Winbond Chip ID (Default: 72h) (Read only) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0] 0 1 1 1 0 0 1 0 Winbond Chip ID. W83194BR-372 (SA5872). Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. -8- W83194BR-372 7.10 Register 9: Reserved (Default: 50h) (Read only) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 1 0 1 0 0 0 0 Reserved Reserved Reserved Reserved 7.11 Register 10: M/N Program (Default: 04h) BIT NAME PWD DESCRIPTION 0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is 7 EN_MN_PROG 0 VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS or desired frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg0 - bit 0). 6 5 4 3 2 1 0 N Reserved IVAL IVAL IVAL IVAL Reserved 0 0 0 0 1 0 0 Reserved Charge pump current selection Programmable N divisor bit 9. Reserved -9- Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 7.12 Register 11: Spread Spectrum Programming (Default: 0Eh) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0] 0 0 0 0 1 1 1 0 Spread Spectrum Down Counter bit 3 ~ bit 0 2’s complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 Spread Spectrum Up Counter bit 3 ~ bit 0. 7.13 Register 12: Divisor and Step-less Enable Control (Default: 88h) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 Reserved Reserved Reserved DS4 DS3 DS2 DS1 DS0 1 0 0 0 1 0 0 0 Reserved Reserved Defined the CPU, ZCLK, AGP, PCI divider ratio - 10 - W83194BR-372 Table-2 CPU, ZCLK, AGP, PCI divider ratio selection Table DS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU Ratio 3 3 3 3 3 3 5 5 4 4 4 4 4 4 6 6 5 5 5 5 5 4 4 4 6 4 4 4 4 4 3 2 ZCLK Ratio 6 6 4 4 3 3 4 4 6 6 4 4 3 5 4 4 6 6 8 6 5 5 6 6 5 4 4 4 5 5 4 3 AGP Ratio 6 8 6 8 6 8 10 12 6 8 6 8 6 10 10 12 9 9 10 9 8 9 9 10 10 8 9 9 9 10 8 6 PCI Ratio 12 12 12 12 12 12 20 20 12 12 12 12 12 20 20 20 18 18 20 20 20 18 18 20 20 16 18 18 18 20 16 12 - 11 - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 7.14 Register 13: FIX Mode Control (Default: 0Fh) BIT NAME PWD DESCRIPTION PCI output frequency select mode 7 FIX_PCI 0 (Valid only when SEL is nonzero) 0: Output frequency according to frequency selection table 1: Output frequency according to FIX frequency table ZCLK output frequency select mode 6 FIX_ZCLK 0 (Valid only when SEL is nonzero) 0: Output frequency according to frequency selection table 1: Output frequency according to FIX frequency table 5 4 3 2 1 0 SPCNT [5] SPCNT [4] SPCNT [3] SPCNT [2] SPCNT [1] SPCNT [0] 0 0 1 1 1 1 Spread Spectrum Programmable time, the resolution is 280ns. Default period is 11.8us 7.15 Register 14: Fix Mode Control (Default: 2Ch) BIT NAME PWD DESCRIPTION AGP output frequency select mode 7 Fix_AGP 0 0: Output frequency according to frequency selection table 1: Output frequency according to FIX frequency table Invert the USB48 phase, 6 5 4 INV_USB48 Reserved SPSP1 0 1 0 0: In phase with USB24_48 1: 180 degrees out of phase Reserved Spread Spectrum type select. 00 : Down 3 SPSP0 1 01 : Down 1% 0.5% 10 : Center +/- 0.5% 11 : Center +/- 0.25% CPU to AGP skew control, Skew resolution is 340ps Expand the skew direction is same as CPU_AGP_SKEW [2:0] setting 2 1 0 ASKEW [2] ASKEW [1] ASKEW [0] 1 0 0 - 12 - W83194BR-372 7.16 Register 15: Skew Control (Default: E4h) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 CPU1STOP_EN CPU0STOP_EN ZSKEW [2] ZSKEW [1] ZSKEW [0] PSKEW [2] PSKEW [1] PSKEW [0] 1 1 1 0 0 1 0 0 Stop CPU1 clocks, 1: Enable stop feature, 0: Disable Stop CPU0 clocks, 1: Enable stop feature, 0: Disable Reserved CPU to ZCLK skew control, Skew resolution is 340ps Expand the skew direction is same as CPU_ZCLK_SKEW [2:0] setting CPU to PCI skew control, Skew resolution is 340ps Expand the skew direction is same as CPU_PCI_SKEW [2:0] setting - 13 - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 8. ACCESS INTERFACE The W83194BR-372 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-372 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write Protocol 8.2 Block Read Protocol ## In block mode, the command code must filled 8’h00 8.3 Byte Write Protocol 8.4 Byte Read Protocol - 14 - W83194BR-372 9. SPECIFICATIONS 9.1 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). PARAMETER RATING Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model) -0.5V to +4.6V - 0.5 V to + 4.6 V 3.135V to 3.465V 3.135V to 3.465V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C 2000V 9.2 General Operating Characteristics VDD48=VDDAGP=VDDREF=VDDPCI= 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF PARAMETER SYM. MIN. MAX. UNITS TEST CONDITIONS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance VIL VIH VOL VOH Idd Cin Cout Lin 0.8 2.0 0.4 2.4 350 5 6 7 Vdc Vdc Vdc Vdc mA pF pF nH All outputs using 3.3V power All outputs using 3.3V power CPU = 100 to 200 MHz PCI = 33.3 Mhz with load 9.3 Skew Group Timing Clock VDD48=VDDAGP=VDDREF=VDDPCI = 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF PARAMETER MIN. TYP. MAX. UNITS TEST CONDITIONS AGP to PCI Skew CPU to CPU Skew AGP to AGP Skew PCI to PCI Skew 48MHz to 48MHz Skew REF to REF Skew 1.5 2.6 3.5 200 250 500 1000 500 ns ps ps ps ps ps Measured at 1.5V Crossing point Measured at 1.5V Measured at 1.5V Measured at 1.5V Measured at 1.5V - 15 - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 9.4 CPU (Open Drain) Electrical Characteristics VDDCPU= 2.5V ± 5 %, TA = 0°C to +70°C, external 1.5V pull-up PARAMETER MIN. MAX. UNITS TEST CONDITIONS Rise Time Fall Time Absolute crossing point Voltages Cycle to Cycle jitter Duty Cycle 550 900 900 1250 250 ps ps mV ps % 100 to 200 Mhz, Vol=20%, Voh=80% 100 to 200Mhz, Vol=20%, Voh=80% 100 to 200Mhz 100 to 200Mhz 100 to 200Mhz 45 55 9.5 AGP, ZCLK Electrical Characteristics VDDAGP=VDDZ= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, PARAMETER MIN. MAX. UNITS TEST CONDITIONS Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 500 500 45 -33 2000 2000 250 55 -33 ps ps ps % mA mA mA mA Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V 30 38 9.6 PCI Electrical Characteristics VDDPCI= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, PARAMETER MIN. MAX. UNITS TEST CONDITIONS Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 500 500 45 -33 2000 2000 250 55 -33 ps ps ps % mA mA mA mA Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V 30 38 - 16 - W83194BR-372 9.7 24M, 48M Electrical Characteristics VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, PARAMETER MIN. MAX. UNITS TEST CONDITIONS Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 500 500 45 -33 2000 2000 500 55 -33 ps ps ps % mA mA mA mA Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V 30 38 9.8 REF Electrical Characteristics VDDREF= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, PARAMETER MIN. MAX. UNITS TEST CONDITIONS Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 1000 1000 45 -33 4000 4000 1000 55 -33 ps ps ps % mA mA mA mA Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V 30 38 9.9 IOAPIC Electrical Characteristics VDDI= 2.5V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, PARAMETER MIN. MAX. UNITS TEST CONDITIONS Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 400 400 45 -27 1600 1600 500 55 -27 ps ps ps % mA mA mA mA Measure from 0.4V to 2.0V Measure from 2.0V to 0.4V Measure 1.25V point Vout=1.0V Vout=2.375V Vout=1.2V Vout=0.3V 27 30 - 17 - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 10. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83194BR-372 48 PIN SSOP Commercial, 0°C to +70°C 11. HOW TO READ THE TOP MARKING W83194BR-372 28051234 342GBASA 1st line: Winbond logo and the type number: W83194BR-372 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G A A SA 342: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision SA: mask version All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. - 18 - W83194BR-372 12. PACKAGE DRAWING AND DIMENSIONS - 19 - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-372 13. REVISION HISTORY VERSION DATE PAGE DESCRIPTION All of the versions before 0.50 are for internal use. 0.5 0.6 0.7 0.8 1.0 1.1 09/03/03 10/01/03 12/18/03 04/27/04 12/28/04 4/13/2005 20 n.a. 1, 6, 7, 10, 11, 12, 16, 17 18 5, 11 First published preliminary version. Modify some description, red text. Correction IC version, correction some description and default value Change frequency table ‘01101’ Update on Web Add disclaimer Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 20 -