W83194BR-S

W83194BR-S 200MHZ 2-DIMM CLOCK FOR SOLANO CHIPSET 1.0 GENERAL DESCRIPTION The W83194BR-S is a Clock Synthesizer for Intel 815 Solano chipset. W83194BR-S provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 different frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194BR-S provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI. The W83194BR-S provides stepless frequency programming by controlling the VCO freq. and the clock output divisor ratio. Also the skew of CPU, SDRAM and 3V66 clock outputs are programmable. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. The W83194BR-S accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 • • • • • • • • • • • • • PRODUCT FEATURES 2 CPU clocks 3 3V66 for chipset and AGP clocks 9 SDRAM clocks for 2 DIMMs 7 PCI synchronous clocks. Optional single or mixed supply: (VddR = VddP=VddS = Vdd48 = Vdd3 = 3.3V, VddLAPIC=VddLCPU=2.5V) Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200 MHz 2 I C 2-Wire serial interface and I2C read back 0.25% and 0.5% center type spread spectrum Programmable registers to enable/stop each output and select modes Two 48 MHz pins for USB 24 MHz for super I/O 48-pin SSOP package Publication Release Date:June 2000 -1Revision 0.42 W83194BR-S PRELIMINARY 3.0 PIN CONFIGURATION REFX2/*FS3 VddR Xin Xout Vss Vdd3 3V66-0 3V66-1 3V66-2 Vss PCICLK0^/ *FS0 PCICLK1^/ FS1# PCICLK2^/*FS2 VssP PCICLK3/MODE1* PCICLK4^ VddP PCICLK5^ PCICLK6 Vss48 48MHz_0 48MHz_1/ FS4# *SIO_SEL/24_48MHz Vdd48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VddLAPIC IOAPIC VddLCPU CPUCLK0 CPUCLK1 VssC VddS SDRAM 0 SDRAM 1 SDRAM 2 VssS SDRAM 3 SDRAM 4 SDRAM 5 VddS SDRAM 6 SDRAM 7 SDRAM 8 VssS PD#/RESET$ SDCLK* VddA VssA SDATA* *: internal pull-up #: active low $: ope drain 4.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low lInternal 250kΩ pull-up Publication Release Date: June 2000 Revision 0.42 -2- W83194BR-S PRELIMINARY 4.1 Crystal I/O SYMBOL Xin Xout PIN 3 4 I/O IN OUT FUNCTION Crystal input with internal loading capacitors(36pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors(36pF). 4.2 CPU, SDRAM, SYMBOL CPUCLK [0:1] PD#/RESET$ PCI, IOAPIC Clock Outputs PIN 45,44 29 I/O OUT IN FUNCTION Low skew (< 250ps) clock outputs for host frequencies such as CPU and Chipset. Pin16 *Mode1=1, Power Down mode when driven low. Pin16 *Mode1=0, RESET# output (4ms low active pulse when Watch Dog time out) Clock outputs synchronous with PCI clock and powered by VddA. SDRAM clock outputs. IOAPIC SDRAM [ 0:8] 47 41,40, 39,37,36,35,33 ,32,31 11 OUT OUT PCICLK0/ *FS0 I/O PCICLK1/ FS1# 12 I/O PCICLK2/ *FS2 13 I/O PCICLK3/MODE1* 15 I/O PCICLK [ 4:6 ] 3V66 [0:2] 16,18,19 7,8,9 OUT OUT 3.3V 33MHz PCI clock during normal operation. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=1). Low skew (< 250ps) PCI clock outputs. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0). Low skew (< 250ps) PCI clock outputs. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=1). PCI clock during normal operation. Latched Input. *Mode1=1, Pin 29 is PD#; *Mode1=0, Pin 29 is RESET$ Low skew (< 250ps) PCI clock outputs. 3.3V output clocks for the chipset. -3- Publication Release Date: June 2000 Revision 0.42 W83194BR-S PRELIMINARY 4.3 I2C Control Interface SYMBOL SDATA SDCLK PIN 25 28 I/O I/O IN 2 FUNCTION Serial data of I C 2-wire control interface Serial clock of I2C 2-wire control interface 4.4 Fixed Frequency Outputs SYMBOL REFX2 / *FS3 PIN 3 I/O I/O FUNCTION 14.318MHz reference clock. This REF output is the stronger buffer for ISA bus loads. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=1). *SIO_SEL/24_48MHz 23 I/O 24MHz or 48MHz output clock. Latched input for SIO_SEL at initial power up for the output frequency of 24MHz(HIGH) and 48MHz(LOW) clocks. 48MHz_0 48MHz_1/ FS4# 21 22 O I/O 48MHz output for USB during normal operation. 48MHz / Latched input for FS4 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). 4.5 Power Pins SYMBOL VddL Vdd48 Vdd3 VddP VddR VddS VddA Vss PIN 48 24 6 16 2 42,34 27 FUNCTION Power supply for CPU & IOAPIC, 2.5V or 3.3V. Power supply for 48MHz output,3.3V. Power supply for 3V_66 output, 3.3V. Power supply for PCICLK, 3.3V. Power supply for REFX2, 3.3V. Power supply for SDRAM[0:8], nominal 3.3V. Power for I2C CLK and DATA. 5,10,14,20,26,30,38, Circuit Ground. 43 -4- Publication Release Date: June 2000 Revision 0.42 W83194BR-S PRELIMINARY 5.0 FREQUENCY SELECTION BY HARDWARE FS4 FS3 FS2 FS1 FS0 CPU(MHz) 75.30 95.00 129.00 150.00 150.00 110.00 140.00 144.00 68.30 105.00 138.00 140.00 66.80 100.20 133.60 133.60 157.30 160.00 146.00 122.00 127.00 122.00 117.00 114.00 80.00 78.00 166.00 160.00 66.60 100.00 133.30 133.30 SDRAM (MHz) 112.95 95.00 129.00 113.00 150.00 110.00 140.00 108.00 102.45 105.00 138.00 105.00 100.20 100.20 133.60 100.20 118.00 120.00 110.00 91.50 127.00 122.00 117.00 114.00 120.00 117.00 166.00 160.00 100.00 100.00 133.30 100.00 3V66(MHz) 75.30 63.33 86.00 75.33 75.00 73.33 70.00 72.00 68.30 70.00 69.00 70.00 66.80 66.80 66.80 66.80 78.67 80.00 73.33 61.00 84.67 81.33 78.00 76.00 80.00 78.00 83.00 80.00 66.67 66.67 66.65 66.67 PCI(MHz) 37.65 31.67 43.00 37.67 37.50 36.67 35.00 36.00 34.15 35.00 34.50 35.00 33.40 33.40 33.40 33.40 39.33 40.00 36.67 30.50 42.33 40.67 39.00 38.00 40.00 39.00 41.50 40.00 33.33 33.33 33.33 33.33 IOAPIC (MHz) 18.83 15.83 21.50 18.83 18.75 18.33 17.50 18.00 17.08 17.50 17.25 17.50 16.70 16.70 16.70 16.70 19.67 20.00 18.33 15.25 21.17 20.33 19.50 19.00 20.00 19.50 20.75 20.00 16.67 16.67 16.66 16.67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -5- Publication Release Date: June 2000 Revision 0.42 W83194BR-S PRELIMINARY 6.0 SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. Frequency Table Setting by I2C (SEL5 ~ SEL0) SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU (MHz) 75.30 95.00 129.00 150.00 150.00 110.00 140.00 144.00 68.30 105.00 138.00 140.00 66.80 100.20 133.60 133.60 157.30 160.00 146.00 122.00 127.00 122.00 117.00 114.00 80.00 78.00 166.00 160.00 66.60 SDRAM (MHz) 112.95 95.00 129.00 113.00 150.00 110.00 140.00 108.00 102.45 105.00 138.00 105.00 100.20 100.20 133.60 100.20 118.00 120.00 110.00 91.50 127.00 122.00 117.00 114.00 120.00 117.00 166.00 160.00 100.00 3V66 (MHz) 75.30 63.33 86.00 75.33 75.00 73.33 70.00 72.00 68.30 70.00 69.00 70.00 66.80 66.80 66.80 66.80 78.67 80.00 73.33 61.00 84.67 81.33 78.00 76.00 80.00 78.00 83.00 80.00 66.67 PCI(MHz) 37.65 31.67 43.00 37.67 37.50 36.67 35.00 36.00 34.15 35.00 34.50 35.00 33.40 33.40 33.40 33.40 39.33 40.00 36.67 30.50 42.33 40.67 39.00 38.00 40.00 39.00 41.50 40.00 33.33 IOAPIC (MHz) 18.83 15.83 21.50 18.83 18.75 18.33 17.50 18.00 17.08 17.50 17.25 17.50 16.70 16.70 16.70 16.70 19.67 20.00 18.33 15.25 21.17 20.33 19.50 19.00 20.00 19.50 20.75 20.00 16.67 -6- Publication Release Date: June 2000 Revision 0.42 W83194BR-S PRELIMINARY 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 100.00 133.30 133.30 CPU (MHz) 136.00 138.00 139.00 141.00 142.00 142.00 143.00 143.00 144.00 144.00 146.00 146.00 147.00 147.00 148.00 148.00 149.00 152.00 153.00 156.00 157.00 158.00 159.00 160.00 162.00 164.00 170.00 175.00 180.00 185.00 190.00 200.40 100.00 133.30 100.00 SDRAM (MHz) 102.00 138.00 104.25 105.75 142.00 106.50 143.00 107.25 144.00 108.00 146.00 109.50 147.00 110.25 148.00 111.00 111.75 152.00 114.75 156.00 117.75 158.00 119.25 160.00 121.50 123.00 127.50 116.67 120.00 185.00 126.67 133.60 66.67 66.65 66.67 3V66 (MHz) 68.00 69.00 69.50 70.50 71.00 71.00 71.50 71.50 72.00 72.00 73.00 73.00 73.50 73.50 74.00 74.00 74.50 76.00 76.50 78.00 78.50 79.00 79.50 80.00 81.00 82.00 85.00 77.78 80.00 61.67 63.33 66.80 33.33 33.33 33.33 PCI(MHz) 34.00 34.50 34.75 35.25 35.50 35.50 35.75 35.75 36.00 36.00 36.50 36.50 36.75 36.75 37.00 37.00 37.25 38.00 38.25 39.00 39.25 39.50 39.75 40.00 40.50 41.00 42.50 38.89 40.00 30.83 31.67 33.40 16.67 16.66 16.67 IOAPIC (MHz) 17.00 17.25 17.38 17.63 17.75 17.75 17.88 17.88 18.00 18.00 18.25 18.25 18.38 18.38 18.50 18.50 18.63 19.00 19.13 19.50 19.63 19.75 19.88 20.00 20.25 20.50 21.25 19.44 20.00 15.42 15.83 16.70 SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -7- Publication Release Date: June 2000 Revision 0.42 W83194BR-S PRELIMINARY 6.1 Register 0: Control Register Bit 7 6 5 4 3 2 @PowerUp X X X X X 1 Pin Description FS0# FS1# FS2# FS3# FS4# If Reg0-bit7=1 0 = ± 0.5% Center type Spread Spectrum Modulation 1 = ± 0.75% Center type Spread Spectrum Modulation If Reg0-bit7=0 0 = -0.6% Down type Spread Spectrum Modulation 1 = -1.0% Down type Spread Spectrum Modulation 0 = Normal 1 = Spread Spectrum enabled 1=CENTER SPREAD 0=DOWN SPREAD 1 0 0 1 - 6.2 Register 1 : SDRAM Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 38 41 42 43 44 47 48 49 Description SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive) 6.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 20 19 18 16 15 13 12 11 Description PCICLK7 (Active / Inactive) PCICLK6 (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK0 (Active / Inactive) -8- Publication Release Date: June 2000 Revision 0.42 W83194BR-S PRELIMINARY 6.4 Register 3: Control Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 9 8 7 23 47 21 22 1 3V66_2(Active/Inactive) 3V66_1(Active / Inactive) 3V66_0(Active / Inactive) 24_48MHz (Active / Inactive) IOAPIC (Active / Inactive) 48MHz0 (Active / Inactive) 48MHz1 (Active / Inactive) REF2X (Active / Inactive) Description 6.5 Register 4: Control Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description SSEL3 (Frequency table selection by software via I2C ) SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C Bit (1,2, 4:6) SSEL4 (Frequency table selection by software via I2C ) SSEL5 (Frequency table selection by software via I2C ) 0 = Running 1 = Tristate all outputs 6.6 Register 5: Skew Register Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 0 0 1 1 Pin 51 52 Description CSkew2 (CPU to SDRAM skew program bit) CSkew1 (CPU to SDRAM skew program bit) CSkew0 (CPU to SDRAM skew program bit) CASkew2 (CPU to 3V66 skew program bit) CASkew1 (CPU to 3V66 skew program bit) CASkew0 (CPU to 3V66 skew program bit) CPUCLK1(Active/Inactive) CPUCLK0(Active / Inactive) -9- Publication Release Date: June 2000 Revision 0.42 W83194BR-S PRELIMINARY 6.7 Register 6~10: Step-less M/N Mode Control Registers 6.12 Register 11: Winbond Chip ID Register Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 0 1 0 0 0 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID (Read Only) Description 6.13 Register 12: Winbond Chip ID Register Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 0 0 0 0 1 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Version ID Winbond Version ID Winbond Version ID (Read Only) Description Register10 Bit3-6 Bit6 DS3 0 0 0 0 0 0 0 0 1 1 Bit 5 DS2 0 0 0 0 1 1 1 1 0 1 Bit 4 DS1 0 0 1 1 0 0 1 1 x x Bit 3 DS0 0 1 0 1 0 1 0 1 x x CPU 4 3 2 2 6 3 6 4 2 2 Ratio SDRAM 4 3 3 2 4 4 3 3 2 4 3V66 6 6 6 6 6 6 6 6 4 6 Publication Release Date: June 2000 Revisio n 0.42 - 10 - W83194BR-S PRELIMINARY 7.0 SPECIFICATIONS 7.1 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Vdd , VIN TSTG TB TA Parameter Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature Rating - 0.5 V to + 7.0 V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C 7.2 Electronical Characteristics---Input/Output Vddq1=Vddq2 = Vddq3 = Vddq4 =3.3V, VddL1 =VddL2= 2.5V , TA = 0° C to +70° C Parameter Input Low Voltage Input High Voltage Input Low Current Input Low Current Input High Current Input Capacitance Symbol VIL VIH IIL IIL IIH CIN COUT CINX Operating Supply Current Power Down Supply Current Settling Time Idd3 Idd2 Ts 27 Min Vss-0.3 2.0 -5 -200 -5 5 5 6 45 100 600 3 mS Typ Max 0.8 Vdd+0.3 Units Vdc Vdc µA µA µA pF pF pF MA µA From first crossing to 1% target freq. Logic inputs Output capacitance Xin and Xout CPU = 66.6 MHz PCI = 33.3 Mhz with load No pull-up resistors Pull-up resistros Test Conditions - 11 - Publication Release Date: June 2000 Revisio n 0.42 W83194BR-S PRELIMINARY Delay tPZH,tPZH tPLZ,tPZH 1 1 10 10 nS nS Output enable delay Output enable delay 7.3 Electronical Characteristics of CPU Clock Symbol RDSP RDSN VOL VOH IOL IOH IOH(min) IOH(max) TRF(min) TRF(max) Dt TSK Tsc-c 45 0.4 1.6 55 175 250 2.0 27 -27 -27 -27 30 -27 Min 13.5 13.5 Typ Max 40 40 0.4 Units Ohm Ohm V V MA MA MA MA ns ns % ps ps Vout = 1.0 V Vout = 2.0V 10pF Load 20pF Load VT=1.25V VT=1.25V VT=1.25V Test Conditions Vdd=2.5V +/- 5%; CL=10-20pF Parameter Ouput Impedance Ouput Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current Pull-Up Current Min Pull-Up Current Max Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Duty Cycle Skew Jitter IOL=1mA IOH=-1mA 7.4 Electronical Characteristics of 3V66 Clock Vdd=3.3V +/- 5%; CL=10-30pF Parameter Ouput Impedance Ouput Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Symbol RDSP RDSN VOL VOH IOL IOH TRF(min) TRF(max) 2.4 30 -33 0.4 1.6 38 -33 Min 15 15 Typ Max 55 55 0.55 Units Ohm Ohm V V MA MA ns ns 10pF Load 20pF Load Test Conditions IOL=1mA IOH=-1mA - 12 - Publication Release Date: June 2000 Revisio n 0.42 W83194BR-S PRELIMINARY Duty Cycle Skew Jitter Dt TSK Tsc-c 45 55 175 500 % ps ps VT=1.5V VT=1.5V VT=1.5V 7.5 Electronical Characteristics of SDRAM Clock Vdd=3.3V +/- 5%; CL=20-30pF Parameter Ouput Impedance Ouput Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Duty Cycle Skew Jitter Symbol RDSP RDSN VOL VOH IOL IOH TRF(min) TRF(max) Dt TSK Tsc-c 45 2.4 54 -54 0.4 1.6 55 250 250 54 -45 Min 13.5 13.5 Typ Max 40 40 0.45 Units Ohm Ohm V V MA MA ns ns % ps ps 10pF Load 20pF Load VT=1.5V VT=1.5V VT=1.5V Test Conditions IOL=1mA IOH=-1mA 7.6 Electronical Characteristics of PCI Clock Vdd=3.3V +/- 5%; CL=10-30pF Parameter Ouput Impedance Ouput Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Symbol RDSP RDSN VOL VOH IOL IOH TRF(min) TRF(max) 2.4 30 -33 0.5 2.0 38 -33 Min 15 15 Typ Max 55 55 0.55 Units Ohm Ohm V V MA MA ns ns 10pF Load 20pF Load Test Conditions IOL=1mA IOH=-1mA - 13 - Publication Release Date: June 2000 Revisio n 0.42 W83194BR-S PRELIMINARY Between 0.4 V and 2.0 V Duty Cycle Skew Jitter Dt TSK Tsc-c 45 55 500 500 % ps ps VT=1.5V VT=1.5V VT=1.5V 7.7 Electronical Characteristics of 48MHz, REF Clock Vdd=3.3V +/- 5%; CL=10-20pF Parameter Ouput Impedance Ouput Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current RiseTime Fall Time Duty Cycle Skew Jitter Symbol RDSP RDSN VOL VOH IOL IOH TR TF Dt TSK Tsc-c 45 2.4 29 -29 1.8 1.7 27 -23 4 4 55 500 1000 Min 20 20 Typ Max 55 55 0.4 Units Ohm Ohm V V MA MA ns ns % ps ps 10pF Load 20pF Load VT=1.5V VT=1.5V VT=1.5V Test Conditions IOL=1mA IOH=-1mA - 14 - Publication Release Date: June 2000 Revisio n 0.42 W83194BR-S PRELIMINARY 8.0 ORDERING INFORMATION Part Number W83194BR-S Package Type 48 PIN SSOP Production Flow Commercial, 0°C to +70°C 9.0 HOW TO READ THE TOP MARKING W83194BR-S 28051234 814GAB 1st line: Winbond logo and the type number: W83194BR-S 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 15 - Publication Release Date: June 2000 Revisio n 0.42 W83194BR-S PRELIMINARY - 16 - Publication Release Date: June 2000 Revisio n 0.42 W83194BR-S PRELIMINARY 10.0 PACKAGE DRAWING AND DIMENSIONS Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 17 - Publication Release Date: June 2000 Revisio n 0.42