W83194R-17A

W83194R-17/-17A 100MHZ AGP CLOCK FOR SIS CHIPSET 1.0 GENERAL DESCRIPTION The W83194R-17/-17A is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor such as Intel PentiumII, PentiumPro , AMD or Cyrix. Eight different frequency of CPU, AGP and PCI clocks are externally selectable with smooth transitions. The W83194R-17/-17A provides AGP clocks especially for clone chipset. The highest CPU frequency provided by the W83194R-17 is up to 100MHz, but the one of W83194R-17A is up to 133MHz. The W83193R-17/-17A provides I2C serial bus interface to program the registers to enable or disable each clock outputs and choose the 0.5% or 1.5% center type spread spectrum to reduce EMI. The W83194R-17/-17A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads Ó as maintaining 50¡ 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES • • • • • • • • • • • • • • • Supports Pentium™, Pentium™ Pro, Pentium™ II, AMD and Cyrix CPUs with I2C. 4 CPU clocks 12 SDRAM clocks for 3 DIMMs Two AGP clocks 6 PCI synchronous clocks. Optional single or mixed supply: (Vdd = Vddq3 = Vddq2 = Vddq2b = 3.3V) or (Vdd =Vddq2 = Vddq3 = 3.3V, Vddq2b = 2.5V) Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns, AGP to CPU sync. skew 0 ns (250 ps) Smooth frequency switch with selections from 60 MHz to 133 MHz CPU I2C 2-Wire serial interface and I2C read back ¡Ó0.5% or ¡Ó1.5% center type spread spectrum function to reduce EMI Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) MODE pin for power Management 48 MHz for USB 24 MHz for super I/O 48-pin SSOP package -1- Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 3.0 BLOCK DIAGRAM PLL2 ~ X1 X2 48MHz ¡Ò2 2 24MHz XTAL OSC STOP REF(0:1) AGP(0:1) 2 PLL1 Spread Spectrum FS(0:2) MODE CPU3.3#_2.5 3 STOP 4 CPUCLK(0:3) LATCH ~ POR 5 12 3 PCI clock Divder SDRAM(0:11) STOP PCICLK(0:4) 5 PCICLK_F CPU_STOP# PCI_STOP# SDATA SCLK Control Logic Config. Reg. 4.0 PIN CONFIGURATION Vdd REF0/CPU3.3#_2.5 Vss Xin Xout Vddq3 PCICLK_F/*FS1 PCICLK0/*FS2 Vss PCICLK1 PCICLK2 PCICLK3 PCICLK4 Vddq3 AGP0 Vss CPU_STOP#/SDRAM11 PCI_STOP#/SDRAM10 Vddq3 SDRAM 9 SDRAM 8 Vss SDATA SDCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vddq2 AGP1 REF1 Vss CPUCLK0 CPUCLK1 Vddq2b CPUCLK2 CPUCLK3 Vss SDRAM 0 SDRAM 1 Vddq3 SDRAM 2 SDRAM 3 Vss SDRAM 4 SDRAM 5 Vddq3 SDRAM 6 SDRAM 7 Vss 48MHz/*FS0 24MHz/*MODE -2- Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 5.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250kΩ pull-up 5.1 Crystal I/O SYMBOL Xin Xout PIN 4 5 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. 5.2 CPU, SDRAM, PCI Clock Outputs SYMBOL CPUCLK [ 0:3 ] PIN 40,41,43,44 I/O OUT FUNCTION Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. Vddq2b is the supply voltage for these outputs. Accelerate Graphic Port clock outputs If MODE =1 (default), then this pin is a SDRAM Clock buffered output. If MODE = 0 , then this pin is CPU_STOP# input used in power management mode for synchronously stopping the all CPU clocks. If MODE = 1 (default), then this pin is a SDRAM clock output. If MODE = 0 , then this pin is PCI_STOP # and used in power management mode for synchronously stopping the all PCI clocks. SDRAM clock outputs which have the same frequency as CPU clocks. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Free running PCI clock during normal operation. AGP[ 0:1] SDRAM11/ CPU_STOP# 15,47 17 OUT I/O SDRAM10/ PCI_STOP# 18 I/O SDRAM [ 0:9] 20,21,28,29,31 ,32,34, 35,37,38 7 O PCICLK_F/ *FS1 I/O -3- Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 5.2 CPU, SDRAM, PCI Clock Outputs, continued SYMBOL PCICLK 0 / *FS2 PIN 8 I/O I/O FUNCTION Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. PCI clock during normal operation. Low skew (< 250ps) PCI clock outputs. PCICLK [ 1:4 ] 10,11,12,13 OUT 5.3 I2C Control Interface SYMBOL SDATA SDCLK PIN 23 24 I/O I/O IN 2 FUNCTION Serial data of I C 2-wire control interface Serial clock of I2C 2-wire control interface 5.4 Fixed Frequency Outputs SYMBOL REF0 / CPU3.3#_2.5 PIN 2 I/O I/O FUNCTION Internal 250kΩ pull-up. Latched input for CPU3.3#_2.5 at initial power up. Reference clock during normal operation. Latched high - Vddq2b = 2.5V Latched low - Vddq2b = 3.3V REF1 24MHz / *MODE 46 25 I/O I/O Internal 250kΩ pull-up. Internal 250kΩ pull-up. Latched input for MODE at initial power up. 24MHz output for super I/O during normal operation. 48MHz / *FS0 26 I/O Internal 250kΩ pull-up. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 48MHz output for USB during normal operation. -4- Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 5.5 Power Pins SYMBOL Vdd Vddq2 Vddq2b Vddq3 Vss PIN 1 42 48 6,14,19, 30, 36 3,9,16,22,27, 33,39,45 FUNCTION Power supply for REF0 crystal and core logic. Power supply for AGP1, REF1either 2.5V or 3.3V. Power supply for CPUCLK[0:3], either 2.5V or 3.3V Power supply for SDRAM, PCICLK and 48/24MHz outputs. Circuit Ground. 6.0 FREQUENCY SELECTION 6.1 W83194R-17 FREQUECY TABLE FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU,SDRAM (MHz) 60 66.8 68.5 75 75 83.3 90 100 PCI (MHz) 30 33.4 34.25 37.5 32 33.3 30 33.3 AGP (MHz) 60 66.8 68.5 75 64 66.6 60 66.6 REF (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 6.2 W83194R-17A FREQUECY TABLE FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU,SDRAM (MHz) 112 66.8 124 75 133.3 83.3 95.25 100.2 PCI (MHz) 37.3 33.4 31 37.5 33.3 33.3 31.75 33.4 AGP (MHz) 74.7 66.8 62 75 66.6 66.6 63.5 66.8 REF (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 -5- Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 7.0 CPU 3.3#_2.5 BUFFER SELECTION CPU 3.3#_2.5 ( Pin 2 ) Input Level 1 0 CPU Operate at VDD = 2.5V VDD = 3.3V -6- Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 8.0 FUNTION DESCRIPTION 8.1 POWER MANAGEMENT FUNCTIONS All clocks can be individually enabled or disabled via the 2-wire control interface. On power up, s external circuitry should allow 3 ms for the VCO’ to stabilize prior to enabling clock outputs to assure correct pulse widths. When MODE=0, pins 18 and 17 are inputs (PCI_STOP#), (CPU_STOP#), when MODE=1, these functions are not available. A particular clock could be enabled as both the 2-wire serial control interface and one of these pins indicate that it should be enabled. The W83194R-17/-17A may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. The CPU and PCI clocks transform between running and stop by waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CPU_STOP# 0 0 1 1 PCI_STOP# 0 1 0 1 CPU & AGP LOW LOW RUNNING RUNNING PCI LOW RUNNING LOW RUNNING OTHER CLKs RUNNING RUNNING RUNNING RUNNING XTAL & VCOs RUNNING RUNNING RUNNING RUNNING 8.2 2-WIRE I2C CONTROL INTERFACE The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the s W83194R-17/-17A initializes with default register settings, and then it’ optional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address and [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: -7- Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY Bytes sequence order for I2C controller : Clock Address A(6:0) & R/W Ack 8 bits dummy Command code Ack 8 bits dummy Byte count Ack Byte0,1,2... until Stop Set R/W to 1 when read back the data sequence is as follows : Clock Address A(6:0) & R/W Ack Byte 0 Ack Byte 1 Ack Byte2, 3, 4... until Stop 8.3 SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. 8.3.1 Register 0: CPU Frequency Select Register Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description 0 = ¡Ó1.5% Spread Spectrum Modulation 1 = ¡Ó0.5% Spread Spectrum Modulation SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit 6:4 0 = Spread Spectrum center spread type 1 = Spread Spectrum down spread type 0 = Normal 1 = Spread Spectrum enabled 0 = Running 1 = Tristate all outputs -8- Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY W83194R-17 Frequency table selection by software via I2C SSEL2 0 0 0 0 1 1 1 1 SSEL1 0 0 1 1 0 0 1 1 SSEL0 0 1 0 1 0 1 0 1 CPU,SDRAM (MHz) 60 66.8 68.5 75 75 83.3 90 100 PCI (MHz) 30 33.4 34.25 37.5 32 33.3 30 33.3 AGP (MHz) 60 66.8 68.5 75 64 66.6 60 66.6 REF (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 W83194R-17A Frequency table selection by software via I2C SSEL2 0 0 0 0 1 1 1 1 SSEL1 0 0 1 1 0 0 1 1 SSEL0 0 1 0 1 0 1 0 1 CPU,SDRAM (MHz) 112 66.8 124 75 133.3 83.3 95.25 100.2 PCI (MHz) 37.3 33.4 31 37.5 33.3 33.3 31.75 33.4 AGP (MHz) 74.7 66.8 62 75 66.6 66.6 63.4 66.8 REF (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 FUNCTION TABLE Function Description Tri-State Normal CPU Hi-Z see table PCI Hi-Z see table Outputs SDRAM Hi-Z CPU REF Hi-Z 14.318 IOAPIC Hi-Z 14.318 -9- Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 8.3.2 Register 1 : CPU , 48/24 MHz Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 40 41 43 44 Reserved Reserved Reserved Reserved CPUCLK3 (Active / Inactive) CPUCLK2 (Active / Inactive) CPUCLK1 (Active / Inactive) CPUCLK0 (Active / Inactive) Description 8.3.3 Register 2: PCI Clock Register(1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp x 1 1 1 1 1 1 1 Pin 7 15 13 12 11 10 8 Reserved PCICLK_F (Active / Inactive) AGP0 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLk1 (Active / Inactive) PCICLK0 (Active / Inactive) Description 8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 28 29 31 32 34 35 37 38 SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive) Description - 10 - Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp x x x x 1 1 1 1 Pin 17 18 20 21 Reserved Reserved Reserved Reserved SDRAM11 (Active / Inactive) SDRAM10 (Active / Inactive) SDRAM9 (Active / Inactive) SDRAM8 (Active / Inactive) Description 8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp x x x 1 x x 1 1 Pin 47 46 2 Reserved Reserved Reserved AGP1 (Active / Inactive) Reserved Reserved REF1 (Active / Inactive) REF0 (Active / Inactive) Description 8.3.7 Register 6: Reserved Register Bit 7 6 5 4 3 2 1 0 @PowerUp x x x x x x x x Pin Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description - 11 - Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 9.0 SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Vdd , VIN TSTG TB TA Parameter Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature Rating - 0.5 V to + 7.0 V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C 9.2 AC CHARACTERISTICS Vdd = Vddq2= Vddq3 = 3.3V ± 5 %, Vddq2b = 2.375V~2.9V , TA = 0° C to +70° C Parameter Output Duty Cycle CPU/SDRAM to PCI Offset Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) & Fall (2.0V ~0.4V) Time Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion VRBE 0.7 2.1 V tTLH tTHL Vover 0.7 1.5 V 0.4 1.6 ns 15 pF Load on CPU and PCI outputs 22 Ω at source of 8 inch PCB run to 15 pF load Ring Back must not enter this range. BWJ 500 KHz tJA 500 ps tOFF tSKEW tCCJ Symbol Min 45 1 Typ 50 Max 55 4 250 ¡Ó250 Units % ns ps ps Test Conditions Measured at 1.5V 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V 9.3 DC CHARACTERISTICS Publication Release Date: Sep. 1998 Revision 0.20 - 12 - W83194R-17/-17A PRELIMINARY Vdd = Vddq2= Vddq3 = 3.3V ± 5 %, Vddq2b = 2.375V~2.9V , TA = 0° C to +70° C Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 4 mA Output High Voltage IOH = 4mA Tri-State leakage Current Dynamic Supply Current for Vdd + Vddq3 Dynamic Supply Current for Vddq2 + Vddq2b CPU Stop Current for Vdd + Vddq3 CPU Stop Current for Vddq2 + Vddq2b PCI Stop Current for Vdd + Vddq3 IPD3 mA ICPUS2 mA Same as above ICPUS3 mA Same as above Idd2 mA Ioz Idd3 10 µA mA CPU = 66.6 MHz PCI = 33.3 Mhz with load Same as above VOH 2.4 Vdc All outputs using 3.3V power Symbol VIL VIH IIL IIH VOL 2.0 -66 5 0.4 Min Typ Max 0.8 Units Vdc Vdc µA µA Vdc All outputs Test Conditions - 13 - Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 9.4 BUFFER CHARACTERISTICS 9.4.1 TYPE 1 BUFFER FOR CPU (0:3) Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.4 1.6 27 Min -27 -27 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 2.0V Vout = 1.2 V Vout = 0.3 V 10 pF Load 20 pF Load 9.4.2 TYPE 2 BUFFER FOR IOAPIC Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.7 V and 1.7 V Rise/Fall Time Max Between 0.7 V and 1.7 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.4 1.8 28 -29 Min Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.4 V Vout = 2.7V Vout = 1.0 V Vout = 0.2 V 10 pF Load 20 pF Load - 14 - Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 9.4.3 TYPE 3 BUFFER FOR REF(0:1), 24MHZ, 48MHZ Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 1.0 4.0 29 Min -29 -23 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 3.135V Vout = 1.95 V Vout = 0.4 V 10 pF Load 20 pF Load 9.4.4 TYPE 4 BUFFER FOR REF0 and SDRAM(0:11) Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.5 1.3 53 -46 Min Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.65V Vout = 3.135V Vout = 1.65 V Vout = 0.4 V 20 pF Load 30 pF Load 9.4.5 TYPE 5 BUFFER FOR PCICLK(0:4,F) Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.5 2.0 30 38 Min -33 -33 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V 15 pF Load 30 pF Load - 15 - Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 10.0 POWER MANAGEMENT TIMING 10.1 CPU_STOP# Timing Diagram CPUCLK (Internal) PCICLK (Internal) PCICLK_F CPU_STOP# 1 2 1 2 CPUCLK[0:3] SDRAM For synchronous Chipset, CPU_STOP# pin is a synchronous “ ctive low ”input pin used to stop the a CPU clocks for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume c output with full pulse width. In this case, CPU “locks on latency“is less than 2 CPU clocks and “clocks off latency” is less then 2 CPU clocks. 10.2 PCI_STOP# Timing Diagram CPUCLK (Internal) PCICLK (Internal) PCICLK_F PCI_STOP# 1 2 1 2 PCICLK[0:4] a For synchronous Chipset, PCI_STOP# pin is a synchronous “ ctive low”input pin used to stop the PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output c c with full pulse width. In this case, PCI “locks on latency“is less than 1 PCI clocks and “locks off ” is less then 1 PCI clocks. latency - 16 - Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 11.0 OPERATION OF DUAL FUCTION PINS Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore, and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these pins are latched into their appropriate internal registers. Once the correct information are properly latched, these pins will change into output pins and will be pulled low by default. At the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency. 2.5V Vdd #2 REF0/CPU3.3#_2.5 #7 PCICLK_F/FS1 #8 PCICLK0/FS2 #25 24/MODE #26 48/FS0 Output tri-state Output pull-low Within 3ms Input All other clocks Output tri-state Output Output pull-low Each of these pins are a large pull-up resistor ( 250 kΩ @3.3V ) inside. The default state will be logic 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. Under these conditions, an external 10 kΩ resistor is recommended to be connected to Vdd if logic 1 is expected. Otherwise, the 10 kΩ resistor is connected to ground if a logic 0 is desired. The 10 kΩ resistor should be place before the serious terminating resistor. Note that these logic will only be latched at initial power on. If optional EMI reducing capacitor are needed, they should be placed as close to the series terminating resistor as possible and after the series terminating resistor. These capacitor has typical values ranging from 4.7pF to 22pF. - 17 - Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY Vdd 10kΩ Device Pin 10kΩ Series Terminating Resistor Clock Trace EMI Reducing Cap Optional Ground Ground Programming Header Vdd Pad 10k Ω Device Pin Ground Pad Series Terminating Resistor Clock Trace EMI Reducing Cap Optional Ground - 18 - Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 12.0 POWER SUPPLY SUGGESTION 1.A solid ground plane should be placed around the clock device. Ground connections should be tied to this main ground plane as short as possible. No cuts should be made in the ground plane around the device. g 2.C21,C22,C31,C36 are decoupling capacitors ( 0.1£ F surface mount, low ESR, ceramic capacitors.) They should be placed as possible as the Vdd pin and the ground via. g 3.C1 and C2 are supply filtering capacitors for low frequency power supply noise. A 22£ F (or 10£gF) tantalum capacitor is recommended. 4.Use of Ferrite Bead’s (FB) are recommended to further reduce the power supply noise. 5.The power supply race to the Vdd pins must be thick enough so that voltage drops across the trace resistance is negligible. Vdd (3.3V) C1 FB1 Vdd Plane C31 Vdd2 Plane C21 FB2 Vdd2 (3.3Vor2.5V) C2 C32 C33 C34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 C22 C36 C35 - 19 - Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 13.0 ORDERING INFORMATION Part Number W83194R-17/-17A Package Type 48 PIN SSOP Production Flow Commercial, 0°C to +70°C 14.0 HOW TO READ THE TOP MARKING W83194R-17 28051234 814GBB W 83194R-17A 28051234 814GBB 1st line: Winbond logo and the type number: W83194R-17/-17A 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR BB: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 20 - Publication Release Date: Sep. 1998 Revision 0.20 W83194R-17/-17A PRELIMINARY 15.0 PACKAGE DRAWING AND DIMENSIONS Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. Publication Release Date: Sep. 1998 Revision 0.20 - 21 -