W83194R-67B

W83194R-67B 100MHZ 3-DIMM CLOCK FOR VIA MVP4 1.0 GENERAL DESCRIPTION The W83194R-67B is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor such as Intel Pentium , AMD and Cyrix. W83194R-67B provides sixteen CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-67B also provides 13 SDRAM clocks controlled by the none-delay buffer_in pin. The W83194R-67B accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable stopping individual 2 clock outputs and frequency selection through I C interface. The device meets the Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up. High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES • • • • • Supports Pentium™ , AMD, Cyrix CPU with I C. 4 CPU clocks (one free-running CPU clock) 13 SDRAM clocks for 3 DIMs 6 PCI synchronous clocks Optional single or mixed supply: (Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 = 3.3V, VddL1 = VdqL2 = 2.5V) < 250ps skew among CPU and SDRAM clocks < 4ns propagation delay SDRAM from buffer input Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns. Smooth frequency switch with selections from 60 MHz to 124 MHz CPU 2 2 I C 2-Wire serial interface and I C read back 0~0.5% down type or ±0.25% or ±0.5% spread spectrum function to reduce EMI Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) 2ms power up clock stable time MODE pin for power Management One 48 MHz for USB & one 24 MHz for super I/O Packaged in 48-pin SSOP 2 • • • • • • • • • • • -1- Publication Release Date: Dec. 1999 Revision 0.50 W83194R-67B P RELIMINARY 3.0 BLOCK DIAGRAM 48MHz 1/2 24MHz PLL2 ~ Xin Xout BUFFER IN XTAL OSC REF(0:1) 2 CPUCLK_F PLL1 Spread Spectrum FS(0:3)* MODE* 4 STOP 3 STOP 12 4 PCI Clock Divider STOP 5 PCICLK_F PCICLK(0:4) CPUCLK(0:2) SDRAM_F LATCH SDRAM(0:11) ~ POR *CPU_STOP# *PCI_STOP# Control Logic Config. Reg. SDATA* SDCLK* 4.0 PIN CONFIGURATION Vddq1 * PCI_STOP#/REF0 Vss Xin Xout Vddq2 PCICLK_F/ *MODE PCICLK0/ *FS3 Vss PCICLK1 PCICLK2 PCICLK3 PCICLK4 Vddq2 BUFFER IN Vss SDRAM11 SDRAM10 Vddq3 SDRAM 9 SDRAM 8 Vss *SDATA *SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/ *FS2 VddL1 CPUCLK_F CPUCLK0 Vss CPUCLK1 CPUCLK2 *CPU_STOP# Vss SDRAM_F SDRAM 0 SDRAM 1 Vddq3 SDRAM 2 SDRAM 3 Vss SDRAM 4 SDRAM 5 Vddq3 SDRAM 6 SDRAM 7 Vddq4 48MHz/ *FS0 24MHz/ *FS1 -2- Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 5.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250kΩ pull-up 5 .1 Crystal I/O SYMBOL PIN I/O FUNCTION Xin Xout 4 5 IN OUT Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. 5 .2 CPU, SDRAM, PCI, IOAPIC Clock Outputs SYMBOL PIN I/O FUNCTION CPUCLK_F CPUCLK[0:2] 46 45,43,42 OUT OUT Free running CPU clock. Not affected by CPU_STOP# Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. Powered by VddL2. Low if CPU_STOP# is low. This asynchronous input halts CPUCLK[0:2] and SDRAM(0:11) at logic level when driven low. Free running SDRAM clock. Not affected by CPU_STOP# SDRAM clock outputs. Fanout buffer outputs from BUFFER IN pin.(Controlled by chipset) Free running PCI clock during normal operation. Latched Input. Mode=1, Pin 2 is REF0; Mode=0, Pin2 is PCI_STOP# *CPU_STOP# SDRAM_F SDRAM [ 0:11] 41 39 17,18,20,21,28 ,29,31,32,34, 35,37,38 7 IN OUT OUT PCICLK_F/ *MODE PCICLK0/*FS3 I/O 8 I/O Low skew (< 250ps) PCI clock outputs. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. PCICLK [ 1:4 ] BUFFER IN 10,11,12,13 15 OUT IN Low skew (< 250ps) PCI clock outputs. Synchronous to CPU clocks with 1/-4ns skew(CPU early). Inputs to fanout for SDRAM outputs. -3- Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 5 .3 I 2C Control Interface SYMBOL PIN I/O FUNCTION *SDATA *SDCLK 23 24 I/O IN Serial data of I C 2-wire control interface with internal pull-up resistor. Serial clock of I C 2-wire control interface with internal pull-up resistor. 2 2 5 .4 Fixed Frequency Outputs SYMBOL PIN I/O FUNCTION REF0 / *PCI_STOP# 2 I/O 14.318MHz reference clock. This REF output is the stronger buffer for ISA bus loads. Halt PCICLK(0:4) clocks at logic 0 level, when input low (In mobile mode. MODE=0) REF1 / *FS2 48 I/O 14.318MHz reference clock. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 24MHz / *FS1 25 I/O 24MHz output clock. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 48MHz / *FS0 26 I/O 48MHz output for USB during normal operation. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 5 .5 Power Pins SYMBOL PIN FUNCTION Vddq1 VddL1 Vddq2 Vddq3 Vddq4 Vss 1 47 6, 14 19, 30, 36 27 Power supply for Ref [0:1] , Xin and Xout crystal. Power supply for CPU clock outputs, either 2.5V or 3.3V. Power supply for PCICLK_F, PCICLK[1:4], 3.3V. Power supply for SDRAM_F,SDRAM[0:11], and PLL core, nominal 3.3V. Power for 24 & 48MHz output buffers and PLL core. 3,9,16,22,33,40,44 Circuit Ground. -4- Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 6.0 FREQUENCY SELECTION FS3 FS2 FS1 FS0 CPU,SDRAM(MHz) PCI(MHz) REF,IOAPIC (MHz) 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 1 0 1 60 66.8 70 90 9 7.0 30(CPU/2) 33.4(CPU/2) 35(CPU/2) 30(CPU/3) 32.33(CPU/3) 14.318 14.318 14.318 14.318 14.318 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 83.3 95.25 100.2 75 80 83.3 105 110 115 124 133 27.77(CPU/3) 31.75(CPU/3) 33.3(CPU/3) 37.5(CPU/2) 40(CPU/2) 41.65(CPU/2) 35(CPU/3) 36.67(CPU/3) 38.33(CPU/3) 31(CPU/4) 33.3(CPU/4) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 7.0 MODE PIN -POWER MANAGEMENT INPUT CONTROL M ODE, Pin7 (Latched Input) PIN 2 0 1 PCI_STOP# (Input) REF0 (Output) -5- Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 8.0 FUNCTION DESCRIPTION 8.1 POWER MANAGEMENT FUNCTIONS All clocks can be individually enabled or disabled via the 2-wire control interface. On power up, external circuitry should allow 3 ms for the VCO? to stabilize prior to enabling clock outputs to assure correct pulse widths. When MODE=0, pins 15 and 46 are inputs (PCI_STOP#), (CPU_STOP#), when MODE=1, these functions are not available. A particular clock could be enabled as both the 2-wire serial control interface and one of these pins indicate that it should be enable. The W83194R-67B may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. The CPU and PCI clocks transform between running and stop by waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CPU_STOP# PCI_STOP# CPUCLK 0:2, SDRAM 0:11 PCI SDRAM_F, CPU_F,PCI_ F OTHER CLKs 0 0 1 1 0 1 0 1 LOW LOW RUNNING RUNNING LOW RUNNING LOW RUNNING RUNNING RUNNING RUNNING RUNNING RUNNING RUNNING RUNNING RUNNING 8 .2 2-W IRE I 2C C O N T R O L I N T E R F A C E The clock generator is a slave I C component which can be read back? The data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2wire control interface allows each clock output individually enabled or disabled. On power up, the W83194R-67B initializes with default register settings, and then it is optional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. 2 Controller can start to write to internal I C registers after the string of data. The sequence order is as follows: Publication Release Date: Dec.. 1999 Revision 0.50 2 -6- W83194R-67B P RELIMINARY Bytes sequence order for I C controller : Clock Address A(6:0) & R/W 2 Ack 8 bits dummy Command code Ack 8 bits dummy Byte count Ack Byte0,1,2... until Stop Set R/W to 1 when read back the data sequence is as follows : Clock Address A(6:0) & R/W Ack Byte 0 Ack Byte 1 Ack Byte2, 3, 4... until Stop 8.3 SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the default state at true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. 8 .3.1 Register 0: CPU Frequency Select Register (default = 0) B it @PowerUp Pin Description 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 - 0 = ±0.25% Center type Spread Spectrum Modulation 1 = ±0.5% Center type Spread Spectrum Modulation SSEL2 (for frequency table selection by software via I C) SSEL1 (for frequency table selection by software via I C) SSEL0 (for frequency table selection by software via I C) 0 = Selection by hardware 1 = Selection by software I C - Bit 2, 6:4 SSEL3 (for frequency table selection by software via I C) 0 = Normal 1 = Spread Spectrum enabled 0 = Running 1 = Tristate all outputs 2 2 2 2 2 -7- Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY F requency table by I2C SSEL3 SSEL2 SSEL1 SSEL0 CPU,SDRA M(MHz) PCI(MHz) REF,IOAPIC (MHz) 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 1 0 1 60 66.8 70 90 9 7.0 30(CPU/2) 33.4(CPU/2) 35(CPU/2) 30(CPU/3) 32.33(CPU/3) 14.318 14.318 14.318 14.318 14.318 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 80 83.3 95.25 100.2 75 80 83.3 105 110 115 124 133 26.67(CPU/3) 27.77(CPU/3) 31.75(CPU/3) 33.3(CPU/3) 37.5(CPU/2) 40(CPU/2) 41.65(CPU/2) 35(CPU/3) 36.67(CPU/3) 38.33(CPU/3) 31(CPU/4) 33.3(CPU/4) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 8 .3.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive) B it @PowerUp Pin Description 7 6 x 1 - Latched FS2# 0 = 0 .5% down type spread, overrides Byte0 -bit7. 1= Center type spread. 5 4 3 2 1 0 1 1 1 1 1 1 42 43 45 46 Reserved Reserved CPUCLK2 (Active / Inactive) CPUCLK1 (Active / Inactive) CPUCLK0 (Active / Inactive) CPUCLK_F (Active / Inactive) -8- Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 8 .3.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive) B it @PowerUp Pin Description 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 7 13 12 11 10 8 Reserved PCICLK_F (Active / Inactive) Reserved PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLk1 (Active / Inactive) PCICLK0 (Active / Inactive) 8 .3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive) B it @PowerUp Pin Description 7 6 5 4 3 2 1 0 1 x 1 1 1 1 1 1 26 25 39 21,20,18,17 32,31,29,28 38,37,35,34 Reserved Latched FS0# 48MHz (Active / Inactive) 24MHz (Active / Inactive) SDRAM_F(Active / Inactive) SDRAM(8:11) (Active / Inactive) SDRAM(4:7) (Active / Inactive) SDRAM(0:3) (Active / Inactive) 8 .3.5 Register 4: Reserved Register (1 = Active, 0 = Inactive) B it @PowerUp Pin Description 7 6 5 4 3 2 1 0 1 1 1 1 x 1 x 1 - Reserved Reserved Reserved Reserved Latched FS1# Reserved Latched FS3# Reserved -9- Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 8 .3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive) B it @PowerUp Pin Description 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 48 2 Reserved Reserved Reserved Reserved Reserved Reserved REF1 (Active / Inactive) REF0 (Active / Inactive) 8 .3.7 Register 6: Winbond Chip ID Register (Read Only) B it @PowerUp Pin Description 7 6 5 4 3 2 1 0 NOTE: 0 1 0 1 1 0 0 0 - Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID 1.Inactive means outputs are held LOW and are disabled from switching. 2.Latched Frequency Selects(FS#) will be inverted logic load of the input frequency select pin conditions. - 10 - Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 9.0 SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Parameter Rating Vdd , VIN TSTG TB TA Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature - 0.5 V to + 7.0 V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C 9.2 AC CHARACTERISTICS Vddq1=Vddq2 = Vddq3 = Vddq4 =3.3V , VddL1 =VddL2= 2.5V , TA = 0° C to +70° C P arameter Symbol Min Typ Max Units Test Conditions Output Duty Cycle CPU/SDRAM to PCI Offset Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) & Fall (2.0V ~0.4V) Time Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion VRBE tTLH tTHL Vover BWJ tJA tOFF tSKEW tCCJ 45 1 50 55 4 250 ±250 500 500 % ns ps ps ps KHz ns Measured at 1.5V 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V 0.4 1.6 15 pF Load on CPU and PCI outputs 22 Ω at source of 8 inch PCB run to 15 pF load Ring Back must not enter this range. 1.5 2.1 V V - 11 - Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 9.3 DC CHARACTERISTICS Vddq1=Vddq2 = Vddq3 = Vddq4 =3.3V, VddL1 =VddL2= 2.5V , TA = 0° C to +70° C P arameter Symbol Min Typ Max Units Test Conditions Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 4 mA Output High Voltage IOH = 4mA Tri-State leakage Current Dynamic Supply Current for Vdd + Vddq3 Dynamic Supply Current for Vddq2 + Vddq2b CPU Stop Current for Vdd + Vddq3 CPU Stop Current for Vddq2 + Vddq2b PCI Stop Current for Vdd + Vddq3 VIL VIH IIL IIH VOL 2.4 2.0 0.8 Vdc Vdc µA µA Vdc All outputs -66 5 0.4 VOH Ioz Idd3 Idd2 ICPUS3 ICPUS2 IPD3 Vdc 10 µA mA mA mA mA mA All outputs using 3.3V power CPU = 66.6 MHz PCI = 33.3 Mhz with load Same as above Same as above Same as above - 12 - Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 9 .4 BUFFER CHARACTERISTICS 9 .4.1 TYPE 1 BUFFER FOR CPU CLOCK P arameter Symbol Min Typ Max Units Test Conditions Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) -27 -27 mA mA mA 27 mA ns 1.6 ns Vout = 1.0 V Vout = 2.0V Vout = 1.2 V Vout = 0.3 V 10pF Load 20pF Load 0.4 9 .4.2 TYPE 3 BUFFER FOR REF[0:1], 24MHZ, 48MHZ P arameter Symbol Min Typ Max Units Test Conditions Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) -29 -23 29 mA mA mA mA Vout = 1.0 V Vout = 3.135V Vout = 1.95 V Vout = 0.4 V 10pF Load 20pF Load 1.0 4.0 ns ns 9 .4.3 TYPE 4 BUFFER FOR SDRAM (F,0:11) P arameter Symbol Min Typ Max Units Test Conditions Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.5 1.3 53 -46 mA mA mA mA ns ns Vout = 1.65 V Vout = 3.135 V Vout = 1.65 V Vout = 0.4 V 20pF Load 30pF Load - 13 - Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 9 .4.4 TYPE 5 BUFFER FOR PCICLK(0:4,F) P arameter Symbol Min Typ Max Units Test Conditions Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) -33 -33 30 38 0.5 2.0 mA mA mA mA ns ns Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V 15pF Load 30pF Load - 14 - Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 10.0 POWER MANAGEMENT TIMING 10.1 CPU_STOP# Timing Diagram CPUCLK (Internal) PCICLK (Internal) PCICLK_F CPU_STOP# 1 2 3 4 1 2 3 4 CPUCLK[0:3] SDRAM For synchronous Chipset, CPU_STOP# pin is an asynchronous “ active low ” input pin used to stop the CPU clocks for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output with full pulse width. In this case, CPU ?locks on latency“ is less than 4 CPU clocks and ?locks off latency” is less then 4 CPU clocks. 10.2 PCI_STOP# Timing Diagram C PUCLK (Internal) PCICLK (Internal) PCICLK_F PCI_STOP# 1 2 1 2 PCICLK[0:5] For synchronous Chipset, PCI_STOP# pin is an asynchronous ?ctive low” input pin used to stop the PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output with full pulse width. In this case, PCI ?locks on latency“ is less than 2 PCI clocks and ?locks off latency” is less then 2 PCI clocks. - 15 - Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 11.0 OPERATION OF DUAL FUCTION PINS Vdd 10kΩ Device Pin 10kΩ Series Terminating Resistor Clock Trace EMI Reducing Cap Optional Ground Ground Programming Header Vdd Pad 10kΩ Device Pin Ground Pad Series Terminating Resistor Clock Trace EMI Reducing Cap Optional Ground - 16 - Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 12.0 ORDERING INFORMATION P art Number Package Type Production Flow W83194R-67B 48 PIN SSOP Commercial, 0°C to +70°C 13.0 HOW TO READ THE TOP MARKING W83194R-67B 28051234 002GAB-10 1st line: Winbond logo and the type number: W83194R-67B 2nd line: Tracking code 2 8051234 2 : wafers manufactured in Winbond FAB 2 8 051234 : wafer production series lot number 3rd line: Tracking code 002 G A B 0 02 : packages made in '00, week 02 G : assembly house ID; A means ASE, S means SPIL, G means GR A B : IC revision A ll the trade marks of products and companies mentioned in this data sheet belong to their respective owners . - 17 - Publication Release Date: Dec.. 1999 Revision 0.50 W83194R-67B P RELIMINARY 14.0 PACKAGE DRAWING AND DIMENSIONS Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners . T hese products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 18 - Publication Release Date: Dec.. 1999 Revision 0.50