W83194R-KX

W83194R-KX 133MHZ 3-DIMM K7 CLOCK 1.0 GENERAL DESCRIPTION The W83194R-KX is a clock generator which provides all clocks required for AMD K7 system. W83194R-KX provides one differential pair CPU clock open drain outputs up to 143MHz which are externally selectable with smooth transitions. W83194R-KX also provides 6 PCI clocks and 13 SDRAM clocks controlled by the none-delay buffer_in pin. The W83194R-KX accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable stopping individual clock 2 outputs and frequency selection through I C interface. The device meets the Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up. High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads, when maintaining 50± 5% duty cycle. The fixed frequency outputs, such as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES • • • • • • • • • • • • • • • • Supports AMD K7 CPU with I C. One pair of differential CPU clocks One chipset clock 13 SDRAM clocks for 3 DIMMs 6 PCI synchronous clocks Optional single or mixed supply: (Vddq3=Vddq2 =3.3V) or (Vddq3 = 3.3V, Vddq2 = 2.5V) < 250ps skew among CPU clocks < 250ps skew among PCI clocks < 5ns propagation delay SDRAM from buffer input Skew from CPU(earlier) to PCI clock 1.5 to 4ns, center 2.6ns. Smooth frequency switch with selections from 66.8 MHz to 143 MHz CPU 2 2 I C 2-Wire serial interface and I C read back ± 0.25% or ± 0.5% spread spectrum function to reduce EMI Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) One 48 MHz for USB & one 24 MHz for super I/O 48-pin SSOP package 2 -1- Publication Release Date: Nov. 1999 Revision 0.35 W83194R-KX PRELIMINARY 3.0 BLOCK DIAGRAM 48MHz 1/2 24_48MHz PLL2 ~~ Xin Xout XTAL OSC REF0/CPU_STOP# REF1 CPUT_CS PD# PLL1 Spread Spectrum FS(0:3)* MODE* 4 LATCH STOP CPUT0 CPUC0 ~ POR 4 PCI Clock Divider PCICLK(0:5) 6 SDATA* SDCLK* BUFFER IN Config. Reg. SDRAM(0:12) 13 4.0 PIN CONFIGURATION -2- Publication Release Date: Nov. 1999 Revision 0.35 W83194R-KX PRELIMINARY Vddq3 CPU_STOP#/REF0 Vss Xin Xout Vddq3 PCICLK0/MODE* PCICLK1/FS1* Vss PCICLK2 PCICLK3 PCICLK4 PCICLK5 Vddq3 BUFFER IN Vss SDRAM11 SDRAM10 Vddq3 SDRAM 9 SDRAM 8 Vss SDATA* SDCLK* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS0* Vss CPUT_CS Vss CPUC0 CPUT0 VddQ2 PD# SDRAM12 Vss SDRAM 0 SDRAM 1 Vddq3 SDRAM 2 SDRAM 3 Vss SDRAM 4 SDRAM 5 Vddq3 SDRAM 6 SDRAM 7 Vddq3 48MHz/FS2* 24_48MHz/FS3* 5.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250kΩ pull-up 5.1 Crystal I/O SYMBOL Xin Xout PIN 4 5 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. 5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs SYMBOL CPUT_CS CPU_C0 CPU_T0 PIN 46 44 43 I/O OD FUNCTION CPU_C0 and CPU_T0 are the differential open drain CPU clocks for K7. CPUT_CS is the open drain pin for the chipset. It has the same phase relationship as CPU_T0. Publication Release Date: Nov. 1999 Revision 0.35 -3- W83194R-KX PRELIMINARY SDRAM [ 0:12] 17,18,20,21,28,2 9,31,32,34, 35,37,38,40 7 OUT SDRAM clock outputs. Fanout buffer outputs from BUFFER IN pin.(Controlled by chipset) They are disabled when PD# is set LOW. Free running PCI clock during normal operation. Latched Input. Mode=1, Pin 2 is REF0; Mode=0, Pin2 is CPU_STOP# Low skew (< 250ps) PCI clock outputs. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. Synchronous to CPU clocks with 1-48ns skew(CPU early). Inputs to fanout for SDRAM outputs. The all clocks will be stopped when this pin set to LOW . PCICLK0/ *MODE PCICLK1/*FS1 I/O 8 I/O PCICLK [ 2:5 ] BUFFER IN PD# 10,11,12,13 15 41 OUT IN IN -4- Publication Release Date: Nov. 1999 Revision 0.35 W83194R-KX PRELIMINARY 5.3 I2C Control Interface SYMBOL *SDATA *SDCLK PIN 23 24 I/O I/O IN 2 FUNCTION Serial data of I C 2-wire control interface with internal pull-up resistor. Serial clock of I C 2-wire control interface with internal pull-up resistor. 2 5.4 Fixed Frequency Outputs SYMBOL REF0 / CPU_STOP# PIN 2 I/O I/O FUNCTION 14.318MHz reference clock. This REF output is the stronger buffer for ISA bus loads. Halt CPU clocks at logic 0 level, when input low (In mobile mode. MODE=0) REF1 / *FS0 48 I/O 14.318MHz reference clock. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 24_48MHz / *FS3 25 I/O 24MHz output clock. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 48MHz / *FS2 26 I/O 48MHz output for USB during normal operation. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 5.5 Power Pins SYMBOL Vddq2 Vddq3 Vss PIN 42 FUNCTION Power supply for CPU clocks, 2.5V or 3.3V. 1,6,14,19,27,30,36 Power supply for PCI, 24_48MHz, SDRAM[0:12], and CPU PLL core, nominal 3.3V. 3,9,16,22,33,39,45, Circuit Ground. 47 -5- Publication Release Date: Nov. 1999 Revision 0.35 W83194R-KX PRELIMINARY 6.0 FREQUENCY SELECTION 6.1 H/W Setting Frequency Table FS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 FS2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU(MHz) 95 103 105 108 90 110 115 120 133.3 83 100.2 66.8 124 129 138 143 PCI(MHz) 31.7 34.3 35 36 30 36.7 38.3 30 33.3 33.3 33.3 33.4 31 32.3 34.5 35.8 7.0 MODE PIN -POWER MANAGEMENT INPUT CONTROL MODE, Pin7 (Latched Input) 0 1 PIN 2 CPU_STOP# (Input) REF0 (Output) -6- Publication Release Date: Nov. 1999 Revision 0.35 W83194R-KX PRELIMINARY 8.0 FUNTION DESCRIPTION 8.1 POWER MANAGEMENT FUNCTIONS All clocks can be individually enabled or disabled via the 2-wire control interface. On power up, external circuitry should allow 3 ms for the VCO to stabilize prior to enabling clock outputs to assure correct pulse widths. When MODE=0, pins 2 is inputs (CPU_STOP#), when MODE=1, these functions are not available. The W83194R-KXmay be disabled in the low state according to the PD# pin41 in order to reduce power consumption. All clocks are stopped in the Power Down state when PD# is set to LOW, but maintain a valid high period on transitions from running to stop. 8.2 2-WIRE I C CONTROL INTERFACE The clock generator is a slave I C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83194R-KX initializes with default register settings. Use of the 2-wire control interface is then optional. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a “Start” condition followed by 7-bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an “acknowledge“ (low) on the SDATA wire will be generated by the clock 2 chip. Controller can start to write to internal I C registers after the string of data. The sequence order is as follows: Bytes sequence order for I C controller : Clock Address A(6:0) & R/W 2 2 2 Ack 8 bits dummy Command code Ack 8 bits dummy Byte count Ack Byte0,1,2... until Stop Set R/W to 1 when “Read back”, the data sequence is as follows, address is [1101 0011] : Clock Address A(6:0) & R/W Ack Byte 0 Ack Byte 1 Ack Byte2, 3, 4... until Stop -7- Publication Release Date: Nov. 1999 Revision 0.35 W83194R-KX PRELIMINARY 8.3 SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the default state at true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the sequence described below (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. Frequency table by software via I2C SSEL3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 SSEL2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 SSEL1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 SSEL0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU(MHz) 95 103 105 108 90 110 115 120 133.3 83 100.2 66.8 124 129 138 143 PCI(MHz) 31.7 34.3 35 36 30 36.7 38.3 30 33.3 33.3 33.3 33.4 31 32.3 34.5 35.8 -8- Publication Release Date: Nov. 1999 Revision 0.35 W83194R-KX PRELIMINARY 8.3.1 Register 0: Frequency Select Register (default = 0) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Reserved SSEL2 (for frequency table selection by software via I C) SSEL1 (for frequency table selection by software via I C) SSEL0 (for frequency table selection by software via I C) 0 = Selection by hardware 1 = Selection by software I C - Bit 6:4, Bit2 SSEL3 (for frequency table selection by software via I C) Reserved Reserved 2 2 2 2 2 Description 8.3.2 Register 1 : CPU Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 @PowerUp 0 0 0 0 1 0 1 1 Pin 40 43 44 46 Reserved Reserved Reserved Reserved SDRAM12 (Active / Inactive) Reserved CPUT0 CPUC0 (Active / Inactive) CPUT_CS (Active / Inactive) Description 8.3.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 7 13 12 11 10 8 Description Reserved PCICLK0 (Active / Inactive) Reserved PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2(Active / Inactive) PCICLK1 (Active / Inactive) -9- Publication Release Date: Nov. 1999 Revision 0.35 W83194R-KX PRELIMINARY 8.3.4 Register 3: SDRAM, 24MHz, 48MHz Clock Register ( 1 = enable, 0 = Stopped ) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 1 1 0 1 1 1 Pin 26 25 21,20,18, 17 32,31,29, 28 38,37,35, 34 Description Reserved SEL24_48 (Select 24MHz or 48MHz for pin25) 48MHz (Active / Inactive) 24_48MHz (Active / Inactive) Reserved SDRAM(8:11) (Active / Inactive) SDRAM(4:7) (Active / Inactive) SDRAM(0:3) (Active / Inactive) 8.3.5 Register 4: Reserved Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @PowerUp X X X X 0 0 0 0 Pin Description Latched FS3# Latched FS2# Latched FS1# Latched FS0# Reserved Reserved 0 = ±0.75% Spread Spectrum Modulation 1 = ±0.5% Spread Spectrum Modulation 0 = Normal 1 = Spread Spectrum enabled 8.3.6 Register 5: Peripheral Control (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 1 1 Pin 46 2 Reserved Reserved Reserved Reserved Reserved Reserved REF1 (Active / Inactive) REF0 (Active / Inactive) Description - 10 - Publication Release Date: Nov. 1999 Revision 0.35 W83194R-KX PRELIMINARY 8.2.7 Register 6: Winbond Chip ID Register (Read Only) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 0 1 0 1 1 1 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description - 11 - Publication Release Date: Nov. 1999 Revision 0.35 W83194R-KX PRELIMINARY 13.0 ORDERING INFORMATION Part Number W83194R-KX Package Type 48 PIN SSOP Production Flow Commercial, 0°C to +70°C 14.0 HOW TO READ THE TOP MARKING W83194R-KX 28051234 814GAB 1st line: Winbond logo and the type number: W83194R-KX 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G A B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR A: Internal use ID B: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 12 - Publication Release Date: Nov. 1999 Revision 0.35 W83194R-KX PRELIMINARY 15.0 PACKAGE DRAWING AND DIMENSIONS Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 13 - Publication Release Date: Nov. 1999 Revision 0.35