W83195BG-118

Winbond Clock Generator W83195BR-118/W83195BG-118 For Intel 915/945 Chipsets Date: May/02/2006 Revision: 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS W83195BR-118 Datasheet Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS 1 2 n.a. 8,13 07/22/2004 11/24/2004 0.5 0.6 n.a. n.a. All of the versions before 0.50 are for internal use. Correction IC version, add register default value and correction some description and default value Add spread spectrum function control bit, and correction some description and default value Add Pb-free part number Refine the description and register value Change the part no from W83195BR119 to W83195BR-118 3 4 5 6 7 8 9 11,13 19 1-4,1012,14-16 All 01/05/2005 01/17/2005 3/25/2005 05/02/2006 0.7 0.71 0.8 0.81 n.a n.a n.a n.a. -I- Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS Tables of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION......................................................................................................... 1 PRODUCT FEATURES.............................................................................................................. 1 PIN CONFIGURATION .............................................................................................................. 2 BLOCK DIAGRAM...................................................................................................................... 3 PIN DESCRIPTION .................................................................................................................... 3 5.1 Crystal I/O .....................................................................................................................................4 5.2 CPU and PCIE, PCI, Clock Outputs ............................................................................................4 5.3 Fixed Frequency Outputs .............................................................................................................4 5.4 I2C Control Interface .....................................................................................................................5 5.5 Power Management Pins .............................................................................................................5 5.6 Power Pins....................................................................................................................................6 6. 7. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE................................................ 7 I2C CONTROL AND STATUS REGISTERS .............................................................................. 8 7.1 Register 0: Frequency Select Register (Default = 10h)...............................................................8 7.2 Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default: E2h) .................................8 7.3 Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) ...................................9 7.4 Register 3: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) ...................................9 7.5 Register 4: 24_48MHz, 48MHz, DOT, REF Control (1 = Enable, 0 = Stopped) (Default: FFh) 9 7.6 Register 5: Watchdog Control (Default: 02h).............................................................................10 7.7 Register 6: SRC, PCIE Control (1 = Enable, 0 = Stopped) (Default: FEh)...............................10 7.8 Register 7: Winbond Chip ID (Default: 22h) (Read Only) .........................................................11 7.9 Register 8: M/N Program (Default: 90h) ....................................................................................11 7.10 Register 9: M/N Program Register (Default: BBh).....................................................................11 7.11 Register 10: Reserved (Default: 3Bh) ........................................................................................12 7.12 Register 11: Spread Spectrum Programming (Default: 0Eh)....................................................12 7.13 Register 12: Divisor Control (Default: 08h) ................................................................................12 7.14 Register 13: Step-less Enable Control (Default: 0Ah)...............................................................13 7.15 Register 14: Control (Default: 10h) ............................................................................................14 7.16 Register 15: SST Control (Default: ECh) ...................................................................................14 7.17 Register 16: Skew Control (Default: E4h)..................................................................................15 7.18 Register 17: Slew rate Control (Default: 00h) ............................................................................15 7.19 Register 18: Reserved (Default: 00h) ........................................................................................15 7.20 Register 19: Skew Control (Default: DAh) .................................................................................15 7.21 Register 20: Watch dog timer (Default: 88h) .............................................................................16 - II - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.22 Register 21: Asynchronous Control (Default: 4Bh) ...................................................................16 8. ACCESS INTERFACE ............................................................................................................. 17 8.1 Block Write protocol....................................................................................................................17 8.2 Block Read protocol....................................................................................................................17 8.3 Byte Write protocol......................................................................................................................17 8.4 Byte Read protocol .....................................................................................................................17 9. SPECIFICATIONS.................................................................................................................... 18 9.1 ABSOLUTE MAXIMUM RATINGS............................................................................................18 9.2 General Operating Characteristics.............................................................................................18 9.3 Skew Group timing clock............................................................................................................19 9.4 CPU 0.7V Electrical Characteristics...........................................................................................19 9.5 SRC 0.7V Electrical Characteristics...........................................................................................19 9.6 PCIE 0.7V Electrical Characteristics..........................................................................................20 9.7 PCI Electrical Characteristics .....................................................................................................20 9.8 24M, 48M Electrical Characteristics...........................................................................................20 9.9 REF Electrical Characteristics....................................................................................................21 9.10 DOT 0.7V Electrical Characteristics...........................................................................................21 10. 11. 12. ORDERING INFORMATION .................................................................................................... 22 HOW TO READ THE TOP MARKING ..................................................................................... 22 PACKAGE DRAWING AND DIMENSIONS ............................................................................. 23 - III - Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 1. GENERAL DESCRIPTION The W83195BR-118 is a Clock Synthesizer for Intel P4 processors and Intel Grandsdale chipsets. W83195BR-118 provides all clocks required for high-speed microprocessor and provides step-less frequency programming, 32 different frequencies of CPU, PCI, PCI-Express clocks setting. Simultaneously W83195BR-118 supports SRC 100MHz for SATA and DOT 96MHz clock outputs for integrated graphic chipsets. All clocks are externally selectable with smooth transitions. The W83195BR-118 programs the registers to enable or disable each clock outputs through I2C serial bus interface and provides -0.5% down type spread spectrum or programmable spread spectrum scale to reduce EMI. The W83195BR-118 also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83195BR-118 is driven with a 14.318 MHz reference crystal and runs on a 3.3V supply. 2. PRODUCT FEATURES • • • • • • • • • • • • • • • • 2 pair 0.7 V current mode Differential clock outputs for CPU 1 pair 0.7V current mode Differential 100 MHz clock outputs for SRC. 1 pair 0.7V current mode Differential 96MHz clock outputs for DOT. 5 pair 0.7V current mode Differential clock outputs for PCI-Express 6 PCI clock outputs for PCI 3 PCI clock free running outputs for PCI 1 24_48Mhz clock output for super I/O. 1 48 MHz clock output for USB. 2 14.318MHz REF clock outputs. Step-less frequency programming I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% down type spread spectrum in H/W and software select mode Programmable spread spectrum scale to reduce EMI in M/N mode Programmable registers to enable/stop each output. Programmable clock outputs to control slew rate and skew. Watch Dog Timer and RESET# output pins • 56 pin SSOP package -1- Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 3. PIN CONFIGURATION GND 1 PCI3 2 PCI4 3 PCI5 4 GND 5 VDDP 6 PCI_F0 7 & FS0/PCI_F1 8 * FS1/PCI_F2 9 VDD48 10 & SEL24_48#/24_48MHz 11 48MHz 12 GND 13 DOTT 14 DOTC 15 VTT_PWRGD#/PD 16 PCIET0 17 PCIEC0 18 VDDPE 19 GND 20 PCIET1 21 PCIEC1 22 PCIET2 23 PCIEC2 24 GND 25 SRCT 26 SRCC 27 VDDS 28 56 VDDP 55 PCI2 54 PCI1 53 PCI0 52 RESET# 51 REF0/& FS2 50 REF1 49 GND 48 XIN 47 XOUT 46 VDDR 45 *SCLK 44 *SDATA 43 CPUT0 42 CPUC0 41 VDDC 40 CPUT1 39 CPUC1 38 GND 37 IREF 36 GNDA 35 VDDA 34 VDDPE 33 PCIET4 32 PCIEC4 31 PCIET3 30 PCIEC3 29 GND #: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND -2- W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 4. BLOCK DIAGRAM 48M H z PLL2 D iv id e r 24_48M H z DO TT DOTC X IN XOUT XTAL OSC 2 2 R E F 0 :1 C P U T 0 :1 C P U C 0 :1 SRCT SRCC PLL1 S p re a d S p e c tru m 2 VCO C LK 5 M /N /R a t io ROM D iv id e r 5 3 P C IE T 0 : 4 P C IE C 0 : 4 P C I_ F 0 :2 F S (0 :2 ) VTT_PW R G D # &SEL24_48# L a tc h &POR 6 P C I 0 :5 PD C o n tr o l L o g ic & C o n f ig R e g is t e r IREF RESET# 475 *S D A T A *S C L K I2 C In te r f a c e 5. PIN DESCRIPTION BUFFER TYPE SYMBOL DESCRIPTION IN INtp120k INtd120k OUT OD I/OD # * & Input Latched input at power up, internal 120kΩ pull up. Latched input at power up, internal 120kΩ pull down. Output Open Drain Bi-directional Pin, Open Drain. Active Low Internal 120kΩ pull-up Internal 120 kΩ pull-down -3- Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 5.1 Crystal I/O PIN PIN NAME TYPE DESCRIPTION 48 47 XIN XOUT IN OUT Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). 5.2 CPU and PCIE, PCI, Clock Outputs PIN PIN NAME TYPE DESCRIPTION 43,42,40,39 CPUT [0:1] CPUC [0:1] 17,18,21,22 PCIET [0:4] ,23,24,31,3 PCIEC [0:4] 0,33,32 7 PCI_F0 8 PCI_F1 & FS0 9 PCI_F2 * OUT OUT Low skew (< 125ps) 0.7V Current mode differential clock outputs for host frequencies of CPU Low skew ( 1: Enable Watchdog Timer feature. 0: Disable Watchdog Timer feature. Read-back this bit => During timer count down the bit read back to 1. If count to zero, this bit read back to 0. R/W R/W 5 WD_TIMEOUT 0 Read Back only. Timeout Flag. This bit is Read Only. 1: Watchdog has ever started and counts to zero. 0: Watchdog is restarted and counting. R 4 3 2 1 0 SAF_FREQ [4] SAF_FREQ [3] SAF_FREQ [2] SAF_FREQ [1] SAF_FREQ [0] 0 0 0 1 0 These bits will be reloaded in Reg-0 to select frequency table. As the watchdog is timeout and EN_SAFE_FREQ=1. R/W 7.7 BIT Register 6: SRC, PCIE Control (1 = Enable, 0 = Stopped) (Default: FEh) NAME PWD DESCRIPTION TYPE 7 6 5 4 3 2 1 0 26,27 Reserved 33,32 31,30 23,24 21,22 17,18 Reserved 1 1 1 1 1 1 1 0 SRCT/C output control Reserved PCIET4/C4 output control PCIET3/C3 output control PCIET2/C2 output control PCIET1/C1 output control PCIET0/C0 output control Reserved R/W R/W R/W R/W R/W R/W R/W R/W - 10 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.8 BIT Register 7: Winbond Chip ID (Default: 22h) (Read Only) NAME PWD DESCRIPTION TYPE 7 6 5 4 3 2 1 0 CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0] 0 0 1 0 0 0 1 0 Winbond Chip ID. W83195BR-118 Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. R R R R R R R R 7.9 BIT Register 8: M/N Program (Default: 90h) NAME PWD DESCRIPTION TYPE 7 6 5 4 3 2 1 0 N_DIV [8] N_DIV [9] M_DIV [5] M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] M_DIV [0] 1 0 0 1 0 0 0 0 Programmable N divisor value. Bit7~0 are defined in the Register R/W 9 Programmable N divisor value. Bit7~0 are defined in the Register R/W 9 Programmable M divisor value. R/W R/W R/W R/W R/W R/W 7.10 Register 9: M/N Program Register (Default: BBh) BIT NAME PWD DESCRIPTION TYPE 7 6 5 4 3 2 1 0 N_DIV [7] N_DIV [6] N_DIV [5] N_DIV [4] N_DIV [3] N_DIV [2] N_DIV [1] N_DIV [0] 1 0 1 1 1 0 1 1 R/W R/W R/W Programmable N divisor value bit 7 ~0. The bit 8 is defined in R/W Register 8. R/W R/W R/W R/W - 11 - Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.11 Register 10: Reserved (Default: 3Bh) BIT NAME PWD DESCRIPTION TYPE 7 SRC_SPSPEN 0 Enable SRC spread spectrum feature 1: Enable 0: Disable Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 1 1 1 0 1 1 R/W R/W R/W R/W R/W R/W R/W 7.12 Register 11: Spread Spectrum Programming (Default: 0Eh) BIT NAME PWD DESCRIPTION TYPE 7 6 5 4 3 2 1 0 SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0] 0 0 0 0 1 1 1 0 Spread Spectrum Up Counter bit 3 ~ bit 0. R/W R/W R/W R/W Spread Spectrum Down Counter bit 3 ~ bit 0 2’s complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 R/W R/W R/W R/W 7.13 Register 12: Divisor Control (Default: 08h) BIT NAME PWD DESCRIPTION TYPE 7 6 5 4 3 2 1 0 Reserved KVAL6 KVAL5 KVAL4 KVAL3 KVAL2 KVAL1 KVAL0 0 X X X X X X X Reserved Define the PCI divider ratio Table-2 integrate the all divider configuration Define the PCIE divider ratio Refer to Table-2 Define the CPU divider ratio Refer to Table-2 R/W R/W R/W R/W R/W R/W R/W R/W - 12 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS Table-2 CPU, PCIE, PCI divider ratio selection Table LSB MSB Bit2/ Bit4/ Bit6 0 1 0 Div12 Div20 PCI Bit5 1 Div16 Div24 0 Div3 Div8 PCIE Bit3 1 Div4 Div6 00 Div2 Div8 01 Div3 Div8 CPU Bit1, 0 10 Div4 Div8 11 Div6 Div8 7.14 Register 13: Step-less Enable Control (Default: 0Ah) BIT NAME PWD DESCRIPTION TYPE 7 EN_MN_PROG 0 0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS or desired frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg0 - bit 0). R/W 6 5 4 3 2 1 0 N Reserved Reserved IVAL IVAL IVAL IVAL 0 0 0 1 0 1 0 Programmable N divisor bit 10. Reserved Reserved Charge pump current selection R/W R/W R/W R/W R/W R/W R/W - 13 - Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.15 Register 14: Control (Default: 10h) BIT NAME PWD DESCRIPTION TYPE 7 DRI_CONT 0 CPUT / SRCT / PCIE_T / DOT_T output state in during POWER R/W DOWN assertion. 1: Driven (2*Iref), 0: Tristate (Floating) CPUT / SRCT / PCIE_T / DOT_T output state in during STOP Mode assertion. 1: Driven (6*Iref), 0: Tristate (Floating) Complementary parts always tri-state (floating) in power down or stop mode. Reserved R/W Spread Spectrum Programmable time, the resolution is 280ns. R/W Default period is 11.8us R/W R/W R/W R/W R/W 6 5 4 3 2 1 0 Reserved SPCNT [5] SPCNT [4] SPCNT [3] SPCNT [2] SPCNT [1] SPCNT [0] 0 0 1 0 0 0 0 7.16 Register 15: SST Control (Default: ECh) BIT NAME PWD DESCRIPTION TYPE 7 6 5 INV_CPU Reserved SPSP_TYPE 1 1 1 Invert the CPU phase, 1: Default, 0: Inverse Reserved Spread spectrum implementation method 1 : Pendulum type 0 : Original Reserved Reserved Reserved Reserved Reserved R/W R/W R/W 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved 0 1 1 0 0 R/W R/W R/W R/W R/W - 14 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.17 Register 16: Skew Control (Default: E4h) BIT NAME PWD DESCRIPTION TYPE 7 6 5 4 3 2 1 0 INV_PCIE INV_PCI CSKEW [2] CSKEW [1] CSKEW [0] PSKEW [2] PSKEW [1] PSKEW [0] 1 1 1 0 0 1 0 0 Invert the PCIE phase, 1: Default, 0: Inverse Invert the PCI phase, 1: Default, 0: Inverse CPU1 to CPU0 skew control, Skew resolution is 300ps The decision of skew direction is same as CSKEW setting CPU1 to PCI skew control, Skew resolution is 300ps The decision of skew direction is same as PSKEW [2:0] setting R/W R/W R/W R/W R/W R/W R/W R/W 7.18 Register 17: Slew rate Control (Default: 00h) BIT NAME PWD DESCRIPTION TYPE 7 6 5 4 3 2 1 0 Reserved INV_48MHz PCI_F0_S2 PCI_F0_S1 Reserved Reserved Reserved Reserved X 0 0 0 0 0 0 0 Reserved Invert the 48MHz phase, 0: In phase with 24_48MHz 1: 180 degrees out of phase PCI_F0 slew rate control 11 : Strong , 00 : Weak , Reserved Reserved Reserved Reserved 10/01 : Normal R/W R/W R/W R/W R/W R/W R/W R/W 7.19 Register 18: Reserved (Default: 00h) 7.20 Register 19: Skew Control (Default: DAh) BIT NAME PWD DESCRIPTION TYPE 7 6 5 4 3 2 1 0 Reserved Reserved PCIESKEW PCIESKEW PCIESKEW Reserved Reserved Reserved 1 1 0 1 1 0 1 0 Reserved Reserved R/W R/W R/W CPU1 to PCIE skew control Skew resolution is 300ps R/W The decision of skew direction is same as PCIESKEW R/W setting Reserved Reserved Reserved R/W R/W R/W Publication Release Date: May 2006 Revision 0.81 - 15 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.21 Register 20: Watch dog timer (Default: 88h) BIT NAME PWD DESCRIPTION TYPE 7 6 5 4 3 2 1 0 Reserved WD_TIME [6] WD_TIME [5] WD_TIME [4] WD_TIME [3] WD_TIME [2] WD_TIME [1] WD_TIME [0] 1 0 0 0 1 0 0 0 Reserved R/W Setting the down count depth (Failure decision). One bit R/W resolution represents 250ms. Default time depth is 8*250ms = R/W 2.0 second. If the watchdog timer is counting, this register will R/W return present down count value. R/W R/W R/W R/W 7.22 Register 21: Asynchronous Control (Default: 4Bh) BIT NAME PWD DESCRIPTION TYPE 7 6 5 4 3 2 1 0 Tri-state Reserved Reserved Reserved Reserved SRC_BASE3 FIX_ADDR FIX_ADDR 0 1 0 0 1 0 1 1 Tri-state all output if set 1 Reserved Reserved Reserved Reserved 1: Asynchronous PCIE / PCI always at 100MHz / 33MHz 0: PCIE / PCI frequency are follow Bit1, 0 setting Asynchronous PCIE / PCI frequency table selection FIX_ADDR => 00: 96 / 36MHz 01 : 96 / 32MHz 10: 128 / 38.4MHz 11 : Output from PLL1 R/W R/W R/W R/W R/W R/W R/W R/W - 16 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 8. ACCESS INTERFACE The W83195BR-118 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83195BR-118 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. The register number is increased by one if using byte data read/write protocol. Example: In block mode, byte number of program register is 1 In byte mode, byte number of program register is 2 (Byte number of block mode +1) Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8’h00 8.3 Byte Write protocol 8.4 Byte Read protocol - 17 - Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). PARAMETER RATING Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model) -0.5V to +4.6V - 0.5V to + 4.6V 3.135V to 3.465V 3.135V to 3.465V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C 2000V 9.2 General Operating Characteristics PARAMETER SYMBOL MIN MAX UNITS TEST CONDITIONS VDD= 3.3V ± 5 %, TA = 0°C to +70°C, Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance VIL VIH VOL VOH Idd Cin Cout Lin 2.4 350 5 6 7 2.0 0.4 0.8 Vdc Vdc Vdc Vdc mA pF pF nH CPU = 100 to 400 MHz PCI = 33.3 Mhz with load 10pF - 18 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 9.3 Skew Group timing clock PARAMETER MIN MAX UNITS TEST CONDITIONS VDD = 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF CPU pair to CPU pair Skew PCIE pair to PCIE pair Skew PCI to PCI Skew 48MHz to 48MHz Skew 125 125 500 1000 ps ps ps ps Measure Crossing point Measure Crossing point Measured at 1.5V Measured at 1.5V 9.4 CPU 0.7V Electrical Characteristics VDDC= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER MIN MAX UNITS TEST CONDITIONS Rise Time Fall Time Absolute Voltages crossing point 175 175 250 660 -150 700 700 550 850 100 ps ps mV mV mV ps % Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 55 9.5 SRC 0.7V Electrical Characteristics VDDS= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER MIN MAX UNITS TEST CONDITIONS Rise Time Fall Time Absolute Voltages crossing point 175 175 250 660 -150 700 700 550 850 100 ps ps mV mV mV ps % Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 55 - 19 - Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 9.6 PCIE 0.7V Electrical Characteristics VDDPE= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER MIN MAX UNITS TEST CONDITIONS Rise Time Fall Time Absolute Voltages crossing point 175 175 250 660 -150 700 700 550 850 100 ps ps mV mV mV ps % Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 55 9.7 PCI Electrical Characteristics PARAMETER MIN MAX UNITS TEST CONDITIONS VDDP= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 500 500 2000 2000 250 55 ps ps ps % mA mA mA mA Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V 9.8 24M, 48M Electrical Characteristics PARAMETER MIN MAX UNITS TEST CONDITIONS VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 500 500 2000 2000 500 55 ps ps ps % mA mA mA mA Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V - 20 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 9.9 REF Electrical Characteristics PARAMETER MIN MAX UNITS TEST CONDITIONS VDD= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 29 27 45 -29 -23 500 500 2000 2000 1000 55 ps ps ps % mA mA mA mA Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V 9.10 DOT 0.7V Electrical Characteristics VDD= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER MIN MAX UNITS TEST CONDITIONS Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 175 175 250 660 -150 700 700 550 850 250 ps ps mV mV mV ps % Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform 45 55 - 21 - Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 10. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83195BR-118 W83195BG-118 56 PIN SSOP 56 PIN SSOP Commercial, 0°C to +70°C Commercial, 0°C to +70°C 11. HOW TO READ THE TOP MARKING W83195BR-118 28051234 520GCASA W83195BG-118 28051234 520GCASA Left line: Winbond logo 1st line: the part number: W83195BR-118, the Pb-free part number W83195BG-118 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 520 G C A SA 520: packages made in '2005, week 20 G: assembly house ID; O means OSE, G means GR C: Internal use code A: IC revision SA: Internal use code All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. - 22 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 12. PACKAGE DRAWING AND DIMENSIONS 56 PIN SSOP-300mil .035 .045 .045 .055 0.40/0.50 DIA SYMBOL DIMENSION IN MM DIMENSION IN INCH E END VIEW HE A A1 A2 b c D HE E e L L1 Y θ MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0.13 0.25 0.005 0.720 0.400 0.292 0.020 0.024 18.2 18.42 18.54 9 10.16 10.31 10.41 7.42 0.51 0.61 7.52 0.64 0.81 1.40 7.59 0.76 1.02 0.08 8 MAX. 0.110 0.016 0.092 0.0135 0.010 TOP VIEW SEE DETAIL "A" c D θ A2 A Y SEATING PLANE e SIDE VIEW A1 0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 8 b PARTING LINE c 0 0 θ L L1 DETAIL"A" - 23 - Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. - 24 -