W83195CG-416

Winbond Clock Generator W83195WG-416 W83195CG-416 For ATI K8 Chipset Date: Feb/27/2006 Revision: 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR W83195WG-416/W83195CG-416 Data Sheet Revision History Pages 1 2 3 4 5 6 7 8 9 10 n.a. 13 Dates 01/20/2006 02/27/2006 Version 0.5 0.6 Web Version n.a. n.a. Main Contents All of the versions before 0.50 are for internal use. Add HTT66 asynchronous mode. Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. I Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR TABLE OF CONTENT 1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 2 BLOCK DIAGRAM ...................................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 3 FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 5 I2C CONTROL AND STATUS REGISTERS ............................................................................... 6 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 8. Register 0: ( Default : 00h ) ......................................................................................................6 Register 1: ( Default : XXh) ......................................................................................................6 Register 2: ( Default : 03h ) ......................................................................................................7 Register 3: ( Default : 03h ) ......................................................................................................7 Register 4: ( Default : FEh) ......................................................................................................8 Register 5: ( Default : 02h ) ......................................................................................................8 Register 6: ( Default : FFh )......................................................................................................9 Register 7: Winbond Chip ID – Project Code Register ( Default : 06h )...............................10 Register 8: ( Default :D0h )..................................................................................................10 Register 9: ( Default : 7Ah )....................................................................................................10 Register 10: Reserved ( Default : 3Bh ).................................................................................11 Register 11: ( Default : 0Eh )..................................................................................................11 Register 12: ( Default : XXh ) .................................................................................................11 Register 13: ( Default : 3Fh )..................................................................................................12 Register 14: ( Default : D0h ) .................................................................................................12 Register 15: ( Default : 5Ch ) .................................................................................................12 Register 16: ( Default : 24h ) ..................................................................................................13 Register 17: Reserved ( Default : 07h ) .................................................................................13 Register 18: Reserved ( Default : 7Ah ).................................................................................13 Register 19: ( Default : 04h ) ..................................................................................................14 Register 20: ( Default : 88h ) ..................................................................................................14 Register 21: ( Default : ECh ).................................................................................................14 Table3: SRC & ATIG Frequency Selection Table..............................................................................16 ACCESS INTERFACE .............................................................................................................. 17 8.1 8.2 8.3 Block Write protocol ...............................................................................................................17 Block Read protocol ...............................................................................................................17 Byte Write protocol .................................................................................................................17 Publication Release Date: Feb 2006 Revision 0.6 II W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 8.4 9. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10. 11. 12. Byte Read protocol.................................................................................................................17 ABSOLUTE MAXIMUM RATINGS .......................................................................................18 General Operating Characteristics ........................................................................................18 Skew Group timing clock........................................................................................................18 CPU 0.7V Electrical Characteristics ......................................................................................19 SRC 0.7V Electrical Characteristics ......................................................................................19 ATIG 0.7V Electrical Characteristics......................................................................................19 PCI Electrical Characteristics.................................................................................................20 USB Electrical Characteristics ...............................................................................................20 REF Electrical Characteristics ...............................................................................................20 SPECIFICATIONS .................................................................................................................... 18 ORDERING INFORMATION..................................................................................................... 21 HOW TO READ THE TOP MARKING...................................................................................... 21 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 22 III Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 1. GENERAL DESCRIPTION The W83195WG-416/W83195CG-416 is a Clock Synthesizer for ATI K8 serial chipsets. W83195WG416/ W83195CG-416 provides all clocks required for the high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, PCI, and SRC clocks setting, all clocks are externally selectable with smooth transitions. The W83195WG-416/W83195CG-416 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides programmable S.S.T. scale to reduce EMI. The W83195WG-416/W83195CG-416 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. 2. PRODUCT FEATURES • • • • • • • • • • • • • 2 pair push-pull Differential clock outputs for CPU. 6 pair current-mode Differential clock outputs for SRC. 2 pair current-mode Differential clock outputs for ATIG programmable. 1 PCI clock output. 1 48 MHz clock output for USB. 3 14.318MHz REF clock outputs. 1 HTT 66MHz clock output. Smooth frequency switch with selections from 100 to 400MHz. Step-less frequency programming. I2C 2-wire serial interface and support byte read/write and block read/write. Programmable S.S.T. scale to reduce EMI in M/N mode. Programmable registers to enable/disable each output and select modes. Programmable clock outputs slew rate control and skew control. • 56 pin TSSOP/SSOP package. 1 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 3. PIN CONFIGURATION XIN XOUT VDD48 USB_48 GND NC SCLK SDATA & FSC & CLKREQA# & CLKREQB# SRCT7 SRCC7 VDDSRC GND SRCT6 SRCC6 SRCT5 SRCC5 GND VDDSRC SRCT4 SRCC4 SRCT3 SRCC3 GND ATIGT1 ATIGC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDREF GND & FSA/REF0 & FSB/REF1 REF2 VDDPCI PCICLK0 GND VDDHTT HTTCLK0 GND CPUCLK8T0 CPUCLK8C0 VDDCPU GND CPUCLK8T1 CPUCLK8C1 VDDA GNDA IREF GND VDDSRC SRCT0 SRCC0 VDDATI GND ATIGT0 ATIGC0 #: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND 4. BLOCK DIAGRAM 2 A TIG LO O P U SB LO O P C PU LO O P Spread Spectrum XIN XO U T XTA L O SC D ivider 2 ATIG T 0:1 A TIG C 0:1 D ivider & Sync 48M H z 3 R EF 0:2 3 3 V CO CLK C PU CLK8T 0:1 CPU C LK8C 0:1 SR C LO O P Spread Spectrum M /N /R atio ROM D ivider & Snyc 6 6 SRC T 0,3:7 SR C C 0,3:7 FS(A:C ) C R#_(A :B ) Latch & PO R H TTC LK0 PC I0 C ontrol Logic &C onfig R egister IREF 475 SD ATA SCLK I2C Interface 2 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 5. PIN DESCRIPTION PIN PIN NAME TYPE DESCRIPTION Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). Crystal input with internal loading capacitors (18pF) and feedback resistors. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 XIN XOUT VDD48 USB_48 GND VTT_PG#/PD SCLK SDATA & IN OUT PWR Power supply for USB_48 OUT 3.3V USB 48Mhz clock output. PWR Ground pin IN IN Notifies CK410 to sample latched input or power down mode Serial clock of I2C 2-wire control interface. I/O Serial data of I2C 2-wire control interface. IN IN IN FSC CPU frequency select Dynamic output control 0 = active, 1 = inactive Dynamic output control 0 = active, 1 = inactive FSC CLKREQA# CLKREQB# & & SRCT7 SRCC7 VDDSRC GND SRCT6 SRCC6 SRCT5 SRCC5 GND VDDSRC SRCT4 SRCC4 SRCT3 SRCC3 GND ATIGT1 ATIGC1 OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC PWR Power supply for SRC PWR Ground pin OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC PWR Ground pin PWR Power supply for SRC OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC PWR Ground pin OUT 0.7V current mode differential clock output for ATIG OUT 0.7V current mode differential clock output for ATIG Publication Release Date: Feb 2006 Revision 0.6 3 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 ATIGC0 ATIGT0 GND VDDATIG SRCC0 SRCT0 VDDSRC GND IREF GNDA VDDA CPUCLK8C1 CPUCLK8T1 GND VDDCPU CPUCLK8C0 CPUCLK8T0 GND HTTCLK0 VDDHTT GND PCICLK0 VDDPCI REF2 & & OUT 0.7V current mode differential clock output for ATIG OUT 0.7V current mode differential clock output for ATIG PWR Ground pin PWR Power supply for ATIG OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC PWR Power supply for SRC PWR Ground pin Deciding the reference current for the differential pairs. The pin OUT was connected to the precision resistor tied to ground to decide the appropriate current; 475 ohm is the standard value. PWR Ground pin for PLL core. PWR 3.3V power supply for PLL core. OUT 3.3V Push Pull differential clock output for AMD K8 OUT 3.3V Push Pull differential clock output for AMD K8 PWR Ground pin PWR Power supply for CPU OUT 3.3V Push Pull differential clock output for AMD K8 OUT 3.3V Push Pull differential clock output for AMD K8 PWR Ground pin OUT 3.3V HTT clock output. PWR Power supply for HTTCLK PWR Ground pin OUT 3.3V PCI clock output. PWR Power supply for PCI OUT 3.3V REF 14.318Mhz clock output. I/O FSB CPU frequency select/3.3V REF 14.318Mhz clock output. I/O FSA CPU frequency select/3.3V REF 14.318Mhz clock output. PWR Ground pin PWR Power supply for REF Publication Release Date: Feb 2006 Revision 0.6 FSB/REF1 FSA/REF0 GND VDDREF 4 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE This frequency table is used at power on latched FS [2:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3). If FS [2:0] no any external circuit to modify power on status the Gray shading is Hardware default frequency. BIT 7 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT 6 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIT 5 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT 4 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT 3 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHZ) 266.68 133.34 200.01 166.59 333.17 100.00 400.01 200.06 266.68 133.34 200.01 166.59 333.17 100.00 400.01 200.06 100.00 133.34 200.01 166.59 199.90 266.68 400.01 333.30 100.00 133.34 200.01 166.59 199.90 266.68 400.01 333.30 SRC (MHZ) 100.00 100.00 100.00 111.06 111.06 100.00 100.00 100.03 100.00 100.00 100.00 111.06 111.06 100.00 100.00 100.03 100.00 100.00 100.00 111.06 99.95 100.00 100.00 111.10 100.00 100.00 100.00 111.06 99.95 100.00 100.00 111.10 PCI (MHZ) 33.33 33.33 33.33 33.32 33.32 33.33 33.33 33.34 33.33 33.33 33.33 33.32 33.32 33.33 33.33 33.34 33.33 33.33 33.33 33.32 33.32 33.33 33.33 33.33 33.33 33.33 33.33 33.32 33.32 33.33 33.33 33.33 5 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 7. I2C CONTROL AND STATUS REGISTERS (The register No. is increased by 1 if use byte data read/write protocol) 7.1 BIT Register 0: ( Default : 00h ) AFFECTED PIN/ FUNCTION NAME(S) PWD AFFECTED PIN / FUNCTION DESCRIPTION TYPE 7 6 5 4 3 SSEL SSEL SSEL SSEL SSEL 0 0 0 0 0 Enable software table selection FS[4:0]. 0 = Hardware table setting (Jump mode). 1 = Software table setting through Bit7~3 . (Jumpless mode) Enable spread spectrum mode under clock output. Software frequency table selection through I2C R/W 2 EN_SSEL 0 R/W 1 SPSPEN 0 0 = Spread Spectrum mode disable 1 = Spread Spectrum mode enable After watchdog timeout 0 = Reload the hardware FS [4:0] latched R/W 0 EN_SAFE_FREQ 0 pins setting. 1 = Reload the desirable frequency table selection defined at Reg-5 Bit 4~0. R/W 7.2 BIT Register 1: ( Default : XXh) AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 Reserved CPUEN 1 1 5 4 3 2 1 0 CPUEN Reserved Reserved FS2_BACK FS1_BACK FS0_BACK 1 X X X X X Reserved CPUCLKT1/C1 output control 1: Enable 0: Disable CPUCLKT0/C0 output control 1: Enable 0: Disable Reserved Reserved Power on latched value of FS2 pin. Default : 0 Power on latched value of FS1 pin. Default : 0 Power on latched value of FS0 pin. Default : 0 R/W R/W R/W R R R R R 6 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 7.3 BIT Register 2: ( Default : 03h ) AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 CLREQA7#_Ctr 0 6 CLREQA6#_Ctr 0 5 CLREQA5#_Ctr 0 4 CLREQA4#_Ctr 0 3 CLREQA3#_Ctr 0 2 1 0 CLREQA0#_Ctr Reserved Reserved 0 1 1 SRCCLK7 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable SRCCLK6 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable SRCCLK5 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable SRCCLK4 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable SRCCLK3 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable SRCCLK0 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable Reserved Reserved R/W R/W R/W R/W R/W R/W R/W R/W 7.4 BIT Register 3: ( Default : 03h ) AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 CLREQB7#_Ctr 0 6 CLREQB6#_Ctr 0 5 CLREQB5#_Ctr 0 4 CLREQB4#_Ctr 0 3 CLREQB3#_Ctr 0 SRCCLK7 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable SRCCLK6 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable SRCCLK5 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable SRCCLK4 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable SRCCLK3 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable R/W R/W R/W R/W R/W 7 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 2 CLREQB0#_Ctr 0 SRCCLK0 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable PCI0 output control 1: Enable 0: Disable HTT66 output control 1: Enable 0: Disable R/W 1 PCIEN 1 R/W 0 HTTEN 1 R/W 7.5 BIT Register 4: ( Default : FEh) AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 Reserved Reserved Reserved REFEN 1 1 1 1 Reserved Reserved Reserved PREF2 output control 1: Enable 0: Disable PREF1 output control 1: Enable 0: Disable PREF0 output control 1: Enable 0: Disable PUSB48 output control 1: Enable 0: Disable Reserved R/W R/W R/W R/W 3 REFEN 1 R/W 2 REFEN 1 R/W 1 0 F48EN Reserved 1 0 R/W R/W 7.6 BIT Register 5: ( Default : 02h ) AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 Reserved 0 Reserved Program this bit => 1 : Enable Watchdog Timer feature. 0 : Disable Watchdog Timer feature. Enable WD sequence => Program this bit to 1 firstly, then program the Reg-20 to start the counting Read-back this bit => R/W 6 CNT_EN 0 R/W 8 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR During timer count down the bit read back to 1. If count to zero, this bit read back to 0. 0 Read Back only. Timeout Flag. 1 : Watchdog has ever started and count to zero. 0 : a.) Watchdog is restarted and counting. b.) Power on default state 5 WD_TIMEOUT R 4 3 2 1 0 SAF_FREQ SAF_FREQ SAF_FREQ SAF_FREQ SAF_FREQ 0 0 0 1 0 These bits will be reloaded in Reg-0 to select frequency table. As the watchdog is timeout and EN_SAFE_FREQ=1. R/W 7.7 BIT Register 6: ( Default : FFh ) AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 SRCEN 1 6 SRCEN 1 5 SRCEN 1 4 SRCEN 1 3 SRCEN 1 2 ATIGEN 1 1 ATIGEN 1 0 SRCEN 1 SRC7 output control 1: Enable 0: Disable SRC6 output control 1: Enable 0: Disable SRC5 output control 1: Enable 0: Disable SRC4 output control 1: Enable 0: Disable SRC3 output control 1: Enable 0: Disable ATIG1 output control 1: Enable 0: Disable ATI clock can’t be controlled by CLKREQ# pins ATIG0 output control 1: Enable 0: Disable ATI clock can’t be controlled by CLKREQ# pins SRC0 output control 1: Enable 0: Disable R/W R/W R/W R/W R/W R/W R/W R/W 9 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 7.8 BIT Register 7: Winbond Chip ID – Project Code Register ( Default : 06h ) AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 3 2 1 0 CHIP_ID [7] CHIP_ID [6] CHIP_ID [5] CHIP_ID [4] CHIP_ID [3] CHIP_ID [2] CHIP_ID [1] CHIP_ID [0] 0 0 0 0 0 1 1 0 Winbond Chip ID.W83195CG/W-416 (BA5A06). Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. R R R R R R R R 7.9 BIT Register 8: ( Default :D0h ) AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 3 2 1 0 NVAL NVAL MVAL MVAL MVAL MVAL MVAL MVAL 1 1 0 1 0 0 0 0 Programmable N divisor value. Bit 7 ~0 are defined in the Register 9. Programmable N divisor value. Bit 7 ~0 are defined in the Register 9. R/W R/W Programmable M divisor R/W 7.10 Register 9: ( Default : 7Ah ) BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 3 2 1 0 NVAL NVAL NVAL NVAL NVAL NVAL NVAL NVAL 0 1 1 1 1 0 1 0 Default value follow FS=0 Programmable N divisor bit 7 ~0. The bit 8,9 is defined in Register 8. R/W 10 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 7.11 Register 10: Reserved ( Default : 3Bh ) 7.12 Register 11: ( Default : 0Eh ) BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 3 2 1 0 SPH VAL SPH VAL SPH VAL SPH VAL SPL VAL SPL VAL SPL VAL SPL VAL 0 0 0 0 1 1 1 0 2’s complement representation. Ex: 1 -> 1111 ; 2 -> 1110 ; 7 -> 1001 ; 8 -> 1000 Spread Spectrum Down Counter bit 3 ~ bit 0 R/W Spread Spectrum Up Counter bit 3 ~ bit 0. 7.13 Register 12: ( Default : XXh ) BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 3 2 1 0 Reserved KVAL KVAL KVAL KVAL KVAL KVAL KVAL 0 X X X X X X X Reserved Define the PCI divider ratio Table-2 integrate the all divider configuration Define the SRC divider ratio Refer to Table-2 Define the CPU divider ratio Refer to Table-2 R/W R/W R/W R/W Table-2 CPU, SRC, PCI divider ratio selection Table LSB MSB 0 HTT/PCI BIT5 1 0 SRC BIT3 1 00 01 CPU BIT1,0 10 11 Bit2/ Bit4/ Bit9 0 1 Reserved Div12 Div10 Div15 Reserved Div8 Div6 Div10 Div2 Div8 Div3 Div8 Div4 Div8 Div6 Div8 11 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 7.14 Register 13: ( Default : 3Fh ) BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 EN_MN_PROG 0 6 5 4 3 2 1 0 Reserved Reserved Reserved IVAL IVAL IVAL IVAL 0 1 1 1 1 1 1 0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS or desired frequency select SAF_FREQ[4:0] depend on EN_SAFE_FREQ (Reg0 – bit0). Reserved Reserved R/W R/W Charge pump current selection R/W 7.15 Register 14: ( Default : D0h ) BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 3 2 1 0 Reserved Reserved SPCNT SPCNT SPCNT SPCNT SPCNT SPCNT 1 1 0 1 0 0 0 0 Reserved Reserved R/W R/W Spread Spectrum Programmable time, the resolution is 280ns. Default period is 11.8us R/W 7.16 Register 15: ( Default : 5Ch ) BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 INV_CPU Reserved 0 1 Invert the CPUCLKT1/0 phase 0: Default 1: Inverse Reserved R/W R/W 12 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR SRCT/ ATIG output state in during POWER DOWN assertion. 1: Driven (2*Iref) 0: Tristate (Floating) SRCT/ ATIG output state in during STOP Mode assertion. 1: Driven (6*Iref) 0: Tristate (Floating) Complementary parts always tri-state (floating) in power down or stop mode. Reserved CPU align with HTT 1 : Enable 0 : Disable CPU1 to HTT66 skew control. Skew resolution is 300ps The decision of skew direction is same as ASKEW setting 5 DRI_CONT 0 R/W 4 3 2 1 0 Reserved CPU2HTT_SYNC AZSKEW AZSKEW AZSKEW 1 1 1 0 0 R/W R/W R/W 7.17 Register 16: ( Default : 24h ) BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 INV_SRC 0 Invert the SRC phase 0: Default 1: Inverse Invert the HTT & PCI phase 0: Default 1: Inverse CPUCLKT1 to CPUCLKT0 skew control Skew resolution is 300ps The decision of skew direction is same as CSKEW setting CPU1 to PCI skew control Skew resolution is 300ps The decision of skew direction is same as PSKEW setting R/W 6 5 4 3 2 1 0 INV_PCI CSKEW CSKEW CSKEW PSKEW PSKEW PSKEW 0 1 0 0 1 0 0 R/W R/W R/W 7.18 Register 17: Reserved ( Default : 07h ) 7.19 Register 18: Reserved ( Default : 7Ah ) 13 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 7.20 Register 19: ( Default : 04h ) BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 3 2 1 0 SRC_FS SRC_FS SRC_FS SRC_FS SRC_FS CENTERSKEW CENTERSKEW CENTERSKEW 0 0 0 0 0 1 0 0 CPU1 center skew control Skew resolution is 300ps The decision of skew direction is same as CENTERSKEW setting SRC frequency table. See Table-3. SRC_FS also is spread spectrum enable bit. R/W R/W R/W R/W 7.21 Register 20: ( Default : 88h ) BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 3 2 1 0 Reserved SEC SEC SEC SEC SEC SEC SEC 1 0 0 0 1 0 0 0 Reserved R/W Setting the down count depth (Failure decision). One bit resolution represent 250ms. Default time depth is 8*250ms = 2.0 second. If the watchdog timer is counting, this register will return present down count value. R/W 7.22 Register 21: ( Default : ECh ) BIT AFFECTED PIN/ FUNCTIONNAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 Reserved CPU2SRC_SYNC 1 1 Reserved CPU align with SRC 1 : Enable 0 : Disable CPU align with PCI 1 : Enable 0 : Disable Reserved Reserved R/W R/W 5 4 3 CPU2PCI_SYNC Reserved Reserved 1 0 1 R/W R/W 14 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 2 1 0 SRCSKEW SRCSKEW SRCSKEW 1 0 0 CPU1 to SRC skew control Skew resolution is 300ps The decision of skew direction is same as SRCSKEW setting R/W R/W R/W 15 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR Table3: SRC & ATIG Frequency Selection Table BIT 7 FS4 BIT 6 FS3 BIT 5 FS2 BIT 4 FS1 BIT 3 FS0 SRC,ATIG (MHZ) SPREAD(%) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 102.00 102.00 102.00 102.00 104.00 104.00 104.00 104.00 100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 102.00 102.00 102.00 102.00 104.00 104.00 104.00 104.00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 16 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 8. ACCESS INTERFACE The W83195BR-416 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83195BR-416 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. The register number is increased by one if using byte data read/write protocol. Example: In block mode, byte number of program register is 1 In byte mode, byte number of program register is 2 (Byte number of block mode +1) 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8’h00 8.3 Byte Write protocol 8.4 Byte Read protocol 17 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). PARAMETER RATING Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model) -0.5V to +4.6V - 0.5V to + 4.6V 3.135V to 3.465V 3.135V to 3.465V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C 2000V 9.2 General Operating Characteristics Parameter Symbol VIL VIH VOL VOH Idd Cin Cout Lin 2.4 350 5 6 7 2.0 0.4 Min Max 0.8 Units Vdc Vdc Vdc Vdc mA pF pF nH CPU = 100 to 400 MHz PCI = 33.3 Mhz with load 10pF Test Conditions VDD= 3.3V ± 5 %, TA = 0°C to +70°C, Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance 9.3 Skew Group timing clock Parameter Min Max 100 125 250 1000 Units ps ps ps ps Test Conditions Measure Crossing point Measure Crossing point Measured at 1.5V Measured at 1.5V VDD = 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF CPU pair to CPU pair Skew SRC pair to SRC pair Skew PCI to PCI Skew 48MHz to 48MHz Skew 18 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 9.4 CPU 0.7V Electrical Characteristics VDDC= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 Min 175 175 250 660 -150 100 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform 9.5 SRC 0.7V Electrical Characteristics VDDS= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 Min 175 175 250 660 -150 100 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform 9.6 ATIG 0.7V Electrical Characteristics VDDPE= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 Min 175 175 250 660 -150 100 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform 19 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 9.7 PCI Electrical Characteristics Parameter Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 Min 500 500 Max 2000 2000 250 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V VDDP= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, 9.8 USB Electrical Characteristics Parameter Min 500 500 45 -29 -23 29 27 Max 2000 2000 300 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 9.9 REF Electrical Characteristics Parameter Min 500 500 45 -33 -33 30 38 Max 2000 2000 700 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V VDD= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 20 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 10. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83195WG-416 W83195CG-416 56 PIN TSSOP 56 PIN SSOP Commercial, 0°C to +70°C Commercial, 0°C to +70°C 11. HOW TO READ THE TOP MARKING W83195WG-416 28051234 604LBABA W83195CG-416 28051234 604GBABA 1st line: Winbond logo and the type number: W83195WG-416/W83195CG-416 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 604 L B A BA 604: packages made in '2006, week 04 L: assembly house ID; O means OSE, G means GR, L means Lingsen. B: Internal use code A: IC revision BA: mask version All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. 21 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR 12. PACKAGE DRAWING AND DIMENSIONS 56 PIN TSSOP-240mil 56 PIN SSOP-300mil .035 .045 DIMENSION IN MM .045 .055 0.40/0.50 DIA DIMENSION IN INCH SYMBOL E END VIEW HE A A1 A2 b c D HE E e L L1 Y θ MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0.13 0.25 0.005 0.720 0.400 0.292 0.020 0.024 18.2 18.42 18.54 9 10.16 10.31 10.41 7.42 0.51 0.61 7.52 0.64 0.81 1.40 7.59 0.76 1.02 0.08 8 MAX. 0.110 0.016 0.092 0.0135 0.010 TOP VIEW SEE DETAIL "A" c D θ A2 A Y SEATING PLANE e b SIDE VIEW A1 PARTING LINE 0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 8 c 0 0 θ L L1 DETAIL"A" 22 Publication Release Date: Feb 2006 Revision 0.6 W83195WG-416/W83195CG-416 STEPLESS FOR ATI K8 CLOCK GENERATOR Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. 23 Publication Release Date: Feb 2006 Revision 0.6