W83195CG-NP

Winbond Clock Generator W83195CG-NP For Intel Napa Platform Date: Mar/2006 Revision: 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM W83195CG-NP Data Sheet Revision History Pages 1 2 3 4 5 6 7 8 9 n.a. Dates 3/17/2006 Version 0.5 Web Version n.a. Main Contents All of the versions before 0.50 are for internal use. Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -I- Publication Release Date: Mar. 2006 Revision 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM Tables of Content1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 2 BLOCK DIAGRAM ...................................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 3 5.1 5.2 5.3 5.4 5.5 5.6 6. 7. Crystal I/O.................................................................................................................................3 CPU, SRC, and PCIEX, PCI, Clock Outputs ..........................................................................3 Fixed Frequency Outputs.........................................................................................................4 I2C Control Interface ................................................................................................................4 Power Management Pins.........................................................................................................4 Power Pins................................................................................................................................5 FREQUENCY SELECTION BY HARDWARE ............................................................................ 5 I2C CONTROL AND STATUS REGISTERS............................................................................... 6 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Register 0: ( Default : FFh )......................................................................................................6 Register 1: ( Default : FEh ) .....................................................................................................6 Register 2: ( Default : FFh).......................................................................................................8 Register 3: ( Default : 00h )....................................................................................................8 Register 4: ( Default : 87) .........................................................................................................9 Register 5: ( Default : 00h ) ....................................................................................................10 Register 6: ( Default : XXh ) ...................................................................................................10 Register 7: Winbond Chip ID – Project Code Register ( Default : 11h )...............................11 Block Write protocol ...............................................................................................................12 Block Read protocol ...............................................................................................................12 Byte Write protocol .................................................................................................................12 Byte Read protocol.................................................................................................................12 ABSOLUTE MAXIMUM RATINGS .......................................................................................13 General Operating Characteristics ........................................................................................13 Skew Group timing clock........................................................................................................14 CPU 0.7V Electrical Characteristics ......................................................................................14 SRC 0.7V Electrical Characteristics ......................................................................................14 PCIE 0.7V Electrical Characteristics......................................................................................15 PCI Electrical Characteristics.................................................................................................15 48M Electrical Characteristics................................................................................................15 - II - 8. ACCESS INTERFACE .............................................................................................................. 12 8.1 8.2 8.3 8.4 9. SPECIFICATIONS .................................................................................................................... 13 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 W83195CG-NP FOR INTEL NAPA PLATFORM 9.9 9.10 10. 11. 12. REF Electrical Characteristics ...............................................................................................16 DOT 0.7V Electrical Characteristics ......................................................................................16 ORDERING INFORMATION..................................................................................................... 16 HOW TO READ THE TOP MARKING...................................................................................... 17 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 18 - III - Publication Release Date: Mar. 2006 Revision 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM 1. GENERAL DESCRIPTION The W83195CG-NP is a CK410M compliant Clock Synthesizer for Intel P4 processors. W83195CGNP provides all clocks required for high-speed microprocessor and provides, 8 different frequencies of CPU, PCI, PCI-Express clocks setting. Simultaneously W83195CG-NP supports DOT 96MHz clock outputs for integrated graphic chipsets. All clocks are externally selectable with smooth transitions. The W83195CG-NP programs the registers to enable or disable each clock outputs through I2C serial bus interface and provides -0.5% spread spectrum or programmable spread spectrum scale to reduce EMI. The W83195CG-NP is driven with a 14.318 MHz reference crystal and runs on a 3.3V supply. 2. PRODUCT FEATURES • • • • • • • • • • • • • 2 pair 0.7 V current mode Differential clock outputs for CPU 6 pair 0.7V current mode Differential clock outputs for SRC and PCIEX. 1 pair 0.7V current mode Differential clock outputs for SATA. 1 pair 0.7 V current mode Differential clock outputs select for CPUCLK_ITP/SRC. 1 pair 0.7V current mode Differential 96MHz clock outputs for DOT. 4 PCI clock outputs for PCI 2 PCI clock free running outputs for PCI 1 48 MHz clock output for USB. 1 14.318MHz REF clock outputs. I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% spread spectrum Programmable spread spectrum scale to reduce EMI Programmable registers to enable/stop each output. • 56 pin TSSOP package -1- Publication Release Date: Mar. 2006 Revision 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM 3. PIN CONFIGURATION VDDPCI GND PCI3 PCI4 PCI5 GND VDDPCI &ITP_EN/PCICLK_F0 PCICLK_F1 Vtt_PWRGd#/PD VDD48 48MHZ/*FS_A GND DOTT_96MHZ DOTC_96MHZ &FS_B SRCT0 SRCC0 SRCT1 SRCC1 VDDSRC SRCT2 SRCC2 SRCT3 SRCC3 SRCT4_SATA SRCC4_SATA VDDSRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCI2 PCI/SRC_STOP# CPU_STOP# &FS_C REF GND X1 X2 VDDREF SDATA SCLK GND CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 IREF GNDA VDDA CPUCLKT2_ITP/SRCT7 CPUCLKC2_ITP/SRCC7 VDDSRC SRCT6 SRCC6 SRCT5 SRCC5 GND #: Active low *: Internal pull up resistor 120KΩ to VDD & : Internal Pull-down resistor 120KΩ to GND 4. BLOCK DIAGRAM 48MHz PLL2 Divider DOTT DOTC XIN XOUT XTAL OSC 2 REF C PUT 0:1 CPUC 0:1 CPUCLKT2_ITP /SRCT7 CPUCLKC2_ITP /SRCC7 SRCT 0:6 SRCC 0:6 PLL1 Spread Spectrum 2 VCOCLK 8 M/N/Ratio ROM Divider 8 2 PCI_F 0:1 FS(A:C) VTT_PWRGD# Latch &POR 4 PCI 2:5 PCI/SRC_STOP# CPU_STOP# PD & ITP_EN Control Logic &Config Register IREF 475 SDATA SCLK I2C Interface -2- W83195CG-NP FOR INTEL NAPA PLATFORM 5. PIN DESCRIPTION BUFFER TYPE SYMBOL DESCRIPTION IN INtp120k INtd120k OUT OD I/OD # * & Input Latched input at power up, internal 120kΩ pull up. Latched input at power up, internal 120kΩ pull down. Output Open Drain Bi-directional Pin, Open Drain. Active Low Internal 120kΩ pull-up Internal 120kΩ pull-down 5.1 Crystal I/O PIN PIN NAME TYPE DESCRIPTION 50 49 XIN XOUT IN OUT Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). 5.2 CPU, SRC, and PCIEX, PCI, Clock Outputs PIN PIN NAME TYPE DESCRIPTION 44,43,41,40 CPUT [0:1] CPUC [0:1] OUT Low skew (< 85ps) 0.7V Current mode differential clock outputs for host frequencies of CPU 0.7V current mode differential clock outputs for SRC. SRC4_SATA is fixed 100MHz for serial ATA. 0.7V Current mode differential clock outputs for SRC (default), select by ITP_EN pin =0. 0.7V Current mode differential clock outputs for host frequency, select by ITP_EN pin =1. 3.3V free running PCI clock output. Latched input for at initial power up to select CPUCLK2_ITP/SRC7 output. 1: CPUCLK2 clock output. 0: SRC7 clock output. This pin has internal 120K pull down. 3.3V free running PCI clock output. Low skew (< 250ps) 3.3V PCI clock outputs 17,18,19,20,2 2,23,24,25,26, SRCT[0:6] 27,31,30,33,3 SRCC[0:6] 2 SRCT/C 7 36,35 CPUCLKT/C2_ITP PCI_F0 8 OUT OUT OUT OUT & ITP_EN INtd120k 9 56,3,4,5 PCI_F1 PCI [2:5] OUT OUT -3- Publication Release Date: Mar. 2006 Revision 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM 5.3 52 Fixed Frequency Outputs PIN PIN NAME TYPE DESCRIPTION REF 48MHz OUT OUT INtp120k OUT INtd120k 3.3V REF 14.318Mhz clock output. 48MHz clock output for USB. Latched iNQut for FSA at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull up. 0.7V current mode 96MHz differential clock outputs for DOT Latched iNQut for FSB at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull down. Latched input for FS2 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull down. 12 * FSA 14,15 16 DOTT/C & FSB 53 & FSC INtd120k 5.4 47 46 I2C Control Interface PIN PIN NAME TYPE DESCRIPTION SDATA SCLK I/O IN Serial data of I C 2-wire control interface Serial clock of I2C 2-wire control interface 2 5.5 Power Management Pins PIN PIN NAME TYPE DESCRIPTION 39 IREF OUT Deciding the reference current for the differential pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current; 475 ohm is the standard value. CPU clock stop control pin, This pin is low active. Internal 120kΩ pull-up. PCI clock stop control pin, This pin is low active. Internal 120kΩ pull-up. Power good is a low active input signal used to determine when FS [2:0] are valid to be sample. Power Down Function. This is power down pin, high active (PD). Internal 120K pull down 54 55 CPU_STOP#* PCI/SRC_STOP#* IN IN VTT_PWRGD# 10 PD IN INtd120k -4- W83195CG-NP FOR INTEL NAPA PLATFORM 5.6 Power Pins PIN PIN NAME TYPE DESCRIPTION 37 1,7 21,28,34 11 42 48 38 2,6,13,29,45,51 VDDA VDDP VDDS VDD48 VDDC VDDR GNDA GND PWR PWR PWR PWR PWR PWR PWR PWR 3.3V power supply for PLL core. 3.3V power supply for PCI. 3.3V power supply for SRC pair. 3.3V power supply for 48MHz. 3.3V power supply for CPU. 3.3V power supply for REF. Ground pin for PLL core. Ground pin 6. FREQUENCY SELECTION BY HARDWARE FS4 FS3 0 0 0 0 0 0 0 0 FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU (MHZ) 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 DOT (MHZ) 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 SRC (MHZ) 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 PCI (MHZ) 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 0 0 0 0 0 0 0 0 -5- Publication Release Date: Mar. 2006 Revision 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM 7. I2C CONTROL AND STATUS REGISTERS 7.1 BIT Register 0: ( Default : FFh ) AFFECTED PIN/ FUNCTION NAME(S) PWD AFFECTED PIN / FUNCTION DESCRIPTION TYPE 7 CPUEN 1 6 SRCEN 1 5 SRCEN 1 4 SRCEN 1 3 SRCEN 1 2 SRCEN 1 1 SRCEN 1 0 SRCEN 1 CPUCLK2_ITP/SRCCLK7 output control 1: Enable 0: Disable SRCCLK6 output control 1: Enable 0: Disable SRCCLK5 output control 1: Enable 0: Disable SRCCLK4 output control 1: Enable 0: Disable SRCCLK3 output control 1: Enable 0: Disable SRCCLK2 output control 1: Enable 0: Disable SRCCLK1 output control 1: Enable 0: Disable SRCCLK0 output control 1: Enable 0: Disable R/W R/W R/W R/W R/W R/W R/W R/W 7.2 BIT Register 1: ( Default : FEh ) AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 PCIFEN 1 PCI_F0 output control 1: Enable 0: Disable DOT96_T/C output control 1: Enable 0: Disable USB48M output control 1: Enable 0: Disable R/W 6 F96EN 1 R/W 5 F48EN 1 R/W -6- W83195CG-NP FOR INTEL NAPA PLATFORM Register 1: ( Default : FEh ), continued BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 4 3 2 REFEN Reserved CPUEN 1 1 1 REFOUT output control 1: Enable 0: Disable Reserved CPUCLK1 output control 1: Enable 0: Disable R/W R/W R/W 1 CPUEN 1 0 SPSPEN 0 CPUCLK0 output control 1: Enable 0: Disable Enable spread spectrum mode under clock output. 0 = Spread Spectrum mode disable 1 = Spread Spectrum mode enable R/W R/W -7- Publication Release Date: Mar. 2006 Revision 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM 7.3 BIT Register 2: ( Default : FFh) AFFECTED PIN/ FUNCTIONNAME(S) PWD FUNCTION DESCRIPTION TYPE 7 PCIEN 1 PCICLK5 output control 1: Enable 0: Disable PCICLK4 output control 1: Enable 0: Disable PCICLK3 output control 1: Enable 0: Disable PCICLK2 output control 1: Enable 0: Disable Reserved Reserved Reserved PCI_F1 output control 1: Enable 0: Disable R/W 6 PCIEN 1 R/W 5 PCIEN 1 R/W 4 3 2 1 0 PCIEN Reserved Reserved Reserved PCIFEN 1 1 1 1 1 R/W R/W R/W R/W R/W 7.4 BIT Register 3: ( Default : 00h ) AFFECTED PIN/ FUNCTIONNAME(S) PWD FUNCTION DESCRIPTION TYPE 7 SRC7_STOP 0 PCI_SRC_STOP# for SRC7 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC6 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC5 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC4 control. 1: Stoppable 0:Free-Running R/W 6 SRC6_STOP 0 R/W 5 SRC5_STOP 0 R/W 4 SRC4_STOP 0 R/W -8- W83195CG-NP FOR INTEL NAPA PLATFORM Register 3: ( Default : 00h ), continued BIT AFFECTED PIN/ FUNCTIONNAME(S) PWD FUNCTION DESCRIPTION TYPE 3 SRC3_STOP 0 PCI_SRC_STOP# for SRC3 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC2 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC1 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC0 control. 1: Stoppable 0:Free-Running R/W 2 SRC2_STOP 0 R/W 1 SRC1_STOP 0 R/W 0 SRC0_STOP 0 R/W 7.5 BIT Register 4: ( Default : 87) AFFECTED PIN/ FUNCTIONNAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 Reserved Reserved Reserved PCIF 1 0 0 0 Reserved Reserved Reserved PCI_SRC_STOP# for PCIF1 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for PCIF0 control. 1: Stoppable 0:Free-Running 1: Enable CPUCLK2_ITP stop feature 0: Disable stop feature 1: Enable CPUCLK1 stop feature 0: Disable stop feature 1: Enable CPUCLK0 stop feature 0: Disable stop feature R/W R/W R/W R/W 3 PCIF 0 R/W 2 1 0 CPUCLK2_FS_ITP CPUCLK1_FS CPUCLK0_FS 1 1 1 R/W R/W R/W -9- Publication Release Date: Mar. 2006 Revision 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM 7.6 BIT Register 5: ( Default : 00h ) AFFECTED PIN/ FUNCTIONNAME(S) PWD FUNCTION DESCRIPTION TYPE CPUT / SRCT / PCI_EXP / DOT96_T output state in during POWER DOWN assertion. 1: Driven (2*Iref) 0: Tristate (Floating) 7 DRI_CONT (Reserved) 0 CPUT / SRCT / PCI_EXP / DOT96_T output state in during STOP Mode assertion. 1: Driven (6*Iref) 0: Tristate (Floating) Complementary parts always tri-state (floating) in power down or stop mode. 6 5 4 3 2 1 Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Power on latched value of ITP_EN/PCICLK_F0 pin. R/W R/W R/W R/W R/W R/W R/W 0 SEL_ITP 0 SRCCLK/CPU_ITP output clock selection : 1: CPU_ITP clock output 0: SRCCLK clock output R/W 7.7 BIT Register 6: ( Default : XXh ) AFFECTED PIN/ FUNCTIONNAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved PCI/SRCCLK_STOP FSC_BACK FSB_BACK FSA_BACK 1 0 0 0 1 X X X To stop all PCICLK and SRCCLK output 1: Disable 0: Enable Power on latched value of FSC pin. Power on latched value of FSB pin. Power on latched value of FSA pin. R/W R R R Reserved R/W - 10 - W83195CG-NP FOR INTEL NAPA PLATFORM 7.8 BIT Register 7: Winbond Chip ID – Project Code Register ( Default : 11h ) AFFECTED PIN/ FUNCTIONNAME(S) PWD FUNCTION DESCRIPTION TYPE 7 6 5 4 3 2 1 0 CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0] 0 0 0 1 0 0 0 1 Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. R R R R R R R R - 11 - Publication Release Date: Mar. 2006 Revision 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM 8. ACCESS INTERFACE The W83195CG-NP provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83195CG-NP is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8’h00 8.3 Byte Write protocol 8.4 Byte Read protocol - 12 - W83195CG-NP FOR INTEL NAPA PLATFORM 9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). PARAMETER RATING Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model) -0.5V to +4.6V - 0.5V to + 4.6V 3.135V to 3.465V 3.135V to 3.465V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C 2000V 9.2 General Operating Characteristics Parameter Symbol VIL VIH VOL VOH Idd Cin Cout Lin 2.4 350 5 6 7 2.0 0.4 Min Max 0.8 Units Vdc Vdc Vdc Vdc mA pF pF nH CPU = 100 to 400 MHz PCI = 33.3 Mhz with load 10pF Test Conditions VDD= 3.3V ± 5 %, TA = 0°C to +70°C, Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance - 13 - Publication Release Date: Mar. 2006 Revision 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM 9.3 Skew Group timing clock Parameter CPU pair to CPU pair Skew PCIE pair to PCIE pair Skew PCI to PCI Skew 48MHz to 48MHz Skew Min Max 100 85 500 1000 Units ps ps ps ps Test Conditions Measure Crossing point Measure Crossing point Measured at 1.5V Measured at 1.5V VDD = 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF 9.4 CPU 0.7V Electrical Characteristics VDDC= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 Min 175 175 250 660 -150 125 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform 9.5 SRC 0.7V Electrical Characteristics VDDS= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 Min 175 175 250 660 -150 85 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform - 14 - W83195CG-NP FOR INTEL NAPA PLATFORM 9.6 PCIE 0.7V Electrical Characteristics VDDPE= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 Min 175 175 250 660 -150 85 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform 9.7 PCI Electrical Characteristics Parameter Min 500 500 45 -33 -33 30 38 Max 2000 2000 250 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V VDDP= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 9.8 48M Electrical Characteristics Parameter Min 500 500 45 -33 -33 30 38 Max 2000 2000 500 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max - 15 - Publication Release Date: Mar. 2006 Revision 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM 9.9 REF Electrical Characteristics Parameter Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 29 27 45 -29 -23 Min 500 500 Max 2000 2000 1000 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V VDD= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF, 9.10 DOT 0.7V Electrical Characteristics VDD= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 Min 175 175 250 660 -150 250 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform 10. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83195CG-NP 56 PIN TSSOP (Lead free part) Commercial, 0°C to +70°C - 16 - W83195CG-NP FOR INTEL NAPA PLATFORM 11. HOW TO READ THE TOP MARKING W83195CG-NP 28051234 504GAABA 1st line: Winbond logo and the part number: W83195CG-NP(Lead free) 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 504 G A A BA 504: packages made in '2005, week 04 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision BA: Internal use code All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. - 17 - Publication Release Date: Mar. 2006 Revision 0.5 W83195CG-NP FOR INTEL NAPA PLATFORM 12. PACKAGE DRAWING AND DIMENSIONS 56 PIN TSSOP-240mil - 18 - W83195CG-NP FOR INTEL NAPA PLATFORM Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 19 - Publication Release Date: Mar. 2006 Revision 0.5