W83195R-08

W83195R-08 150MHZ 4-DIMM CLOCK 1.0 GENERAL DESCRIPTION The W83195R-08 is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor such as Intel Pentium II. W83195R-08 provides sixteen CPU/PCI frequencies which are externally selectable with smooth transitions. W83195R-08 also provides 17 SDRAM clocks controlled by the none-delay buffer_in pin. The W83195R-08 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. Spread spectrum built in at ¡Ó0.5% or ¡Ó0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots(ISA, PCI, CPU, DIMM) is not recommend. The add on cards may have a pull up or pull down. High drive seven PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads, when maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs, such as REF, 24MHz and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES • • • • • • Supports Pentium™ II CPU with I2C. 3 CPU clocks (one free-running CPU clock) 17 SDRAM clocks for 4 DIMs 7 PCI synchronous clocks Two IOAPIC clocks for multiprocessor support Optional single or mixed supply: (Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 = 3.3V, VddL1 = VdqL2 = 2.5V) < 250ps skew among CPU and SDRAM clocks < 250ps skew among PCI clocks < 5ns propagation delay SDRAM from buffer input Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns. Smooth frequency switch with selections from 50 MHz to 133 MHz CPU I2C 2-Wire serial interface and I2C read back ¡Ó0.25% or ¡Ó0.5% center type spread spectrum function to reduce EMI Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) • • • • • • • • • MODE pin for power Management • One 48 MHz for USB & one 24 MHz for super I/O • 56-pin SSOP package -1- Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 3.0 BLOCK DIAGRAM PLL2 ~ Xin Xout BUFFER IN XTAL OSC 1/2 STOP 48MHz 24MHz IOAPIC 2 REF(0:1) CPUCLK_F 6 PLL1 Spread Spectrum FS(0:3)* MODE* 4 LATCH STOP CPUCLK1 SDRAM_F STOP 17 4 PCI Clock Divider STOP 5 SDRAM(0:15) ~ POR CPU_STOP# PCI_STOP# SDATA* SDCLK* PCICLK(0:4) PCICLK_F Control Logic Config. Reg. 4.0 PIN CONFIGURATION Vddq1 REF1/ FS2* * PCI_STOP#/REF0 Vss Xin Xout Vddq2 PCICLK_F/MODE* PCICLK0/FS3* Vss PCICLK1 PCICLK2 PCICLK3 PCICLK4 Vddq2 PCICLK5 BUFFER IN SDRAM11 SDRAM10 Vddq3 SDRAM 9 SDRAM 8 Vss SDRAM 15 SDRAM 14 Vss SDATA SDCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VddL1 IOAPIC0 IOAPIC_F Vss CPUCLK_F CPUCLK1 VddL2 CPU_STOP# SDRAM12 Vss SDRAM_F Vddq3 SDRAM 0 SDRAM 1 Vss SDRAM 2 SDRAM 3 SDRAM 4 SDRAM 5 Vddq3 SDRAM 6 SDRAM 7 Vss SDRAM 12 SDRAM 13 Vddq4 48MHz/FS0* 24MHz/FS1* -2- Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 5.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250kΩ pull-up 5.1 Crystal I/O SYMBOL Xin Xout PIN 5 6 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. 5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs SYMBOL CPUCLK_F CPUCLK1 PIN 52 51 I/O OUT OUT FUNCTION Free running CPU clock. Not affected by CPU_STOP# Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. Powered by VddL2. Low if CPU_STOP# is low. This asynchronous input halts CPUCLK1,IOAPIC & SDRAM(0:12) at logic “0” level when driven low. High drive buffered output of the crystal, and is powered by VddL1. Free running IOAPIC clock, and not affected by CPU_STOP# SDRAM clock outputs. Fanout buffer outputs from BUFFER IN pin.(Controlled by chipset) CPU_STOP# IOAPIC0 IOAPIC_F SDRAM [ 0:15] 47 55 54 18,19,21,22,24 ,25,32,33,35, 36,38,39,40,41 ,43,44 8 IN OUT OUT OUT PCICLK_F/ *MODE PCICLK0/*FS3 I/O 9 I/O PCICLK [ 1:5 ] BUFFER IN SDRAM_F 11,12,13,14,16 17 46 OUT IN O Free running PCI clock during normal operation. Latched Input. Mode=1, Pin 2 is REF0; Mode=0, Pin2 is PCI_STOP# Low skew (< 250ps) PCI clock outputs. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. Synchronous to CPU clocks with 1-48ns skew(CPU early). Inputs to fanout for SDRAM outputs. Free running SDRAM clock, and not affected by CPU_STOP# Publication Release Date: Mar. 1999 Revision 0.30 -3- W83195R-08 PRELIMINARY 5.3 I2C Control Interface SYMBOL *SDATA *SDCLK PIN 27 28 I/O I/O IN 2 FUNCTION Serial data of I C 2-wire control interface with internal pull-up resistor. Serial clock of I2C 2-wire control interface with internal pull-up resistor. 5.4 Fixed Frequency Outputs SYMBOL REF0 / PCI_STOP# PIN 3 I/O I/O FUNCTION 14.318MHz reference clock. This REF output is the stronger buffer for ISA bus loads. Halt PCICLK(0:4) clocks at logic 0 level, when input low (In mobile mode. MODE=0) REF1 / *FS2 2 I/O 14.318MHz reference clock. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 24MHz / *FS0 30 I/O 24MHz output clock. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 48MHz / *FS1 29 I/O 48MHz output for USB during normal operation. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 5.5 Power Pins SYMBOL Vddq1 VddL1 VddL2 Vddq2 Vddq3 Vddq4 Vss PIN 1 56 50 7,15 20,37,45 31 FUNCTION Power supply for Ref [0:1] crystal and core logic. Power supply for IOAPIC output, either 2.5V or 3.3V. Power supply for CPUCLK_F & CPUCLK[1:2], either 2.5V or 3.3V. Power supply for PCICLK_F, PCICLK[0:5], 3.3V. Power supply for SDRAM_F & SDRAM[0:15], and CPU PLL core, nominal 3.3V. Power for 24 & 48MHz output buffers and fixed PLL core. 4,10,23,26,34,42,48, Circuit Ground. 53 Publication Release Date: Mar. 1999 Revision 0.30 -4- W83195R-08 PRELIMINARY 6.0 FREQUENCY SELECTION FS3=0 FS2 0 0 0 0 1 1 1 1 FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS3=1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 120 115 110 105 140 150 124 133 40.00(CPU/3) 38.33(CPU/3) 36.67(CPU/3) 35.00(CPU/3) 35.00(CPU/4) 37.50(CPU/4) 31.00(CPU/4) 33.25(CPU/4) FS0 0 1 0 1 0 1 0 1 124 75 83.3 66.8 103 112 133 100.3 CPU,SDRAM (MHz) 41.33(CPU/3) 37.5(CPU/2) 41.65(CPU/2) 33.4(CPU/2) 34.3(CPU/3) 37.33(CPU/3) 44.33(CPU/3) 33.3(CPU/3) PCI (MHz) CPU,SDRAM (MHz) PCI (MHz) REF,IOAPIC (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 REF,IOAPIC (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 7.0 MODE PIN -POWER MANAGEMENT INPUT CONTROL MODE, Pin8 (Latched Input) 0 1 PIN 3 PCI_STOP# (Input) REF0 (Output) -5- Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 8.0 FUNTION DESCRIPTION 8.1 POWER MANAGEMENT FUNCTIONS All clocks can be individually enabled or disabled via the 2-wire control interface. On power up, external circuitry should allow 3 ms for the VCO’s to stabilize prior to enabling clock outputs to assure correct pulse widths. When MODE=0, pins 3 and 47 are inputs (PCI_STOP#), (CPU_STOP#), when MODE=1, these functions are not available. A particular clock can be enabled as both the 2wire serial control interface and one of these pins indicate that it should be enable. The W83195R-08 may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. The CPU and PCI clocks transform between running and stop by waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CPU_STOP# PCI_STOP# CPUCLK[1:2] IOAPIC0 & SDRAM [0:15] LOW LOW RUNNING RUNNING PCI OTHER CLKs XTAL & VCOs 0 0 1 1 0 1 0 1 LOW RUNNING LOW RUNNING RUNNING RUNNING RUNNING RUNNING RUNNING RUNNING RUNNING RUNNING 8.2 2-WIRE I2C CONTROL INTERFACE The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83195R-08 initializes with default register settings. Use of the 2-wire control interface is then optional. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Publication Release Date: Mar. 1999 Revision 0.30 -6- W83195R-08 PRELIMINARY Bytes sequence order for I C controller : Clock Address A(6:0) & R/W 2 Ack 8 bits dummy Command code Ack 8 bits dummy Byte count Ack Byte0,1,2... until Stop Set R/W to 1 when read back the data sequence is as follows [1101 0011] : Clock Address A(6:0) & R/W Ack Byte 0 Ack Byte 1 Ack Byte2, 3, 4... until Stop 8.3 SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the PowerUp column gives the default state at true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the sequence described below (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. 8.3.1 Register 0: CPU Frequency Select Register (default = 0) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description 0 = ¡Ó0.25% Spread Spectrum Modulation 1 = ¡Ó0.5% Spread Spectrum Modulation SSEL2 (for frequency table selection by software via I2C) SSEL1 (for frequency table selection by software via I2C) SSEL0 (for frequency table selection by software via I2C) 0 = Selection by hardware 2 1 = Selection by software I C - Bit 6:4, 2 SSEL3 (for frequency table selection by software via I2C) 0 = Normal 1 = Spread Spectrum enabled 0 = Running 1 = Tristate all outputs Note : The frequency table selected by software via I2C is the same as the hardware setting frequency table. -7- Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 8.3.2 Register 1 : CPU , 48/24 MHz Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 46 49 51 52 Reserved Reserved Reserved Reserved SDRAM16 (Active / Inactive) CPUCLK2 (Active / Inactive) CPUCLK1 (Active / Inactive) CPUCLK_F (Active / Inactive) Description 8.3.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 8 16 14 13 12 11 9 Reserved PCICLK_F (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLk1 (Active / Inactive) PCICLK0 (Active / Inactive) Description 8.3.4 Register 3: SDRAM Clock Register ( 1 = enable, 0 = Stopped ) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 30 29 33,32,25,24 22,21,19,18 39,38,36,35 44,43,41,40 Description Reserved Reserved 48MHz (Active / Inactive) 24MHz (Active / Inactive) SDRAM(12:15) (Active / Inactive) SDRAM(8:11) (Active / Inactive) SDRAM(4:7) (Active / Inactive) SDRAM(0:3) (Active / Inactive) -8- Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 8.3.5 Register 4: Reserved Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @PowerUp X 1 1 1 x 1 x 1 Pin Latched FS0# Reserved Reserved Reserved Latched FS1# Reserved Latched FS3# Reserved Description 8.3.6 Register 5: Peripheral Control (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 X 1 1 1 1 1 1 Pin 54 55 2 3 Reserved Latched FS2# Reserved IOAPIC _F(Active / Inactive) IOAPIC0 (Active / Inactive) Reserved REF1 (Active / Inactive) REF0 (Active / Inactive) Description -9- Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 9.0 SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Vdd , VIN TSTG TB TA Parameter Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature Rating - 0.5 V to + 7.0 V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C 9.2 AC CHARACTERISTICS Vddq4 = Vddq3 = Vddq2 = Vddq1=3.3V ± 5 %, VddL1=VddL2 = 2.375V~2.9V , TA = 0° C to +70° C Parameter Output Duty Cycle CPU/SDRAM to PCI Offset Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) & Fall (2.0V ~0.4V) Time Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion VRBE 0.7 2.1 V tTLH tTHL Vover 0.7 1.5 V 0.4 1.6 ns 15 pF Load on CPU and PCI outputs 22 Ω at source of 8 inch PCB run to 15 pF load Ring Back must not enter this range. BWJ 500 KHz tJA 500 ps tOFF tSKEW tCCJ Symbol Min 45 1 Typ 50 Max 55 4 250 ¡Ó250 Units % ns ps ps Test Conditions Measured at 1.5V 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V - 10 - Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 9.3 DC CHARACTERISTICS Vddq4 = Vddq3 = Vddq2 = Vddq1=3.3V ± 5 %, VddL1=VddL2 = 2.375V~2.9V , TA = 0° C to +70° C Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 4 mA Output High Voltage IOH = 4mA Tri-State leakage Current Dynamic Supply Current for Vdd + Vddq3 Dynamic Supply Current for Vddq2 + Vddq2b CPU Stop Current for Vdd + Vddq3 CPU Stop Current for Vddq2 + Vddq2b PCI Stop Current for Vdd + Vddq3 IPD3 mA ICPUS2 mA Same as above ICPUS3 mA Same as above Idd2 mA Ioz Idd3 10 µA mA CPU = 66.6 MHz PCI = 33.3 Mhz with load Same as above VOH 2.4 Vdc All outputs using 3.3V power Symbol VIL VIH IIL IIH VOL 2.0 -66 5 0.4 Min Typ Max 0.8 Units Vdc Vdc µA µA Vdc All outputs Test Conditions - 11 - Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 9.4 BUFFER CHARACTERISTICS 9.4.1 TYPE 1 BUFFER FOR CPU CLOCK Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.4 1.6 27 Min -27 -27 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 2.0V Vout = 1.2 V Vout = 0.3 V 10pF Load 20pF Load 9.4.2 TYPE 2 BUFFER FOR IOAPIC Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.7 V and 1.7 V Rise/Fall Time Max Between 0.7 V and 1.7 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.4 1.8 28 -29 Min Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.4 V Vout = 2.7 V Vout = 1.0 V Vout = 0.2 V 10pF Load 20pF Load - 12 - Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 9.4.3 TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 1.0 4.0 29 Min -29 -23 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 3.135V Vout = 1.95 V Vout = 0.4 V 10pF Load 20pF Load 9.4.4 TYPE 4 BUFFER FOR SDRAM (0:15) Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.5 1.3 53 -46 Min Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.65 V Vout = 3.135 V Vout = 1.65 V Vout = 0.4 V 20pF Load 30pF Load 9.4.5 TYPE 5 BUFFER FOR PCICLK(0:5,F) Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.5 2.0 30 38 Min -33 -33 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V 15pF Load 30pF Load - 13 - Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 10.0 POWER MANAGEMENT TIMING 10.1 CPU_STOP# Timing Diagram CPUCLK (Internal) PCICLK (Internal) PCICLK_F CPU_STOP# 1 2 3 4 1 2 3 4 CPUCLK[0:3] SDRAM For synchronous Chipset, CPU_STOP# pin is an asynchronous “ active low ” input pin used to stop the CPU clocks for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output with full pulse width. In this case, CPU “clocks on latency“ is less than 4 CPU clocks and “clocks off latency” is less then 4 CPU clocks. 10.2 PCI_STOP# Timing Diagram CPUCLK (Internal) PCICLK (Internal) PCICLK_F PCI_STOP# 1 2 1 2 PCICLK[0:5] For synchronous Chipset, PCI_STOP# pin is an asynchronous “active low” input pin used to stop the PCICLK [0:5] for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output with full pulse width. In this case, PCI “clocks on latency“ is less than 2 PCI clocks and “clocks off latency” is less then 2 PCI clocks. Publication Release Date: Mar. 1999 Revision 0.30 - 14 - W83195R-08 PRELIMINARY 11.0 OPERATION OF DUAL FUCTION PINS Pins 2,8, 9, 29,30 are dual function pins and are used for selecting different functions in this device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore, and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these pins is latched into their appropriate internal registers. Once the correct information is properly latched, these pins will change into output pins and will be pulled low by default. At the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency. 2.5V Vdd #2 REF1/ FS2* #8 PCICLK_F/ MODE* #9 PCICLK0/ FS3* #30 24/FS0 #29 48/FS1 Output tri-state Output pull-low Within 3ms Input All other clocks Output tri-state Output pull-low Output Each of these pins has a large pull-up resistor ( 250 kΩ @3.3V ) inside. The default state will be logic 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. Under these conditions, an external 10 kΩ resistor is recommended to be connected to Vdd if logic 1 is expected. Otherwise, there should be direct connection to ground if a logic 0 is desired. The 10 kΩ resistor should be placed before the serious terminating resistor. Note that these logic will only be latched at initial power on. If optional EMI reducing capacitor are needed, they should be placed as close to the series terminating resistor as possible and after the series terminating resistor. These capacitors have typical values ranging from 4.7pF to 22pF. - 15 - Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY Vdd 10kΩ Device Pin 10kΩ Series Terminating Resistor Clock Trace EMI Reducing Cap Optional Ground Ground Programming Header Vdd Pad 10k Ω Device Pin Ground Pad Series Terminating Resistor Clock Trace EMI Reducing Cap Optional Ground - 16 - Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 13.0 ORDERING INFORMATION Part Number W83195R-08 Package Type 56 PIN SSOP Production Flow Commercial, 0°C to +70°C 14.0 HOW TO READ THE TOP MARKING W83195R-08 28051234 814GBB 1st line: Winbond logo and the type number: W83195R-08 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR BB: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 17 - Publication Release Date: Mar. 1999 Revision 0.30 W83195R-08 PRELIMINARY 15.0 PACKAGE DRAWING AND DIMENSIONS .035 .045 DIMENSION IN MM .045 .055 0.40/0.50 DIA END VIEW DIMENSION IN INCH SYMBOL HE A A1 A2 b c D HE TOP VIEW SEE DETAIL "A" MIN. 2.41 0.20 2.24 0.20 0.13 18.2 9 10.16 7.42 0.51 0.61 NOM MAX. MIN. NOM 0.095 0.101 2.57 2.79 0.30 0.41 0.008 0.012 0.088 0.090 2.34 2.29 0.25 0.34 0.008 0.010 0.25 18.42 18.54 10.31 10.41 7.52 0.64 0.81 1.40 7.59 0.76 1.02 0.08 8 0.005 0.720 0.725 0.400 0.406 0.292 0.296 0.020 0.025 0.024 0.032 0.055 0 MAX. 0.110 0.016 0.092 0.0135 0.010 0.730 0.410 0.299 0.030 0.040 0.003 8 D θ E e L L1 Y θ A2 A A1 PARTING LINE SIDE VIEW 0 θ DETAIL"A" Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. Publication Release Date: Mar. 1999 Revision 0.30 - 18 -