W83196S-14

Preliminary W83196S-14 100 MHZ CLOCK FOR BX CHIPSET (2 CHIP) 1. GENERAL DESCRIPTION The W83196S-14 is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor. Twelve different frequency of CPU, and PCI clocks are externally selectable with smooth transitions. The W83196S-14 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and choose the 0.5% center type spread spectrum to reduce EMI. The W83196S-14 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1V/nS slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1V/nS slew rate into 20 pF loads as maintaining 50 ±5% duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide better than 0.5V/nS slew rate. 2. FEATURES • Supports Pentium™ II CPUs with I C 2 • 12 sets of CPU frequencies selection • 2 CPU clocks (one free running CPU clock) • 7 PCI synchronous clocks(one free running PCI clock) • Optional single or mixed supply: (VDDR = VDDCore = VDDP = VDD4 = 3.3V ±5%) (VDDA = VDDC = 2.5V ±5%) • Skew form CPU to PCI clock 1.5 to 4.0 nS, CPU leads. • CPU clock jitter less than 200 pS • PCI_F, PCI1: 6 clock skew less than 500 pS • Smooth frequency switch with selections from 66.8 MHz to 150 MHz CPU • I C 2-Wire serial interface and I C read back • ±0.5% center type spread spectrum function to reduce EMI • Programmable registers to enable/stop each output and select modes 2 2 (mode as Tri-state or Normal ) • MODE pin for power management • 48 MHz for USB • 24 MHz for super I/O • Packaged in 28-pin SOP -1- Publication Release Date: March 1999 Revision A1 Preliminary W83196S-14 3. BLOCK DIAGRAM VDDR REF2X X1 X2 XTAL OSC IOAPIC VDDA VDDC SEL100/66# PLL1 Spread Spectrum ¡Ò2/3/4 STOP CPUCLK_F CPUCLK1 SEL48* MODE* Latch VDDC VDDP PCI clock Divder STOP 6 PCICLK_F PCICLK(1:6) CPU_STOP# PCI_STOP# SDATA* SCLK* Contro Logic Config. Reg. PLL2 VDDP VDD4 48MHz 24/48MHz VDD4 4. PIN CONFIGURATION Xin Xout VssP PCICLK_F PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDP PCI_STOP#/PCICLK5 CPU_STOP#/PCICLK6 VDD4 48MHz/Mode* 24/48MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VssR REF2X/SEL48* VDDR VDDA IOAPIC VDDC CPUCLK_F CPUCLK1 VDDCore VssC SDATA SDCLK SEL100/66# Vss4 -2- Preliminary W83196S-14 5. PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Low active * - Internal 250kΩ pull-up 5.1 Crystal I/O SYMBOL Xin Xout PIN 1 2 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318 MHz nominally. 5.2 CPU, PCI Clock Outputs SYMBOL CPUCLK_F CPUCLK1 PCICLK [ 1:4 ] PCICLK_F PCICLK5/ PCI_STOP# 10 I/O If Mode* =1 (default), then this pin is a PCICLK5 buffered output of the crystal. If Mode* = 0 , then this pin is PCI_STOP# input used in power management mode for synchronously stopping the all CPU clocks. If Mode* = 1 (default), then this pin is a PCICLK6 clock output. If Mode* = 0 , then this pin is CPU_STOP # and used in power management mode for synchronously stopping the all PCI clocks. PIN 22, 21 I/O FUNCTION OUT Low skew (