W83304D

W83304D/W83304G Winbond ACPI Controller W83304D W83304G TM For AMD Claw Hammer CPU -1- Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G W83304D Data Sheet Revision History PAGES DATES VERSION VERSION ON WEB MAIN CONTENTS 1 2 3 4 5 6 7 8 June/04 April/06 0.50 0.51 N/A N/A Preliminary Version Add Pb-free part no of W83304G Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -2- W83304D/W83304G Table of Content1. 2. 3. 4. 5. 6. 7. 8. 9. 10. GENERAL FUNCTION DESCRIPTION...................................................................................... 4 PIN-OUT...................................................................................................................................... 5 PIN DESCRIPTIONS .................................................................................................................. 6 BLOCK DIAGRAM ...................................................................................................................... 9 ELECTRICAL SPECIFICATION ............................................................................................... 10 5.1 AC CHARACTERISTICS.............................................................................................. 10 APPLICATION CIRCUIT........................................................................................................... 12 POWER SEQUENCE ............................................................................................................... 13 ORDERING INSTRUCTION ..................................................................................................... 14 HOW TO READ THE TOP MARKING...................................................................................... 14 PACKAGE DIMENSION ........................................................................................................... 15 -3- Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G 1. GENERAL FUNCTION DESCRIPTION Provides Powers - 5V Active/Sleep (5VDL) - Provide a switch 5VDLEN pin to enable/disable 5VDL output in S5 state for USB application. - 3.3V Active/Sleep (3.3VDUAL) - Dual-Channel 2.5V Active/Sleep (2.5VSTR) for DDR - 1.5V for AGP 4X/8X Voltage - Two 1.25V~5V Linear Voltage Regulators Support VCC/VSTR/VDL/VSB Voltages - 1.25V DDR Bus Termination Regulated Voltage - 1.2V VLDT for AMD_K8 CPU Hyper transport. - 2.5VDDA for AMD_K8 PLL. - 1.25VREF for AMD_K8 reference. - Up to 0.3V/0.1V incremental voltage on DDR RAM for over-clocking application. Provides Signals for ATX Power Supply PS_ON# Control Support AMD K8 Claw Hammer Specific Power Up/Down Sequence Provides fault signal control. Internal Charge Pump Support Up to 9.5VSB Drive All N-Channel MOSFET Soft Start Under-Voltage Monitoring for VAGP, VRAM, VLDT, 3.3VDUAL Channels -4- W83304D/W83304G 2. PIN-OUT 5VDRV/3VDRV 3VSB_DRV VAGP_DRV 3VSB_SEN VAGP_SEN VLDT_DRV 26 LR1_DRV LR2_DRV LR1_SEN LR2_SEN 36 35 34 33 32 31 30 29 28 27 5VSB 25 24 23 22 21 20 19 5VUSB_DRV C1 C2 CHR_PMP 5VSB GND RSMRST# 5VDL_EN MISC_EN PWR_OK S3# S5# 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 VLDT_SEN GND VDDIO_DRV1 ISEN1 VDDIO_DRV2 ISEN2 VDDIO_SEN VTT_DRV VTT_SEN VTT_SINK ISET SS 1.25VREF 18 17 16 15 14 13 W83304D VDDIO_SET0 VDDIO_SET1 PS_ON_OUT# VDD_EN PS_ON_IN# ALL_PWR_OK OV_CLK# VDD_GD -5- Publication Release Date: April, 2006 Revision 0.51 2.5VDDA Fault# GND VCC3 W83304D/W83304G 3. PIN DESCRIPTIONS I/O12t I/O12ts O12 AO12 OD12 INt INts AIN - TTL level bi-directional pin with 12 mA source-sink capability,open drain output - TTL level and schmitt trigger - Output pin with 12 mA source-sink capability - Output pin(Analog) with 12mA capability - Open-drain output pin with 12 mA sink capability - TTL level input pin - TTL level input pin and schmitt trigger - Input pin(Analog) NO NAME I/O POWER SOURCE FUNCTION DESCRIPTION 1 ALL_PWR_OK OD24 5VSB Power OK Signal. The signal is drove high to indicate all power ready. H/W Trapping Pin for Over-Clocking Application. 1: Normal 0: +50mV is added on All regulated powers (VDDIO, VDDA, VAGP, VLDT, 1.25VREF ). VDDIO Output Voltage Setting Pin. VDDIO output with OV_CLK# = High VDDIO_SET1 VDDIO_SET0 0 1 0 1 VRAMSET0 0 1 0 1 2 OV_CLK# I 5VSB 3 VDDIO_SET0 Its 5VSB 2.5V 2.6V 2.7V 2.8V 0 0 1 1 VRAMSET1 VDDIO output with OV_CLK# = Low 2.55V 2.65V 2.75V 2.85V 5 Fault# Its Its 0 0 1 1 4 VDDIO_SET1 Its 5VSB System Fault Input Signal. Pull the pin low when any critical event alerted; the chip will shut the system down when the signal pulled low. ATX PS_ON# Signal Input. The PS_ON# signal of ATX power supply is routed through the chip for power fault control. 6 7 PS_ON_IN# PS_ON_OUT# OD12 -6- W83304D/W83304G Pin Descriptions, continued NO NAME I/O POWER SOURCE FUNCTION DESCRIPTION 8 9 10 11 12 13 14 VDD_GD VDD_EN VCC3 2.5VDDA GND 1.25VREF SS I OD24 P AO200mA P AO5mA AI/AO 5VSB 5VSB CPU Power Good Signal. The signal is inputted for power sequence control. Signal Output to Enable CPU Power. The signal output to enable CPU power for sequence control. Power VCC. VCC3 2.5V Power for CPU PLL Core. Power Ground. 3VSB 5VSB 1.25V Reference Voltage. Soft-Start Pin. A capacitor (0.1u) is attached in this pin for soft-start slope rate adjustment. Reference Current Input. An input current for internal circuit reference. Power VTT. A bi-direction linear regulator is provided to regulate voltage for DDR bus terminator. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ISET VTT_SINK VTT_SEN VTT_DRV VDDIO_SEN ISEN2 VDDIO_DRV2 ISEN1 VDDIO_DRV1 GND VLDT_SEN VLDT_DRV 5VSB LR2_SEN LR2_DRV LR1_SEN LR1_DRV AI/AO AO AI AO AI AI AO AI AO P AI AO P AI AO AI AO 5VSB 5VSB 5VSB 9VSB 9VSB Power VDDIO. A dual-channels linear regulator with current balancing architecture is provided for higher current DDR SDRAM application. Power Ground. 5VSB 9VSB Power VLDT. 1.2V power for LDT bus. Standby Power Pin. 5VSB 9VSB 5VSB 9VSB Linear Regulator 1. A general purpose linear regulator is provided to generate 1.2V~5.0V power for specific device. Linear Regulator 2. A general purpose linear regulator is provided to generate 1.2V~5.0V power for specific device. -7- Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G Pin Descriptions, continued NO NAME I/O POWER SOURCE FUNCTION DESCRIPTION 32 33 34 35 36 36 37 38 39 40 41 42 43 VAGP_SEN VAGP_DRV 3VSB_DRV 3VSB_SEN 5VDRV/3VDRV 5VDRV/3VDRV 5VUSB_DRV C1 C2 CHR_PMP 5VSB GND RSMRST# AI AO AO AI AO AO AO I I P P 5VSB 9VSB 9VSB 5VSB 9VSB 9VSB 9VSB 5VSB 5VSB 5VSB Power for AGP Core. 1.5V power is regulated for AGP core. Power 3.3VDL. A linear regulator and switch is combined to generate 3V dual power. Power for USB Device. A 5V switch power is provided for USB device and can be programmed for various USB application with configuration of pin 44. Charge Pump Pins. It supports achieve 10mA driving current and insures output voltage 9.5V or above. Standby Power Pin. Power Ground. OD12 Signal to Indicate Status of Standby Power. The signal will be pulled high to indicate the standby power stable. 5VUSB Power Type Setting Pin. 5VUSB_EN=Low, support power for USB device in S0, S3 state. 5VUSB_EN =High, support power for USB device in S0, S3, S5 state. Signal to Enable Miscellaneous Power. Power OK Signal form ATX Power Supply. ACPI Control Signals. 44 5VDL_EN I 5VSB 45 46 47 48 MISC_EN PWR_OK S3# S5# OD24 Its I I 5VSB 5VSB -8- W83304D/W83304G 4. BLOCK DIAGRAM S3# S5# PWR_OK# ALL_PWR_OK RSMRST# OV_CLK 5VUSB_EN MISC_EN VDD_GD VDD_EN VDDIO_SET0 VDDIO_SET1 PS_ON_IN# PS_ON_OUT# Fault# CHR_PMP C1 C2 VLDT_DRV VLDT_SEN Charge Pump 3.3VDL 3VDRV 3.3VSB_DRV 3.3VSB_SEN VTT_DRV VTT_SEN VTT SINK 1.25VREF 5VDRV 5VSB_DRV 5VUSB_EN VDDIO_DRV1 ISEN1 VDDIO_SEN VDDIO_DRV2 ISEN2 1.2VLDT Control Logic 1.25VTT 1.25VREF SS Soft Start 5VUSB ISET Ref. Current 2.5VRAM Linear Regulator Linear Regulator VAGP_DRV VAGP_SEN 1.5VAGP 2.5VDDA LR1_DRV LR1_SEN LR2_DRV LR2_SEN -9- Publication Release Date: April, 2006 Revision 0.51 VDDA_DRV W83304D/W83304G 5. ELECTRICAL SPECIFICATION 5.1 AC CHARACTERISTICS Vcc=5V ± 5 %, TA = 0°C to +70°C PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS VAGP Linear Regulator Nominal Output Voltage Nominal Output Voltage Regulation Under-Voltage Falling Threshold 1.25VREF Nominal Output Voltage Nominal Output Voltage 1.2VLDT Linear Regulator Nominal Output Voltage Nominal Output Voltage Regulation Under-Voltage Falling Threshold VDDIO Regulator VRAMSET0 87.5 1.2 1.25 5 V V % % OVA#=1 OVA#=0 1.25 1.3 Iload < 5mA; OVA#=1 Iload < 5mA; OVA#=0 86.67 1.5 1.55 5 V V % % OVA#=1 OVA#=0 VDDIO VOLTAGE SETTING OVA#=1 VRAMSET1 2.5V 2.6V 2.7V 2.8V 0 0 1 1 VRAMSET0 0 1 0 1 VRAMSET1 VDDIO VOLTAGE SETTING OVA#=0 VRAMSET1 2.55V 2.65V 2.75V 2.85V 0 0 1 1 84 5 VRAMSET0 0 1 0 1 % % Under-Voltage Falling Threshold Regulation - 10 - W83304D/W83304G AC CHARACTERISTICS, continued Vcc=5V ± 5 %, TA = 0°C to +70°C PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS 2.5VDDA Nominal Output Voltage Nominal Output Voltage Bus Terminator Nominal Output Voltage / V(VRAM2.5_SEN) Nominal Output Voltage 5VDUAL Switch Controller 5VDRV Output High Voltage 5VSBDRV Output High Voltage 5VUSB SS Sourcing Current 3.3VDual Under-Voltage Falling Threshold 5VDRV Output High Voltage 3VSBDRV Charge Pump Charge Pump Frequency Charge Pump Voltage Two linear regulator Nominal Output Voltage Linear regulator from1.2V~5V 9.5 180 KHz 9 3.3 78.79 % V Regulation 9 9 2.5 uA Cap Loading Cap Loading @ Soft-start Regulate a 1.25V for DDR bus termination Half of VDDIO voltage 2.5 2.55 Iload < 200mA; OVA#=1 Iload < 200mA; OVA#=0 50 % 1.25 V - 11 - Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G 6. APPLICATION CIRCUIT 5VSB VCC3 3 C1 100U DUAL/VSB/STR/VCC 3 DUAL/VSB/STR/VCC 3 VLR1=1.2/R3*(R1+R3) Q2 1 VLR1 R2 R C7 C R4 R 3VDUAL C8 C C3 47U Q3 1 VLR2 C4 47U VLR2=1.2/R4*(R2+R4) C2 1000U VCC3 2 2 1 Q4 C5 1000U C6 1500U 1 R3 R 3 2 R1 R 2 VAGP 2 3 Q1 1 Q5 3VDUAL 3 C9 1500U VCC3 W5VSB Q6 1 VCC5 2 C11 100U Q9 1 Q10 1 C14 2200p 5VUSB C16 1500U RSMRST#(to SB) 5VDL_EN MISC_EN PWR_OK(from ATX) C18 5VSB 5VSB R11 4.7K 0.1U R13 4.7K C21 0.1U ALL_PWR_OK OV_CLK# VDDIO_SET0 VDDIO_SET1 Fault# PS_ON_IN#(connect to MB) PS_ON_OUT#(to ATX) VDD_GD VDD_EN VCC3 5VSB 5VSB 5VSB VCC3 R19 4.7K R20 4.7K R21 4.7K R22 4.7K R23 4.7K VCC3 C26 1U C27 1U S3# S5# C15 0.1U W5VSB 37 38 39 40 41 42 43 44 45 46 47 48 3 2 5VSB 36 35 34 33 32 31 30 29 28 27 26 25 U1 1.2VLDT C12 2000U ISEN1 VDDIO_DRV1 Q7 1 3 Q8 1 VDDIO_DRV2 2 C10 1000U 3 3 R5 4m R6 4m 2 5VDRV/3VDRV 3VSB_SEN 3VSB_DRV VAGP_DRV VAGP_SEN LR1_DRV LR1_SEN LR2_DRV LR2_SEN 5VSB VLDT_DRV VLDT_SEN C13 0.1U 24 23 22 21 20 19 18 17 16 15 14 13 VDDIO_DRV1 ISEN1 VDDIO_DRV2 ISEN2 2 ISEN2 VDDIO ALL_PWR_OK OV_CLK# VDDIO_SET0 VDDIO_SET1 Fault# PS_ON_IN# PS_ON_OUT# VDD_GD VDD_EN VCC3 2.5VDDA GND 5VUSB_DRV C1 C2 CHR_PMP 5VSB GND RSMRST# 5VDL_EN MISC_EN PWR_OK S3# S5# W83304D GND VDDIO_DRV1 ISEN1 VDDIO_DRV2 ISEN2 VDDIO_SEN VTT_DRV VTT_SEN VTT_SINK ISET SS 1.25VREF C17 3000U 3 R7 4.7K VDDIO_SET0 VDDIO_SET1 R9 4.7K (OPT) R10 4.7K (OPT) R8 4.7K 5VSB Q11 1 1.25VREF(S0,S3) C19 3 0.1U R12 100K 2 VTT C20 1500U Q12 OV_CLK# 5VSB VDDIO_SET1 VDDIO_SET0 0 0 0 1 1 0 1 1 VDDIO 2.5V 2.6V 2.7V 2.8V R14 4.7K 5VSB 1 2 3 4 5 6 7 8 9 10 11 12 1 C22 1n (OPT) 2.5VDDA C25 1U C24 CAP R17 5VSB 5 W5VSB C23 1n (OPT) 5VDL_EN 2 R15 OV_CLK# 0 2.5VDDA,VDDIO,VLDT,AGP,1.25VREF ADD 4.7K 5OmV (OPT) 1 Normal R16 4.7K R18 4.7K (OPT) 5VSB 5VDL_EN 0 1 5VUSB STR DUAL - 12 - W83304D/W83304G 7. POWER SEQUENCE W83304D power sequence(RUN_MISC default) 8 2mS 4.3 3.7 5VSB RSMRST# PSIN# S3# S5# PSOUT# VCC AGP 2.5VDDA PWROK RUN_MISC V TT & V RAM & 1.25VREF V CORE _EN V CORE _PG 1.2VLDT 1.2VLDT_PG ALLPWR_OK Note: 1. When at power up sequence, the delay time between adjacent power planes is 5ms after the previous power plane is power-good. 2. When at power down sequence, the delay time between adjacent power planes is 20ms after the previous power plane is power-down. 3. After 1.2VLDT_PG=H and delay 20ms, the ALLPWR_OK will be High(ALLPWR_OK=H). 4. All “LUV” detect is enabled after the power plane have power-good. - 13 - Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G 8. ORDERING INSTRUCTION PART NO. PACKAGE REMARKS W83304D W83304G 48-pin LQFP 48-pin LQFP Pb-free package 9. HOW TO READ THE TOP MARKING inbond W83304D 214658302 310GBRA inbond W83304G 214658302 310GBRA 1st Line: Winbond Logo 2nd Line: Part_No W83304D, W83304G (Pb-free package) 3rd Line: lot no 4th Line: tracking code 310GBRA 310：date code,310 means package was made in ’03 week 10 G：Assembly ID, G means GR, A means ASE…etc. B：Chip Version, A means version A, B means version B RA：Winbond internal use - 14 - W83304D/W83304G 10. PACKAGE DIMENSION HD D A A2 36 25 24 A1 37 HE E 48 13 1 e b 12 c SEATING PLANE Y L1 Controlling dimension : Millimeters L θ Symbol Dimension in inch Dimension in mm Min Nom Max 0.002 0.004 0.053 0.055 0.006 0.008 0.004 0.006 0.272 0.276 0.272 0.276 0.014 0.350 0.350 0.018 0.006 0.057 0.010 0.008 0.280 0.280 Min Nom Max 0.05 1.35 0.15 0.10 6.90 6.90 0.35 8.90 8.90 0.45 0.10 1.40 0.20 0.15 7.00 7.00 0.50 9.00 9.00 0.60 1.00 0.15 1.45 0.25 0.20 7.10 7.10 0.65 9.10 9.10 0.75 A A1 A2 b c D E e HD HE L L1 Y 0 0.020 0.026 0.354 0.354 0.024 0.039 0.004 0.358 0.358 0.030 0.10 0 7 0 7 - 15 - Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 16 -