W83310DG

W inbond Bus Termination Regulator W83310DS/DG W83310DS Datasheet Revision History Pages 1 2 3 4 5 6 7 8 1 5 5 10,11 11 All 1 Dates May/03 May/03 May/03 Jul./03 Feb./04 Mar./04 Sep./04 May/05 Version 0.5 0.51 0.60 0.61 0.70 0.71 0.8 0.9 Version on Web N.A. N.A. N.A. N.A. N.A. N.A. N.A. N.A. Main Contents All versions before 0.5 are only for internal use. Typo corrected. Electrical characteristics update. Electrical characteristics update. Package dimension outline and Thermal data. Thermal data update. Add Pb-free part W83310DG. Add DDR II support spec Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83310DS/DG PRELIMINARY 1. General Description The W83310DS/DG is a linear regulator provides a power achieves continuous 2.0Amp bi-directional sinking and driving capability for a high speed bus terminator application. The chip simply implements a stable power supply which tracks half of input power dynamically for bus terminator with a single chip; it’s also can be fixed with the input of VREF1 and VREF2 pins following with setting of pin BOOT_SEL. The W83310DS/DG is promoted with small footprint 8-SOP 150mil power package. With W83310DS/DG design, a high integration, high performance, and cost-effective solution is promoted. 2. Features Regulates a bi-directional power with driving and sinking capability Provides achieve continuous 2.0Amp driving and sinking current Power MOSFET integrated Low external component count Low output voltage offset VCNTL Operates with +3.3V & 2.5 V power 8-SOP 150mil small power package Low cost and easy to use 3. Applications DDR/DDRII Bus Termination Regulator Active Termination Bus Intel® Springdale GMCH-VTT Support SSTL-2 SSTL-3 All Trademark and Brand name belong to their respective owners. 1 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY 4. Pin Configuration and Description - W83310DS/DG VIN GND VREF1 VOUT 1 2 3 4 8 7 VREF2 ENABLE VCNTL BOOT_SEL W 83310DS/DG 6 5 SYMBOL VIN GND VREF1 VOUT BOOT_SEL VCNTL ENABLE VREF2 PIN 1 2 3 4 5 6 7 8 Power ground. FUNCTION Main power input pin. Internal reference voltage source 1. Reference voltage on the pin will be referred with the value of pin BOOT_SEL set high. Voltage output pin. A signal for the chip reference voltage source selection. The function is designed for Intel® Springdale chipset GMCH_VTT application. Power for internal control logic use Chip function enable pin. 1: Enable; 0: Disable Internal reference voltage source 2. Reference voltage of the pin will be referred with the value of pin BOOT_SEL set low. All Trademark and Brand name belong to their respective owners. 2 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY 5. Application Circuit - W83310DS/DG for DDR SDRAM Application 2.5VREF R1 1K VRAM C1 1000u 1 2 3 DDRVTT 4 U1 VIN GND VREF1 VOUT VREF2 ENABLE VCTRL BOOTSEL 8 7 6 5 C2 10u C5 0.1U 3VDUAL ENABLE (0:DISABLE 1:ENABLE) R2 1K W 83310DS C3 1u C4 1500u - W83310DS/DG for Intel® Springdale GMCH_VTT Application 2.5VREF R1 R VCC2.5 R2 R C1 1000u 1 2 3 GMCHVTT 4 CPU_VTT GMCH_VTT U1 VIN GND VREF1 VOUT VREF2 ENABLE VCTRL BOOTSEL 8 7 6 5 C2 10u C5 0.1U VCC3 PWOK R3 R W83310DS/DG C3 1u C4 1500u BOOTSELECT BOOTSELECT=0 GMCHVTT=1.45V for Intel® NORTHWOOD CPU BOOTSELECT=1 GMCHVTT=1.225V for Intel® PRESCOTT CPU All Trademark and Brand name belong to their respective owners. 4 Ω 3 50 8 ( & ) ¨91¤"  3 3 0 5&( 7¤726©  R1: R2: R3 = 4.66: 1.00: 5.44 Ω 4 3 0 )( &$      ¡ ¡ §§¥£¡ (21'%#"¥!¦©¤¨¦¤¢  Ω Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY - Dual Layout of W83310DS/DG and W83310S-R2 for DDR VTT Application 2.5VREF R1 10K VRAM C1 1000u 1 2 3 D DRVTT 4 U1 VIN GND VREF1 VOUT VREF2 ENABLE VCTRL BOOTSEL 8 7 6 5 C5 100U C2 1u 3VDUAL R2 10K W 83310DS/DG C3 1u C4 1500u W83310S-R2, W83310DS/DG DUAL LAYOUT 6. Internal Block Diagram VCTRL VIN ENABLE VREF2 Control Logic VREF1 Control Logic Circuit VOUT BOOT_SEL GND All Trademark and Brand name belong to their respective owners. 4 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY 7. Electrical Characteristics AC CHARACTERISTICS Cout=1000uF, TA = 0°C to +70°C Parameter Symbol Output Offset Voltage Vos Load Regulation Input Voltage Range Operating Current of VCNTL Short Current Limit VIN VCNTL ICNTL ILMT 1.62 3.3 0.5 4.0 Min -5 Typ 0 0.8 0.8 Max +5 Units mV % 3.63 3.63 1 V mA A No Load(Iout=0A) Test Conditions Iout=0A Loading: 0A 2.0A Loading: 0A -2.0A Note: Load regulation is tested by using a 1ms current pulse and VOUT measuring. Cout=1000uF, TA = 0°C to +70°C Parameter Symbol Output Offset Voltage Vos Load Regulation Input Voltage Range Operating Current of VCNTL VREF1 Threshold trigger BOOT_SEL Threshold Trigger Short Current Limit ILMT VIN VCNTL ICNTL 1.62 3.3 0.5 0.8 0.2 1 0.2 4.0 Min -5 Typ 0 0.8 0.8 Max +5 Units mV % 3.63 3.63 1 V mA V V V V A No Load(Iout=0A) Output=High Output=Low BOOT_SEL=High BOOT_SEL=Low Test Conditions Iout=0A Loading: 0A 2.0A Loading: 0A -2.0A Note: Load regulation is tested by using a 1ms current pulse and VOUT measuring. Cout=1000uF, TA = 0°C to +70°C Parameter Symbol Output Offset Voltage Vos Load Regulation Input Voltage Range Operating Current of VCNTL VREF2 Threshold trigger BOOT_SEL Threshold Trigger Short Current Limit ILMT VIN VCNTL ICNTL 1.62 3.3 0.5 0.8 0.2 1 0.2 4.0 Min -5 Typ 0 0.8 0.8 Max +5 Units mV % 3.63 3.63 1 V mA V V V V A No Load(Iout=0A) Output=High Output=Low BOOT_SEL=High BOOT_SEL=Low Test Conditions Iout=0A Loading: 0A 2.0A Loading: 0A -2.0A Note: Load regulation is tested by using a 1ms current pulse and VOUT measuring. All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May Revision 0.9 5 W83310DS/DG PRELIMINARY 8. Typical Operating Waveform Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.225V; 2.0Amp pulse driving current. Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.225V; 2.0Amp pulse sinking current. All Trademark and Brand name belong to their respective owners. 6 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.45V; 2.0Amp pulse driving current. Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.45V; 2.0Amp pulse sinking current. All Trademark and Brand name belong to their respective owners. 7 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.25V; 2.0Amp pulse driving current. Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.25V; 2.0Amp pulse sinking current. All Trademark and Brand name belong to their respective owners. 8 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY Short Current Limit - VCTRL = 3.3V - VCTRL = 3.6V All Trademark and Brand name belong to their respective owners. 9 Publication Release Date: 2005/May Revision 0.9 W83310DS PRELIMINARY 9. Package Dimension 8L Power SOP 150mil All Trademark and Brand name belong to their respective owners. 10 Publication Release Date: 2005/May Revision 0.90 W83310DS/DG 10. Thermal Performance Component Temp. ( C) Package 100 Die 145 Downset 79 Lead 78 Ambient 25 o o PRELIMINARY jc ( C /W) 14.7 Test on Four-Layer (2S2P) JEDEC Test Board Package PSOP-8 Power (W) 3.05 An area of 190mil*150mil on the top layer is use as a thermal pad for W83310DS and this is connected to the bottom layer by vias. The ja of the W83310DS mounted on this demo board is abo o o out 39 C /W.Assuming the TA=25 C and TJ=160 C,the maximum power dissipation is calculated as: PD(max)=(160-25)/39=3.46W 11. Ordering Information Part Number W 83310DS Package Type Power SOP-8 Production Flow 12. How to Read the Top Marking W83 310DS 249GA! Left line: Winbond logo st nd 1 & 2 line: W83310DS/DG – the part number 3rd line: Tracking code 318 G A 318: packages assembled in Year 03’, week 18 G: assembly house ID; O means OSE, G means GR, etc. A: the IC version W83 310DG 249GA! All Trademark and Brand name belong to their respective owners. 11 Publication Release Date: 2005/May Revision 0.90 W83310DS/DG PRELIMINARY Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2727 North First Street San Jose, California 95134 TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. All Trademark and Brand name belong to their respective owners. 12 Publication Release Date: 2005/May Revision 0.90