W83310S-R

W inbond Bus Termination Regulator W83310S-R/N Date: April 13, 2005 Revision: 1.0 W83310S-R/N Table of Content1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. GENERAL DESCRIPTION......................................................................................................1 FEATURES..............................................................................................................................1 APPLICATIONS.......................................................................................................................1 PIN CONFIGURATION AND DESCRIPTION.........................................................................2 APPLICATION CIRCUIT .........................................................................................................3 INTERNAL BLOCK DIAGRAM................................................................................................5 ELECTRICAL CHARACTERISTICS .......................................................................................6 TYPICAL OPERATING WAVEFORM.....................................................................................7 PACKAGE DIMENSION........................................................................................................10 ORDERING INFORMATION.................................................................................................11 HOW TO READ THE TOP MARKING ..................................................................................11 REVISION HISTORY ............................................................................................................12 I Publication Release Date: April 13, 2005 Revision 1.0 W83310S-R/N 1. GENERAL DESCRIPTION The W83310S-R/N is a linear regulator which provides achieves 1.5Amp bi-directional sinking and driving capability for DDR SDRAM bus terminator application. The chip simply implement a stable power supply which can track half of input power dynamically for bus terminator with a single chip; that is the chip integrates two power MOSFETs. There is no any external power device needed. The W83310S-R/N is promoted with small footprint 8-SOP 150mil package. With W83301S-R/N design, a high integration, high performance, and cost-effective solution is promoted. 2. FEATURES Regulates a bi-directional power with driving and sinking capability Provides achieve 1.5Amp driving and sinking current Power MOSFET integrated Low external component count Low output voltage offset Operates with +5V,+3.3V and +2.5V power Small package Low cost and easy to use 3. APPLICATIONS DDR Bus Termination Regulator Active Termination Bus SSTL-2 SSTL-3 1 Publication Release Date: April 13, 2005 Revision 1.0 W83310S-R/N 4. PIN CONFIGURATION AND DESCRIPTION - W83310S-R VIN GND VREF VOUT 1 2 3 4 8 VCNTL inbond W83310S-R 7 VCNTL 6 5 SYMBOL VIN GND VREF VOUT VCNTL VCNTL VCNTL VCNTL PIN 1 2 3 4 5 6 7 8 Power input pin. FUNCTION Ground. Reference voltage and Chip enable. Output voltage. Gate drive voltage. Gate drive voltage. Gate drive voltage. Gate drive voltage. - W83310S-N N/C GND VSEN VREF 1 2 3 4 8 VTT inbond W83310S-N 7 PVIN 6 5 2 Publication Release Date: April 13, 2005 Revision 1.0 W83310S-R/N SYMBOL N/C GND VSENSE VREF VDDQ AVIN PVIN VTT PIN 1 2 3 4 5 6 7 8 No internal connection. FUNCTION Ground. Feedback pin for regulating VTT. Internal reference voltage of VDDQ/2. Input for internal reference equal to VDDQ/2. Analog input pin. Power input pin. Output voltage for connection to termination resistors. 5. APPLICATION CIRCUIT - W83310S-R 2.5V C1 1000u 3 VOU Enable# 1 2 Q 2N7002 C 1u C 1u 1 2 3 4 C U VI GN VRE VOU VCNT VCNT VCNT VCNT 8 7 6 5 C 1u 3.3V W83310S-R 1000u 3 Publication Release Date: April 13, 2005 Revision 1.0 W83310S-R/N - W83310S-N VTT U 1 2 3 4 C 1 N/ GN VSE VRE VTT PVI AVI VDD 8 7 C 6 5 C 1 1000 3.3 C 1 C 1000 2.5 VRE W83310S-N 4 Publication Release Date: April 13, 2005 Revision 1.0 W83310S-R/N 6. INTERNAL BLOCK DIAGRAM - W83310S-R VCNTL VIN 5K VREF 5K Control Logic VOUT - W83310S-N GND VDDQ AVIN PVIN 5K VREF Control Logic Ci it 5K VTT VSEN GND 5 Publication Release Date: April 13, 2005 Revision 1.0 W83310S-R/N 7. ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS W83310S-R VIN=2.5V,VCNTL=3.3V,VREF=1.25V,Cout=100uF, TA = 0°C to +70°C Parameter Output Offset Voltage Load Regulation VIN VCNTL ICNTL 0.4 0.1 ISHDN 10 Symbol VOS Min -5 Typ 0 0.8 0.8 2.5 3.3 0.5 1 % Max +5 Units mV Test Conditions IOUT=0A Loading: 0A 1.5A Loading: 0A -1.5A Input Voltage Range Operating Current of VCNTL Shutdown Threshold Trigger Shutdown Current V mA V V uA No Load(IOUT=0A) Output=High Output=Low VREF