W83320S

W83320S/W83320G W inbond N-Channel FET Synchronous Buck Regulator Controller W 83320S W 83320G -1- Publication Release Date: January 10, 2006 Revision 0.51 W83320S/W83320G W83320S Data Sheet Revision History PAGES DATES VERSION VERSION ON WEB MAIN CONTENTS 1 2 N.A. N.A. N.A. N.A. 0.50 0.51 N.A. N.A. All version before 0.5 are for internal use only. Add Pb-free part no :W83320G Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -2- W83320S/W83320G Table of Content1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. GENERAL DESCRIPTION ......................................................................................................... 4 FEATURES ................................................................................................................................. 4 APPLICATIONS .......................................................................................................................... 4 PIN-OUT ..................................................................................................................................... 5 PIN DESCRIPTION..................................................................................................................... 6 INTERNAL BLOCK DIAGRAM ................................................................................................... 7 APPLICATION CIRCUIT............................................................................................................. 9 ELECTRICAL CHARACTERISTICS......................................................................................... 10 TYPICAL PERFORMANCE CHARACTERISTICS................................................................... 11 PACKAGE DIMENSION OUTLINE........................................................................................... 16 ORDERING INSTRUCTION ..................................................................................................... 17 HOW TO READ THE TOP MARKING...................................................................................... 17 -3- Publication Release Date: January 10, 2006 Revision 0.51 W83320S/W83320G 1. GENERAL DESCRIPTION The W83320S is a high-speed, N-Channel synchronous buck regulator controller optimized for wide reference input range. The W83320S employs adjustable frequency ranging from 100 KHz to 400 KHz voltage-mode PWM control architecture. The regulator is biased from a 5V rail and the power for the high-side MOSFET can be supplied by a separate 12V rail or supplied from the internal charge pump. A Current limit protection is implemented by monitoring the voltage drop across the switch ON resistance of the low-side MOSFET. This method can eliminate the requirement of extra current sensing resistor and avoids false trigger of OC protection when VIN varies efficiently. The adaptive non-overlapping MOSFET gate drivers help avoid potential shoot-through problems while maintaining high efficiency. All these together with Power-good flag, enable and soft start features make power sequencing easy. 2. FEATURES 1.8V to 5V power stage input voltage Providing +/-1.5% reference voltage Power Good flag Current limit without sense resistor Soft start Switching frequency from 100 kHz to 400 kHz Tiny plastic SOP-14 package 3. APPLICATIONS DDR SDRAM and AGP core power for Desktop PC Set-Top Boxes/ Home Gateways Core Logic Regulators High-Efficiency Buck Regulation -4- W83320S/W83320G 4. PIN-OUT LGATE VDD VDDA PWOK GNDA SS COMP 1 2 3 4 5 6 7 14 13 12 ISEN GND UGATE BOOT BG_REF VREF FB W83320S 11 10 9 8 -5- Publication Release Date: January 10, 2006 Revision 0.51 W83320S/W83320G 5. PIN DESCRIPTION PIN NAME FUNCTION 1 2 3 4 5 6 7 8 LGATE VDD VDDA PWROK GNDA SS COMP FB Low-Side N-Channel MOSFET Gate Drive Pin. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET turned off. +5V supply rail for the lower gate driver and control logic circuit. VDDA: +5V supply rail for the chip. Power OK. Open drain output. This pin will be opened in following conditions: 1. No over-current detected; 2. VREF_IN >0.6V; 3. FB > 75% of VREF_IN; 4. SS >3V. Ground for analog circuit. Connect it to system ground. Soft Start Pin. A capacitor should be attached in this pin to ground for soft start output clamping. This capacitor, along with an internal 12uA current source, set the output clamp ramp up speed. Internal Error Amplifier Output Pin. This pin is available for compensation of the control loop. Inverting Input of the Error Amplifier. This pin is available for compensation of the control loop. Non-inverting Input of the Error Amplifier. Voltage on this pin provides reference input to the PWM control loop. When the VREF_IN voltage is less than 0.27V, the PWM is shut-down and the H_DRV and L_DRV are driven low. Due to its wide input range (0 ~ 3.6V), the VREF_IN voltage can be raised slowly to perform the input clamp function. Besides, a special function is implemented in this IC to inform the reference provider of over current alarm. Each time as the OC occurs, VREF_IN will be short to GND (through 170 ohms) for about 5~10uS. The reference provider can be aware of the OC condition by detecting this pulse. Internal Bandgap Reference Voltage Output. Supply rail for the high-side MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage or a separate 12V supply can be used. High-Side N-Channel MOSFET Gate Drive Pin. This pin is also monitored by the adaptive shoot through protection circuitry to determine when the high-side MOSFET has turned off. Ground for signal level circuit. Connect it to system ground. Current limit threshold setting. Connect a resistor (ROCSET) between this pin and the drain of the low-side MOSFET. An internal 72uA current source will flow through RISEN and cause a fixed voltage drop on it while the low-side MOSFET is turned on. In the mean while, the W83320S compares the voltage drop with the voltage across the low-side MOSFET and determines whether the current limit has been reached. The equation for over-current limit is: ILIM = (72uA * RISEN)/RDSON 9 VREF 10 11 12 13 BG_REF BOOT UDRV GND 14 ISEN -6- W83320S/W83320G 6. INTERNAL BLOCK DIAGRAM 12µA . SS VDDA VDD POR 72µA Soft Start 0.6V Logic . . . ISEN Control Logic BOOT UGATE VREF FB COMP BG_REF .. X0.7 + - EA Output Clamp . Oscillator Gate Control + - Logic VDD IREF & VREF LGATE GND GNDA -7- Publication Release Date: January 10, 2006 Revision 0.51 W83320S/W83320G Soft-Start When VDDA and VDD ramp over 4.3V and the voltage at pin VREF ramps over 0.27V; the soft start capacitor begins to charge through an internal 12uA (IREF/2) current source. The error amplifier (and the PWM duty) is both output clamped by the voltage on soft-start pin VSS and input clamped by the voltage on VREF. There are two ways to soft start the power that’s following the rising of the slower one between VSS or VREF; during soft-start, PWOK is forced to low and the internal Over-Current Protection is triggered to work. 0.4V to 1.9V of VSS is roughly mapping to 0 to 100% pulse-width. Smaller than 0.27V on VREF will disable the PWM controller and discharge CSS. MOSFET Gate Drivers The power for the high-side driver is flowing through the BOOT pin. This voltage can be supplied by a separate, higher voltage source, or supplied from a local charge pump structure or combination of the two. Since the voltage of the low-side MOSFET gate and the high-side MOSFET gate are being monitored to determine the state of the MOSFET, it should be taken carefully to add external components between the gate drivers and their respective MOSFET gates. Doing so may interfere with the shootthrough protection. Current Limit Current limit is implemented by sensing the voltage across the low-side MOSFET while it is ON. This method enhances the converter's efficiency and reduces total cost by eliminating a current sensing resistor. While low-side MOSFET is turned on, a constant current of 72uA (IREF X 3) is forced through ROCSET which is an external resistor connected between phase and ISEN, causing a fixed voltage drop. This fixed voltage is compared against VDS and if the latter is higher, the chip enters current limit mode. In the current limit mode both the high-side and low-side MOSFETS are turned off and the soft start capacitor CSS will be discharged immediately. The VREF is shorted to GND for 5~10uS to indicate the over current condition. After a 5mS delay, a soft-start cycle is initiated. If the cause of the over-current is still present after the delay interval, the current limit would be triggered again. The shut down - delay - soft start cycle will be repeated indefinitely until the over-current event been removed. Input Tracking When the VREF voltage is less than 0.3V, the PWM is shut-down and the UGATE and LGATE are driven low. Due to its wide input range (0 ~ 3.6V), this chip is suitable for reference input tracking application. But note that the chip will be shut-down when VREF