W83627THF

Winbond LPC I/O W83627THF Date: August 7, 2003 Revision: 0.8 W83627THF W83627THF Data Sheet Revision History PAGES 1 2 3 4 N.A. P.104 P.117~120 P.116~122 P.7 P.18 DATES 01/16/2003 03/25/2003 04/10/2003 08/07/2003 VERSION 0.50 0.60 0.70 0.80 WEB VERSION MAIN CONTENTS First published preliminary version. SUSLED data correction. Add Item 7.8.9 Update Appendix A to demo circuit Add Block Diagram Add description for GP26(Pin93) Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -1- Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES ................................................................................................................................. 3 BLOCK DIAGRAM ...................................................................................................................... 7 PIN CONFIGURATION ............................................................................................................... 8 PIN DESCRIPTION..................................................................................................................... 9 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 LPC Interface ................................................................................................................ 10 FDC Interface................................................................................................................ 11 Multi-Mode Parallel Port ............................................................................................... 12 Serial Port Interface ...................................................................................................... 14 KBC Interface................................................................................................................ 15 Hardware Monitor Interface .......................................................................................... 16 Game Port..................................................................................................................... 17 General Purpose I/O Port ............................................................................................. 18 5.8.1 5.8.2 5.8.3 5.8.4 General Purpose I/O Port 1 (Power source is Vcc) ........................................................18 General Purpose I/O Port 2 (Power source is Vcc) ........................................................18 General Purpose I/O Port 3, 4 (Power source is VSB) ...................................................19 General Purpose I/O Port 5 (Power source is Vcc) ........................................................20 5.9 5.10 6. 7. Power Pins.................................................................................................................... 20 GPIO PIN Power Source .............................................................................................. 20 GENERAL PURPOSE I/O......................................................................................................... 21 HARDWARE MONITOR ........................................................................................................... 24 7.1 7.2 7.3 General Description ...................................................................................................... 24 Access Interface ........................................................................................................... 24 Analog Inputs ................................................................................................................ 26 7.3.1 7.3.2 7.3.3 Monitor over 4.096V voltage:..........................................................................................26 CPUVCORE voltage detection method: .........................................................................27 Temperature Measurement Machine..............................................................................28 Fan speed count.............................................................................................................29 Fan speed control...........................................................................................................31 Thermal Cruise mode .....................................................................................................32 Fan Speed Cruise mode.................................................................................................33 Manual Control Mode .....................................................................................................34 7.4 FAN Speed Count and FAN Speed Control ................................................................. 29 7.4.1 7.4.2 7.5 SmartFanTM Control ...................................................................................................... 32 7.5.1 7.5.2 7.5.3 - II - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.6 SMI# Interrupt Mode ..................................................................................................... 34 7.6.1 7.6.2 7.6.3 7.6.4 Voltage SMI# mode: .......................................................................................................34 Fan SMI# mode: .............................................................................................................34 The W83627THF temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes: ............35 The W83627THF temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6...................................................36 7.7 7.8 OVT# Interrupt Mode .................................................................................................... 37 Registers and RAM....................................................................................................... 38 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 7.8.6 7.8.7 7.8.8 7.8.9 7.8.10 7.8.11 7.8.12 7.8.13 7.8.14 7.8.15 7.8.16 7.8.17 7.8.18 7.8.19 7.8.20 7.8.21 7.8.22 7.8.23 7.8.24 7.8.25 7.8.26 7.8.27 7.8.28 7.8.29 7.8.30 7.8.31 Address Port (Port x5h) ..................................................................................................38 Data Port (Port x6h)........................................................................................................38 Configuration Register  Index 40h...............................................................................39 Interrupt Status Register 1 Index 41h .........................................................................39 Interrupt Status Register 2  Index 42h ........................................................................40 SMI# Mask Register 1  Index 43h ...............................................................................41 SMI# Mask Register 2  Index 44h ...............................................................................41 Reserved Register  Index 45h—46h ...........................................................................41 Fan Divisor Register I  Index 47h................................................................................42 Value RAM  Index 20h- 3Fh......................................................................................42 Device ID Register - Index 49h.....................................................................................44 Reserved Register  Index 4Ah ..................................................................................44 Fan Divisor Register II - Index 4Bh...............................................................................44 SMI#/OVT# Control Register- Index 4Ch .....................................................................45 FAN IN/OUT and BEEP Control Register- Index 4Dh ..................................................46 Register 50h ~ 5Fh Bank Select Register - Index 4Eh .................................................47 Winbond Vendor ID Register - Index 4Fh.....................................................................47 Winbond Test Register -- Index 50h - 55h (Bank 0) .....................................................48 BEEP Control Register 1-- Index 56h (Bank 0) ............................................................48 BEEP Control Register 2-- Index 57h (Bank 0) ............................................................49 Chip ID -- Index 58h (Bank 0) .......................................................................................49 Diode Selection Register -- Index 59h (Bank 0) .........................................................50 Reserved -- Index 5Ah (Bank 0) ...................................................................................50 Reserved -- Index 5Bh (Bank 0) ...................................................................................50 Reserved -- Index 5Ch (Bank 0) ...................................................................................50 VBAT Monitor Control Register -- Index 5Dh (Bank 0) .................................................51 Reserved Register --5Eh (Bank 0)................................................................................51 Reserved Register --5Fh (Bank 0)................................................................................51 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1) .. .....................................................................................................................................52 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1)52 CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1) ................53 - III - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.32 7.8.33 7.8.34 7.8.35 7.8.36 7.8.37 7.8.38 7.8.39 7.8.40 7.8.41 7.8.42 7.8.43 7.8.44 7.8.45 7.8.46 7.8.47 7.8.48 7.8.49 7.8.50 7.8.51 7.8.52 7.8.53 7.8.54 7.8.55 7.8.56 7.8.57 7.8.58 7.8.59 7.8.60 7.8.61 7.8.62 7.8.63 7.8.64 7.8.65 7.8.66 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1) ..53 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) ...54 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1) .........................................................................................................................54 CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 1) ..................................................................................................................................55 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2)... .....................................................................................................................................55 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2)56 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2).................56 AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2) ..57 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) ...57 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) ........................................................................................................................58 AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 2) ..................................................................................................................................58 Interrupt Status Register 3 -- Index 50h (BANK4).........................................................59 SMI# Mask Register 3 -- Index 51h (BANK 4)............................................................59 Reserved Register -- Index 52h (Bank 4) .....................................................................60 BEEP Control Register 3-- Index 53h (Bank 4) ............................................................60 SYSTIN Temperature Sensor Offset Register -- Index 54h (Bank 4) ...........................60 CPUTIN Temperature Sensor Offset Register -- Index 55h (Bank 4) ...........................61 AUXTIN Temperature Sensor Offset Register -- Index 56h (Bank 4) ...........................61 Reserved Register -- Index 57h--58h (Bank4) ..............................................................61 Real Time Hardware Status Register I -- Index 59h (Bank 4).......................................62 Real Time Hardware Status Register II -- Index 5Ah (Bank 4) .....................................63 Real Time Hardware Status Register III -- Index 5Bh (Bank 4) ....................................64 Reserved Register -- Index 5Ch (Bank 4).....................................................................64 Reserved Register -- Index 5Dh (Bank 4).....................................................................64 Value RAM 2 Index 50h - 5Ah (BANK 5) ..................................................................64 Winbond Test Register -- Index 50h (Bank 6) ..............................................................65 Reserved Register--Index00h (Bank 0) ........................................................................65 SYSFANOUT Output Value Control Register-- 01h (Bank 0) .......................................65 Reserved Register—Index02h (Bank 0) .......................................................................66 CPUFANOUT Output Value Control Register-- 03h (Bank 0).......................................66 FAN Configuration Register I -- Index 04h (Bank 0) .....................................................66 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register -- Index 05h (Bank 0) ........................................................................................................................67 CPUTIN Target Temperature Register/ CPUFANIN Target Speed Register -- Index 06h (Bank 0) ........................................................................................................................68 Tolerance of Target Temperature or Target Speed Register -- Index 07h (Bank 0) ........68 SYSFANOUT Stop Value Register -- Index 08h (Bank 0) ............................................69 - IV - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.67 7.8.68 7.8.69 7.8.70 7.8.71 7.8.72 7.8.73 7.8.74 7.8.75 7.8.76 7.8.77 7.8.78 7.8.79 7.8.80 7.8.81 7.8.82 7.8.83 7.8.84 7.8.85 CPUFANOUT Stop Value Register -- 09h (Bank 0)......................................................69 SYSFANOUT Start-up Value Register -- Index 0Ah (Bank 0) ......................................69 CPUFANOUT Start-up Value Register -- Index 0Bh (Bank 0) ......................................70 SYSFANOUT Stop Time Register -- Index 0Ch (Bank 0).............................................70 CPUFANOUT Stop Time Register -- Index 0Dh (Bank 0) ............................................71 Fan Output Step Down Time Register -- Index 0Eh (Bank 0) .......................................71 Fan Output Step Up Time Register -- Index 0Fh (Bank 0)............................................72 Reserved Register—Index10h (Bank 0) .......................................................................72 AUXFANOUT Output Value Control Register-- 11h (Bank 0) .......................................72 FAN Configuration Register II -- Index 12h (Bank 0) ....................................................73 AUXTIN Target Temperature Register/ AUXFANIN Target Speed Register -- Index 13h (Bank 0) ........................................................................................................................74 Tolerance of Target Temperature or Target Speed Register -- Index 14h (Bank 0) .....74 AUXFANOUT Stop Value Register -- Index 15h (Bank 0) ............................................75 AUXFANOUT Start-up Value Register -- Index 16h (Bank 0).......................................75 AUXFANOUT Stop Time Register -- Index 17h (Bank 0) .............................................76 VRM & OVT Configuration Register -- Index 18h (Bank 0)...........................................76 Reserved -- Index 19h (Bank 0)....................................................................................77 User Defined Register -- Index 1A- 1Bh (Bank 0).........................................................77 Reserved Register-- Index 1Ch-1Fh (Bank 0) ..............................................................77 8. PLUG AND PLAY CONFIGURATION ...................................................................................... 78 8.1 Compatible PnP ............................................................................................................ 78 8.1.1 8.1.2 8.1.3 Extended Function Registers .........................................................................................78 Extended Functions Enable Registers (EFERs) .............................................................79 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) .......................................................................................................................................79 Enter the extended function mode..................................................................................79 Configuration the configuration registers ........................................................................80 Exit the extended function mode ....................................................................................80 Software programming example.....................................................................................80 8.2 Configuration Sequence ............................................................................................... 79 8.2.1 8.2.2 8.2.3 8.2.4 9. CONFIGURATION REGISTER................................................................................................. 81 9.1 Chip (Global) Control Register...................................................................................... 81 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 Logical Device 0 (FDC) ..................................................................................................87 Logical Device 1 (Parallel Port) ......................................................................................91 Logical Device 2 (UART A).............................................................................................92 Logical Device 3 (UART B).............................................................................................93 Logical Device 5 (KBC) ..................................................................................................95 Logical Device 7 (Game Port and MIDI Port and GPIO Port 1 and 5) ............................96 -V- Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 9.1.7 9.1.8 Logical Device 8 (GPIO Port 2 This power of the Port is VCC source)...........................97 Logical Device 9 (GPIO Port 3, 4. These two ports are powered by VSB) .....................99 9.2 9.3 10. 10.1 10.2 11. 11.1 11.2 11.3 12. 13. 14. Logical Device A (ACPI) ............................................................................................. 100 Logical Device B (Hardware Monitor) ......................................................................... 109 Absolute Maximum Ratings ........................................................................................ 110 DC Characteristics ...................................................................................................... 110 Parallel Port Extension FDD ....................................................................................... 115 Parallel Port Extension 2FDD ..................................................................................... 116 Four FDD Mode .......................................................................................................... 116 ELECTRICAL CHARACTERISTICS....................................................................................... 110 APPLICATION CIRCUITS ...................................................................................................... 115 HOW TO READ THE TOP MARKING.................................................................................... 117 PACKAGE DIMENSIONS ....................................................................................................... 118 APPENDIX A : DEMO CIRCUIT ............................................................................................. 119 - VI - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 1. GENERAL DESCRIPTION W83627THF is a Winbond LPC I/O product. It integrates the following major peripheral functions in a chip: the disk driver adapter (FDC), Serial port (UART), Parallel port (SPP/EPP/ECP), Keyboard controller (KBC), SIR, Game port, MIDI port, Hardware Monitor, ACPI, On Now Wake-Up features. The disk drive adapter functions of W83627THF include a floppy disk drive controller compatible with the industry standard 82077/765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83627THF greatly reduces the number of components required for interfacing with floppy disk drives. The W83627THF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s, 1 Mb/s, and 2 Mb/s. The W83627THF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupts system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps, which support higher speed modems. In addition, the W83627THF provides IR functions: IrDA 1.0 (SIR for 1.152K bps) The W83627THF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature demand of Windows 95/98TM, which makes system resource allocation more efficient than ever. The W83627THF provides functions that complies with ACPI (Advanced Configuration and Power Interface), which includes support of legacy and ACPI power management through PME# or PSOUT# function pins. For OnNow keyboard Wake-Up, OnNow mouse Wake-Up. The W83627THF also has auto power management to reduce the power consumption. The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable ROM and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEY Phoenix MultiKey/42 TM TM -2, , or customer code. The W83627THF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. -1- Publication Release Date: August 7, 2003 Revision 0.8 W83627THF The W83627THF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide. Moreover, W83627THF is made to meet the specification of PC2001's requirement in the power management: ACPI 1.0/1.0b/2.0 and DPM (Device Power Management). The W83627THF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices. They are very important for an entertainment or consumer computer. The W83627THF supports hardware status monitoring for personal computers. It can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly. Moreover, W83627THF support the Smart Fan control system, including the “Thermal CruiseTM” and “Speed CruiseTM” functions. Smart Fan can make system more stable and user friendly. The special characteristic of Super I/O product line is to avoid power rails short. This is especially true to a multi-power system where power partition is much more complex than a single-power one. Special care might be applied during layout stage or the IC will fail even though its intended function is OK. -2- Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 2. FEATURES General Meet LPC Spec. 1.1 Support LDRQ#(LPC DMA), SERIRQ (serial IRQ) Compliant with Microsoft PC98/PC2001 Hardware Design Guide Support DPM (Device Power Management), ACPI Programmable configuration settings Single 24 or 48 MHz clock input FDC Compatible with IBM PC AT disk drive systems Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and underrun conditions Built-in address mark detection circuit to simplify the read electronics FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) Support up to four 3.5-inch or 5.25-inch floppy disk drives Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate Support 3-mode FDD, and its Win95/98/NT/2K/XP driver UART Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop bits generation -3- Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1) Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz Infrared Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps Parallel Port Compatible with IBM parallel port Support PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port Enhanced printer port back-drive current protection Keyboard Controller Asynchronous Access to Two Data Registers and One status Register Software compatibility with the 8042 Support PS/2 mouse Support port 92 Support both interrupt and polling modes Fast Gate A20 and Hardware Keyboard Reset 8 Bit Timer/ Counter Support binary and BCD arithmetic 6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency -4- Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Game Port Support two separate Joysticks Support every Joystick two axis (X, Y) and two button (A, B) controllers MIDI Port The baud rate is 31.25 K baud rate 16-byte input FIFO 16-byte output FIFO General Purpose I/O Ports 6 sets programmable general purpose I/O ports General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer output, power LED output, infrared I/O pins, KBC control I/O pins, suspend LED output, RSMRST# signal, PWROK signal, STR (suspend to DRAM) function, VID control function, OnNow Functions Keyboard Wake-Up by programmable keys Mouse Wake-Up by programmable buttons On Now Wake-Up from all of the ACPI sleeping states (S1-S5) -5- Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Hardware Monitor Functions Smart fan control system, support “Thermal CruiseTM” and “Speed CruiseTM” 3 thermal inputs from optionally remote thermistors or 2N3904 transistors or PentiumTM II/III/4 thermal diode output 4 external voltage detect inputs. 3 intrinsic voltage monitoring (typical for Vbat, +5VSB , +5VCC) 3 fan speed monitoring inputs 3 fan speed control (DC analog output) Build in Case open detection circuit WATCHDOG comparison of all monitored values Programmable hysteresis and setting points for all monitored items Over temperature indicate output Issue SMI#, IRQ, OVT# to activate system protection Winbond Hardware DoctorTM Support Intel LDCMTM compatible Package 128-pin PQFP -6- Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 3. BLOCK DIAGRAM LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ LPC Interface Joystick interface signals MSI MSO General-purpose I/O pins Hardware monitor channel and Vref Keyboard/Mouse data and clock Game Port MIDI FDC Floppy drive interface signals Serial port A, B interface signals IRRX IRTX URA, B GPIO IR HM PRT Printer port interface signals KBC ACPI -7- Publication Release Date: August 7, 2003 Revision 0.8 CPUTIN SYSTIN GP55 GP54 GP53 GP52 GP51 GP50 AUXFANIN CPUFANIN SYSFANIN AVCC CPUFANOUT SYSFANOUT AGND GP22 GP21/MSI IRQIN0/GP20/MSO GP17/GPSA2 GP16/GPSB2 GP15/GPY1 GP14/GPY2 GP13/GPX2 GP12/GPX1 GP11/GPSB1 GP10/GPSA1 4. PIN CONFIGURATION 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 W83627THF -8- DRVDEN0 IRQIN1/SMI# INDEX# MOA# OVT# DSA# AUXFANOUT DIR# STEP# WD# WE# VCC TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN PME# GND PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 3VCC LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AUXTIN VREF CPUVCORE VIN0 VIN1 VIN2 GP23 GP24 GP25 GP26 GP30/PWRGD GP31/3VSBSW# GP32/PLED GP33/WDTO IRRX/GP34 IRTX GP35 RIB# DCDB# PEN48/SOUTB SINB DTRB# RTSB# DSRB# CTSB# GP36 CASEOPEN# GP40 VBAT SLP_SX#/GP41 PWRCTL#/GP42 PWROK/GP43 RSMRST#/GP44 GP45 PSIN/GP46 PSOUT#/GP47 MDAT MCLK W83627THF Publication Release Date: August 7, 2003 Revision 0.8 SUSLED/GP37 KDAT KCLK 5VSB KBRST GA20M BEEP RIA# DCDA# GND PENKBC/SOUTA SINA PNPCSV/DTRA# HEFRAS/RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 W83627THF 5. PIN DESCRIPTION Note: Please refer to Section 6.2 DC CHARACTERISTICS for details. AOUT AIN INcs INt INtd INts INtsp3 INtu I/O8t I/O12t I/O12tp3 I/OD12ts I/OD12tp3 I/OD16cs I/OD24t OUT12tp3 OUT8 OUT12 OUT24 OD8 OD12 OD24 - Analog output pin - Analog input pin - CMOS level Schmitt-triggered input pin - TTL level input pin - TTL level input pin with internal pull down resistor - TTL level Schmitt-triggered input pin - 3.3V TTL level Schmitt-triggered input pin - TTL level input pin with internal pull up resistor - TTL level bi-directional pin with 8 mA source-sink capability - TTL level bi-directional pin with 12 mA source-sink capability - 3.3 V TTL level bi-directional pin with 12 mA source-sink capabilities - TTL level bi-directional Schmitt-triggered pin. - 3.3 V TTL level bi-directional pin. Open-drain output with 12 mA sink capability Open-drain output with 12 mA sink capability Open-drain output with 16 mA sink capability - CMOS level Schmitt-triggered bi-directional pin. - TTL level bi-directional pin. Open-drain output with 24 mA sink capability - 3.3V TTL level output pin with 12 mA source-sink capability - TTL level output pin with 8 mA source-sink capability - TTL level output pin with 12 mA source-sink capability - TTL level output pin with 24 mA source-sink capability - Open-drain output pin with 8 mA sink capability - Open-drain output pin with 12 mA sink capability - Open-drain output pin with 24 mA sink capability -9- Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 5.1 LPC Interface PIN 18 19 21 22 23 24-27 29 30 I/O INt OD8 INtsp3 OUT12tp3 I/OD12tp3 I/O12tp3 INtsp3 INtsp3 FUNCTION System clock input. According to the input frequency 24MHz or 48MHz, it is selectable through register. Default is 24MHz input. Generated PME event. PCI 33 MHz clock input. Encoded DMA Request signal. Serial IRQ input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host. SYMBOL CLKIN PME# PCICLK LDRQ# SERIRQ LAD[3:0] LFRAME# LRESET# - 10 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 5.2 FDC Interface PIN 1 I/O OD24 Drive Density Select bit 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion Step output pulses. This active low open drain output produces a pulse to move the head to another track. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Write enable. An open drain output. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). The read data input signal from the FDD. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by a 1 KΩ . The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). FUNCTION SYMBOL DRVDEN0 INDEX# 3 INcs MOA# DSA# 4 6 OD24 OD24 OD24 OD24 OD24 OD24 INcs DIR# 8 STEP# WD# WE# TRAK0# 9 10 11 13 WP# 14 INcs RDATA# 15 INcs HEAD# 16 OD24 DSKCHG# 17 INcs - 11 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 5.3 Multi-Mode Parallel Port PIN I/O PRINTER MODE: SLCT 31 INt An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. PRINTER MODE: PE 32 INt An active high input on this pin indicates that the printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: BUSY 33 INt An active high input indicates that the printer is not ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. PRINTER MODE: ACK# ACK# 34 INt An active low input on this pin indicates that the printer has received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: ERR# ERR# 45 INt An active low input on this pin indicates that the printer has encountered an error condition. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: SLIN# SLIN# 43 OD12 Output line for detection of printer selection. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: INIT# INIT# 44 OD12 Output line for the printer initialization. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: AFD# AFD# 46 OD12 An active low output from this pin causes the printer to auto feed a line after a line is printed. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. FUNCTION The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL - 12 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 3.3 Multi-Mode Parallel Port, continued SYMBOL PIN I/O PRINTER MODE: STB# FUNCTION An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD0 STB# 47 OD12 PD0 42 I/O12t Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WP2# PRINTER MODE: PD3 PD1 41 I/O12t PD2 40 I/O12t PD3 39 I/O12t Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD7 Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PD4 38 I/O12t PD5 37 I/O12t PD6 36 I/O12t PD7 35 I/O12t - 13 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 5.4 Serial Port Interface PIN 49 I/O INt INt I/O12t INt FUNCTION Clear To Send. It is the modem control input. CTSA# The function of these pins can be tested by reading bit 4 of the handshake status register. Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. RTSA# HEFRAS 51 I/O8t During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 kΩ is recommended if intends to pull up. (select 4EH as configuration I/O port′s address) UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. UART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. DTRA# PNPCSV# 52 I/O8t During power-on reset, this pin is pulled down internally and is defined as PNPCSV#, which provides the power-on value for CR24 bit 0 (PNPCSV#). A 4.7 kΩ is recommended if intends to pull up. (clear the default value of FDC, UARTs, PRT, Game port and MIDI port) UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Serial Input. It is used to receive serial data through the communication link. Serial Input. It is used to receive serial data through the communication link. SYMBOL CTSB# 78 DSRA# 50 DSRB# 79 INt RTSB# 80 I/O8t DTRB# SINA SINB 81 53 82 I/O8t INt INtt - 14 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 3.4 Serial Port Interface, continued SYMBOL PIN I/O FUNCTION UART A Serial Output. It is used to transmit serial data out to the communication link. SOUTA PENKBC 54 I/O8t During power-on reset, this pin is pulled down internally and is defined as PENKBC, which provides the power-on value for CR24 bit 2 (ENKBC). A 4.7 kΩ resistor is recommended if intends to pull up. (enable KBC) UART B Serial Output. During power-on reset, this pin is pulled down internally and is defined as PEN48, which provides the power-on value for CR24 bit 6 (EN48). A 4.7 k Ω resistor is recommended if intends to pull up. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. SOUTB PEN48 DCDA# DCDB# RIA# RIB# 83 I/O8t 56 84 57 85 INt INt INt INt 5.5 KBC Interface PIN 59 60 63 65 66 I/O OUT12 OUT12 I/OD16cs I/OD16cs I/OD16cs FUNCTION Gate A20 output. This pin is high after system reset. (KBC P21) Keyboard reset. This pin is high after system reset. (KBC P20) Keyboard Data. PS2 Mouse Clock. PS2 Mouse Data. GA20M KBRST KDAT MCLK MDAT SYMBOL - 15 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 5.6 Hardware Monitor Interface SYMBOL BEEP CASEOPEN# VIN0 VIN1 VIN2 CPUVCORE VREF AUXTIN CPUTIN SYSTIN OVT# AUXFANIN CPUFANIN SYSFANIN SYSFANOUT CPUFANOUT AUXFANOUT PIN 58 76 99 98 97 100 101 102 103 104 111 5 112 113 116 115 7 AOUT Fan speed control. Output analog voltage level to control the Fan's speed. I/O12ts 0V to +5V amplitude fan tachometer input. I/O OD8 INt AIN AIN AIN AIN AOUT AIN AIN AIN OD12 FUNCTION Beep function for hardware monitor. This pin is low after system reset. CASE OPEN. An active low input from an external device when case is opened. This signal can be latched if pin VBAT is connect to battery, even W83627THF is power off. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. Reference Voltage for temperature maturation. Temperature sensor 3 inputs. It is used for temperature maturation. Temperature sensor 2 inputs. It is used for CPU1 temperature maturation. Temperature sensor 1 input. It is used for system temperature maturation. Over temperature Shutdown Output. temperature is over temperature limit. It indicated the - 16 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 5.7 Game Port PIN 128 127 126 I/O INcs I/OD12cs INcs I/OD12cs I/OD12cs I/OD12cs I/OD12cs I/OD12cs 124 I/OD12cs 123 I/OD12cs I/OD12cs INcs I/OD12cs INcs I/OD12cs FUNCTION Active-low, Joystick I switch input 1. (Default) General purpose I/O port 1 bit 0. Active-low, Joystick II switch input 1. (Default) General purpose I/O port 1 bit 1. Joystick I timer pin. this pin connects to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 2. Joystick II timer pin. this pin connects to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 3. Joystick II timer pin. this pin connects to Y positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 4. Joystick I timer pin. this pin connects to Y positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 5. Active-low, Joystick II switch input 2. This pin has an internal pullup resistor. (Default) General purpose I/O port 1 bit 6. Active-low, Joystick I switch input 2. This pin has an internal pullup resistor. (Default) General purpose I/O port 1 bit 7. SYMBOL GPSA1 GP10 GPSB1 GP11 GPX1 GP12 GPX2 GP13 GPY2 GP14 GPY1 GP15 GPSB2 GP16 GPSA2 GP17 125 122 121 - 17 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 5.8 5.8.1 5.8.2 General Purpose I/O Port General Purpose I/O Port 1 (Power source is Vcc) see 3.7 Game Port General Purpose I/O Port 2 (Power source is Vcc) PIN 120 I/O I/OD12t OUT12 INt I/OD12t INtu I/OD12t I/OD12t I/OD12t I/OD12t I/OD12t OD24 INt FUNCTION General purpose I/O port 2 bit 0. MIDI serial data output. (Default) IRQ channel input 0. General purpose I/O port 2 bit 1. MIDI serial data input. It is internally pulled up by a 40 K ohms resistor. (Default) General purpose I/O port 2 bit 2. (Default) General purpose I/O port 2 bit 3. (Default) General purpose I/O port 2 bit 4. (Default) General purpose I/O port 2 bit 5. (Default) General purpose I/O port 2 bit 6. (Default) System Management Interrupt channel output. IRQ channel input 1. SYMBOL GP20 MSO IRQIN0 GP21 MSI GP22 GP23 GP24 GP25 GP26 SMI# IRQIN1 119 118 96 95 94 93 2 - 18 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 5.8.3 General Purpose I/O Port 3, 4 (Power source is VSB) PIN 92 91 90 89 88 87 86 64 75 73 I/O I/OD12t I/OD12t I/OD24t OUT24 I/OD12t OUT12 I/OD12ts INts OUT12 I/OD12t I/OD24t OUT24 I/OD8t I/OD12t INt I/OD12t OD12 I/OD12t OD12 I/OD12t OD12 I/OD12t I/OD12t INtd I/OD12t OD12 FUNCTION General purpose I/O port 3 bit 0. General purpose I/O port 3 bit 1. General purpose I/O port 3 bit 2. Power LED output. General purpose I/O port 3 bit 3. (Default) Watchdog time out output. General purpose I/O port 3 bit 4. IRRX input. (Default) Infrared Transmitter Output. (Default) General purpose I/O port 3 bit 5. (Default) General purpose I/O port 3 bit 7. Suspend LED output, it can program to flash when suspend state. This function can work without VCC. (Default) General purpose I/O port 4 bit 0. General purpose I/O port 4 bit 1. SLP_S3# input. (Default) General purpose I/O port 4 bit 2. This pin generates the PWRCTL# signal while the power failure. (Default) General purpose I/O port 4 bit 3. This pin generates the PWROK signal while the VCC come in. (Default) General purpose I/O port 4 bit 4. This pin generates the RSMRST signal while the VSB come in. (Default) General purpose I/O port 4 bit 5. General purpose I/O port 4 bit 6. Panel Switch Input. This pin is high active with an internal pull down resistor. (Default) General purpose I/O port 4 bit 7. Panel Switch Output. This signal is used for Wake-Up system from S5c o l d state. This pin is pulse output, active low. (Default) SYMBOL GP30 GP31 GP32 PLED GP33 WDTO GP34 IRRX IRTX GP35 GP37 SUSLED/ GP40 GP41 SLP_SX# GP42 PWRCTL# GP43 PWROK GP44 RSMRST# GP45 GP46 PSIN GP47 PSOUT# 72 71 70 69 68 67 - 19 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 5.8.4 General Purpose I/O Port 5 (Power source is Vcc) PIN 110 109 108 107 106 105 I/O I/O12tp3 I/O12tp3 I/O12tp3 I/O12tp3 I/O12tp3 I/O12tp3 FUNCTION General purpose I/O port 5 bit 0. General purpose I/O port 5 bit 1. General purpose I/O port 5 bit 2. General purpose I/O port 5 bit 3. General purpose I/O port 5 bit 4. General purpose I/O port 5 bit 5. SYMBOL GP50 GP51 GP52 GP53 GP54 GP55 Note. The GPIO Port 5 could be used as VID input / output function for VRD10. 5.9 Power Pins SYMBOL VCC 5VSB 3VCC AVCC VBAT AGND GND PIN 12, 48 61 28 114 74 117 20, 55 FUNCTION +5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. +3.3V power supply for driving 3V on host interface. Analog VCC input. Internally supplier to all analog circuitry. Battery voltage input. Analog ground. Ground. 5.10 GPIO PIN Power Source SYMBOL GPIO port 1 GPIO port 2 GPIO port 3 GPIO port 4 GPIO port 5 POWER SOURCE Vcc Vcc VSB VSB Vcc - 20 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 6. GENERAL PURPOSE I/O W83627THF provides 36 input/output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 36 GP I/O ports are divided into five groups . The first and fifth groups are configured through control registers in logical device 7, the second group in logical device 8, and the third and forth groups in logical device 9. Users can configure each individual port to be an input or output port by programming respective bit in selection register (CRF0/F3: 0 = output, 1 = input). Invert port value by setting inversion register (CRF2/F5: 0 = non-inverse, 1 = inverse). Port value is read/written through data register (CRF1/CRF4). Table 4-1 and 4-2 give more details on GPIO's assignment. Figure 4-1 shows the GP I/O port's structure. After power-on reset those ports default to perform basic input function which maintains its previous settings until a battery loss condition. SELECTION BIT 0 = OUTPUT 1 = INPUT 0 0 1 1 INVERSION BIT 0 = NON INVERSE 1 = INVERSE 0 1 0 1 Basic non-inverting output Basic inverting output Basic non-inverting input Basic inverting input Table 4-1 BASIC I/O OPERATIONS - 21 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Table 4-2 GP I/O PORT DATA REGISTER REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 GP I/O PORT GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP30 GP31 GP32 GP33 GP34 GP35 GP36 GP37 GP40 GP41 GP42 GP43 GP44 GP45 GP46 GP47 GP50 GP51 GP52 GP53 GP54 GP55 GP1(VCC POWER) GP2(VCC POWER) BIT 3 BIT 4 BIT 5 BIT 6 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 GP3(VSB POWER) GP4(VSB POWER) GP5(VCC POWER) - 22 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Figure 4-1 - 23 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7. HARDWARE MONITOR 7.1 General Description The W83627THF can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and properly. W83627THF provides LPC interface to access hardware . An 8-bit analog-to-digital converter (ADC) was built inside W83627THF. The W83627THF can simultaneously monitor 3 analog voltage inputs (addition monitor VBAT, 5VSB & 5VCC power), 3 fan tachometer inputs, 3 remote temperature inputs and one case-open detection signal. The remote temperature sensing can be performed by thermistors, 2N3904 NPN-type transistors, or directly from IntelTM CPU thermal diode output. Also the W83627THF provides: 3 analog outputs for fan speed control. Beep tone output for warning; SMI#(can through SERIRQ pin), OVT# signals for system protection events. Through the application software or BIOS, the users can read all the monitored parameters of system from time to time. And a pop-up warning can be also activated when the monitored item was out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM, or IntelTM LDCM (LanDesk Client Management), or other management application software. Also the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate one programmable and maskable interrupts. An optional beep tone could be used as warning signal when the monitored parameters are out of the preset range. 7.2 Access Interface W83627THF uses LPC Bus to access which the ports address of low byte (bit2~bit0) are defined in the port 5h and 6h. The other higher bits of these ports are set by W83627THF itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: Index port. Port 296h: Data port. The register structure is showed as the Figure 5-1 - 24 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Smart Fan Configuration Registers 00h-1Fh Configuration Register 40h Interrupt Status Registers 41h, 42h SMI# Mask Registers 43h-44h Fan Divisor Register I 47h Serial Bus Address 48h LPC Bus Monitor Value Registers 20h~3Fh Port 5h Device ID Index Register 49h Temperature 2, 3 Serial Bus Address 4Ah Fan Divisor Register I 4Bh SMI#/OVT# Control Register 4Ch Fan IN/OUT and BEEP/GPO# Control Register 4Dh Bank Select for 50h~5Fh Registers. 4Eh Winbond Vendor ID 4Fh BANK 0 Winbond Test Registers 50h~55h BANK 0 BEEP Control Registers 56h~57h BANK 0 Chip ID Register 58h BANK 0 Temperature Sensor Type Configuration & Fan Divisor Bit2 Registers 59h,5Dh BANK 1 CPUTIN Temperature Control/Staus Registers 50h~56h BANK 2 VTIN Temperature Control/Staus Registers 50h~56h BANK 4 Interrupt Status & SMI Mask Registers 50h~51h BANK 4 Beep Control Registers 53h BANK 4 Temperature Offset Registers 54h~56h BANK 4 Read Time Status Registers 59h~5Bh BANK 5 Monitor Value Registers 59h~5Bh Port 6h Data Register Figure 5-1 : LPC interface access diagram - 25 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.3 Analog Inputs The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU Vcore voltage, +3.3V, battery(pin 74), AVCC(pin 114) and 5VSB voltage can directly connected to these analog inputs. The +12V voltage inputs should be reduced a factor with external resistors so as to obtain the input range. As Figure 3.2 shows. AVCC Power Inputs VBAT 5VSB Pin 114 Pin 74 Pin 61 VIN1(+3.3V) CPUVCORE R1 V1 Positive Voltage Input R2 VIN0 Pin 98 Pin 100 Pin 99 8-bit ADC with 16mV LSB Negative Voltage Input V2 R5 R3 VIN2 Pin 97 R4 RTHM 10K@25 C, beta=3435K R 10K, 1% VREF R 30K, 1% AUXTIN CPUTIN SYSTIN CPUD+ CAP,3300p CPUDPin 102 Pin 103 Pin 104 Pin 101 Figure. 5-2 7.3.1 Monitor over 4.096V voltage: The +12V input voltage can be expressed as following equation. VIN 0 = V1 × R2 R1 + R2 The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node voltage of VIN0 can be subject to less than 4.096V for the maximum input range of the 8-bit ADC. - 26 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF The -12V input voltage can be expressed as following equation. VIN 2 = (V2 − 3.6) × R4 + 3.6, whereV2 = −12 R3 + R 4 The value of R3 and R4 can be selected to 232K Ohms and 56K Ohms, respectively, when the input voltage V2 is -12V. The node voltage of VIN2 can be subject to less than 4.096V for the maximum input range of the 8-bit ADC. The Pin 114 is connected to the power supply VCC with +5V. There are two functions in this pin with 5V. The first function is to supply internal analog power in the W83627THF and the second function is that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage. The W83627THF internal two serial resistors are 34K ohms and 51K ohms so that input voltage to ADC is 3V which is less than 4.096V of ADC maximum input voltage. The express equation can represent as follows. Vin = VCC × 51KΩ ≅ 3V 51KΩ + 34 KΩ where VCC is set to 5V. The Pin 61 is connected to 5VSB voltage. W83627THF monitors this voltage and the internal two serial resistors are 34K Ω and 51K Ω so that input voltage to ADC is 3V which less than 4.096V of ADC maximum input voltage. 7.3.2 CPUVCORE voltage detection method: W83627THF provides two detection methods for CPUVCORE(pin100). (1). VRM8 method: The LSB of this mode is 16mV. This means that the detected voltage equals to the reading of this voltage register multiplies 16mV. The formula is as the following: Detected Voltage = Re ading ∗ 0.016 V (2). VRM9 method: (Default) The LSB of this mode is 4.88mV which is especially designed for the low voltage CPU. The formula is as the following: Detected Voltage = Re ading ∗ 0.00488 + 0.69 V - 27 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.3.3 Temperature Measurement Machine The temperature data format is 8-bit two's-complement for sensor SYSTIN and 9-bit two'scomplement for sensor CPUTIN and AUXTIN. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the Bank1/Bank2 CR[50h] and the LSB from the Bank1/Bank2 CR[51h] bit 7. The format of the temperature data is show in Table 5-1. TEMPERATURE +125°C +25°C +1°C +0.5°C +0°C -0.5°C -1°C -25°C -55°C 8-BIT DIGITAL OUTPUT 8-Bit Binary 0111,1101 0001,1001 0000,0001 0000,0000 1111,1111 1110,0111 1100,1001 8-Bit Hex 7Dh 19h 01h 00h FFh E7h C9h Table 5-1 7.3.3.1 Monitor temperature from thermistor: 9-BIT DIGITAL OUTPUT 9-Bit Binary 0,1111,1010 0,0011,0010 0,0000,0010 0,0000,0001 0,0000,0000 1,1111,1111 1,1111,1110 1,1100,1110 1,1001,0010 9-Bit Hex 0FAh 032h 002h 001h 000h 1FFh 1FFh 1CEh 192h The W83627THF can connect three thermistors to measure three different environment temperature. The specification of thermistor should be considered to (1) β value is 3435K, (2) resistor value is 10K ohms at 25°C. In the Figure 5-2, the themistor is connected by a serial resistor with 10K Ohms, then connect to VREF (Pin 101). 7.3.3.2 Monitor temperature from Pentium IITM/Pentium IIITM thermal diode or bipolar transistor 2N3904 The W83627THF can alternate the thermistor to Pentium IITM/Pentium IIITM thermal diode interface or transistor 2N3904 and the circuit connection is shown as Figure 5-3. The pin of Pentium IITM/Pentium IIITM D- is connected to AGND and the pin D+ is connected to temperature sensor pin in the W83627THF. The resistor R = 30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C = 3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied together to act as a thermal diode. - 28 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF VREF R=30K,1% Bipolar Transistor Temperature Sensor VTIN R=30K,1% C=3300pF C B E 2N3904 W83627THF OR Pentium II/III CPU Therminal Diode D+ C=3300pF DAGND CPUTIN Figure 5-3 7.4 7.4.1 FAN Speed Count and FAN Speed Control Fan speed count Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can’t be over VCC. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as Figure 5-4 ~ 5-7. Determine the fan counter according to: Count = 1.35 ×10 6 RPM × Divisor In other words, the fan speed counter has been read from register CR28 or CR29 or CR2A, the fan speed can be evaluated by the following equation. 1.35 × 10 6 RPM = Count × Divisor The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are three bits for divisor. That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, RPM, and count . Publication Release Date: August 7, 2003 Revision 0.8 - 29 - W83627THF DIVISOR 1 2 (default) 4 8 16 32 64 128 NOMINAL RPM 8800 4400 2200 1100 550 275 137 68 TIME PER REVOLUTION 6.82 mS 13.64 mS 27.27 mS 54.54 mS 109.08 mS 218.16 mS 436.32 mS 872.64 mS COUNTS 153 153 153 153 153 153 153 153 70% RPM 6160 3080 1540 770 385 192 96 48 TIME FOR 70% 9.84 mS 19.48 mS 38.96 mS 77.92 mS 155.84 mS 311.68 mS 623.36 mS 1246.72 mS Table 5-2 +12V +5V Pull-up resister 4.7K Ohms +12V Pull-up resister 4.7K Ohms +12V FAN Out GND Fan Input Pin112 -113,5 +12V FAN Out 14K~39K Pin 112-113,5 Fan Input W83627THFD GND FAN Connector FAN Connector 10K W83627THFD Figure 5-4. Fan with Tach Pull-Up to +5V Figure 5-5. Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Register Attenuator +12V +12V +12V FAN Out GND Pull-up resister > 1K Pin 112-113,5 Fan Input Pull-up resister < 1K or totem-pole output +12V FAN Out > 1K Pin 112-113,5 Fan Input 3.9V Zener W83627THFD GND 3.9V Zener W83627THFD FAN Connector FAN Connector Figure 5-7. Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp Figure 5-6. Fan with Tach Pull-Up to +12V and Zener Clamp - 30 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.4.2 Fan speed control The W83627THF has a 4 bit DAC which produces 0 to 5 volts DC output that provides maximum 3 sets for fan speed control. The analog output can be programmed in the Bank0 Index 01h, Index 03h and Index 11h. The default value is 0xFY,Y is reserved nibble, that is default output value is 5 V. The expression of output voltage can be represented as follow , OUTPUT Voltage = AVCC × Programmed 4 - bit Register Value 16 The application circuit is shown as follow, IO+12V IO+12V Q1 R1 FANOUT 0 3 2 NPN 4 + LM358 1 C1 0.1U Tachometer output 11 IO-12V R3 28K FAN 3 2 1 R4 20K Figure 5-8 Must be take care when choosing the OP-AMP and the transistor. The OP-AMP is used for amplify the 5V range of the DC output up to 12V . The transistor should has a suitable β value to avoid its base current pulling down the OP-AMP ’s output and gain the common current to operate the fan at fully speed. - 31 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.5 SmartFanTM Control SmartFanTM Control provides two mechanisms. One is Thermal Cruise mode and the other is Fan Speed Cruise mode. No matter which mode you use, the FAN will full speed run at beginning. 7.5.1 Thermal Cruise mode There are maximum 3 pairs of Temperature/FANOUT control at this mode: SYSTIN with SYSFANOUT, CPUTIN with CPUFANOUT, AUXTIN with AUXFANOUT. At this mode, W83627THF provides the Smart Fan system which can control the fan speed automatically depend on current temperature to keep it with in a specific range. At first a wanted temperature and interval must be set (ex. 55 °C ± 3 °C) by BIOS, as long as the real temperature remains below the setting value, the fan will be off. Once the temperature exceeds the setting high limit temperature ( 58°C), the fan will be turned on with a specific speed set by BIOS (ex: 3.75 V) and automatically controlled its DC voltage output with the temperature varying. Three conditions may occur : (1) If the temperature still exceeds the high limit (ex: 58°C), DC Fan output voltage will increase slowly. If the fan has been operating in its fully speed but the temperature still exceeds the high limit(ex: 58°C) after 3 minutes, a warning message will be issued to protect the system. (2) If the temperature goes below the high limit (ex: 58°C), but above the low limit (ex: 52°C), the fan speed will be fixed at the current speed because the temperature is in the target area(ex: 52 °C ~ 58°C). (3) If the temperature goes below the low limit (ex: 52°C), DC Fan output voltage will decrease slowly to 0 until the temperature exceeds the low limit. Figure 5-9 and 5-10 give the illustration for Thermal Cruise Mode . A Tolerance Target Temperature Tolerance 52`C 5 2.5 0 58`C 55`C B C D DC Output Voltage Fan Start = 1.875 V Figure 5-9 - 32 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF D A Tolerance Target Temperature Tolerance 52`C DC Output Voltage 5 2.5 0 Figure 5-10 58`C 55`C B C Fan Start = 1.875V Fan Stop = 1.25V Fan Start = 1.875V One more protection is provided that DC FAN output voltage will not be decreased to 0 in the above (3) situation in order to keep the fans running with a minimum speed. By setting CR[12h] bit3-5 to 1, FAN output voltage will be decreased to the “ Stop Value ” which are defined at CR[08h],CR[09h] and CR[15h]. 7.5.2 Fan Speed Cruise mode There are 3 pairs of FANIN/FANOUT control at this mode: SYSFANIN with SYSFANOUT, CPUFANIN with CPUFANOUT, AUXFANIN with AUXFANOUT. At this mode, W83627THF provides the Smart Fan system which can control the fan speed automatically depend on current fan speeds to keep it with in a specific range. A wanted fan speed count and interval must be set (ex. 160 ± 10 ) by BIOS. As long as the fan speed count is the specific range, output voltage will keep the current value. If current fan speed count is higher than the high limit (ex. 160+10), output voltage will be increased to keep the count less than the high limit. Otherwise, if current fan speed is less than the low limit(ex. 160-10), output voltage will be decreased to keep the count higher than the low limit. See Figure 5-11 example. Count 170 160 150 5 2.5 0 A C DC Output Voltage Figure 5-11 - 33 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.5.3 Manual Control Mode Smart Fan control system can be disabled and the fan speed control algorithmic can be programmed by BIOS or application software. The programming method is just as section 5.4.2. 7.6 SMI# Interrupt Mode The SMI#/IRQIN1 pin(pin2) is a multi-function pin. The SMI# function is selected at Configuration Register CR[2Ah] bit 2. 7.6.1 Voltage SMI# mode: SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 5-12) 7.6.2 Fan SMI# mode: SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 5-13) High limit Low limit Fan Count limit SMI# * * * * SMI# * * *Interrupt Reset when Interrupt Status Registers are read Figure 5-12 Figure 5-13 - 34 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.6.3 The W83627THF temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes: (1) Comparator Interrupt Mode Setting the THYST (Temperature Hysteresis) limit to 127°C will set temperature sensor 1 SMI# to the Comparator Interrupt Mode. Temperature exceeds TO (Over Temperature) Limit causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the TO , the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below TO. (Figure 5-14) . Setting the THYST lower than TO will set temperature sensor 1 SMI# to the Interrupt Mode. The following are two kinds of interrupt modes, which are selected by Index 4Ch bit5 : (2) Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 5-15 ) (3) One-Time Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will not cause an interrupt. Once an interrupt event has occurred by exceeding TO , then going below THYST, an interrupt will not occur again until the temperature exceeding TO. (Figure 5-16 ) T HYST 127'C T OI T OI T HYST SMI# * * * * SMI# * * * *Interrupt Reset when Interrupt Status Registers are read Figure 5-14 Figure 5-15 - 35 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF T OI T HYST SMI# * * *Interrupt Reset when Interrupt Status Registers are read Figure 5-16 7.6.4 The W83627THF temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. (1) Comparator Interrupt Mode Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below THYST. ( Figure 5-17 ) (2) Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 5-18 ) T OI T OI T HYST T HYST SMI# * * * * * SMI# * * * *Interrupt Reset when Interrupt Status Registers are read Figure 5-17 Figure 5-18 - 36 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.7 OVT# Interrupt Mode The OVT# mode selection bits are at Bank0 Index18h bit4, Bank1 Index52h bit1 and Bank2 Index52h bit1. (1) Comparator Mode: Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST. ( Figure 5-19) (2) Interrupt Mode: Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor registers. Temperature exceeding TO, then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor registers. Once the OVT# is activated by exceeding TO , then reset, if the temperature remains above THYST , the OVT# will not be activated again.( Figure 5-19) To T HYST OVT# (Comparator Mode; default) OVT# (Interrupt Mode) * * * *Interrupt Reset when Temperature sensor registers are read Figure 5-19 - 37 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8 Registers and RAM Address Port and Data Port are set in the register CR60 and CR61 of Logical Device B which is Hardware Monitor Device. The value in CR60 is high byte and that in CR61 is low byte. For example, setting CR60 to 02 and CR61 to 90 cause the Address Port to be 0x295 and Data Port to be 0x296. 7.8.1 Address Port (Port x5h) Port x5h 00h Bit 6:0 Read/write , Bit 7: Reserved 8 bits 7 6 5 4 3 2 1 0 Address Port: Power on Default Value Attribute: Size: Data Bit7: Reserved Bit 6-0: Read/Write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved (Power On default 0) Address Pointer (Power On default 00h) A6 A5 A4 A3 A2 A1 A0 7.8.2 Data Port (Port x6h) Data Port: Power on Default Value Attribute: Size: Port x6h 00h Read/write 8 bits 7 6 5 4 3 2 1 0 Data Bit 7-0: Data to be read from or to be written to RAM and Register. Publication Release Date: August 7, 2003 Revision 0.8 - 38 - W83627THF 7.8.3 Configuration Register  Index 40h Register Location: 40h Power on Default Value 03h Attribute: Read/write Size: 8 bits 7 6 5 4 3 2 1 0 START SMI#Enable Reserved INT_Clear Reserved Reserved Reserved INITIALIZATION Bit 7: A one restores power on default value to some registers. This bit clears itself since the power on default is zero. Bit 6: Reserved Bit 5: Reserved Bit 4: Reserved Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. Bit 2: Reserved Bit 1: A one enables the SMI# Interrupt output. Bit 0: A one enables startup of monitoring operations, a zero puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit. 7.8.4 Interrupt Status Register 1 Index 41h Register Location: 41h Power on Default Value Attribute: Size: 7 00h Read Only 8 bits 6 5 4 3 2 1 0 CPUVCORE VIN0 VIN1 AVCC(pin 114) SYSTIN CPUTIN SYSFANIN CPUFANIN - 39 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Bit 7: A one indicates the fan count limit of CPUFANIN has been exceeded. Bit 6: A one indicates the fan count limit of SYSFANIN has been exceeded. Bit 5: A one indicates a High limit of CPUTIN temperature has been exceeded. Bit 4: A one indicates a High limit of SYSTIN temperature has been exceeded . Bit 3: A one indicates a High or Low limit of AVCC(pin 114) has been exceeded. Bit 2: A one indicates a High or Low limit of VIN1 has been exceeded. Bit 1: A one indicates a High or Low limit of VIN0 has been exceeded. Bit 0: A one indicates a High or Low limit of CPUVCORE has been exceeded. 7.8.5 Interrupt Status Register 2  Index 42h Register Location: 42h Power on Default Value 00h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 VIN2 Reserved Reserved AUXFANIN CaseOpen AUXTIN TAR1 TAR2 Bit 7: A one indicates that the CPUTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Bit 6: A one indicates that the SYSTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Bit 5: A one indicates a High or Low limit of AUXTIN temperature has been exceeded. Bit 4: A one indicates case has been opened. Bit 3: A one indicates the fan count limit of AUXFANIN has been exceeded . Bit 2: Reserved. Bit 1: Reserved. Bit 0: A one indicates a High or Low limit of VIN2 has been exceeded. - 40 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.6 SMI# Mask Register 1  Index 43h Register Location: 43h Power on Default Value FEh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 CPUVCORE VIN0 VIN1 AVCC (pin 114) SYSTIN CPUTIN SYSFANIN CPUFANIN Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. 7.8.7 SMI# Mask Register 2  Index 44h Register Location: 44h Power on Default Value FFh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 VIN2 Reserved Reserved AUXFANIN CaseOpen AUXTIN TAR1 TAR2 Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. 7.8.8 Reserved Register  Index 45h—46h - 41 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.9 Fan Divisor Register I  Index 47h Register Location: 47h Power on Default Value: 5Fh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved SYSFANINDIV_B0 SYSFANINDIV_B1 CPUFANINDIV_B0 CPUFANINDIV_B1 Bit 7-6: CPUFANIN Divisor bit1:0 . Bit 5-4: SYSFANIN Divisor bit1:0. Note : Please refer to Bank0 CR[5Dh] , Fan divisor table. 7.8.10 Value RAM  Index 20h- 3Fh ADDRESS A6-A0 DESCRIPTION 20h 21h 22h 23h 24h 25h 26h 27h 28h CPUVCORE reading VIN0 reading VIN1 reading AVCC(pin 114)reading VIN2 reading Reserved Reserved SYSTIN temperature sensor reading SYSFANIN reading Note: This location stores the number of counts of the internal clock per revolution. 29h CPUFANIN reading Note: This location stores the number of counts of the internal clock per revolution. - 42 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 5.8.10 Value RAM  Index 20h- 3Fh, continued ADDRESS A6-A0 DESCRIPTION 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh CPUVCORE High Limit (Power on default value is 1.75V) CPUVCORE Low Limit (Power on default value is 0V) VIN0 High Limit VIN0 Low Limit VIN1 High Limit VIN1 Low Limit AVCC(pin 114) High Limit AVCC(pin 114) Low Limit VIN2 High Limit VIN2 Low Limit Reserved Reserved Reserved Reserved SYSTIN temperature sensor High Limit SYSTIN temperature sensor Hysteresis Limit SYSFANIN Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Ch CPUFANIN Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Dh AUXFANIN Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. 3E- 3Fh Reserved Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits. - 43 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.11 Device ID Register - Index 49h Register Location: Power on Default Value Attribute: Size: 7 49h 03h bit Read Only; bit Read/Write 8 bits 6 5 4 3 2 1 0 Reserved DID Bit 7-1: Read Only - Device ID Bit 0 :Reserved. 7.8.12 Reserved Register  Index 4Ah 7.8.13 Fan Divisor Register II - Index 4Bh Register Location: Power on Default Value Attribute: Size: 7 6 4Bh 44h. Read/Write 8 bits 5 4 3 2 1 0 Reserved Reserved Reserved Reserved ADCOVSEL ADCOVSEL AUXFANINDIV_B0 AUXFANINDIV_B1 Bit 7-6:AUXFANIN speed divisor. Please refer to Bank0 CR[5Dh] , Fan divisor table. - 44 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Bit 5-4: Select A/D Converter Clock Input. = 00 - default. ADC clock select 22.5 Khz. = 01- ADC clock select 5.6 Khz. (22.5K/4) = 10 - ADC clock select 1.4Khz. (22.5K/16) = 11 - ADC clock select 0.35 Khz. (22.5K/64) Bit 3-2: These two bits should be set to 01h. The default value is 01h. Bit 1-0: Reserved. 7.8.14 SMI#/OVT# Control Register- Index 4Ch Register Location: Power on Default Value Attribute: Size: 7 4Ch 18h Read/Write 8 bits 6 5 4 3 2 1 0 Reserved Reserved OVTPOL DIS_OVT2 DIS_OVT3 EN_T1_ONE T2T3_INTMode Reserved Bit 7: Reserved. User Defined. Bit 6: Set to 1, the SMI# output type of Temperature CPUTIN/AUXTIN is set to Comparator Interrupt mode. Set to 0, the SMI# output type is set to Two-Times Interrupt mode. (default 0) Bit 5: Set to 1, the SMI# output type of temperature SYSTIN is One-Time interrupt mode. Set to 0, the SMI# output type is Two-Times interrupt mode. Bit 4: Disable temperature sensor AUXTIN over-temperature (OVT) output if set to 1. Set 0, enable AUXTIN OVT output through pin OVT#. Bit 3: Disable temperature sensor CPUTIN over-temperature (OVT) output if set to 1. Set 0, enable CPUTIN OVT output through pin OVT#. Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1: Reserved. Bit 0: Reserved. - 45 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.15 FAN IN/OUT and BEEP Control Register- Index 4Dh Register Location: Power on Default Value Attribute: Size: 7 4Dh 15h Read/Write 8 bits 6 5 4 3 2 1 0 FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 Reserved Reserved Bit 7~6: Reserved. Bit 5: AUXFANIN output value if FANINC3 sets to 0. Write 1, pin 5 generates a logic high signal. Write 0, pin 5 generates a logic low signal. This bit is default 0. Bit 4: AUXFANIN Input Control. Set to 1, pin 5 acts as FAN tachometer input, which is default value. Set to 0, this pin 5 acts as FAN control signal and the output value of FAN control is set by this register bit 5. Bit 3: CPUFANIN output value if FANINC2 sets to 0. Write 1, then pin 112 always generate logic high signal. Write 0, pin 112 always generates logic low signal. This bit default 0. Bit 2: CPUFANIN Input Control. Set to 1, pin 112 acts as FAN tachometer input, which is default value. Set to 0, this pin 112 acts as FAN control signal and the output value of FAN control is set by this register bit 3. Bit 1: SYSFANIN output value if FANINC1 sets to 0. Write 1, then pin 113 always generate logic high signal. Write 0, pin 113 always generates logic low signal. This bit default 0. Bit 0: SYSFANIN Input Control. Set to 1, pin 113 acts as FAN tachometer input, which is default value. Set to 0, this pin 113 acts as FAN control signal and the output value of FAN control is set by this register bit 1. - 46 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.16 Register 50h ~ 5Fh Bank Select Register - Index 4Eh Register Location: Power on Default Value Attribute: Size: 7 6 4Eh 80h Read/Write 8 bits 5 4 3 2 1 0 BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register. Set to 0, access Register 4Fh low byte register. Default 1. Bit 6-3: Reserved. This bit should be set to 0. Bit 2-0: Index ports 0x50~0x5F Bank select. Set to 0, select Bank0. Set to 1, select Bank1. Set to 2, select Bank2. 7.8.17 Winbond Vendor ID Register - Index 4Fh Register Location: Power on Default Value Attribute: Size: 15 4Fh = 5CA3h Read Only 16 bits 8 7 0 VIDH VIDL Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch. Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h. - 47 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.18 Winbond Test Register -- Index 50h - 55h (Bank 0) 7.8.19 BEEP Control Register 1-- Index 56h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 56h 00h Read/Write 8 bits 6 5 4 3 2 1 0 EN_VCORE_BP EN_VIN0_BP EN_VIN1_BP EN_AVCC_BP EN_SYSTIN_BP EN_CPUTIN_BP EN_SYSFANIN_BP EN_CPUFANIN_BP Bit 7: BEEP output control for CPUFANIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 6: BEEP output control for SYSFANIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 5: BEEP output control for temperature CPUTIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 4: BEEP output control for temperature SYSTIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 3: BEEP output control for AVCC(pin 114) if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 2: BEEP output control for VIN1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 1: BEEP output control for VIN0 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 0: BEEP output control for CPUVCORE if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. - 48 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.20 BEEP Control Register 2-- Index 57h (Bank 0) Register Location: Attribute: Size: 57h Read/Write 8 bits 7 6 5 4 3 2 1 0 Power on Default Value 80h EN_VIN2_BP Reserved Reserved EN_AUXFANIN_BP EN_CASO_BP EN_AUXTIN_BP Reserved EN_GBP Bit 7: Global BEEP Control. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP output. Bit 6: Reserved. Bit 5: BEEP output control for temperature AUXTIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 4: BEEP output control for case open if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 3: BEEP output control for AUXFANIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 2-1: Reserved. Bit 0: BEEP output control for VIN1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. 7.8.21 Chip ID -- Index 58h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 58h 90h Read Only 8 bits 5 4 3 2 1 0 CHIPID Bit 7-0: Winbond Chip ID number. Read this register will return 90h. - 49 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.22 Diode Selection Register -- Index 59h (Bank 0) Register Location: 59h Power on Default Value 70h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 SELPIIV3 Reserved Bit 7 : Reserved Bit 6: Diode mode selection of temperature AUXTIN if index 5Dh bit3 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 5: Diode mode selection of temperature CPUTIN if index 5Dh bit2 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 4: Diode mode selection of temperature SYSTIN if index 5Dh bit1 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 3-0: Reserved 7.8.23 Reserved -- Index 5Ah (Bank 0) 7.8.24 Reserved -- Index 5Bh (Bank 0) 7.8.25 Reserved -- Index 5Ch (Bank 0) - 50 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.26 VBAT Monitor Control Register -- Index 5Dh (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 5Dh 00h Read/Write 8 bits 6 5 4 3 2 1 0 EN_VBAT_MNT DIODES1 DIODES2 DIODES3 Reserved FANDIV1_B2 FANDIV2_B2 FANDIV3_B2 Bit 7: AUXFANIN divisor Bit2. Bit 6: CPUFANIN divisor Bit2. Bit 5: SYSFANIN divisor Bit2. Bit 4: Reserved. Bit 3: Sensor type selection of AUXTIN. Set to 1, select diode sensor. Set to 0, select thermistor sensor. Bit 2: Sensor type selection of CPUTIN. Set to 1, select diode sensor. Set to 0, select thermistor sensor. Bit 1: Sensor type selection of SYSTIN. Set to 1, select diode sensor. Set to 0, select thermistor sensor. Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. After set this bit from 0 to 1, the monitored value will be updated to the VBAT reading value register after one monitor cycle time. Fan divisor table: Bit 2 0 0 0 0 Bit 1 0 0 1 1 Bit 0 0 1 0 1 Fan Divisor 1 2 4 8 Bit 2 1 1 1 1 Bit 1 0 0 1 1 Bit 0 0 1 0 1 Fan Divisor 16 32 64 128 Table 5-3 7.8.27 Reserved Register --5Eh (Bank 0) 7.8.28 Reserved Register --5Fh (Bank 0) - 51 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.29 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1) Register Location: Attribute: Size: 50h Read Only 8 bits 7 6 5 4 3 2 1 0 TEMP Bit 7: Temperature of CPUTIN sensor, which is high byte, means 1°C. 7.8.30 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) Register Location: Attribute: Size: 51h Read Only 8 bits 7 6 5 4 3 2 1 0 Reserved TEMP Bit 7: Temperature of CPUTIN sensor, which is low byte, means 0.5°C. Bit 6-0: Reserved. - 52 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.31 CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1) Register Location: Power on Default Value Size: 7 6 52h 00h 8 bits 5 4 3 2 1 0 STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor. 7.8.32 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1) Register Location: Power on Default Value Attribute: Size: 7 6 53h 4Bh Read/Write 8 bits 5 4 3 2 1 0 THYST Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. - 53 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.33 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) Register Location: Power on Default Value Attribute: Size: 7 54h 00h Read/Write 8 bits 6 5 4 3 2 1 0 Reserved THYST Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 7.8.34 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1) Register Location: Power on Default Value Attribute: Size: 7 6 55h 50h Read/Write 8 bits 5 4 3 2 1 0 TOVF Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. - 54 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.35 CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 1) Register Location: Power on Default Value Attribute: Size: 7 56h 00h Read/Write 8 bits 6 5 4 3 2 1 0 Reserved TOVF Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. 7.8.36 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2) Register Location: Attribute: Size: 50h Read Only 8 bits 7 6 5 4 3 2 1 0 TEMP Bit 7: Temperature of sensor 2, which is high byte, means 1°C. - 55 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.37 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2) Register Location: Attribute: Size: 51h Read Only 8 bits 7 6 5 4 3 2 1 0 Reserved TEMP Bit 7: Temperature of sensor3, which is low byte, means 0.5°C. Bit 6-0: Reserved. 7.8.38 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2) Register Location: Power on Default Value Size: 7 52h 00h 8 bits 6 5 4 3 2 1 0 STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor. - 56 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.39 AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2) Register Location: Power on Default Value Attribute: Size: 7 53h 4Bh Read/Write 8 bits 6 5 4 3 2 1 0 THYST Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 7.8.40 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) Register Location: Power on Default Value Attribute: Size: 7 54h 00h Read/Write 8 bits 6 5 4 3 2 1 0 Reserved THYST Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. - 57 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.41 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) Register Location: Power on Default Value Attribute: Size: 7 55h 50h Read/Write 8 bits 6 5 4 3 2 1 0 TOVF Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 7.8.42 AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 2) Register Location: Power on Default Value Attribute: Size: 7 56h 00h Read/Write 8 bits 6 5 4 3 2 1 0 Reserved TOVF Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. - 58 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.43 Interrupt Status Register 3 -- Index 50h (BANK4) Register Location: Power on Default Value Attribute: Size: 7 50h 00h Read Only 8 bits 6 5 4 3 2 1 0 5VSB VBAT TAR3 Reserved Reserved Reserved Reserved Reserved Bit 7-3: Reserved. Bit 2: A one indicates that the AUXTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM . Bit 1: A one indicates a High or Low limit of VBAT has been exceeded. Bit 0: A one indicates a High or Low limit of 5VSB has been exceeded. 7.8.44 SMI# Mask Register 3 -Register Location: Power on Default Value Attribute: Size: 51h FFh Index 51h (BANK 4) Read/Write 8 bits 7 6 5 4 3 2 1 0 5VSB VBAT Reserved Reserved TAR3 Reserved Reserved Reserved Bit 7-5: Reserved. Bit 4: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 2-3: Reserved. Bit 1: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt. - 59 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.45 Reserved Register -- Index 52h (Bank 4) 7.8.46 BEEP Control Register 3-- Index 53h (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 53h 00h Read/Write 8 bits 6 5 4 3 2 1 0 EN_5VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved Bit 7-6: Reserved. Bit 5: User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is inactive. (Default 0) Bit 4-2: Reserved. Bit 1: BEEP output control for VBAT if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 0: BEEP output control for 5VSB if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. 7.8.47 SYSTIN Temperature Sensor Offset Register -- Index 54h (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 6 54h 00h Read/Write 8 bits 5 4 3 2 1 0 OFFSET Bit 7-0: SYSTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. Publication Release Date: August 7, 2003 Revision 0.8 - 60 - W83627THF 7.8.48 CPUTIN Temperature Sensor Offset Register -- Index 55h (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 6 55h 00h Read/Write 8 bits 5 4 3 2 1 0 OFFSET Bit 7-0: CPUTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. 7.8.49 AUXTIN Temperature Sensor Offset Register -- Index 56h (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 56h 00h Read/Write 8 bits 6 5 4 3 2 1 0 OFFSET Bit 7-0: AUXTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. 7.8.50 Reserved Register -- Index 57h--58h (Bank4) - 61 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.51 Real Time Hardware Status Register I -- Index 59h (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 6 59h 00h Read Only 8 bits 5 4 3 2 1 0 VCORE_STS VIN0_STS VIN1_STS AVCC_STS SYSTIN_STS CPUTIN_STS SYSFANIN_STS CPUFANIN_STS Bit 7: CPUFANIN Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 6: SYSFANIN Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 5: CPUTIN temperature sensor status. Set 1, the temperature exceeds the over-temperature limit value. Set 0, the temperature is in under the hysteresis value. Bit 4: SYSTIN temperature sensor status. Set 1, the temperature exceeds the over-temperature limit value. Set 0, the temperature is in under the hysteresis value. Bit 3: AVCC Voltage Status. Set 1, the voltage of AVCC is over the limit value. Set 0, the voltage of AVCC is in the limit range. Bit 2: VIN1 Voltage Status. Set 1, the voltage of VIN1 is over the limit value. Set 0, the voltage of VIN1 is in the limit range. Bit 1: VIN0 Voltage Status. Set 1, the voltage of VIN0 is over the limit value. Set 0, the voltage of VIN0 is in the limit range. Bit 0: VCORE Voltage Status. Set 1, the voltage of VCORE is over the limit value. Set 0, the voltage of VCORE is in the limit range. - 62 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.52 Real Time Hardware Status Register II -- Index 5Ah (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 5Ah 00h Read Only 8 bits 6 5 4 3 2 1 0 VIN2_STS Reserved Reserved AUXFANIN_STS CASE_STS AUXTIN_STS TAR1_STS TAR2_STS Bit 7: Smart CPUFANIN warning status. Set 1, the CPUTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Set 0, the temperature does not reach the warning range yet. Bit 6: Smart SYSFANIN warning status. Set 1, the SYSTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Set 0, the temperature does not reach the warning range yet. Bit 5: AUXTIN temperature sensor status. Set 1, the temperature exceeds the over-temperature limit value. Set 0, the temperature is in under the hysteresis value. Bit 4: Case Open Status. Set 1, the case open is detected and latched. Set 0, the case is not latched open. Bit 3: CPUFANIN Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 2-1: Reserved. Bit 0: VIN2 Voltage Status. Set 1, the voltage of VIN2 is over the limit value. Set 0, the voltage of VIN2 is in the limit range. - 63 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.53 Real Time Hardware Status Register III -- Index 5Bh (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 5Bh 00h Read Only 8 bits 6 5 4 3 2 1 0 5VSB_STS VBAT_STS TAR3 Reserved Reserved Reserved Reserved Reserved Bit 7-2: Reserved. Bit 2: Smart AUXFANIN warning status. Set 1, the AUXTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Set 0, the temperature does not reach the warning range yet. Bit 1: VBAT Voltage Status. Set 1, the voltage of VBAT is over the limit value. Set 0, the voltage of VBAT is during the limit range. Bit 0: 5VSB Voltage Status. Set 1, the voltage of 5VSB is over the limit value. Set 0, the voltage of 5VSB is in the limit range. 7.8.54 Reserved Register -- Index 5Ch (Bank 4) 7.8.55 Reserved Register -- Index 5Dh (Bank 4) 7.8.56 Value RAM 2 Index 50h - 5Ah (BANK 5) ADDRESS A6-A0 50h DESCRIPTION 51h 52h 53h 54h 55h 56h 57h 5VSB reading VBAT reading. The reading is meaningless if EN_VBAT_MNT bit(CR5D bit0) is not set. Reserved Reserved 5VSB High Limit 5VSB Low Limit. VBAT High Limit VBAT Low Limit - 64 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.57 Winbond Test Register -- Index 50h (Bank 6) 7.8.58 Reserved Register--Index00h (Bank 0) 7.8.59 SYSFANOUT Output Value Control Register-- 01h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 01h FFh Read/Write 8 bits 5 4 3 2 1 0 Reserved Reserved Reserved Reserved SYSFANOUT Value Bit 7-4: SYSFANOUT voltage control. OUTPUT Voltage = AVCC * If AVCC= 5V , output voltage table is BIT 7 BIT 6 BIT 5 BIT 4 OUTPUT VOLTAGE FANOUT 16 BIT 7 BIT 6 BIT 5 BIT 4 OUTPUT VOLTAGE 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0.31 0.63 0.97 1.25 1.56 1.88 2.19 1 1 1 1 1 1 1 1 Table 5-4 . 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2.50 2.81 3.13 3.44 3.75 4.06 4.38 4.69 Note. The accuracy of FANOUT voltage is +/- 0.16 V. - 65 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.60 Reserved Register—Index02h (Bank 0) 7.8.61 CPUFANOUT Output Value Control Register-- 03h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 03h FFh Read/Write 8 bits 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved CPUFANOUT Value Bit 7-4: CPUFANOUT voltage control. OUTPUT Voltage = AVCC * Note: See the Table 5-4 FANOUT 16 7.8.62 FAN Configuration Register I -- Index 04h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 04h 00h Read/Write 8 bits 6 5 4 3 2 1 0 Reserved Reserved SYSFAN_Mode SYSFAN_Mode CPUFAN_Mode CPUFAN_Mode Reserved Reserved Bit7-6: Reserved Bit5-4: CPUFANOUT mode control. Set 00, CPUFANOUT is as Manual Mode. (Default). Publication Release Date: August 7, 2003 Revision 0.8 - 66 - W83627THF Set 01, CPUFANOUT is as Thermal Cruise Mode. Set 10, CPUFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit3-2: SYSFANOUT mode control. Set 00, SYSFANOUT is as Manual Mode. (Default). Set 01, SYSFANOUT is as Thermal Cruise Mode. Set 10, SYSFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 1-0:Reserved. 7.8.63 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register -Index 05h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 5 4 05h 00h Read/Write 8 bits 3 2 1 0 Target Temperature / Target Speed (1).When at Thermal Cruise mode: Bit7: Reserved. Bit6-0: SYSTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit7-0: SYSFANIN Target Speed. - 67 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.64 CPUTIN Target Temperature Register/ CPUFANIN Target Speed Register -Index 06h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 5 4 06h 00h Read/Write 8 bits 3 2 1 0 Target Temperature / Target Speed (1).When at Thermal Cruise mode: Bit7: Reserved. Bit6-0: CPUTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit7-0: CPUFANIN Target Speed. 7.8.65 Tolerance of Target Temperature or Target Speed Register -- Index 07h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 5 4 07h 00h Read/Write 8 bits 3 2 1 0 SYSTIN Target Temperature Tolerance / SYSFANIN Target Speed Tolerance CPUTIN Target Temperature Tolerance / CPUFANIN Target Speed Tolerance (1).When at Thermal Cruise mode: Bit7-4: Tolerance of CPUTIN Target Temperature. Bit3-0: Tolerance of SYSTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit7-4: Tolerance of CPUFANIN Target Speed. Bit3-0: Tolerance of SYSFANIN Target Speed. Publication Release Date: August 7, 2003 Revision 0.8 - 68 - W83627THF 7.8.66 SYSFANOUT Stop Value Register -- Index 08h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 5 08h 01h Read/Write 8 bits 4 3 2 1 0 Reserved Reserved Reserved Reserved SYSFANOUT Stop Value When at Thermal Cruise mode, SYSFANOUT voltage will decrease to this register value. This register should be written a non-zero minimum output value. 7.8.67 CPUFANOUT Stop Value Register -- 09h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 09h 01h Read/Write 8 bits 5 4 3 2 1 0 Reserved Reserved Reserved Reserved CPUFANOUT Stop Value When at Thermal Cruise mode, CPUFANOUT voltage will decrease to this register value. This register should be written a non-zero minimum output value. 7.8.68 SYSFANOUT Start-up Value Register -- Index 0Ah (Bank 0) Register Location: Power on Default Value Attribute: Size: 0Ah 01h Read/Write 8 bits - 69 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved SYSFANOUT Start-up Value When at Thermal Cruise mode, SYSFANOUT voltage will increase from 0 to this register value to provide a minimum value to turn on the fan. 7.8.69 CPUFANOUT Start-up Value Register -- Index 0Bh (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 5 0Bh 01h Read/Write 8 bits 4 3 2 1 0 Reserved Reserved Reserved Reserved CPUFANOUT Start-up Value When at Thermal Cruise mode, CPUFANOUT voltage will increase from 0 to this register value to provide a minimum value to turn on the fan. 7.8.70 SYSFANOUT Stop Time Register -- Index 0Ch (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 0Ch 3Ch Read/Write 8 bits 5 4 3 2 1 0 SYSFANOUT Stop Time When at Thermal Cruise mode, this register determines the time of which SYSFANOUT voltage is from stop value to 0. The unit of this register is 0.1 second. The default time is 6 seconds. - 70 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.71 CPUFANOUT Stop Time Register -- Index 0Dh (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 0Dh 3Ch Read/Write 8 bits 5 4 3 2 1 0 CPUFANOUT Stop Time When at Thermal Cruise mode, this register determines the time of which CPUFANOUT voltage is from stop value to 0. The unit of this register is 0.1 second. The default time is 6 seconds. 7.8.72 Fan Output Step Down Time Register -- Index 0Eh (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 5 0Eh 0Ah Read/Write 8 bits 4 3 2 1 0 FANOUT Value Step Down Time This register determines the speed of FANOUT decreasing the voltage in Smart Fan Control mode. The Unit is 1.6 second. - 71 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.73 Fan Output Step Up Time Register -- Index 0Fh (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 5 0Fh 0Ah Read/Write 8 bits 4 3 2 1 0 FANOUT Value Step Up Time This register determines the speed of FANOUT increasing the voltage in Smart Fan Control mode. The Unit is 1.6 second 7.8.74 Reserved Register—Index10h (Bank 0) 7.8.75 AUXFANOUT Output Value Control Register-- 11h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 11h FFh Read/Write 8 bits 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved AUXFANOUT Value Bit 7-4: AUXFANOUT voltage control. OUTPUT Voltage = AVCC * Note: See the Table 5-4 FANOUT 16 - 72 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.76 FAN Configuration Register II -- Index 12h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 12h 00h Read/Write 8 bits 5 4 3 2 1 0 Reserved AUXFANOUT_Mode AUXFANOUT_Mode AUXFANOUT_MIN_Volt CPUFANOUT_MIN_Volt SYSFANOUT_MIN_Volt Reserved Reserved Bit7-6: Reserved Bit 5: Set 1, SYSFANOUT voltage will decrease to and keep the value set in Index 08h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, SYSFANOUT duty cycle will decrease to 0 when temperature goes below target range. Bit 4: Set 1, CPUFANOUT duty cycle will decrease to and keep the value set in Index 09h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, CPUFANOUT duty cycle will decrease to 0 when temperature goes below target range. Bit 3: Set 1, AUXFANOUT duty cycle will decrease to and keep the value set in Index 15h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, AUXFANOUT duty cycle will decrease to 0 when temperature goes below target range. Bit2-1: AUXFANOUT mode control. Set 00, AUXFANOUT is as Manual Mode. (Default). Set 01, AUXFANOUT is as Thermal Cruise Mode. Set 10, AUXFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 0:Reserved. - 73 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.77 AUXTIN Target Temperature Register/ AUXFANIN Target Speed Register -Index 13h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 5 4 13h 00h Read/Write 8 bits 3 2 1 0 Target Temperature / Target Speed (1).When at Thermal Cruise mode: Bit7: Reserved. Bit6-0: AUXTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit7-0: AUXFANIN Target Speed. 7.8.78 Tolerance of Target Temperature or Target Speed Register -- Index 14h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 5 4 14h 00h Read/Write 8 bits 3 2 1 0 AUXTIN Target Temperature Tolerance / AUXFANIN Target Speed Tolerance Reserved (1).When at Thermal Cruise mode: Bit3-0: Tolerance of AUXTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit3-0: Tolerance of AUXFANIN Target Speed. - 74 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.79 AUXFANOUT Stop Value Register -- Index 15h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 15h 01h Read/Write 8 bits 5 4 3 2 1 0 Reserved Reserved Reserved Reserved AUXFANOUT Stop Value When at Thermal Cruise mode, AUXFANOUT value will decrease to register value. This register should be written a non-zero minimum output value. 7.8.80 AUXFANOUT Start-up Value Register -- Index 16h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 5 16h 01h Read/Write 8 bits 4 3 2 1 0 Reserved Reserved Reserved Reserved AUXFANOUT Start-up Value When at Thermal Cruise mode, AUXFANOUT value will increase from 0 to this register value to provide a minimum voltage to turn on the fan. - 75 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.81 AUXFANOUT Stop Time Register -- Index 17h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 17h 3Ch Read/Write 8 bits 5 4 3 2 1 0 AUXFANOUT Stop Time When at Thermal Cruise mode, this register determines the time of which AUXFANOUT voltage is from stop value to 0. The unit of this register is 0.1 second. The default time is 6 seconds. 7.8.82 VRM & OVT Configuration Register -- Index 18h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 18h 43h Read/Write 8 bits 6 5 4 3 2 1 0 VCORE_AD_SEL Reserved Reserved Reserved OVT1_Mode Reserved DIS_OVT1 Reserved Bit 7: Reserved. Bit 6: Set to 1, disable temperature sensor SYSTIN over-temperature (OVT#) output. Set to 0, enable the SYSTIN OVT# output. Bit 5: Reserved. Bit 4: SYSTIN OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 3-1: Reserved. Bit 0: CPUVCORE pin voltage detection method selection. Set to 1, VRM9 formula is selected. Set to 0, VRM8 formula is selected. This bit default value is 1. - 76 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 7.8.83 Reserved -- Index 19h (Bank 0) 7.8.84 User Defined Register -- Index 1A- 1Bh (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 1A-1Bh FFh Read/Write 8 bits 6 5 4 3 2 1 0 User-defined User-defined User-defined User-defined User-defined User-defined User-defined User-defined Bit 7-0: User can write any value into these bits and read. 7.8.85 Reserved Register-- Index 1Ch-1Fh (Bank 0) - 77 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 8. PLUG AND PLAY CONFIGURATION The W83627THF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83627THF, there are eleven Logical Devices (from Logical Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), KBC (logical device 5), GPIO, 5 (logical device 7), GPIO2 (logical device 8), GPIO3,4 (logical device 9), ACPI ((logical device A), and hardware monitor (logical device B). Each Logical Device has its own configuration registers (above CR30). Host can access those registers by writing an appropriate logical device number into logical device select register at CR7. 8.1 8.1.1 Compatible PnP Extended Function Registers In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the Extended Function mode as follows: HEFRAS address and value 0 1 write 87h to the location 2Eh twice write 87h to the location 4Eh twice After Power-on reset, the value on RTSA# (pin 43) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Functions Index Register (I/O port address 2Eh or 4Eh same as Extended Functions Enable Register) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 2Fh or 4Fh). After programming of the configuration register is finished, an additional value (AAh) should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration Publication Release Date: August 7, 2003 Revision 0.8 - 78 - W83627THF registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. 8.1.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83627THF enters the default operating mode. Before the W83627THF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 2Eh or 4Eh (as described in previous section). 8.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 2Eh or 4Eh (as described in section 12.2.1) on PC/AT systems, the EFDRs are read/write registers with port address 2Fh or 4Fh (as described in section 9.2.1) on PC/AT systems. 8.2 Configuration Sequence To program W83627THF configuration registers, the following configuration sequence must be followed: (1). Enter the extended function mode (2). Configure the configuration registers (3). Exit the extended function mode 8.2.1 Enter the extended function mode To place the chip into the extended function mode, two successive writes of 0x87 must be applied to Extended Function Enable Registers(EFERs, i.e. 2Eh or 4Eh). - 79 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 8.2.2 Configuration the configuration registers The chip selects the logical device and activates the desired logical devices through Extended Function Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the same address as EFER, and EFDR is located at address (EFIR+1). First, write the Logical Device Number (i.e.,0x07) to the EFIR and then write the number of the desired logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not required. Secondly, write the address of the desired configuration register within the logical device to the EFIR and then write (or read) the desired configuration register through EFDR. 8.2.3 Exit the extended function mode To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the extended function mode, it is in the normal running mode and is ready to enter the configuration mode. 8.2.4 Software programming example The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 2Eh, so EFIR is located at 2Eh and EFDR is located at 2Fh. If HEFRAS (CR26 bit 6) is set, 4Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh. ;----------------------------------------------------------------------------------; Enter the extended function mode, interruptible double-write | ;----------------------------------------------------------------------------------MOV DX,2EH MOV AL,87H OUT DX,AL OUT DX,AL ;----------------------------------------------------------------------------; Configuration logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV DX,2EH MOV AL,07H OUT DX,AL ; point to Logical Device Number Reg. MOV DX,2FH MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,2EH MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,2FH MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;-----------------------------------------; Exit extended function mode | ;-----------------------------------------MOV DX,2EH MOV AL,AAH OUT DX,AL - 80 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 9. CONFIGURATION REGISTER 9.1 Chip (Global) Control Register CR02 (Default 0x00) Bit 7 - 1 : Reserved. Bit 0 CR07 : SWRST --> Soft Reset. Bit 7 - 0 : LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0 CR20 Bit 7 - 0 : DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x82(read only). CR21 Bit 7 - 0 : DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 = 0x83 (read only, 1 is version no.). CR22 (Default 0xff) Bit 7 Bit 6 : RESERVED. : HMPWD = 0 Power down = 1 No Power down Bit 5 : URBPWD = 0 Power down = 1 No Power down Bit 4 : URAPWD = 0 Power down = 1 No Power down Bit 3 : PRTPWD = 0 Power down = 1 No Power down Bit 2 - 1 : Reserved. Bit 0 : FDCPWD = 0 Power down = 1 No Power down - 81 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CR23 (Default 0x00) Bit 7 - 1 : RESERVED. Bit 0 : IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down mode immediately. CR24 (Default 0s110s1sb) Bit 7 Bit 6 : Reserved : CLKSEL = 0 The clock input on Pin 18 should be 24 MHz. = 1 The clock input on Pin 18 should be 48 MHz. The corresponding power-on setting pin is SOUTB (pin 83). Bit 5 - 3 : Reserved Bit 2 : ENKBC =0 =1 KBC is disabled after hardware reset. KBC is enabled after hardware reset. This bit is read only, and set/reset by power-on setting pin. The corresponding poweron setting pin is SOUTA (pin 54). Bit 1 Bit 0 : Reserved. Must be 1. : PNPCSV =0 =1 The Compatible PnP address select registers have default values. The Compatible PnP address select registers have no default value. When trying to make a change to this bit, new value of PNPCVS must be complementary to the old one to make an effective change. For example, the user must set PNPCSV to 0 first and then reset it to 1 to reset these PnP registers if the present value of PNPCSV is 1. The corresponding power-on setting pin is NDTRA (pin 52). CR25 (Default 0x00) Bit 7 - 6 : Reserved Bit 5 Bit 4 Bit 3 Bit 0 : URBTRI : URATRI : PRTTRI : FDCTRI. Bit 2 - 1 : Reserved - 82 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CR26 (Default 0s000000b) Bit 7 : SEL4FDD = 0 Select two FDD mode. = 1 Select four FDD mode. Bit 6 : HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is NRTSA (pin 51). HEFRAS Address and Value = 0 Write 87h to the location 2Eh twice. = 1 Write 87h to the location 4Eh twice. Bit 5 : LOCKREG = 0 Enable R/W Configuration Registers = 1 Disable R/W Configuration Registers. Bit 4 Bit 3 : Reserved : DSFDLGRQ = 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective on selecting IRQ = 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective on selecting IRQ Bit 2 : DSPRLGRQ = 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ = 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective on electing IRQ. Bit 1 : DSUALGRQ = 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ. = 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ. Bit 0 : DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ - 83 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CR28 (Default 0x00) Bit 7 - 3 : Reserved. Bit 2 - 0 : PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode CR29 (GPIO Group 1 multiplexed pin selection register 1. Vcc powered. Default 0x00) Bit 7, 6 Port Select (select pin 121 ~ 128 as Game Port, General Purpose I/O Port 1 decoding feature. = 00 Game Port. = 01 General Purpose I/O Port 1. = 10 Reserved. = 11 Reserved. Bit 5 PIN105S. = 0 GP55 = 1 Winbond Test Mode Bit 4 XUR_SEL. It selects the function of pin 78 ~ 85. = 0 Pin 78 ~ 85 serve as URB function. = 1 Winbond Test Mode Bit 3 - 2 Reserved. Bit 1, 0 PIN120S1, PIN120S0 = 00 MSO (MIDI Serial Output). = 01 GP20 = 10 Reserved = 11 IRQIN0 (select IRQ resource through CRF4 Bit 7-4 of Logical Device 8). CR2A (GPIO2 multiplexed pin selection register. Vcc powered. Default 0x00) Bit 7, 6 PIN119S1, PIN119S0. = 00 MSI. = 01 GP21. = 10 Winbond Test Mode = 11 Reserved. - 84 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Bit 5 PIN118S. = 0 GP22. = 1 Winbond Test Mode Bit 4 PIN96S. = 0 GP23. = 1 Winbond Test Mode . Bit 3 PIN95S. = 0 GP24. = 1 Winbond Test Mode Bit 2 PIN94S. = 0 GP25. = 1 Winbond Test Mode. Bit 1 PIN93S. = 0 GP26. = 1 Winbond Test Mode Bit 0 PIN2S = 0 SMI#. = 1 IRQIN1 (select IRQ resource through CRF4 Bit 7-4 of Logical Device8). CR2B (GPIO3 multiplexed pin selection register 3. VSB powered. Default 0x00ssssssb) Bit 7 Bit 6 Reserved PIN86S. = 0 GP35. = 1 Winbond Test Mode Bit 5, 4 PIN88S1, PIN88S0. = 00 IRRX. = 01 GP34. = 10 Winbond Test Mode = 11 Reserved Bit 3, 2 PIN89S1, PIN89S0. = 00 GP33. = 01 WDTO. = 10 Reserved = 11 Reserved - 85 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Bit 1, 0 PIN90S1, PIN90S0. = 00 GP32. = 01 PLED. = 10 Reserved. = 11 Reserved. CR2C (GPIO3 multiplexed pin selection register 2. VSB powered. Default 0xssssss00b) Bit 7, 6 : PIN91S1, PIN91S0. = 00 GP31. = 01 Reserved. = 10 Reserved. = 11 Reserved Bit 5, 4 : PIN92S1, PIN92S0. = 00 GP30. = 01 Reserved. = 10 Reserved. = 11 Reserved Bit 3, 2 : PIN64S1, PIN64S0. = 00 SUSLED. = 01 GP37. = 10 Reserved. = 11 Reserved. Bit 1 : PIN87S. = 0 IRTX. = 1 Winbond Test Mode. Bit 0 : Reserved. CR2D (GPIO4 multiplexed pin selection register. VSB powered. Default 0x00s00000b) Bit 7 : PIN67S. = 0 PSOUT#. = 1 GP47. Bit 6 : PIN68S. = 0 PSIN. = 1 GP46. - 86 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Bit 5 : PIN69S. = 0 GP45. = 1 Reserved. Bit 4 : PIN70S. = 0 RSMRST#. = 1 GP44. Bit 3 : PIN71S. = 0 PWROK. = 1 GP43. Bit 2 : PIN72S. = 0 PWRCTL#. = 1 GP42. Bit 1 : PIN73S. = 0 SLP_SX#. = 1 GP41. Bit 0 : PIN75S. = 0 GP40 = 1 Winbond Test Mode CR2E (Default 0x00) Test Modes: Reserved for Winbond. CR2F (Default 0x00) Test Modes: Reserved for Winbond. 9.1.1 Logical Device 0 (FDC) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise) Publication Release Date: August 7, 2003 Revision 0.8 - 87 - W83627THF Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resource for FDC. CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit 7 - 3 : Reserved. Bit 2 - 0 : These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04 - 0x07 No DMA active CRF0 (Default 0x0E) FDD Mode Register Bit 7 : FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. = 0 The internal pull-up resistors of FDC are turned on. (Default) = 1 The internal pull-up resistors of FDC are turned off. Bit 6 : INTVERTZ = 0 FDD interface signals are active low. = 1 FDD interface signals are active high. Bit 5 Bit 4 : DRV2EN (PS2 mode only) : Swap Drive 0, 1 Mode = 0 No Swap (Default) = 1 Drive and Motor select 0 and 1 are swapped. Bit 3 - 2 :Interface Mode = 11 AT Mode (Default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A. This bit determines the polarity of all FDD interface signals. - 88 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Bit 1 : FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default) Bit 0 : Floppy Mode = 0 Normal Floppy Mode (Default) = 1 Enhanced 3-mode FDD CRF1 (Default 0x00) Bit 7 - 6 : Boot Floppy = 00 FDD A = 01 FDD B = 10 FDD C = 11 FDD D Bit 5, 4 : Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. = 00 Normal (Default) = 01 Normal = 10 1 (Forced to logic 1) = 11 0 (Forced to logic 0) Bit 1 : DISFDDWR = 0 Enable FDD write. = 1 Disable FDD write(forces pins WE, WD stay high). Bit 0 : SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not. = 1 FDD is always write-protected. CRF2 (Default 0xFF) Bit 3 - 2 : Density Select Bit 7 - 6 : FDD D Drive Type Bit 5 - 4 : FDD C Drive Type Bit 3 - 2 : FDD B Drive Type Bit 1 - 0 : FDD A Drive Type - 89 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRF4 (Default 0x00) FDD0 Selection: Bit 7 Bit 6 : Reserved. : Pre-comp. Disable. = 1 Disable FDC Pre-compensation. = 0 Enable FDC Pre-compensation. Bit 5 : Reserved. = 00 Select Regular drives and 2.88 format = 01 3-mode drive = 10 2 Meg Tape = 11 Reserved Bit 4 - 3 : DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A). Bit 2 Bit 1:0 : Reserved. : DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. TABLE A DRIVE RATE TABLE SELECT DRTS1 DRTS0 DATA RATE DRATE1 DRATE0 SELECTED DATA RATE MFM FM SELDEN 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K --250K 150K 125K --250K 250K 125K --250K --125K 1 1 0 0 1 1 0 0 1 1 0 0 - 90 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF TABLE B DTYPE0 DTYPE1 DRVDEN0(pin 2) DRVDEN1(pin 3) DRIVE TYPE 0 0 SELDEN DRATE0 4/2/1 MB 3.5”“ 2/1 MB 5.25” 2/1.6/1 MB 3.5” (3-MODE) 0 1 1 1 0 1 DRATE1 SELDEN DRATE0 DRATE0 DRATE1 DRATE0 9.1.2 Logical Device 1 (Parallel Port) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0x78 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Parallel Port I/O base address. [0x100:0xFFC] on 4 byte boundary (EPP not supported) or [0x100:0xFF8] on 8 byte boundary (All modes supported, EPP is only available when the base address is on 8 byte boundary). CR70 (Default 0x07 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for Parallel Port. CR74 (Default 0x04) Bit 7 - 3 : Reserved. Bit 2 - 0 : These bits select DRQ resource for Parallel Port. 0x00 = DMA0 0x01 = DMA1 0x02 = DMA2 0x03 = DMA3 0x04 - 0x07 = No DMA active - 91 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRF0 (Default 0x3F) Bit 7 : Reserved. Bit 6 - 3 : ECP FIFO Threshold. Bit 2 - 0 : Parallel Port Mode (CR28 PRTMODS2 = 0) = 100 Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode. 9.1.3 Logical Device 2 (UART A) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resource for Serial Port 1. CRF0 (Default 0x00) Bit 7 - 2 : Reserved. Bit 1 - 0 : SUACLKB1, SUACLKB0 = 00 UART A clock source is 1.8462 MHz (24MHz/13) = 01 UART A clock source is 2 MHz (24MHz/12) = 10 UART A clock source is 24 MHz (24MHz/1) = 11 UART A clock source is 14.769 MHz (24mhz/1.625) - 92 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 9.1.4 Logical Device 3 (UART B) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for Serial Port 2. CRF0 (Default 0x00) Bit 7 - 4 : Reserved. Bit 3 : RXW4C = 0 No reception delay when SIR is changed from TX mode to RX mode. = 1 Reception delays 4 characters - time (40 bit-time) when SIR is changed from TX mode to RX mode. Bit 2 : TXW4C = 0 No transmission delay when SIR is changed from RX mode to TX mode. = 1Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX mode to TX mode. Bit 1 - 0 : SUBCLKB1, SUBCLKB0 = 00 UART B clock source is 1.8462 MHz (24 MHz/ 13) = 01 UART B clock source is 2 MHz (24 MHz/ 12) = 10 UART B clock source is 24 MHz (24 MHz/ 1) = 11 UART B clock source is 14.769 MHz (24 MHz/ 1.625) - 93 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRF1 (Default 0x00) Bit 7 Bit 6 : Reserved. : IRLOCSEL. IR I/O pins' location select. = 0 Through SINB/SOUTB. = 1 Through IRRX/IRTX. Bit 5 Bit 4 Bit 3 IR MODE : IRMODE2. IR function mode selection bit 2. : IRMODE1. IR function mode selection bit 1. : IRMODE0. IR function mode selection bit 0. IR FUNCTION IRTX IRRX 00X 010* 011* 100 101 110 111* Disable IrDA IrDA ASK-IR ASK-IR ASK-IR ASK-IR tri-state Active pulse 1.6 µS Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock high Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX Note: The notation is normal mode in the IR function. Bit 2 : HDUPLX. IR half/full duplex function select. = 0 The IR function is Full Duplex. = 1 The IR function is Half Duplex. Bit 1 : TX2INV = 0 The SOUTB pin of UART B function or IRTX pin of IR function in normal condition. = 1 Inverse the SOUTB pin of UART B function or IRTX pin of IR function. Bit 0 : RX2INV. = 0 The SINB pin of UART B function or IRRX pin of IR function in normal condition. = 1 Inverse the SINB pin of UART B function or IRRX pin of IR function - 94 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 9.1.5 Logical Device 5 (KBC) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x60 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the first KBC I/O base address [0x100:0xFFF] on 1 byte boundary. CR62, CR 63 (Default 0x00, 0x64 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundary. CR70 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for KINT (keyboard). CR72 (Default 0x0C if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for MINT (PS2 Mouse) CRF0 (Default 0x80) Bit 7 - 6 : KBC clock rate selection = 00 Select 6MHz as KBC clock input. = 01 Select 8MHz as KBC clock input. = 10 Select 12Mhz as KBC clock input. = 11 Select 16Mhz as KBC clock input. Bit 5 - 3 : Reserved. Bit 2 Bit 1 Bit 0 = 0 Port 92 disable. = 1 Port 92 enable. = 0 Gate20 software control. = 1 Gate20 hardware speed up. = 0 KBRST software control. = 1 KBRST hardware speed up. - 95 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 9.1.6 Logical Device 7 (Game Port and MIDI Port and GPIO Port 1 and 5) CR30 (Default 0x00) Bit 7 - 4 : Reserved. Bit 3 Bit 2 Bit 1 Bit 0 = 1 Enable GPIO port 5. = 0 Disable GPIO port 5. = 1 Enable MIDI Port. = 0 MIDI Port is disabled if bit 0 of this register is also 0. = 1 Enable game Port. = 0 Game Port is disabled if bit 0 of this register is also 0. = 1 Enable GPIO port 1, game Port and MIDI Port. = 0 Disable GPIO port 1. Game Port and MIDI Port are enabled/disabled by bit 1 and 2 of this register respectively. CR60, CR 61 (Default 0x02, 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the Game Port base address [0x100:0xFFF] on 1 byte boundary. CR62, CR 63 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the MIDI Port base address [0x100:0xFFF] on 2 byte boundary. CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for MIDI Port . CRF0 (GP1[7:0] I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP1[7:0] data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP1[7:0] inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. - 96 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRF3 (GP5[5:0] I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF4 (GP5[5:0] data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF5 (GP5[5:0] inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. 9.1.7 Logical Device 8 (GPIO Port 2 This power of the Port is VCC source) CR30 (GP2[7:0] Default 0x00) Bit 7 - 1 : Reserved. Bit 0 = 1 Activate GPIO2. = 0 GPIO2 is inactive. CRF0 (GP2[7:0] I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP2[7:0] data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP2[7:0] inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF3 (Default 0x00) Bit 7 - 4 : These bits select IRQ resource for IRQIN1. Bit 3 - 0 : These bits select IRQ resource for IRQIN0. - 97 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRF4 (Reserved) CRF5 (PLED mode register. Default 0x00) Bit 7-6 : Select PLED mode = 00 Power LED pin is tri-stated. = 01 Power LED pin is driven low. = 10 Power LED pin is a 1Hz toggle pulse with 50 duty cycle = 11 Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle. Bit 5-4 Bit 3 : Reserved : Select WDTO counter type. = 0 By second = 1 By minute Bit 2 : Enable the rising edge of keyboard Reset (P20) to force Time-out event. = 0 Disable = 1 Enable Bit 1-0 : Reserved CRF6 (Default 0x00) Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. If the Bit 7 and Bit 6 are set, any Mouse Interrupt or Keyboard Interrupt event will also cause the reload of previously-loaded non-zero value to Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog Counter instead of Watch Dog Timer Time-out value. Bit 7 - 0 = 0x00 Time-out Disable = 0x01 Time-out occurs after 1 second/minute = 0x02 Time-out occurs after 2 second/minutes = 0x03 Time-out occurs after 3 second/minutes ................................................ = 0xFF Time-out occurs after 255 second/minutes - 98 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRF7 (Default 0x00) Bit 7 : Mouse interrupt reset Enable or Disable = 1 Watch Dog Timer is reset upon a Mouse interrupt = 0 Watch Dog Timer is not affected by Mouse interrupt Bit 6 : Keyboard interrupt reset Enable or Disable = 1 Watch Dog Timer is reset upon a Keyboard interrupt = 0 Watch Dog Timer is not affected by Keyboard interrupt Bit 5 Bit 4 : Force Watch Dog Timer Time-out, Write only* = 1 Force Watch Dog Timer time-out event; this bit is self-clearing. : Watch Dog Timer Status, R/W = 1 Watch Dog Timer time-out occurred = 0 Watch Dog Timer counting Bit 3 -0 : These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI. 9.1.8 Logical Device 9 (GPIO Port 3, 4. These two ports are powered by VSB) CR30 (Default 0x00) Bit 7 - 2 : Reserved Bit 1 Bit 0 = 1 Activate GPIO4. = 0 GPIO4 is inactive. = 1 Activate GPIO3. = 0 GPIO3 is inactive. CRF0 (GP3[7:0] I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP3[7:0] data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP3[7:0] inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. - 99 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRF3 (SUSLED mode register. Default 0x00) Bit 7-6 : Select Suspend LED mode = 00 Suspend LED pin is drove low. = 01 Suspend LED pin is tri-stated. = 10 Suspend LED pin is a 1Hz toggle pulse with 50 duty cycle. = 11 Suspend LED pin is a 1/4Hz toggle pulse with 50 duty cycle. This mode selection bit 7-6 keep its settings until VSB power loss. Bit 5 - 0 : Reserved. CRF4 (GP4[7:0] I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF5 (GP4[7:0] data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF6 (GP4[7:0] inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. 9.2 Logical Device A (ACPI) (The CR30, 70, F0~F9 are Vcc power source; CR E0~E7 are VRTC power source) CR30 (Default 0x00) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR70 (Default 0x00) Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resources for PME . - 100 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRE0 (Default 0x00) Bit 7 Bit 6 Bit 5 Bit 4 : DIS-PANSW_IN. Disable panel switch input to turn system power supply on. = 0 PANSW_IN is wire-ANDed and connected to PANSW_OUT. = 1 PANSW_IN is blocked and can not affect PANSW_OUT. : ENKBWAKEUP. Enable Keyboard to wake-up system via PANSW_OUT. = 0 Disable Keyboard wake-up function. = 1 Enable Keyboard wake-up function. : ENMSWAKEUP. Enable Mouse to wake-up system via PANSW_OUT. = 0 Disable Mouse wake-up function. = 1 Enable Mouse wake-up function. : MSRKEY. This bit combining with MSXKEY (bit 1 of CRE0 of logical device A) and ENMDAT_UP (bit 7 of CRE6 of logical device A) define what kind of mouse wake-up event can trigger an active low pulse on PSOUT#. Their combination is described in the following table. ENMDAT_UP 1 1 0 0 0 0 MSRKEY x x 0 1 0 1 MSXKEY 1 0 1 1 0 0 WAKE UP EVENT Any button click or any movement one click of left/right button one click of left button one click of right button two times click of left button two times click of right button Bit 3 Bit 2 Reserved : KB/MS Swap. Enable Keyboard/Mouse port-swap. = 0 Keyboard/Mouse ports are not swapped. = 1 Keyboard/Mouse ports are swapped. Bit 1 : MSXKEY. This bit combining with MSRKEY (bit 4 of CRE0 of logical device A) and ENMDAT_UP (bit 7 of CRE6 of logical device A) define what kind of mouse wake-up event can trigger an active low pulse on PSOUT#. Their combination is described in the following table. ENMDAT_UP 1 1 0 0 0 0 MSRKEY x x 0 1 0 1 MSXKEY 1 0 1 1 0 0 WAKE UP EVENT Any button click or any movement one click of left/right button one click of left button one click of right button two times click of left button two times click of right button Bit 0 : KBXKEY. Enable any character received from Keyboard to wake-up the system =0 Only predetermined specific key combination can wake up the system. =1 Any character received from Keyboard can wake up the system. - 101 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRE1 (Default 0x00) Keyboard Wake-Up Index Register This register is used to indicate which Keyboard Wake-Up Shift register or Predetermined key Register is to be read/written via CRE2. The first set of wake up key combination is in the range of 0x00 - 0x0E, the second set 0x30 – 0x3E, and the third set 0x40 – 0x4E. Incoming key combination can be read through 0x10 – 0x1E. CRE2 Keyboard Wake-Up Data Register This register holds the value of wake-up key register indicated by CRE1. This register can be read/written. CRE3 (Read only) Keyboard/Mouse Wake-Up Status Register Bit 7-5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 : Reserved. : PWRLOSS_STS: This bit is set when power loss occurs. Reserved : PANSW_STS. The Panel switch event is caused by PANSW_IN. This bit is cleared by reading this register. : Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is cleared by reading this register. : Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is cleared by reading this register. CRE4 (Default 0x00) : Power loss control bit 2. = 0 Disable ACPI resume = 1 Enable ACPI resume Bit 6-5 : Power loss control bit = 00 System always turn off when come back from power loss state. = 01 System always turn on when come back from power loss state. = 10 System turn on/off when come back from power loss state depend on the state before power loss. = 11 Reserved. Bit 4 : Reserved Bit 3 : Keyboard wake-up type select for wake-up the system from S1/S2. = 0 LA.CRE0.bit0 determines how system wake up from S1/S2. = 1 Any key. Bit 2 : Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This bit is cleared when wake-up event occurs. = 0 Disable. = 1 Enable. Bit 1 - 0 : Reserved. Must be 00b. Bit 7 - 102 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRE5 (Default 0x00) Bit 7 : Reserved. Bit 6 - 0 : Compared Code Length. When the compared codes are storied in the data register, these data length should be written to this register. CRE6 (Default 0x00) Bit 7 ENMDAT_UP. This bit combining with MSRKEY (bit 4 of CRE0 of logical device A) and MSXKEY (bit 1 of CRE0 of logical device A) define what kind of mouse wake-up event can trigger an active low pulse on PSOUT#. Their combination is described in the following table. ENMDAT_UP MSRKEY MSXKEY WAKE UP EVENT 1 1 0 0 0 0 Bit6 Chassis Status Clear x x 0 1 0 1 1 0 1 1 0 0 Any button click or any movement one click of left/right button one click of left button one click of right button two times click of left button two times click of right button = 1 Clear CASEOPEN# (Pin76) event. = 0 Disable Clear Function. Bit 5 - 0 Reserved - 103 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRE7 (Default 0x00) Bit 7 ENKD3. Enable the third set of keyboard wake-up key combinations. Its values are accessed through keyboard wake-up index register (CRE1 of logical device A) and keyboard wake-up data register (CRE2 of logical device A) at index from 40h to 4eh. = 0 disable wake-up function of the third set of key combinations. = 1 enable wake-up function of the third set of key combinations. Bit 6 ENKD2. Enable the second set of keyboard wake-up key combinations. Its values are accessed through keyboard wake-up index register (CRE1 of logical device A) and keyboard wake-up data register (CRE2 of logical device A) at index from 30h to 3eh. = 0 disable wake-up function of the second set of key combinations. = 1 enable wake-up function of the second set of key combinations. Bit 5 ENWIN98KEY. Enable WIN98 keyboard dedicated key to wake up system through PANSW_OUT if keyboard wake up function is enabled. = 0 Disable WIN98 keyboard wake up. = 1 Enable WIN98 keyboard wake up. Bit 4 EN_ONPSOUT. Enable to issue a 0.5s long PSOUT# pulse when system returns from power loss state and is supposed to be on as described in CRE4 bit 6, 5 of logical device A. = 0 Disable this function for Intel’s Chipset. = 1 Enable this function for Clone’s chipset. Bit 3 SELWDTORST: Select whether Watch Dog timer function is reset by LRESET_L signal or PWROK signal. =0 Watch Dog timer function is reset by LRESET_L signal. =1 Watch Dog timer function is reset by PWROK signal. Bit 2 Bit 1 Bit 0 Reserved Reserved Reserved - 104 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRF0 (Default 0x00) Bit 7 : CHIPPME. Chip level auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. Bit 6 Bit 5 Reserved : MIDIPME. MIDI port auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. Bit 4 Bit 3 : Reserved. Return zero when read. : PRTPME. Printer port auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. Bit 2 : FDCPME. FDC auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. Bit 1 : URAPME. UART A auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. Bit 0 : URBPME. UART B auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. - 105 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRF1 (Default 0x00) Bit 7 : WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working state. This bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. = 0 the chip is in the sleeping state. = 1 the chip is in the working state. Bit 6 - 5 : Devices' trap status. Bit 4 : Reserved. Return zero when read. Bit 3 - 0 : Devices' trap status. CRF3 (Default 0x00) Bit 7 - 0 : Device's IRQ status. These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 : Reserved. : Reserved. : MOUIRQSTS. MOUSE IRQ status. : KBCIRQSTS. KBC IRQ status. : PRTIRQSTS. printer port IRQ status. : FDCIRQSTS. FDC IRQ status. : URAIRQSTS. UART A IRQ status. : URBIRQSTS. UART B IRQ status. CRF4 (Default 0x00) Bit 7 : Reserved. Return zero when read. Bit 6 - 0 : These bits indicate the IRQ status of the individual GPIO function or logical device respectively. The status bit is set by their source function or device and is cleared by writing a1. Writing a 0 has no effect. Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 :Reserved : HMIRQSTS. Hardware monitor IRQ status. : WDTIRQSTS. Watch dog timer IRQ status. Reserved : IRQIN1STS. IRQIN1 status. : IRQIN0STS. IRQIN0 status. - 106 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRF6 (Default 0x00) Bit 7 - 0 : Enable bits of the SMI / PME generation due to the device's IRQ. These bits enable the generation of an SMI / PME interrupt due to any IRQ of the devices. SMI / PME logic output = (MOUIRQEN and MOUIRQSTS) or (KBCIRQEN and KBCIRQSTS) or (PRTIRQEN and PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or (HMIRQEN and HMIRQSTS) or (WDTIRQEN and WDTIRQSTS) or (IRQIN3EN and IRQIN3STS) or (IRQIN2EN and IRQIN2STS) or (IRQIN1EN and IRQIN1STS) or (IRQIN0EN and IRQIN0STS) Bit 7 Bit 6 Bit 5 Reserved. Reserved : MOUIRQEN. = 0 disable the generation of an SMI / PME interrupt due to MOUSE's IRQ. = 1 enable the generation of an SMI / PME interrupt due to MOUSE's IRQ. Bit 4 : KBCIRQEN. = 0 disable the generation of an SMI / PME interrupt due to KBC's IRQ. = 1 enable the generation of an SMI / PME interrupt due to KBC's IRQ. Bit 3 : PRTIRQEN. = 0 disable the generation of an SMI / PME interrupt due to printer port's IRQ. = 1 enable the generation of an SMI / PME interrupt due to printer port's IRQ. Bit 2 : FDCIRQEN. = 0 disable the generation of an SMI / PME interrupt due to FDC's IRQ. = 1 enable the generation of an SMI / PME interrupt due to FDC's IRQ. Bit 1 : URAIRQEN. = 0 disable the generation of an SMI / PME interrupt due to UART A's IRQ. = 1 enable the generation of an SMI / PME interrupt due to UART A's IRQ. Bit 0 : URBIRQEN. = 0 disable the generation of an SMI / PME interrupt due to UART B's IRQ. = 1 enable the generation of an SMI / PME interrupt due to UART B's IRQ. - 107 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRF7 (Default 0x00) Bit 7 : Reserved. Return zero when read Bit 6 - 0 : Enable bits of the SMI / PME generation due to the GPIO IRQ function or device's IRQ. Bit 6 Reserved Bit 5 : HMIRQEN. = 0 disable the generation of an SMI / PME interrupt due to hardware monitor's IRQ. Bit 4 = 1 enable the generation of an SMI / PME interrupt due to hardware monitor's IRQ. : WDTIRQEN. = 0 disable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. Bit 3 Bit 2 = 1 enable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. Reserved : MIDIIRQEN. = 0 disable the generation of an SMI / PME interrupt due to MIDI's IRQ. Bit 1 = 1 enable the generation of an SMI / PME interrupt due to MIDI's IRQ. : IRQIN1EN. = 0 disable the generation of an SMI / PME interrupt due to IRQIN1's IRQ. Bit 0 = 1 enable the generation of an SMI / PME interrupt due to IRQIN1's IRQ. : IRQIN0EN. = 0 disable the generation of an SMI / PME interrupt due to IRQIN0's IRQ. = 1 enable the generation of an SMI / PME interrupt due to IRQIN0's IRQ. CRF9 (Default 0x00) Bit 7 - 3 : Reserved. Return zero when read. Bit 2 : PME_EN: Select the power management events to be either an PME or SMI interrupt for the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1. = 0 the power management events will generate an SMI event Bit 1 = 1 the power management events will generate an PME event. : FSLEEP: This bit selects the fast expiry time of individual devices. = 0 1 second. = 1 8 mS : SMIPME_OE: This is the SMI and PME output enable bit. = 0 neither SMI nor PME will be generated. Only the IRQ status bit is set. = 1 an SMI or PME event will be generated. Bit 0 - 108 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF CRFE, FF (Default 0x00) Reserved for Winbond test. 9.3 Logical Device B (Hardware Monitor) CR30 (Default 0x00) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select Hardware Monitor base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ channel for Hardware Monitor. - 109 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 10. ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings PARAMETER RATING UNIT Power Supply Voltage (5V) Input Voltage RTC Battery Voltage VBAT Operating Temperature Storage Temperature -0.5 to 7.0 -0.5 to VDD+0.5 2.2 to 4.0 0 to +70 -55 to +150 V V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 10.2 DC Characteristics (Ta = 0 °C to 70 °C, VDD = 5V ± 10%, VSS = 0V) PARAMETER SYM. MIN. TYP MAX. UNIT CONDITIONS RTC Battery Quiescent Current ACPI Stand-by Power Supply Quiescent current INcs IBAT IBAT 2.4 2.0 uA mA VBAT = 2.5 V VSB = 5.0 V, All ACPI pins are not connected. VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5 V VIN = 0 V - CMOS level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage INt - TTL level input pin VtVt+ VTH ILIH ILIL VIL VIH ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 1.7 3.8 V V V +10 -10 µA µA Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage 0.8 2.0 +10 -10 V V µA µA VIN = 5 V VIN = 0 V - 110 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF DC Characteristics, continued PARAMETER SYM. MIN. TYP MAX. UNIT CONDITIONS INtd - TTL level input pin with internal pull down resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage pull down resistor INts VIL VIH ILIH ILIL R 2.0 0.8 V V +10 -10 47 µA µA VIN = 5 V VIN = 0 V KΩ V V V VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5 V VIN = 0 V VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V VIN = 3.3 V VIN = 0 V - TTL level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage INtsp3 VtVt+ VTH ILIH ILIL VtVt+ VTH ILIH ILIL VIL VIH ILIH ILIL R 0.8 1.8 0.8 0.9 1.9 1.0 1.0 2.0 +10 -10 µA µA - 3.3 V TTL level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage 0.5 1.6 0.5 0.8 2.0 1.2 1.1 2.4 V V V +10 -10 µA µA INtu - TTL level input pin with internal pull up resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage pull up resistor 0.8 2.0 +10 -10 40 V V µA µA VIN = 5 V VIN = 0 V KΩ - 111 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF DC Characteristics, continued PARAMETER SYM. MIN. TYP MAX. UNIT CONDITIONS I/O8t - TTL level bi-directional pin with source-sink capability of 8 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL VIL VIH VOL VOH ILIH ILIL VIL VIH VOL VOH ILIH ILIL 2.4 2.0 2.4 2.0 2.4 2.0 0.8 0.4 +10 -10 0.8 0.4 +10 -10 0.8 V V V V µA µA IOL = 8 mA IOH = - 8 mA VIN = 5 V VIN = 0 V I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA V V V V µA µA IOL = 12 mA IOH = -12 mA VIN = 5 V VIN = 0 V I/O12tp3 - 3.3 V TTL level bi-directional pin with source-sink capability of 12 mA V V 0.4 V V µA µA IOL = 12 mA IOH = -12 mA VIN = 3.3 V VIN = 0 V +10 -10 I/OD12ts - TTL level bi-directional Schmitt-triggered pin. Open-drain output with 12 mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.8 1.8 0.8 0.9 1.9 1.0 1.0 2.0 V V V VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA VIN = 5 V VIN = 0 V 0.4 +10 -10 V µA µA - 112 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF DC Characteristics, continued PARAMETER SYM. MIN. TYP MAX. UNIT CONDITIONS I/OD12tp3 – 3.3 V TTL level bi-directional pin. Open-drain output with 12 mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 2.0 0.8 V V 0.4 +10 -10 V µA µA IOL = 12 mA VIN = 3.3V VIN = 0V I/OD16cs - CMOS level Schmitt-triggered bi-directional pin. Open-drain output with 16 mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VIL VIH VOL ILIH ILIL VIL VIH VOL ILIH ILIL VOL VOL 1.3 3.2 1.5 1.5 3.5 2 1.7 3.8 V V V VDD = 5 V VDD = 5 V VDD = 5 V 0.8 2.0 0.4 +10 -10 V V V µA µA IOL = 16 mA VIN = 5 V VIN = 0 V I/OD24t - TTL level bi-directional pin. Open-drain output with 24 mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage Output Low Voltage Output Low Voltage 0.8 2.0 0.4 +10 -10 0.4 0.4 V V V µA µA IOL = 24 mA VIN = 5 V VIN = 0 V IOL = 8 mA IOL = 12 mA OD8 - Open-drain output pin with sink capability of 8 mA V V OD12 - Open-drain output pin with sink capability of 12 mA - 113 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF DC Characteristics, continued PARAMETER SYM. MIN. TYP MAX. UNIT CONDITIONS OD24 - Open-drain output pin with sink capability of 24 mA Output Low Voltage Output Low Voltage Output High Voltage VOL VOL VOH VOL VOH VOL VOH VOL VOH 2.4 2.4 2.4 2.4 0.4 0.4 V V V IOL = 24 mA IOL = 8 mA IOH = -8 mA IOL = 12 mA IOH = -12 mA IOL = 24 mA IOH = -24 mA IOL = 12 mA IOH = -12 mA OUT8 - TTL level output pin with source-sink capability of 8 mA OUT12 - TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage 0.4 V V OUT24 - TTL level output pin with source-sink capability of 24 mA Output Low Voltage Output High Voltage 0.4 V V OUT12tp3 - 3.3 V TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage 0.4 V V - 114 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 11. APPLICATION CIRCUITS 11.1 Parallel Port Extension FDD JP13 WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK PD7 PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 JP 13A DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSB2 IDX2 RWC2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 EXT FDC PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram - 115 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 11.2 Parallel Port Extension 2FDD JP13 WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK DSA2/PD7 MOA2/PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 JP 13A DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSA2 DSB2 MOA2 IDX2 RWC2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 EXT FDC PRINTER PORT Parallel Port Extension 2FDD Connection Diagram 11.3 Four FDD Mode W83977F DSA DSB MOA MOB 74LS139 G1 A1 B1 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 7407(2) DSA DSB DSC DSD MOA MOB MOC MOD G2 A2 B2 - 116 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 12. HOW TO READ THE TOP MARKING Example: The top marking of W83627THF inbond W83627THF 030A7C282012345UA 1st line: Winbond logo 2nd line: the type number: W83627THF 3rd line: the tracking code 030A7C282012345UA 030: packages made in '00, week 30 A: assembly house ID; A means ASE, S means SPIL.... etc. 7: code version; 7 means code 007 C: IC revision; A means version A, B means version B 282012345: wafer production series lot number UA: Winbond internal use. - 117 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 13. PACKAGE DIMENSIONS (128-pin QFP) HE E 102 65 Symbol Dimension in mm Dimension in inch Min 0.25 2.57 0.10 0.10 13.90 19.90 Nom 0.35 2.72 0.20 0.15 14.00 20.00 0.50 Max 0.45 2.87 0.30 0.20 14.10 20.10 Min 0.010 0.101 0.004 0.004 0.547 0.783 Nom 0.014 0.107 0.008 0.006 0.551 0.787 0.020 Max 0.018 0.113 0.012 0.008 0.555 0.791 103 64 D HD 128 39 1 e b 38 A1 A2 b c D E e HD HE L L1 y 0 c 17.00 23.00 0.65 17.20 23.20 0.80 1.60 17.40 23.40 0.95 0.669 0.905 0.025 0.677 0.913 0.031 0.063 0.685 0.921 0.037 0.08 0 7 0 0.003 7 Note: 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec. A A2 See Detail F Seating Plane A1 L L1 Detail F y 5. PCB layout please use the "mm". Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 118 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF 14. APPENDIX A : DEMO CIRCUIT 5 WDTO PLED GP31 GP30 GP26 GP25 GP24 GP23 7 VIN3 7 VIN2 7 VIN1 7 CPUVCORE IRRX IRTX RIB# DCDB# SOUTB SINB DTRB# RTSB# DSRB# CTSB# CASEOPEN# GP40 IO5V SLP_SX# PWRCTL# IO5V PWROK IOBAT 7 7 7 7 VREF VTIN CPUTIN SYSTIN RSMRST# GP45 PSIN GP36 GP35 PANSWOUT# 5 5 For Wake Up Function 5 MDAT MCLK 2 2 To Power supply for turn ON VCC. 5 Indicated the VCC is OK. 3 3 3 3 3,5 3 3 3 3 3 7 COMB & IR 4.7K R1 H/W MONITOR R2 4.7K 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 U1 Keyboard & PS2 Mouse. For VRD10's VID Control Don't need pull-up resistor 6 6 6 2 2 2 2 2 2 2 2 2 2 GP55 GP54 GP53 GP52 GP51 GP50 OVT# FANIN2 FANIN1 FANOUT2 FANOUT1 GP22 MSI MSO GPSA2 GPSB2 GPY1 GPY2 GPX2 GPX1 GPSB1 GPSA1 AVCC MIDI PORT GAME PORT 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VTIN VREF CPUVCORE VIN1 VIN2 VIN3 GP23 GP24 GP25 GP26 GP30 GP31 PLED/GP32 WDTO/GP33 IRRX/GP34 IRTX GP35 RIB# DCDB# PEN48/SOUTB SINB DTRB# RTSB# DSRB# CTSB# GP36 CASEOPEN# GP40 VBAT SLP_SX#/GP41 PWRCTL#/GP42 PWROK/GP43 RSMRST#/GP44 GP45 PSIN/GP46 PSOUT#/GP47 MDAT MCLK CPUTIN SYSTIN GP55 GP54 GP53 GP52 GP51 GP50 OVT# FANIN2 FANIN1 AVCC FANOUT2 FANOUT1 AGND GP22 MSI/GP21 MSO/IRQIN0/GP20 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/GP14 GPX2/GP13 GPX1//GP12 GPSB1/GP11 GPSA1/GP10 W83627THF SUSLED/GP37 KDAT KCLK VSB KBRST GA20M BEEP RIA# DCDA# VSS PENKBC/SOUTA SINA PNPCSV/DTRA# HEFRAS/RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 SUSLED KDAT KCLK KBRST GA20M BEEP RIA# DCDA# SOUTA SINA DTRA# RTSA# DSRA# CTSA# STB# AFD# ERR# INIT# SLIN# 5 2 2 IOVSB C1 3 3 3,5 3 3,5 3,5 3 3 4 4 4 4 4 0.1UF COMA IO5V C2 .1UF DRVDEN0 SMI#/IRQIN1 INDEX# MOA# FANIN3 DSA# FANOUT3 DIR# STEP# WD# WE# VCC TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN PME# VSS PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 VCC3V LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4 AVCC L1 FB IO5V Printer PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD[0..7] 4 JP1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 U2 RWC# INDEX# MOA# DSA# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# 6 6 SMI# FANIN3 FANOUT3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ACK# BUSY PE SLCT 4 4 4 4 HEADER 17X2 IO5V 4 C3 3 2 5 5 5 PME# PCICLK LDRQ# SERIRQ LAD[0..3] 5 LFRAME# LRESET# LAD[0..3] IO5V 0.1UF IO3V C4 .1UF VCC O/P GND |LINK |627THF_1.SCH |627THF_2.SCH |627THF_3.SCH |627THF_4.SCH |627THF_5.SCH |627THF_6.SCH |627THF_7.SCH OSC 24M/48M Hz LPC INTERFACE LAD3 LAD2 LAD1 LAD0 Winbond Electronic Corp. Title Size B Date: W83627THF APPLICATION CIRCUIT Document Number W83627THF + FDC Wednesday, April 09, 2003 Sheet 1 of 7 Rev 0.1 - 119 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF OnNow or Wake_up function power D1 IO5V 2 1N4148 VWAKE F1 VWAKE C5 10U R3 4.7K R4 4.7K FUSE 2 JP2 KB/MS D2 IOVSB 1N4148 1 L2 1 MDAT FB L3 1 MCLK C6 47P C7 47P FB J1 1 2 3 4 5 6 HEADER 6 VWAKE CIRCUIT 1 PS2 MOUSE VWAKE R5 4.7K R6 4.7K L4 1 KDAT FB L5 C8 0.1U 3 2 1 1 KCLK C9 47P C10 47P FB C11 0.1U J2 1 2 3 4 5 6 HEADER 6 BATTERY CIRCUIT IOBAT BT1 BATTERY 3V R7 1K D3 1N4148 JP3:1-2 Clear CMOS 2-3 Enable ONNOW functions JP3 HEAD3 KEYBOARD GAME & MIDI PORT CIRCUIT IO5V IO5V IO5V IO5V IO5V R8 2.2K R9 2.2K R10 2.2K R11 2.2K L6 FB 1 1 1 1 1 1 1 1 1 1 MSI GPSA2 GPSB2 GPY1 GPY2 MSO GPX2 GPX1 GPSB1 GPSA1 R12 2.2K R13 2.2K R14 2.2K R15 2.2K R16 2.2K R17 2.2K 8 15 7 14 6 13 5 12 4 11 3 10 2 9 1 P1 R18 1M R19 1M R20 1M R21 1M PRT C12 0.01U C13 0.01U C14 0.01U C15 0.01U C16 0.01U C17 0.01U C18 0.01U C19 0.01U C20 0.01U Winbond Electronic Corp. Title Size B Date: W83627THF APPLICATION CIRCUIT Document Number GAME & MIDI & KBC Wednesday, April 09, 2003 Sheet 2 of 7 Rev 0.1 - 120 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF COM PORT IO5V 1,5 1,5 1,5 1 1 1 1 1 RTSA# DTRA# SOUTA RIA# CTSA# DSRA# SINA DCDA# RTSA# DTRA# SOUTA RIA# CTSA# DSRA# SINA DCDA# 20 16 15 13 19 18 17 14 12 11 U3 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND +12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 IO+12V NRTSA NDTRA NSOUTA NRIA NCTSA NDSRA NSINA NDCDA IO-12V GND NRIA NDTRA NCTSA NSOUTA NRTSA NSINA NDSRA NDCDA 5 9 4 8 3 7 2 6 1 P2 IR CONNECTOR IO5V J3 CONNECTOR DB9 1 2 3 4 5 CN2X5 6 7 8 9 10 (SOP20) W83778 COMA (UARTA) 1 1 IRRX IRTX IO5V 1 1 1,5 1 1 1 1 1 RTSB# DTRB# SOUTB RIB# CTSB# DSRB# SINB DCDB# 20 16 15 13 19 18 17 14 12 11 U4 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND +12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 IO+12V NRTSB NDTRB NSOUTB NRIB NCTSB NDSRB NSINB NDCDB IO-12V NDCDB NSOUTB GND NRTSB NRIB JP4 1 3 5 7 9 2 4 6 8 10 NSINB NDTRB NDSRB NCTSB HEADER 5X2 (SOP20) W83778 COMB (UARTB) Winbond Electronic Corp. Title Size B Date: W83627THF APPLICATION CIRCUIT Document Number UART+IR Wednesday, April 09, 2003 Sheet 3 of 7 Rev 0.1 - 121 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF IO5V D4 DIODE PRT PORT 1 2 3 4 PD[0..7] PD0 PD1 PD2 PD3 1 2 3 4 RP5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 RP1 2.7K 1 2 3 4 1 2 3 4 RP2 2.7K RP3 2.7K 1 2 3 4 1 2 3 4 8 7 6 5 RP4 2.7K R22 2.7K 1 1 1 1 1 STB# AFD# INIT# SLIN# PD[0..7] 22 RP6 8 7 6 5 NDP2 NDP15 NDP3 NDP4 NDP5 NDP6 22 PD4 PD5 PD6 PD7 1 2 3 4 RP7 8 7 6 5 22 1 1 1 1 1 ERR# ACK# BUSY PE SLCT NDP10 NDP11 NDP12 NDP13 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 J4 DB25 C21 180P C30 180P C22 180P C31 180P C23 180P C32 180P C24 180P C33 180P C25 180P C26 180P C34 180P C27 180P C35 180P C36 180P C28 180P C37 180P C29 180P Winbond Electronic Corp. Title Size B Date: W83627THF APPLICATION CIRCUIT Document Number PRINT PORT Wednesday, April 09, 2003 Sheet 4 of 7 Rev 0.1 - 122 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF POWER ON SETTING PIN STREN HEFRAS PNPCSV1,3 PENKBC1,3 PEN48 1,3 1,3 GP42 RTSA# DTRA# SOUTA SOUTB 1 2 3 4 5 S1 10 9 8 7 6 R23 4.7K R?(8P4RA1 1 8 2 7 3 6 4 5 4.7K IOVSB IO5V SW DIP-5 SUSPEND LED CIRCUIT IOVSB R24 150 D5 Q1 2N3904 SUSLED R25 4.7K 1 SUSLED POWER ON SETTING PIN HEFRAS 1,3 PNPCSV 1,3 PENKBC 1,3 PEN48 1,3 RTSA# DTRA# SOUTA SOUTB 1 2 3 4 RP8 8 7 6 5 IO5V 4.7K POWER LED CIRCUIT R26 150 IO5V LED R27 4.7K D6 Q2 2N3904 1 PLED PANEL SWITCH IOVSB 1 PSIN R29 10K R28 1K JP5 1 2 HEADER 2 C38 0.1U 0 RTSA# DTRA# SOUTA SOUTB 2E DEFAULT KBC DISABLE CLK 24M 1 4E ALL 0 KBC ENABLE CLK 48M PIN18 INPUT CLK VALUE I/O CONFIGURATION ADDRESS I/O PORT BASE DEFAULT VALUE Signal Pullhigh IO3VSB RP9 1 1 1 1 PME# PANSWOUT# RSMRST# PWRCTL# 1 2 3 4 8 7 6 5 IO3V 8 7 6 5 IOVSB 4.7K 1 2 3 4 RP10 1 1 1 LDRQ# LFRAME# SERIRQ 4.7K IO3V 1 2 3 4 RP11 8 7 6 5 1 LAD[0..3] 4.7K Winbond Electronic Corp. Title Size B Date: W83627THF APPLICATION CIRCUIT Document Number Power setting Wednesday, April 09, 2003 Sheet 5 of 7 Rev 0.1 - 123 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Circuit for DC FAN speed control Type 1 : Transistor 2SC5706 Type 2 : PMOS CEB05P03 IO+12V IO+12V U5B 4 1 1N4148 D7 R30 4.7K R31 FANIN1 27K R33 10K R38 1 IO+12V JP7 3 2 1 HEADER 3 FANOUT2 6 5 LM358 7 470K 8 D + R57 G S Q4 CEB05P03 IO+12V IO+12V U5A 1 LM358 4 R34 JP6 3 2 1 HEADER 3 Q3 NPN 2SC5706 IO+12V 1 FANOUT1 3 2 8 + - 1N4148 D8 R32 4.7K R35 FANIN2 27K R37 10K 1 R36 20K 28K R39 20K 28K Type 3 : LDO LM1117 IO+12V U6 2 1 IO+12V U7A 1 LM358 4 R43 ADJ OUT IO+12V LM1117 1N4148 D9 R40 4.7K R41 FANIN3 27K R42 10K 1 IN Note : 1. Transistor,MOSFET,LDO We suggest TO-252 or TO-262 type of package 2. Use 2SC5706, Max. FANVCC 3. Use CEB05P03, Max. FANVCC is 10.2V is 12V 1 FANOUT3 3 2 8 + - 3 JP8 3 2 1 HEADER 3 4. Use LM1117, Max. FANVCC max is 10.8V R44 20K 28K Winbond Electronic Corp. Title Size B Date: W83627THF APPLICATION CIRCUIT Document Number FAN Control Wednesday, April 09, 2003 Sheet 6 of 7 Rev 0.1 - 124 - Publication Release Date: August 7, 2003 Revision 0.8 W83627THF Temperature Sensing VREF RT1 R45 10K 1% RT2 R46 1 VTIN 10K 1% THERMISTOR R48 4.7K R47 100 LS1 THERMISTOR IO5V 1 SYSTIN R49 1 CPUTIN 30K C39 3300P t t CPUD+ 1 BEEP FROM CPU'S THERM DIODE Q5 NPN SPEAKER CPUD- R50 IOBAT 2M CASEOPEN# 1 Voltage Sensing S2 SW SPST R51 CPUVCO 10K R52 IO+12V 28K 1% R55 1 VREF 56K 1% 232K 1% VIN2 1 10K 1% VIN1 R56 IO-12V 1 R53 IO3V 10K 1% R54 VIN3 1 CPUVCORE 1 Winbond Electronic Corp. Title Size B Date: W83627THF APPLICATION CIRCUIT Document Number Temperature+Voltage sensing Wednesday, April 09, 2003 Sheet 7 of 7 Rev 0.1 - 125 - Publication Release Date: August 7, 2003 Revision 0.8