W83793G Winbond H/W Monitor
DATE: DECEMBER 11, 2006 REVISION: 1.0
W83793G
W83793G DATA SHEET REVISION HISTORY
PAGES DATES VERSION WEB VERSION MAIN CONTENTS
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0.1 0.2 0.3 0.32 0.33
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Preliminary Modify pin type for VID pins. Sec4.1 and 5.2 Add Vtt and PECI pin.
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1. Modify chap4(block chap5(pin configuration)
diagram)
and
Modify Register for B version. 1. Modify the formula to calculate the RPM
6
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0.34
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2. Add information of “The Top Marking” 3. Change the part name to W83793G
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0.35
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Add FANIN9~FANIN12 function description 1. Modify 8.8.2.3 register description. 2. Update 8.9.2.1 Voltage reading formula 3. Remove AMD SI description 4. Update 8.3.2.2 Index 0Ch I2CADDR75B registers 5. Update AC Characteristic on Chap 9.3
8
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
Table of Contents1. 2. GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES ................................................................................................................................. 2 2.1 2.2 2.3 2.4 2.5 3. 4. 5. 6. Monitoring Items ............................................................................................................. 2 Address Resolution Protocol and Alert Standard Format .............................................. 2 Actions Enabling ............................................................................................................. 3 General ........................................................................................................................... 3 Package .......................................................................................................................... 3
KEY SPECIFICATIONS .............................................................................................................. 3 BLOCK DIAGRAM ...................................................................................................................... 4 PIN CONFIGURATION ............................................................................................................... 5 PIN DESCRIPTION..................................................................................................................... 6 6.1 6.2 Pin Type Description....................................................................................................... 6 Pin Description List ......................................................................................................... 6
7. 8.
FUNCTIONAL DESCRIPTION ................................................................................................. 11 CONFIGURATION REGISTERS .............................................................................................. 12 8.1 ID, Bank Select Registers............................................................................................. 12
8.1.1 8.1.2 ID, Bank Select Registers Map...............................................................................12 ID, Bank Select Register Details.............................................................................12 Watch Dog Timer Registers Map............................................................................14 Watch Dog Timer Register Details .........................................................................15 Register Maps ........................................................................................................17 Register Details ......................................................................................................17 VID Control/Status Registers Map..........................................................................20 VID Register Details ...............................................................................................21 INT/SMI Control/Status Register Map ....................................................................27 INT/SMI Control/Status Register Details.................................................................27 OVT/BEEP Control Registers Map .........................................................................33 OVT/BEEP Control Registers Details .....................................................................33 Multi-Function Pin Control Register Map ................................................................36 Multi-Function Pin Control Register Details ............................................................37
8.2
Watch Dog Timer Registers ......................................................................................... 14
8.2.1 8.2.2
8.3
Configuration and Address Select Registers................................................................ 17
8.3.1 8.3.2
8.4
VID Control/Status Registers........................................................................................ 20
8.4.1 8.4.2
8.5
INT/SMI# Control/Status Registers .............................................................................. 26
8.5.1 8.5.2
8.6
OVT/BEEP Control Register......................................................................................... 33
8.6.1 8.6.2
8.7
Multi-Function Pin Control Register.............................................................................. 36
8.7.1 8.7.2
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W83793G
8.8 Temperature Sensors Control Register........................................................................ 40
8.8.1 8.8.2 Temperature Sensors Control Register Map ..........................................................40 Temperature Sensors Control Register Details ......................................................40 Voltage Channel Registers Map .............................................................................44 Voltage Channel Register Details ...........................................................................45 Temperature Channel Register Map.......................................................................48 Temperature Channel Register Details...................................................................49 Fan Register Map ...................................................................................................51 Fan Register Details ...............................................................................................56 PECI Register Map.................................................................................................82 PECI Register Details .............................................................................................83 ASF Register Map ..................................................................................................89 ASF Register Details ..............................................................................................95
8.9
Voltage Channel Registers ........................................................................................... 44
8.9.1 8.9.2
8.10
Temperature Channel Registers .................................................................................. 48
8.10.1 8.10.2
8.11
Fan Control Registers................................................................................................... 51
8.11.1 8.11.2
8.12
PECI Control Registers................................................................................................. 81
8.12.1 8.12.2
8.13
ASF Control Registers .................................................................................................. 89
8.13.1 8.13.2
9.
ELECTRICAL CHARACTERISTICS....................................................................................... 112 9.1 9.2 9.3 Absolute Maximum Ratings ........................................................................................ 112 DC Characteristics...................................................................................................... 112 AC Characteristics ...................................................................................................... 114
9.3.1 9.3.2 9.3.3 Access Interface ...................................................................................................114 Dynamic Vcore Limit Setting.................................................................................115 Power On Reset ...................................................................................................116
10. 11. 12. 13.
ORDER INFORMATION ......................................................................................................... 116 APPENDIX .............................................................................................................................. 117 11.1 Register Summary ...................................................................................................... 117 THE TOP MARKING............................................................................................................... 125 PACKAGE DRAWING AND DIMENSIONS............................................................................ 126
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
1. GENERAL DESCRIPTION
W83793G is an evolving version of the W83792D. Besides the conventional functions of W83792D, W83793G uniquely provides several innovative features such as ASF 2.0 specification compliant, SMBus 2.0 ARP command compatible, 8 sets of Smart fanTM. Conventionally, W83793G can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system, such as server, workstation…etc, working very stably and efficiently. A 10-bit analog-to-digital converter (ADC) is built inside W83793G. W83793G can simultaneously monitor 11 analog voltage inputs (including power VDD/5VSB/VBAT monitoring), 12 fan tachometer inputs, 6 remote temperatures, 4 of which support current mode (dual current source) temperature measurement method, and Watch Dog Timer function. The sense of remote temperature can be performed by thermistors, or directly from Intel® / AMDTM CPU with thermal diode output. W83793G provides 8 PWM (pulse width modulation) / DC fan output modes for smart fan control - Thermal CruiseTM mode and Smart FanTM II mode. Under Thermal CruiseTM mode, temperatures of CPU and the system can be maintained within specific programmable ranges under the hardware control. As Smart FanTM II, which provides 8 sets of temperatures point each could control fan’s duty cycle, depends on this construction, fan could be operated at the lowest possible speed so that the acoustic noise could be avoided. As for warning mechanism, W83793G provides SMI#, OVT#, IRQ, BEEP signals for system protection events. W83793G also has 2 specific pins to provide selectable address setting for application of multiple devices (up to 4 devices) wired through I2C interface. W83793G can uniquely serve as an ASF sensor to respond to ASF master’s request for the implementation of network management in OS-absent status. Through W83793G’s compliance with ASF2.0 sensor specification, network server is able to monitor the environmental status of each client in OS-absent state by PET (Platform Event Trap) frame values returned from W83793G, such as temperatures, voltages, fan speed and case open. Moreover, W83793G supports SMBus 2.0 ARP command to solve the problem of address conflicts by dynamically assigning a new unique address for W83793G ASF Function after W83793G’s UDID is sent. Through the application software or BIOS, the users can read all the monitored parameters of the system from time to time. A pop-up warning can also be activated when the monitored item is out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM or other management application software. Besides, the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and activate corresponding maskable interrupts.
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
2. FEATURES
2.1
•
Monitoring Items
VOLTAGE
Monitoring 11 voltages (3 power pins – VSB, VCC, VBAT, 8 external pins – Vcore x 4, +3V, +12V, Others x 2).
TEMPERATURE
• • •
4 thermal diode (D+, D-) inputs, supporting current mode (dual current source) temperature measurement method 2 thermistor inputs Support Intel® PECI
FAN
• • •
8 DC/PWM Fan outputs for fan speed control 8 Fan speed inputs for monitoring (up to 12 by register setups) Smart FanTM -- control the most fitting speed automatically by temperature.
CASEOPEN
•
Case open detection input.
2.2
• • • • •
Address Resolution Protocol and Alert Standard Format
Support System Management Bus (SMBus) version 2.0 specification Comply with hardware sensor slave ARP (Address Resolution Protocol) Response ASF 2.0 command --- Get Event Data, Get Event Status, Device Type Poll Comply with ASF 2.0 sensors (Monitoring fan speed, voltage, temperature, thermal trip and case open event/status) Support Remote Control subset: Remote Power-on/ Power-off/ Reset.
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W83793G
2.3
• •
Actions Enabling
Issue SMI#, OVT# signals to activate system protection Issue BEEP signal to activate system speaker or buzzer
2.4
• • • •
2
P P
General
I C serial bus interface Watch Dog Timer function with pin: WDTRST#, SYSRST_IN. 2 pins (A0, A1) to provide selectable address settings for application of multiple devices (up to 4 devices) wired together through I 2 C interface
P P
5V operation
2.5
•
Package
56 Pin SSOP 300mil.
3. KEY SPECIFICATIONS
Voltage monitoring accuracy Temperature Sensor Accuracy Remote Diode Sensor Accuracy Resolution Supply Voltage (Pin 7, 5VSB) Operating Supply Current Current without 48MHz input at Pin 1 ADC Resolution ± 1° C 0.5 ℃ 5±0.25V 25 mA typ. 8 mA typ. 10 Bits ±1%
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
4. BLOCK DIAGRAM
PWRBTN# ADDR [0:1]
IRQ/SMI# OVT#/BEEP
Beep/Alert Generator
Control Circuit & Value Ram
ASF Command Decoder SMBus & ARP
SMBus Interface SCL SDA
Current Dispatcher Channel D+[1:4] D-[1:4] THR [1:2] VCORE / VSEN [1:2] VREF Band Gap Reference W83793G SYSRSTIN# VIDA 7:0 VIDB 7:0 Watch Dog Timer VID Control Amplify Circuit Mux 10-bits Delta_sigma ADC
Control
Vtt Intel PECI Interface PECI FANIN [1:12] FANCTRL [1:8] Caseopen Caseopen
Fan Control
WDTRST#
VIDBSEL
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W83793G
5. PIN CONFIGURATION
W83793G (56 SSOP)
CLK OVT#/BEEP IRQ/SMI# SCL SDA PWRBTN# 5VSB CASEOPEN# VBAT VIDA4/FANIN8 VIDA5/FANCTL8 VIDA6 VIDA7 WDTRST# SYSRSTIN# GND PECI VTT VSEN1 VSEN2 VSEN3 VSEN4 VCOREA VCOREB 5VDD VREF THR1 THR2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VIDB7/FANCTL8 VIDB6/FANIN8 VIDB5/FANCTL7 VIDB4/FANIN7 VIDB3/FANCTL6 VIDB2/FANIN6 VIDB1/FANCTL5 VIDB0/FANCTL4 FANIN5 FANIN4 FANCTL3/VIDBSEL FANIN3 FANCTL2/ADDR1 FANIN2 FANCTL1/ADDR0 FANIN1 VIDA3/FANIN12 VIDA2/FANIN11 VIDA1/FANIN10 VIDA0/FANIN9 4_D4_D+ 3_D3_D+ 2_D2_D+ 1_D1_D+
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W83793G
6. PIN DESCRIPTION
6.1 Pin Type Description
SYMBOL DESCRIPTION
t v1 v2 v3 s 12 OUT OD AOUT IN AIN
TTL level Vil/Vih=0.4/0.6 level Vil/Vih=0.8/1.4 level Vtt level Schmitt trigger 12mA sink/source capability Output pin Open-drain output pin Output pin (Analog) Input pin (digital) Input pin(Analog)
6.2
Pin Description List
PIN NAME PIN NO. POWER PLANE TYPE DESCRIPTION
CLK OVT# BEEP IRQ SMI# SCL SDA
1
5VSB
INts
2
5VSB
OD12
3 4 5
5VSB 5VSB 5VSB
OUT12 OD12 INts IN/OD12ts
48MHz System clock while VCC5V powered up. PECI and FAN will use this clock to drive logics. Over temperature alert. Low active. BEEP output when abnormal event occurs. When this is no abnormal events, this pin asserts low. Interrupt request output when abnormal events occur. System Management Interrupt (open drain). Serial Bus Clock. Serial Bus bi-directional data. Power Button output for enable/disable power supply. This pin is related to ASF commands. This pin is power for W83793G. Bypass with the parallel combination of 10µF (electrolytic or tantalum) and 0.1µF (ceramic) bypass capacitors. CASE OPEN detection. An active low input from an external device when case is Intruded. This signal will be latched even the case is closed.
PWRBTN#
6
5VSB
OD12
5VSB
7
-
POWER
CASEOPEN#
8
VBAT
INts
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W83793G
Pin Description List, continued.
PIN NAME
PIN NO.
POWER PLANE
TYPE
DESCRIPTION
VBAT VIDA4 FANIN8 VIDA5
9
POWER INv1s or INv2s INts INv1s or INv2s
10
5VSB
VBAT supplies power for CASEOPEN. Besides, it is also a voltage monitor channel. Voltage Supply readouts bit 4 from CPU A. (Default) 0V to +5V amplitude fan tachometer input Voltage Supply readouts bit 5 from CPU A. (Default) FAN control output. The 8th fan control signal can be programmed to output through pin 56 or this pin. When this pin is programmed to be fan control signal, it only supports PWM mode. 0V to +5V amplitude fan tachometer input Voltage Supply readouts bit 6 from CPU A. Voltage Supply readouts bit 7 from CPU A. (Default) Low active system reset. If triggered, this pin will send out 100ms low pulse for system reset. System reset input, used to control WDT. System Ground. Intel® CPU PECI interface Intel® CPU Vtt power Voltage sensor input. Detect range is 0~4.096V Voltage sensor input. Detect range is 0~4.096V +12V voltage input for monitoring. This +12V input voltage needs external resistors to scale it down. The detect range is 0~2.048V. +3V voltage input for monitoring. The detect range is 0~4.096V.
FANCTL8
11
5VSB
OUT / OD12a INts
FANIN12 VIDA6 VIDA7 WDTRST# SYSRSTIN# GND PECI VTT VSEN1 VSEN2 +12VSEN +3VSEN 12 13 14 15 16 17 18 19 20 21 22 5VDD 5VSB 5VSB 5VSB 5VSB
INv1s or INv2s INv1s or INv2s OD12 INts POWER IN/OV3 POWER AIN AIN AIN AIN
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W83793G
Pin Description List, continued.
PIN NAME
PIN NO.
POWER PLANE
TYPE
DESCRIPTION
VCOREA VCOREB 5VDD VREF THR1 THR2 1_D+ 1_D2_D+ 2_D3_D+ 3_D4_D+ 4_DVIDA0
23 24 25 26 27 28 29 30 31 32 33 34 35 36 -
AIN AIN POWER AOUT AIN AIN AIN AIN AIN AIN AIN AIN AIN AIN INv1s or INv2s INts INv1s or INv2s INts
CPU A core voltage input. Detect range is 0~2.048V CPU B Core Voltage Input. Detect range is 0~2.048V. +5V VDD power. Bypass with the parallel combination of 10µF (electrolytic or tantalum) and 0.1µF (ceramic) bypass capacitors. Reference voltage output. Thermistor 1 terminal input. Thermistor 2 terminal input. Thermal diode 1 D+ . Thermal diode 1 D- . Thermal diode 2 D+ . Thermal diode 2 D- . Thermal diode 3 D+ . Thermal diode 3 D- . Thermal diode 4 D+ . Thermal diode 4 D- . Voltage Supply readouts bit 0 from CPU A. (Default) 0V to +5V amplitude fan tachometer input Voltage Supply readouts bit 1 from CPU A. (Default) 0V to +5V amplitude fan tachometer input
37 FANIN9 VIDA1 38 FANIN10
5VSB
5VSB
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W83793G
Pin Description List, continued.
PIN NAME
PIN NO.
POWER PLANE
TYPE
DESCRIPTION
VIDA2 39 FANIN11 VIDA3 FANIN12 FANIN1 41 5VSB 40 5VSB 5VSB
INv1s INts INv1s INts INts
Voltage Supply readouts bit 2 from CPU A. (Default) 0V to +5V amplitude fan tachometer input Voltage Supply readouts bit 3 from CPU A. (Default) 0V to +5V amplitude fan tachometer input 0V to +5V amplitude fan tachometer input Fan speed control PWM/DC output. When the power of 5VDD is 0V, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. As DC output, 64 steps output voltage scaled to 0~5VSB. I2C device address bit 0 trapping during 5VSB power on. 0V to +5V amplitude fan tachometer input Fan speed control PWM/DC output. When the power of 5VDD is 0V, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. As DC output, 64 steps output voltage scaled to 0~5VSB. I2C device address bit 1 trapping during 5VSB power on. 0V to +5V amplitude fan tachometer input Fan speed control PWM/DC output. When the power of 5VDD is 0V, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. As DC output, 64 steps output voltage scaled to 0~5VSB. The pin straps Fan mode and VID mode during 5VSB power on. . When the strap to high, it will select VID mode. When strapped to low, it will select Fan mode for pin49~56.
FANCTL1 42 ADDR0 FANIN2 43 5VSB 5VSB
OUT / OD12 / AOUT
INts INts
FANCTL2 44 ADDR1 5VSB
OUT / OD12 / AOUT
INts
FANIN3
45
5VSB
INts
FANCTL3 46 VIDBSEL 5VSB
OUT / OD12 / AOUT
INts
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W83793G
Pin Description List, continued.
PIN NAME
PIN NO.
POWER PLANE
TYPE
DESCRIPTION
FANIN4 FANIN5
47 48
5VSB 5VSB
INts INts
0V to +5V amplitude fan tachometer input 0V to +5V amplitude fan tachometer input Fan speed control PWM/DC output. When the power of 5VDD is 0V, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. As DC output, 64 steps output voltage scaled to 0~5VSB. Voltage Supply readouts bit 0 from CPU B. Fan speed control PWM/DC output. When the power of 5VDD is 0V, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. As DC output, 64 steps output voltage scaled to 0~5VSB. Voltage Supply readouts bit 1 from CPU B. 0V to +5V amplitude fan tachometer input 0V to +5V amplitude fan tachometer input Voltage Supply readouts bit 2 from CPU B. Fan speed control PWM/DC output. When the power of 5VDD is 0V, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. As DC output, 64 steps output voltage scaled to 0~5VSB. 0V to +5V amplitude fan tachometer input Voltage Supply readouts bit 3 from CPU B. 0V to +5V amplitude fan tachometer input Voltage Supply readouts bit 4 from CPU B.
FANCTL4 49 VIDB0 5VSB
OUT / OD12 / AOUT INv1s or INv2s OUT / OD12 / AOUT
FANCTL5 50 VIDB1 FANIN9 FANIN6 51 VIDB2 5VSB 5VSB
INv1s or INv2s INts INts INv1s or INv2s OUT / OD12 / AOUT 52 5VSB INts INv1s or INv2s INts 53 5VSB INv1s or INv2s
FANCTL6
FANIN10 VIDB3 FANIN7 VIDB4
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W83793G
Pin Description List, continued.
PIN NAME
PIN NO.
POWER PLANE
TYPE
DESCRIPTION
FANCTL7 54 FANIN11 VIDB5 FANIN8 55 VIDB6 5VSB 5VSB
OUT / OD12 / AOUT
Fan speed control PWM/DC output. When the power of 5VDD is 0V, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. As DC output, 64 steps output voltage scaled to 0~5VSB. 0V to +5V amplitude fan tachometer input Voltage Supply readouts bit 5 from CPU B. 0V to +5V amplitude fan tachometer input Voltage Supply readouts bit 6 from CPU B. Fan speed control PWM/DC output. The 8th fan control signal can be programmed to output through pin 11 or this pin. When the power of 5VDD is 0V, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. As DC output, 64 steps output voltage scaled to 0~5VSB. Voltage Supply readouts bit 7 from CPU B.
INts INv1s or INv2s INts INv1s or INv2s
FANCTL8 56 5VSB
OUT / OD12 / AOUT
VIDB7
INv1s or INv2s
7. FUNCTIONAL DESCRIPTION
This section is blank now. Refer Chap 8 for function description.
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W83793G
8. CONFIGURATION REGISTERS
8.1 ID, Bank Select Registers
W83793G inside resides three banks of registers, customer must set bank correctly so that correct registers can be accessed. All the registers described here can be access in all banks.
8.1.1
ID, Bank Select Registers Map
Address 00HEX, 0DHEX, 0EHEX, 0FHEX in all three register banks are reserved as ID, Bank Select registers.
MNEMONIC REGISTER NAME TYPE
BankSel. VendorID. ChipID. DeviceID.
Bank Select Winbond Vendor ID Winbond Chip ID Winbond Device Version ID
RW RO RO RO
8.1.2
8.1.2.1
ID, Bank Select Register Details
Bank Select Register (Bank Select)
Three banks of registers are inside W83793G. The register bank could be selected by programming Bank Select register. All Address 00HEX in these there banks is defined as Bank Select register. Location: Type: Reset: Bank 0, 1, 2 Address 00HEX Read / Write VSB5V (Pin 7) Rising, Init Reset (CR40.Bit7) is set, VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set, SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
BANKSELECT BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
HBACS 1 0HEX
Reserve 0HEX
DESCRIPTION
BANK Select
HBACS (High Byte Access) 7 6-3 0: Return the low byte while reading Winbond Vendor ID. 1: Return the high byte while reading Winbond Vendor ID. Reserved.
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W83793G
Continued
BIT
DESCRIPTION
BANK Select. 2-0 000BIN: Bank 0 is selected to access. 001BIN: Bank 1 is selected to access. 010BIN: Bank 2 is selected to access. 8.1.2.2 Winbond Vendor ID Register (Vender ID)
The Winbond Vendor ID contains two bytes data. By programming register HBACS, it can customer can select to access either high or low byte of Winbond Vendor ID. Location: Type: Reset: Bank 0, 1, 2 Address 0DHEX Read Only No Reset
VENDORID (WINBOND VENDOR ID) BIT 7 6 5 4 3 2 1 0
Name Fixed
BIT
VendorID 5CHEX / A3HEX
DESCRIPTION
7-0 8.1.2.3
VendorID. Return 5CHEX if HBACS = 1; return A3HEX if HBACS = 0. Winbond Chip ID Register (ChipID) Bank 0, 1, 2 Address 0EHEX Read Only No Reset
CHIPID (WINBOND CHIP ID)
Location: Type: Reset:
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
ChipID 7BHEX
DESCRIPTION
7-0
ChipID. Chip ID of W83793G is 7BHEX
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W83793G
8.1.2.4 Location: Type: Reset: Winbond Version ID Register (Device ID) Bank 0, 1, 2 Address 0FHEX Read Only No Reset
VERSION ID BIT 7 6 5 4 3 2 1 0
Name Fixed
BIT
DeviceID 11HEX /12HEX
DESCRIPTION
7-0
Version ID. Device ID of W83793G B Version is 11HEX, C Version is 12HEX
8.2
Watch Dog Timer Registers
W83793G is built in with a Watch Dog Timer, which enable users to reset the system by Pin 14 while system becomes abnormal. Once Watch Dog is enabled, W83793G starts to count down, and host should set the timer for further count down or clear/disable the timer to prevent W83793G issue reset signal.
8.2.1
Watch Dog Timer Registers Map
Watch Dog Timer is consisted of four registers. WDTLock and ENABLE_WDT are used to activate Soft-WDT and Hard-WDT, respectively. WDT_STS and DownCounter can inform the host whether the system is time up or not.
MNEMONIC REGISTER NAME TYPE
WDTLock. EnableWDT. WDT_STS. DownCounter.
Lock Watch Dog Watch Dog Enable Watch Dog Status Watch Dog Timer
WO RO R/W R/W
Two kinds of watchdog timer functions are supported by W83793G. One is so-called Soft Watch Dog Timer, and the other is Hard Watch Dog Timer. Hard Watch Dog timer if enabled that will start a 4 minutes WDT after completion of system reset. (A Low to High transition on SYSRSTIN# pin). BIOS need to write a 00HEX into Watch Dog Timer Register (04HEX) to disable timer within 4 minutes, otherwise pin 14 WDTRST# will assert to reset system. Soft Watch Dog Timer will start down counting whenever Timeout Time is set and Soft Watch Dog Timer is enabled. A WDTRST# will be issued while the timer timeouts. Soft Watch Dog Timer will be disabled automatically after received a SYSRSTIN_N low signal. Bank0. CR40 [2]/ENWDT must set to 1 if there four Watch Dog Timer Registers want to be programming.
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W83793G
8.2.2
8.2.2.1
Watch Dog Timer Register Details
Lock Watch Dog Register (WDT Lock)
Writing this register enable the Soft Watch Dog Timer or Hard Watch Dog Timer. This register is written only and user can confirm the write success by reading ENABLE_WDT. Location: Type: Reset: Bank 0 Address 01HEX Write Only VSB5V (Pin 7) Rising, SYSRSTIN_N (Pin 15) Falling in Soft WDT mode.
WDTLOCK (WATCH DOG TIMER LOCK) BIT 7 6 5 4 3 2 1 0
Name
BIT
UNLOCK CODE
DESCRIPTION
Unlock Code. Write 55HEX, Enable Soft Watch Dog Timer. 7-0 Write AAHEX, Disable Soft Watch Dog Timer. Write 33HEX, Enable Hard Watch Dog Timer. Write CCHEX, Disable Hard Watch Dog Timer. 8.2.2.2 Location: Type: Reset: Watch Dog Enable Register (Enable WDT) Bank 0 Address 02HEX Read Only VSB5V (Pin 7) Rising.
ENABLE WDT (WATCH DOG TIMER ENABLE STATUS) BIT 7 6 5 4 3 2 1 0
Name Reset 0 0 0
Reserve 0 0 0
HARD 0
SOFT 0
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W83793G
BIT
DESCRIPTION
7-2 1
Reserved HARD. 1: indicates the Hard Watch Dog is enabled. 0: Hard Watch Dog is disabled. SOFT.
0
1: indicates the Soft Watch Dog is enabled. 0: Soft Watch Dog is disabled.
8.2.2.3 Location: Type: Reset:
Watch Dog Status Register Bank 0 Address 03HEX Read / Write VSB5V (Pin 7) Rising.
WDT_STS (WATCH DOG STATUS)
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
Reserve 0
Reserve 0
Reserve 0
Reserve 0
WDT STAGE 0 0
HARD_TO SOFT_TO 0 0
DESCRIPTION
7-4 3-2
Reserved WDT Stage. These 2 bits record last WDT stage for BIOS readout. The information is used to help BIOS to identify WDT timeout issue. HARD_TO. 1: a hard timeout occurs. This bit will be cleared after reading. SOFT_TO. 1: a soft timeout occurs. This bit will be cleared after reading.
1 0
8.2.2.4 Location: Type: Reset:
Watch Dog Timer Register (Down Counter) Bank 0 Address 04HEX Read / Write VSB5V (Pin 7) Rising.
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W83793G
DOWN COUNTER (WATCH DOG TIMER) BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Timeout Time 00HEX
DESCRIPTION
Timeout Time. 7-0 To write 00HEX can disable timer while in Hard Watch Dog Timer mode. To set Timeout Time for SOFT Watch Dog Timer, unit is min. The Timeout Time is unit in minutes, and 0 represents the timer is timeout or cleared. 1 represents there still have 1 sec to 1 minute for this timer. In this fashion, 2 shows time to time up is 1 minute 1 sec to 2 minutes.
8.3
8.3.1
Configuration and Address Select Registers
Register Maps
I2C Address Registers Map
MNEMONIC REGISTER NAME TYPE
8.3.1.1
I2CADDR TEMPD1/2ADDR
I C Address LM75 Temperature Sensor I2C Address
2
R/W R/W
There are four Addresses (58HEX, 5AHEX, 5CHEX, 5EHEX) can be assigned for W83793G I2C interface. And it also provides four I2C Addresses for each LM75-like Temperature Sensor (90HEX, 92HEX, 94HEX, 96HEX for TD1 and 98HEX, 9AHEX, 9CHEX, 9EHEX for TD2). These three addresses can be set by trapping pin 42 & 44 input value at 100ms after power ready. The registers for Temperature sensor D1 & D2 can also be accessed by respective addresses that set as I2C address of W83793G. The LM75-like functions default are enabled and can be disabled by setting bit 3 and bit 7 of TEMPD1/2ADDR to 1. 8.3.1.2 Configuration Register Maps
MNEMONIC REGISTER NAME TYPE
CONFIG
Configuration Register
R/W
Configuration Register controls the system reset source, stop, power down and warning output mode.
8.3.2
8.3.2.1
Register Details
I2C Address Register (I2CADDR) Bank 0 Address 0BHEX Read / Write 100ms after VSB5V (Pin 7) Rising.
Location: Type: Reset:
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
I2CADDR BIT 7 6 5 4 3 2 1 0
Name
BIT
SMBUSADDR
DESCRIPTION
SMBUSADDR. The value of SMBUSADDR is trapping pin voltage on PADDR0 (pin42) and PADDR1 (pin44) at 100ms after VSB power ready. ADDR1 ADDR0 I2C Address 7-0 0 0 1 1 0 1 0 1 58HEX 5AHEX 5CHEX 5EHEX
8.3.2.2 Location: Type: Reset:
LM75-like Temperature Sensor I2C Address Register Bank 0 Address 0CHEX Read / Write 100ms after VSB5V (Pin 7) Rising.
TEMPD1/2ADDR
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
DIS_TD2 0
I2CADDR75B Trapped Value
DIS_TD1 0
I2CADDR75A Trapped Value
DESCRIPTION
7
DIS_TD2. If set to 1, it cannot access registers for temperature sensor 2 by temperature sensor 2 I2C address. I2CADDR75B. The value of I2CADDR75B is trapping PADDR0 (pin42) and PADDR1 (pin44) at 100ms after VSB power good issue. ADDR1 ADDR0 I2CADDR75B Temperature sensor 2 I2C Address 0 0 100 98HEX 0 1 101 9AHEX 1 0 110 9CHEX 1 1 111 9EHEX DIS_TD1. If set to 1, it cannot access registers for temperature sensor 1 by temperature sensor 1 I2C address.
6-4
3
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W83793G
Continued.
BIT
DESCRIPTION
2-0
I2CADDR75A. The value of I2CADDR75B is trapping PADDR0 (pin42) and PADDR1 (pin44) at 100ms after VSB power good issue. ADDR1 ADDR0 I2CADDR75A Temperature sensor 1 I2C Address 0 0 000 90HEX 0 1 001 92HEX 1 0 010 94HEX 1 1 011 96HEX Configuration Register Bank 0 Address 40HEX Read / Write bit 0~3 & 7: VSB5V (Pin 7) Rising, Init Reset (CR40.Bit7) is set, VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set, SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set. Bit 4 & 5: VSB5V (Pin 7) Rising, Init Reset (CR40.Bit7) is set.
CONFIG
8.3.2.3 Location: Type: Reset:
BIT
7
6
5
4
3
2
1
0
Name INIT Reserve SYSRST_MD RST_VDD_MD EN_BAT_MNT EN_WDT INT_Clear START Reset
BIT
0
0
0
0
DESCRIPTION
0
0
0
0
INIT. 7 6 5 Set one restores power on default value to all registers except the Serial Bus Address register. This bit clears itself since the power on default is zero. Reserved SYSRST_MD. Write 1, whole chip will reset when SYSRSTIN# input. Write 0, no any operation when SYSRSTIN# input. RST_VDD_MD. Write 1, whole chip will reset when 5VDD up. Write 0, no any operation when 5VDD up.
4
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
Continued
BIT
DESCRIPTION
EN_BAT_MNT. 3 Write 1, enable battery voltage monitor. Write 0, disable battery voltage monitor. If enable this bit, the monitor value is valid after one monitor cycle. EN_WDT. 2 Set this bit to 1 will enable the Watch Dog Timer function. Watch dog timer function will reset system (pin 47) while it timeouts. INT_Clear. 1 A one disables the SMI# and IRQ# outputs without affecting the contents of Interrupt Status Registers. The device will stop monitoring at last channel. It will resume upon clearing of this bit. START. 0 1 : enables startup of monitoring operations; 0 : puts the analog part in Power-down mode.
8.4
VID Control/Status Registers
W83793G provides dual Vcore monitoring channels. Vcore Channels are automatically monitored once 5VSB applied onto W83793G, but W83793G will issue alert information only when their corresponding high/low limit is being violated. ASF is also based on these limit register to judge the current channel status and report to host. Two methods are used to assign the Vcore Limits. Assigning it manually; or assigning it automatically by VID inputs. The following registers set can let users choose their preferred method.
8.4.1
VID Control/Status Registers Map
MNEMONIC REGISTER NAME TYPE
VIDIN_A VIDIN_B VIDA_Latch VIDB_Latch VID_Control VCORE_LIMHI VCORE_LIMLO
VIDA Input Value VIDB Input Value VIDA Latch Value VIDB Latch Value VID Control Vcore High Tolerance Vcore Low Tolerance
RO RO RO RO R/W R/W R/W
W83793G supplies two sets of VID input pin for VOCREA and VCOREB channels. If dynamic VID function is enabled, the high/low limit of VCOREA and VCOREB channel will auto-update while VID input value change. Some VIDA and all VIDB input pins are multi function pin. It needs programming Bank0 CR58 Multi function Pin Control Registers adequately.
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W83793G
8.4.2
8.4.2.1 Location: Type:
VID Register Details
VIDA Input Value Register (VIDIN_A) Bank 0 Address 05HEX Read Only
VIDIN_A BIT 7 6 5 4 3 2 1 0
Name
BIT
VIDAIN7
VIDAIN6
VIDAIN5
VIDAIN4
VIDAIN3
VIDAIN2
VIDAIN1
VIDAIN0
DESCRIPTION
INT_Clear. 1 A one disables the SMI# and IRQ# outputs without affecting the contents of Interrupt Status Registers. The device will stop monitoring at last channel. It will resume upon clearing of this bit. VIDAIN7. Real time pin 13 input value. That is available for VRM11 only. VIDAIN6. Real time pin 12 input value. That is available for VRM10 and VRM11 only. VIDAIN5. 5 Real time pin 11 input value. That is available for VRM10, VRM11 and AMD OpteronTM 6bit VID only. VIDAIN4. Real time pin 10 input value. VIDAIN3. Real time pin 40 input value. VIDAIN2. Real time pin 39 input value. VIDAIN1. Real time pin 38 input value. VIDAIN0. Real time pin 37 input value.
7 6
4 3 2 1 0
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W83793G
8.4.2.2 Location: Type: VIDB Input Value Register (VIDIN_B) Bank 0 Address 06HEX Read Only
VIDIN_B BIT 7 6 5 4 3 2 1 0
Name
VIDBIN7
VIDBIN6
VIDBIN5
VIDBIN4
VIDBIN3
VIDBIN2
VIDBIN1
VIDBIN0
BIT
DESCRIPTION
7 6
VIDBIN7. Real time pin 56 input value. That is available for VRM11 only. VIDBIN6. Real time pin 55 input value. That is available for VRM10 and VRM11 only. VIDBIN5. Real time pin 54 input value. That is available for VRM10, VRM11 and AMD OpteronTM 6-bit VID only. VIDBIN4. Real time pin 53 input value. VIDBIN3. Real time pin 52 input value. VIDBIN2. Real time pin 51 input value. VIDBIN1. Real time pin 50 input value. VIDBIN0. Real time pin 49 input value. VIDA Latch Value Register (VIDA_Latch)
5
4 3 2 1 0 8.4.2.3
Previous VIDIN_A and VIDIN_B allows user to readout the current value on VID pins, but VIDA_Latch and VIDB_Latch can let users to keep the VID value at any time by assigning the Latch_VIDA/Latch_VIDB bits to 1. Location: Type: Bank 0 Address 07HEX Read Only
VIDA_LATCH BIT 7 6 5 4 3 2 1 0
Name
VIDA7
VIDA6
VIDA5
VIDA4
VIDA3
VIDA2
VIDA1
VIDA0
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W83793G
BIT DESCRIPTION
VIDA7. 7 To read this bit will return VIDA7 register value if Latch_VIDA is set to 1 else return the pin value of VIDAIN7. VIDA6. 6 To read this bit will return VIDA6 register value if Latch_VIDA is set to 1 else return the pin value of VIDAIN6. VIDA5. 5 To read this bit will return VIDA5 register value if Latch_VIDA is set to 1 else return the pin value of VIDAIN5. VIDA4. 4 To read this bit will return VIDA4 register value if Latch_VIDA is set to 1 else return the pin value of VIDAIN4. VIDA3. 3 To read this bit will return VIDA3 register value if Latch_VIDA is set to 1 else return the pin value of VIDAIN3. VIDA2. 2 To read this bit will return VIDA2 register value if Latch_VIDA is set to 1 else return the pin value of VIDAIN2. VIDA1. 1 To read this bit will return VIDA1 register value if Latch_VIDA is set to 1 else return the pin value of VIDAIN1. VIDA0. 0 To read this bit will return VIDA0 register value if Latch_VIDA is set to 1 else return the pin value of VIDAIN0.
8.4.2.4 Location: Type:
VIDB Latch Value Register (VIDB_Latch) Bank 0 Address 08HEX Read Only
VIDB_LATCH
BIT
7
6
5
4
3
2
1
0
Name
VIDB7
VIDB6
VIDB5
VIDB4
VIDB3
VIDB2
VIDB1
VIDB0
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W83793G
BIT
DESCRIPTION
7 6 5 4 3 2 1 0
VIDB7. To read this bit will return VIDB7 register value if Latch_VIDB is set to 1 else return the pin value of VIDBIN7. VIDB6. To read this bit will return VIDB6 register value if Latch_VIDB is set to 1 else return the pin value of VIDBIN6. VIDB5. To read this bit will return VIDB5 register value if Latch_VIDB is set to 1 else return the pin value of VIDBIN5. VIDB4. To read this bit will return VIDB4 register value if Latch_VIDB is set to 1 else return the pin value of VIDBIN4. VIDB3. To read this bit will return VIDB3 register value if Latch_VIDB is set to 1 else return the pin value of VIDBIN3. VIDB2. To read this bit will return VIDB2 register value if Latch_VIDB is set to 1 else return the pin value of VIDBIN2. VIDB1. To read this bit will return VIDB1 register value if Latch_VIDB is set to 1 else return the pin value of VIDBIN1. VIDB0. To read this bit will return VIDB0 register value if Latch_VIDB is set to 1 else return the pin value of VIDBIN0.
8.4.2.5 Location: Type: Reset:
VID Control Register (VID_Control) Bank 0 Address 59HEX Read / Write VSB5V (Pin 7) Rising, Init Reset (CR40.Bit7) is set, VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set, SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
VID_CONTROL
BIT
7
6
5
4
3
2
1
0
Name Reset
Level_Select 00BIN
EN_DVID 0
Latch_VIDB 0
Latch_VIDA 0
VID_SEL 001BIN
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W83793G
BIT
DESCRIPTION
Level_Select. Set VID input pin VIH/VIL level 7-6 00BIN : 0.6V/0.4 for VRM10, 11 01BIN : 1.6V/0.8V for AMD VID 10BIN : 2.0V/0.8V 11BIN :.Reserved. EN_DVID. 5 Write 1, dynamic VID function is enabled. If VID changed, auto-updating high/low limit of corresponding Vcore sensing voltage. If programming High/Low limit of Vcore sensing voltage manually is required, this bit has to be cleared as 0. 4 3 Latch_VIDB. Write 1, CR08 latches current pin value of VIDB. Latch_VIDA. Write 1, CR07 latches current pin value of VIDA. VID_SEL. Selectable VID tables: 000BIN : Reserved 2-0 001BIN : VRM10 (default) 010BIN : VRM11 011BIN : AMD OpteronTM 5 bit VID Codes 100BIN : AMD OpteronTM 6 bit VID Codes
8.4.2.6 Location : Type : Reset :
Vcore High Tolerance Register (VCORE_LIMHI) Bank 0 Address 09HEX Read / Write VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
VCORE_LIMHI BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Vcore High Tolerance 64HEX
DESCRIPTION
Vcore High Tolerance. 7-0 While enable dynamic VID function (set Bank0 CR59 bit5 to 1), writing Tolerance register will force VCORE Limit updated with new voltage limit for VCORE. The unit is 2mV
8.4.2.7 Location : Type : Reset :
Vcore Low Tolerance Register (VCORE_LIMLO) Bank 0 Address 0AHEX Read / Write VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
VCORE_LIMLO
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
Vcore Low Tolerance 64HEX
DESCRIPTION
Vcore Low Tolerance. 7-0 While enable dynamic VID function (set Bank0 CR59 bit5 to 1), writing Tolerance register will force VCORE Limit Generator generate new voltage limit for VCORE. The unit is 2mV
8.5
INT/SMI# Control/Status Registers
Several mechanisms are provided to alarm system when monitored channels are abnormal. At this paragraph, three kinds of control/status registers are introduced, ‘real time status’, shows currently status of each channel; ‘Channel Mask’, defines which channel need issue warning when abnormal, and when channel should not be cared due to floating or other circumstances. Final one, ‘Interrupt Status’, it gives host information of which channel is issuing alert, and host can base on this channel and do proper process to ensure system reliable.
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W83793G
8.5.1 INT/SMI Control/Status Register Map
MNEMONIC REGISTER NAME TYPE
INT_STS1 INT_STS5 MASK1 MASK5 REAL_STS1 REAL_STS5 SMIINT_Ctrl
Interrupt Status 1 RO Interrupt Status 5 SMI/IRQ Mask 1 R/W SMI/IRQ Mask 5 Real Time status 1 RO Real Time status 5 SMI/IRQ Control R/W
Pin 3 of W83793G is a multi-function pin. It can be the IRQ output or the SMI# output signal. The function is selected by programming Bank0 CR50 SMI/IRQ Control register. The interrupt mode for voltage and FANIN is only two-time interrupt mode. For temperature, there are three modes to serve: Comparator mode, One-Time Interrupt mode, and Two-Time Interrupt mode.
8.5.2
8.5.2.1
INT/SMI Control/Status Register Details
Interrupt Status Register (INT_STS)
A one represents corresponding channel have been exceed its limit. Read Interrupt Status will clear the interrupt flag. VIDCHG will assert while VID are on the fly. It indicates VID have change in last 1ms. TART will assert while target temperature cannot be achieved after 3 minutes full speed of corresponding FAN. Location: INT_STS1 - Bank 0 Address 41HEX INT_STS2 - Bank 0 Address 42HEX INT_STS3 - Bank 0 Address 43HEX INT_STS4 - Bank 0 Address 44HEX INT_STS5 - Bank 0 Address 45HEX Type: Reset: Read Only VSB5V (Pin 7) Rising, Init Reset (CR40.Bit7) is set, VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set, SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set. Publication Release Date: Dec. 11, 2006 Revision 1.0
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W83793G
INT_STS1 BIT 7 6 5 4 3 2 1 0
Name Reset
12VSEN 0
3VSEN 0
VSEN2 0
VSEN1 0
INT_STS2
Reserve 0
VTT 0
VCOREB 0
VCOREA 0
BIT
7
6
5
4
3
2
1
0
Name Reset
TD4 0
TD3 0
TD2 0
TD1 0
VIDCHG 0
VBAT 0
5VSB 0
5VDD 0
INT_STS3 BIT 7 6 5 4 3 2 1 0
Name Reset
FANIN6 0
FANIN5 0
FANIN4 0
FANIN3 0
INT_STS4
FANIN2 0
FANIN1 0
TR2 0
TR1 0
BIT
7
6
5
4
3
2
1
0
Name Reset
Reserve 0
Chassis 0
FANIN12 0
FANIN11 0
INT_STS5
FANIN10 0
FANIN9 0
FANIN8 0
FANIN7 0
BIT
7
6
5
4
3
2
1
0
Name Reset 8.5.2.2 0
Reserve 0
TART6 0
TART5 0
TART4 0
TART3 0
TART2 0
TART1 0
SMI/IRM Mask Register (MASK) interrupt
Set to one will disable the corresponding interrupt sources. Clear to 0 will enable that source.
SMI Mask4 bit 7 is CLR_CHS (Clear Chassis), write this bit with an one will clear internal caseopen latch, and after latch is clear, CLR_CHS will be reset to 0 itself. Location: MASK1 - Bank 0 Address 46HEX MASK2 - Bank 0 Address 47HEX MASK3 - Bank 0 Address 48HEX MASK4 - Bank 0 Address 49HEX MASK5 - Bank 0 Address 4AHEX
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W83793G
Type: Reset: Read / Write VSB5V (Pin 7) Rising, Init Reset (CR40.Bit7) is set, VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set, SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
MASK1 BIT 7 6 5 4 3 2 1 0
Name Reset
12VSEN 0
3VSEN 0
VSEN2 0
VSEN1 0
MASK2
Reserve 0
VTT 0
VCOREB 0
VCOREA 0
BIT
7
6
5
4
3
2
1
0
Name Reset
TD4 0
TD3 0
TD2 0
TD1 0
MASK3
VIDCHG 0
VBAT 0
5VSB 0
5VDD 0
BIT
7
6
5
4
3
2
1
0
Name Reset
FANIN6 0
FANIN5 0
FANIN4 0
FANIN3 0
MASK4
FANIN2 0
FANIN1 0
TR2 0
TR1 0
BIT
7
6
5
4
3
2
1
0
Name Reset
CLR_CHS 0
Chassis 0
FANIN12 0
FANIN11 0
MASK5
FANIN10 0
FANIN9 0
FANIN8 0
FANIN7 0
BIT
7
6
5
4
3
2
1
0
Name Reset 0
Reserve 0
TART6 0
TART5 0
TART4 0
TART3 0
TART2 0
TART1 0
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W83793G
8.5.2.3 Real Time status Register (REAL_STS)
Real-time status registers show the related channel exceeding limit or not at the polling moment. Return 1 represents related channel has exceeded the limit defined in limit registers. Location : REAL_STS1 - Bank 0 Address 4BHEX REAL_STS2 - Bank 0 Address 4CHEX REAL_STS3 - Bank 0 Address 4DHEX REAL_STS4 - Bank 0 Address 4EHEX REAL_STS5 - Bank 0 Address 4FHEX Type : Read Only Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
REAL_STS1 BIT 7 6 5 4 3 2 1 0
Name Reset
12VSEN 0
3VSEN 0
VSEN2 0
VSEN1 0
REAL_STS2
Reserve 0
VTT 0
VCOREB 0
VCOREA 0
BIT
7
6
5
4
3
2
1
0
Name Reset
TD4 0
TD3 0
TD2 0
TD1 0
REAL_STS3
VIDCHG 0
VBAT 0
5VSB 0
5VDD 0
BIT
7
6
5
4
3
2
1
0
Name Reset
FANIN6 0
FANIN5 0
FANIN4 0
FANIN3 0
REAL_STS4
FANIN2 0
FANIN1 0
TR2 0
TR1 0
BIT
7
6
5
4
3
2
1
0
Name Reset
Reserve 0
Chassis 0
FANIN12 0
FANIN11 0
FANIN10 0
FANIN9 0
FANIN8 0
FANIN7 0
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W83793G
REAL_STS5 BIT 7 6 5 4 3 2 1 0
Name Reset 8.5.2.4 Location : Type : Reset : 0
Reserve 0
TART6 0
TART5 0
TART4 0
TART3 0
TART2 0
TART1 0
SMI/IRQ Control Register (SMIINT_Ctrl) Bank 0 Address 50HEX Read / Write VSB5V(Pin 7) Rising, Init Reset (CR40.Bit7) is set, VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set, SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
SMIINT_CTRL
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
Reserve 0 0
IRQ_MD 0
IRQSEL 0
TEMP_SMI_MD 0 0
EN_IRQSMI 0
POL 0
DESCRIPTION
7-6 5
Reserved. IRQ_MD. Set 0, IRQ output level signal. Set 1, output 200 us pulse signal. Default is 0. IRQ_SEL. Set Pin 3 to IRQ mode. While 1 and EN_IRQSMI set to 1, Pin 3 enabled with IRQ interrupt output. TEMP_SMI_MD. Temperature SMI# Mode Select. 00BIN : Comparator Interrupt Mode:(Default) Temperature TD1/TD2/TD3/TD4/TR1/TR2 exceeds TO (Over-temperature) limit causes an interrupt and this interrupt will be reset by reading all the Interrupt Status.
4
3-2
01BIN : Two Time Interrupt Mode: These bits use in temperature sensor TD1/TD2/TD3/TD4/TR1/TR2 interrupt mode with hysteresis type. Temperature exceeding TO (Critical Temperature), causes an interrupt and then temperature going below THYST (Critical Temperature Hysteresis) will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO (Critical Temperature), then reset, if the temperature remains above the THYST (Critical Temperature Hysteresis).
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W83793G
Continued
BIT
DESCRIPTION
10BIN : One Time Interrupt Mode: This bit use in temperature sensor TD1/TD2/TD3/TD4/TR1/TR2 interrupt mode with hysteresis type. Temperature exceeding TO (Critical Temperature) causes an interrupt and then temperature going below THYST (Critical Temperature Hysteresis) will not cause an interrupt. Once an interrupt event has occurred by exceeding TO (Critical Temperature), then going below THYST (Critical Temperature Hysteresis), and interrupt will not occur again until the temperature exceeding TO (Critical Temperature). 11BIN : Two Time Non-related Interrupt Mode: This bit use in temperature sensor TD1/TD2/TD3/TD4/TR1/TR2 interrupt mode with hysteresis type. Temperature exceeding TO, causes an interrupt and then temperature going below THYST will also cause an interrupt. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST. If this mode is selected, for all monitor channels (it is not necessary to read the status for generating the next IRQ/SMI# pulse. 3-2
Tcritical Tcrit-hysteresis Twarning Twarning-hysteresis SMI#
**
**
**
**
Two-Time Intrrupt Mode ** : Interrupt Status is read Note: It can be programmed to be as not necessary to read the status for generating the next SMI# pulse by setting TEMP_SMI_MD = 2'b11.
1 0
EN_IRQSMI. A one enables the IRQ/SMI# Interrupt output. POL. (polarity) When set to 1, IRQ/SMI# active high. Set to 0, IRQ/SMI# active low.
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W83793G
8.6 OVT/BEEP Control Register
Another solution to deal with abnormal situation is through OVT(Over Temperature) or Beep. OVT, as it naming, represents for temperature abnormal is happening. In some applications, it can be combined with Fan control and used to throttle the Fan Speed. Beep can directly use sound of two tones to inform user system abnormal. Unlike OVT, Beep can associate with any channel.
8.6.1
OVT/BEEP Control Registers Map
MNEMONIC REGISTER NAME TYPE
OVT_Ctrl OVT_BeepEn BEEP_Ctrl1 BEEP_Ctrl5
OVT Control OVT/Beep Global Enable BEEP Control 1
R/W R/W
R/W BEEP Control 5
Pin 2 of W83793G is also a multi-function pin. It can be OVT# output signal or BEEP output signal and be selected by programming Bank0 CR52 OVT/BEEP Control register.
8.6.2
8.6.2.1
OVT/BEEP Control Registers Details
OVT Control Register (OVT_Ctrl) Bank 0 Address 51HEX Read / Write VSB5V(Pin 7) Rising.
OVT_CTRL
Location : Type : Reset :
BIT
7
OVT_MD
6
5
4
3
2
1
0
OVTPOL
Name Reset
EN_OVTR2 EN_OVTR1 EN_OVTD4 EN_OVTD3 EN_OVTD2 EN_OVTD1
0
0
0
0
0
0
0
0
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W83793G
BIT
DESCRIPTION
OVT_MD. There are two OVT# signal output type. 0BIN : Comparator Mode: (Default) Temperature exceeding Tcritical (Critical Temperature) causes the OVT# output activated until the temperature is less than THYST (Critical Temperature Hysteresis). 1BIN : Interrupt Mode: 7 Setting temperature exceeding Tcritical (Critical Temperature) causes the OVT# output activated indefinitely until reset reading temperature sensor TD1/TD2/TD3/TD4/TR1/TR2 registers. Temperature exceeding Tcritical (Critical Temperature), then OVT# reset, and then temperature going below THYST (Critical Temperature Hysteresis) will also cause the OVT# activated indefinitely until reset by reading temperature sensor TD1/TD2/TD3/TD4/TR1/TR2(reading interrupt status). Once the OVT# will not be activated by exceeding Tcritical (Critical Temperature), then reset, if the temperature remains above THYST (Critical Temperature Hysteresis), the OVT# will not be activated again. 6 EN_OVTR2. Enable temperature sensor TR2 over-temperature (OVT) output if set to 1. Default 0; disable OVTR2 output through pin OVT#. The pin OVT# is wire OR with OVTD1, OVTD2, OVTD3, OVTD4 and OVTR1. EN_OVTR1. Enable temperature sensor TR1 over-temperature (OVT) output if set to 1. Default 0; disable OVTR1 output through pin OVT#. The pin OVT# is wire OR with OVTD1, OVTD2, OVTD3, OVTD4 and OVTR2. EN_OVTD4. Enable temperature sensor TD4 over-temperature (OVT) output if set to 1. Default 0; disable OVTD4 output through pin OVT#. The pin OVT# is wire OR with OVTD1, OVTD2, OVTD3, OVTR1 and OVTR2 EN_OVTD3. Enable temperature sensor TD3 over-temperature (OVT) output if set to 1. Default 0; disable OVTD3 output through pin OVT#. The pin OVT# is wire OR with OVTD1, OVTD2, OVTD4, OVTR1 and OVTR2 EN_OVTD2. Enable temperature sensor TD2 over-temperature (OVT) output if set to 1. Default 0; disable OVTD2 output through pin OVT#. The pin OVT# is wire OR with OVTD1, OVTD3, OVTD4, OVTR1 and OVTR2 EN_OVTD1. Enable temperature sensor TD1 over-temperature (OVT) output if set to 1. Default 0; disable OVTD1 output through pin OVT#. The pin OVT# is wire OR with OVTD2, OVTD3, OVTD4, OVTR1 and OVTR2 OVTPOL. Write 1, OVT# active high. Write 0, OVT# active low.
5
4
3
2
1
0
- 34 -
W83793G
8.6.2.2 Location : Type : Reset : OVT/Beep Global Enable Register (OVT_BeepEn) Bank 0 Address 52HEX Read / Write VSB5V(Pin 7) Rising.
OVT_BEEPEN BIT 7 6 5 4 3 2
BEEPSEL
1
EN_BEEP
0
Name Reset
BIT
Reserved 0 0 0 0 0
EN_OVT 0
0
0
DESCRIPTION
7-3 2
Reserved. BEEPSEL. 1 : Direct Beep signal to Pin 2. 0 : Direct OVT signal to Pin 2. EN_BEEP. (Beep Output Global Enable)
1
1 : Beep is enabled, customer can select event trigger source from BEEP_Ctrl. 0 : Beep is disabled. ENOVT. (OVT Output Global Enable)
0
1 : OVT is enabled, users can select OVT trigger source from OVT_Ctrl. 0 : OVT is disable.
8.6.2.3 Location:
BEEP Control Register (BEEP_Ctrl)
Set to one will enable the corresponding BEEP output. Clear to 0 will disable that BEEP output. BEEP_Ctrl1 - Bank 0 Address 53HEX BEEP_Ctrl2 - Bank 0 Address 54HEX BEEP_Ctrl3 - Bank 0 Address 55HEX BEEP_Ctrl4 - Bank 0 Address 56HEX BEEP_Ctrl5 - Bank 0 Address 57HEX Type: Read / Write Init Reset (CR40.Bit7) is set, VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set, SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set. Reset: VSB5V (Pin 7) Rising,
- 35 -
Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
BEEP_CTRL1 BIT 7 6 5 4 3 2 1 0
Name Reset
12VSEN 0
3VSEN 0
VSEN2 0
VSEN1 0
Reserve 0
VTT 0
VCOREB 0
VCOREA 0
BEEP_CTRL2 BIT 7 6 5 4 3 2 1 0
Name Reset
TD4 0
TD3 0
TD2 0
TD1 0
RESERVE 0
VBAT 0
5VSB 0
5VDD 0
BEEP_CTRL3 BIT 7 6 5 4 3 2 1 0
Name Reset
FANIN6 0
FANIN5 0
FANIN4 0
FANIN3 0
FANIN2 0
FANIN1 0
TR2 0
TR1 0
BEEP_CTRL4 BIT 7 6 5 4 3 2 1 0
Name Reset
Reserve 0
Chassis 0
FANIN12 0
FANIN11 0
FANIN10 0
FANIN9 0
FANIN8 0
FANIN7 0
BEEP_CTRL5 BIT 7 6 5 4 3 2 1 0
Name Reset 0
Reserve 0
TART6 0
TART5 0
TART4 0
TART3 0
TART2 0
TART1 0
8.7
Multi-Function Pin Control Register
Many functions exhibited in W83793G are not default function, and they might share pin out with other functions. Here lists three registers defines the function enable registers.
8.7.1
Multi-Function Pin Control Register Map
MNEMONIC REGISTER NAME TYPE
MFC FANIN_Ctrl FAN_SEL
Multi-Function Pin Control FANIN Control FANIN Input Pin Redirection
R/W R/W R/W
In W83793G Pin 10~13, Pin 37~40, Pin 49~56 are multi-function pin. All non-default functions are enabled by setting Bank0 CR58, CR5C and CR5D. - 36 -
W83793G
8.7.2
8.7.2.1 Location: Type: Reset: bit 0~6: VSB5V (Pin 7) Rising, Init Reset (CR40.Bit7) is set, VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set, SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set. Bit7: Trapping at 100ms after VSB5V (Pin 7) Rising.
MFC BIT 7 6 5 4 3 2 1 0
Multi-Function Pin Control Register Details
Multi-Function Pin Control Register (MFC) Bank 0 Address 58HEX Read / Write
Name Reset
VIDBSEL Trap
SIB_SEL 0 0
SID_SEL 0 0
SIC_SEL 0
SIA_SEL 0
FAN8SEL 0
BIT
DESCRIPTION
VIDBSEL. Pin 49~56 function select. Power On Trapping input value of Pin 46. 7 1BIN: Pin49~56 are VIDB. 0BIN : Pin 49~54 are fan speed control output or fan tachometer input; function of Pin 55~56 is controlled by bit SIB_SEL. SIB_SEL. While VIDBSEL is 0, SIB_SEL set function of Pin55~56: 6 0BIN: Pin55~56 are FANIN8/FANCTRL8. 1BIN: SID_SEL. Set function of Pin39~40: 5-4 0XBIN: Pin 39~40 are VIDA2/VIDA3. 10BIN: Pin 39~40 are FANIN1/FANIN12. 11BIN:Reserved. These two bits should not be set to 11BIN. Reserved. This bit must be set to 0.
- 37 -
Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
Continued.
BIT
DESCRIPTION
SIC_SEL. Set function of Pin37~38: 3-2 0xBIN: Pin 37~38 are VIDA0/VIDA1. 10BIN: Pin 37~38 are FAIN9/FANI10. 11BIN:. Reserved. These two bits should not be set to 11BIN. SIA_SEL. Set function of Pin12~13: 0BIN: Pin 12~13 are VIDA6/VIDA7. 1BIN:. Reserved. This bit must be set to 0. FAN8SEL. Set function of Pin10~11: 0BIN: Pin 10~11 are VIDA4/VIDA5. 1BIN: Pin 12~13 are FANIN8/FANCTRL8. FANIN Control Register (FANIN_Ctrl) The register enables setup the functions of multi-function fan inputs, while reset it is cleared. (00HEX) Location: Type: Reset: Bank 0 Address 5CHEX Read / Write VSB5V (Pin 7) Rising, Init Reset (CR40.Bit7) is set, VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set, SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
FANIN_CTRL BIT 7 6 5 4 3 2 1 0
EN_FANIN6
1
0
8.7.2.2
Name Reserve EN_FANIN12 EN_FANIN11 EN_FANIN10 EN_FANIN9 Reset
BIT
EN_FANIN8 EN_FANIN7
0
0
0
0
0
0
0
0
DESCRIPTION
7 6
Reserved. EN_FANIN12.(Fan In 12 Enable Bit) 1 : If SID_SEL = 10BIN, enable FANIN12 monitor. 0 : Disable . Default is VID function.
- 38 -
W83793G
Continued.
BIT
DESCRIPTION
EN_FANIN11.(Fan In 11 Enable Bit) 5 If SID_SEL = 10, Setting to 1 will enable FANIN11 monitor. If cleared, Pin39 can be selected as Processor A VID Bit 2(EN_D-VID). EN_FANIN10.(Fan In 10 Enable Bit) 4 If SIC_SEL = 10, Setting to 1 will enable FANIN10 monitor. If cleared, Pin 38 can be selected as Processor A VID Bit 1. EN_FANIN9.(Fan In 9 Enable Bit) 3 If SIC_SEL = 10, Setting to 1 will enable FANIN9 monitor. If cleared, Pin 37 can be selected as Processor A VID Bit 0(EN_D-VID). EN_FANIN8.(Fan In 8 Enable Bit) Setting to 1 enables FANIN8 monitor. 2 If FANIN8 connect to Pin55 is desired, setting VIDBSEL = 0, SIDB_SEL = 0 and FAN8SEL = 0 are must. If FANIN8 connect to Pin 10, Setting FAN8SEL = 1 is a must. Setting to 0 enables Pin 10 with Processor A VID Bit 4(EN_D-VID) EN_FANIN7.(Fan In 7 Enable Bit) 1 If VIDBSEL = 0, Setting to 1 will enable FANIN7 monitor. Setting to 0 enables Pin 53 with Processor B VID Bit 4(VIDBSEL = 1) EN_FANIN6.(Fan In 6 Enable Bit) 0 If VIDBSEL = 0, Setting to 1 will enable FANIN6 monitor. Setting to 0 enables Pin 51 with Processor B VID Bit2(VIDBSEL = 1) 8.7.2.3 Location : Type : Reset : FANIN Input Pin Redirection Register(FANIN_Sel) Bank 0 Address 5DHEX Read / Write VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
FANIN_SEL BIT 7 6 5 4 3 2 1 0
Name Reset 0
Reserved 0 0 0
FANIN12Sel 0
FANIN11Sel 0
FANIN10Sel 0
FANIN9Sel 0
- 39 -
Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
BIT
DESCRIPTION
7-4 3
Reserve. FANIN12Sel. If FANIN12Sel is set to 0, connecting FANIIN12 to Pin 40; else connect FANIN9 to Pin 11. While FANIIN12 connect to Pin 11, Bank0 CR58 bit0 FAN8SEL must set to 1. FANIN11Sel. If FANIN11Sel is set to 0, connecting FANIIN11 to Pin 39; else connect FANIN11 to Pin 54. While FANIIN11 connect to Pin 54, Bank0 CR58 bit7 VIDBSEL must set to 0. FANIN10Sel.
2
1
If FANIN10Sel is set to 0, connecting FANIIN10 to Pin 38; else connect FANIN10 to Pin 52. While FANIIN10 connect to Pin 52, VIDBSEL must set to 0. FANIN9Sel. If FANIN9Sel is set to 0, connecting FANIIN9 to Pin 37; else connect FANIN9 to Pin 50. While FANIIN9 connect to Pin 50, VIDBSEL must set to 0.
0
8.8
Temperature Sensors Control Register
W83793G provides two sets of LM75-like sensors, and they can be treated as two independent sensors through different I2C address access(90HEX ~ 9EHEX). Two sensor can also be accessed and controlled from W83793G address(58HEX ~ 5EHEX). Here lists the control registers for the LM75-like sensors.
8.8.1
Temperature Sensors Control Register Map
MNEMONIC REGISTER NAME TYPE
TD1_Config. TD2_Config. TD_MD TR_MD TempOffeset
Temperature Sensor TD1 Configuration (LM75A) Temperature Sensor TD2 Configuration (LM75B) Temperature Sensor mode Select 1 Temperature Sensor mode Select 2 Temperature Channel Offset
R/W R/W R/W R/W R/W
8.8.2
8.8.2.1
Temperature Sensors Control Register Details
TD1 Configuration (LM75A) Register (TD1_Config) Bank 0 Address 5AHEX
Location :
Type : Read / Write Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, - 40 -
W83793G
VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
TD1_CONFIG BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserve 0 0
FaultQ1 00 0
DESCRIPTION
Reserve 0 0
STOP1 0
7-6 5-4 3-1 0
Reserved. FaultQ1. Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Reserved. STOP1. If temperature sensor TD1 is set as internal temperature sensor (CR5D), set to 1 the temperature sensor will stop monitor. TD2 Configuration (LM75B) Register (TD2_Config) Bank 0 Address 5BHEX Read / Write VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
TD2_CONFIG
8.8.2.2 Location : Type : Reset :
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
Reserve 0 0
FaultQ2 00 0
DESCRIPTION
Reserve 0 0
STOP2 0
7-6 5-4 3-1 0
Reserved. FaultQ2. Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Reserved. STOP2. If temperature sensor TD2 is set as internal temperature sensor (CR5D), set to 1 the temperature sensor will stop monitor.
- 41 -
Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
8.8.2.3 TD Mode Select Register (TD_MD)
Before enable monitor, it needs to set function of pins (Bank0.CR58) and sensor select (Bank0.CR5E) to correct value. Location : Type : Reset : TD_MD - Bank 0 Address 5EHEX Read / Write VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
TD_MD BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
TD4_MD 01
TD3_MD 01
DESCRIPTION
TD2_MD 01
TD1_MD 01
TD4_MD. Temperature D4 mode 00BIN : Temperature D4 stop monitor 7-6 01BIN : Temperature D4 start monitor using internal temperature sensor (default). 10BIN : Reserved. 11BIN : Temperature D4 start monitor using temperature sensor in Intel CPU and get result by PECI. TD3_MD. Temperature D3 mode 00BIN : Temperature D3 stop monitor 5-4 01BIN : Temperature D3 start monitor using internal temperature sensor (default). 10BIN : Reserved. 11BIN : Temperature D3 start monitor using temperature sensor in Intel CPU and get result by PECI. TD2_MD. Temperature D2 mode 00BIN: Temperature D2 stop monitor 3-2 01BIN: Temperature D2 start monitor using internal temperature sensor (default). 10BIN:. Reserved. 11BIN: Temperature D2 start monitor using temperature sensor in Intel CPU and get result by PECI. - 42 -
W83793G
Continued.
BIT
DESCRIPTION
TD1_MD. Temperature D1 mode 00BIN : Temperature D1 stop monitor 1-0 01BIN : Temperature D1 start monitor using internal temperature sensor (default). 10BIN : Reserved. 11BIN : Temperature D1 start monitor using temperature sensor in Intel CPU and get result by PECI. 8.8.2.4 Location : Type : Reset : TR Mode Select Register (TR_MD) TR_MD - Bank 0 Address 5FHEX Read / Write VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
TR_MD BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserve 0 0 0 0 0 0
TR2_MD 1
TR1_MD 1
DESCRIPTION
7-2 1 0 8.8.2.5
Reserve. TR2_MD. Setting to 1 will enable Temperature sensor TR2 monitor. TR1_MD. Setting to 1 will enable Temperature sensor TR1 monitor. Temperature Channel Offset Register (TempOffset)
Each temperature channel has a corresponding offset register, in some situation customer may want to shift the offset. Default is 00HEX. Location : TD1Offset - Bank 0 Address A8HEX TD2Offset - Bank 0 Address A9HEX TD3Offset - Bank 0 Address AAHEX
- 43 -
Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
TD4Offset - Bank 0 Address ABHEX TR1Offset - Bank 0 Address ACHEX TR2Offset - Bank 0 Address ADHEx Type : Reset : Read / Write VSB5V(Pin 7) Rising.
TD/TROFFSET BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Sign 0 0 0 0
Offset value 0 0 1 1
DESCRIPTION
7-0
TD1~TR2 Offset Value.
8.9
Voltage Channel Registers
Here, both monitored value and their corresponding limitation settings are listed. W83793G provides more detailed resolution for VCoreA, VCoreB, and Vtt channels, besides 8-bit readout, they have lower-bit can be read.
8.9.1
8.9.1.1
Voltage Channel Registers Map
Voltage Channel Monitor Value Register Map
MNEMONIC REGISTER NAME TYPE
VcoreA. VcoreB. Vtt. VINLowB. VSEN1. VSEN2. 3VSEN. 12VSEN. 5VDD. 5VSB. VBAT.
VCOREA Readout VCOREB Readout Vtt Readout VIN Low bit Readout VSEN1 Readout VSEN2 Readout 3VSEN Readout 12VSEN Readout 5VDD Readout 5VSB Readout VBAT Readout
RO RO RO RO RO RO RO RO RO RO RO
- 44 -
W83793G
8.9.1.2 Voltage Channel Limit Value Registers Map
MNEMONIC REGISTER NAME TYPE
VcoreA HL/LL. VcoreB HL/LL. Vtt HL/LL. VINHLLowB. VINLLLowB. VSEN1 HL/LL. VSEN2 HL/LL. 3VSEN HL/LL. 12VSEN HL/LL. 5VDD HL/LL. 5VSB HL/LL. VBAT HL/LL.
VCOREA High/Low Limit VCOREB High/Low Limit Vtt High/Low Limit VIN High Limit Low bit VIN Low Limit Low bit VSEN1 High/Low Limit VSEN2 High/Low Limit 3VSEN High/Low Limit 12VSEN High/Low Limit 5VDD High/Low Limit 5VSB High/Low Limit VBAT High/Low Limit
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
8.9.2
8.9.2.1
Voltage Channel Register Details
Voltage Channel Monitored Value
Location : VCOREA Readout - Bank 0 Address 10HEX VCOREB Readout - Bank 0 Address 11HEX Vtt Readout - Bank 0 Address 12HEX VIN Low bit - Bank 0 Address 1BHex VSEN1 Readout - Bank 0 Address 14HEX VSEN2 Readout - Bank 0 Address 15HEX 3VSEN Readout - Bank 0 Address 16HEX 12VSEN Readout - Bank 0 Address 17HEX 5VDD Readout - Bank 0 Address 18HEX 5VSB Readout - Bank 0 Address 19HEX VBAT Readout - Bank 0 Address 1AHEX Type : Reset : Read Only No Reset
- 45 -
Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
VOLTAGE READOUT BIT 7 6 5 4 3 2 1 0
Name
Voltage Voltage
VIN LOW BIT READOUT
BIT
7
6
5
4
3
2
1
0
Name
Reserve
VttL
VCOREBL
VcoreAL
Channel VcoreA/B, and Vtt combined two registers for each channel to express their monitor result, and so it is 10-bit format data. For example, Monitored value of VCOREA can get from combination of VCOREA Readout and VIN Low bit Readout bit1~0. In order to read the correct monitor result, it needs to read high byte first than to read its corresponding low byte. The real voltage calculation of these three channels should follow the formula Vcore A Voltage = (CR [10]*4 + CR [1B] &0x03) * 0.002; Vcore B Voltage = (CR [11]*4 + (CR [1B] &0x0C)/4) * 0.002; Vtt Voltage = (CR [12]*4 + (CR [1B] &0x30)/16) * 0.002; The rest of voltage channels only supply 8-bit output format. The real voltage calculation of these three channels should follow the formula VSEN1 VSEN2 3VSEN 12VSEN 5VSB Voltage = CR [14] * (2 * 0.008); Voltage = CR [15] * (2 * 0.008); Voltage = CR [16] * (2 * 0.008); Voltage = CR [17] * 0.008;
5VDD Voltage = CR [18] * (2 * 1.5 * 0.008)+0.15; Voltage = CR [19] * (2 * 1.5 * 0.008)+0.15; VBAT Voltage = CR [1A] * (2 * 0.008); 8.9.2.2 Location : VCOREA High Limit Bank 0 Address 60HEX VCOREA Low Limit VCOREB High Limit VCOREB Low Limit Vtt High Limit Vtt Low Limit High Limit Low bit Low Limit Low bit VSEN1 High Limit VSEN1 Low Limit VSEN2 High Limit Bank 0 Address 61HEX Bank 0 Address 62HEX Bank 0 Address 63HEX Bank 0 Address 64HEX Bank 0 Address 65HEX Bank 0 Address 68HEX Bank 0 Address 69HEX Bank 0 Address 6AHEX Bank 0 Address 6BHEX Bank 0 Address 6CHEX Voltage Channel Limitation Registers
VSEN2 Low Limi Bank 0 Address 6DHEX - 46 -
W83793G
3VSEN High Limit Bank 0 Address 6EHEX 3VSEN Low Limit Bank 0 Address 6FHEX 12VSEN High Limit Bank 0 Address 70HEX 12VSEN Low Limit Bank 0 Address 71HEX 5VDD High Limit Bank 0 Address 72HEX 5VDD Low Limit Bank 0 Address 73HEX 5VSB High Limit Bank 0 Address 74HEX 5VSB Low Limit Bank 0 Address 75HEX VBAT High Limit Bank 0 Address 76HEX VBAT Low Limit Bank 0 Address 77HEX Type : Reset : Read / Write VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set. Voltage High Limit
BIT 7 6 5 4 3 2 1 0
Name Reset
Voltage High Limit FFHEX
VOLTAGE LOW LIMIT
BIT
7
6
5
4
3
2
1
0
Name Reset
Voltage Low Limit 00HEX
VIN HIGH LIMIT LOW BIT
BIT
7
6
5
4
3
2
1
0
Name Reset
Reserve 00
VTTHLL 11
VCOREBHLL 11
VcoreAHLL 11
VIN LOW LIMIT LOW BIT BIT 7 6 5 4 3 2 1 0
Name Reset
Reserve 00
VTTLLL 00
VCOREBLLL 00
VcoreALLL 00
The code calculation of high/low limit should follow the formula VCoreA, VCoreB, Vtt Limit Setup CR60~66 CR68/69 = = [Desired Voltage]/0.008; ([Desired Voltage]/0.002) – CR60~67 * 4;
- 47 -
Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
VSEN1, VSEN2, 3VSEN Limit Setup CR6A~6F = [Desired Voltage] / 0.016;
12VSEN Limit Setup CR70~71 = [Desired Voltage] / 0.08;
5VDD, 5VSB Limit Setup CR72~75 VBAT Limit Setup CR76~77 = [Desired Voltage] / 0.016; = [Desired Voltage] / 0.024;
8.10 Temperature Channel Registers
8.10.1 Temperature Channel Register Map
8.10.1.1 Temperature Channel Monitored Value Register Map
MNEMONIC REGISTER NAME TYPE
TD1. TD2. TD3. TD4. TDLowB. TR1. TR2.
Temperature Sensor TD1 Readout Temperature Sensor TD2 Readout Temperature Sensor TD3 Readout Temperature Sensor TD4 Readout Temperature Sensor TD Low Bit Readout Temperature Sensor TR1 Readout Temperature Sensor TR2 Readout
RO RO RO RO RO RO RO
8.10.1.2 Temperature Channel Limitation Value Register Map
MNEMONIC REGISTER NAME TYPE
TD1 CT/CTH. TD1 WT/WTH. TD2 CT/CTH. TD2 WT/WTH. TD3 CT/CTH. TD3 WT/WTH. TD4 CT/CTH. TD4 WT/WTH. TR1 CT/CTH.
TD1 Critical Temperature / Critical Temperature Hysteresis TD1 Warning Temperature / Warning Temperature Hysteresis TD2 Critical Temperature / Critical Temperature Hysteresis TD2 Warning Temperature / Warning Temperature Hysteresis TD3 Critical Temperature / Critical Temperature Hysteresis TD3 Warning Temperature / Warning Temperature Hysteresis TD4 Critical Temperature / Critical Temperature Hysteresis TD4 Warning Temperature / Warning Temperature Hysteresis TR1 Critical Temperature / Critical Temperature Hysteresis
R/W R/W R/W R/W R/W R/W R/W R/W R/W
- 48 -
W83793G
Continued.
MNEMONIC
REGISTER NAME
TYPE
TR1 WT/WTH. TR2 CT/CTH. TR2 WT/WTH.
TR1 Warning Temperature / Warning Temperature Hysteresis TR2 Critical Temperature / Critical Temperature Hysteresis TR2 Warning Temperature / Warning Temperature Hysteresis
R/W R/W R/W
8.10.2 Temperature Channel Register Details
8.10.2.1 Temperature Channel Monitored Registers Location : TD1 Readout TD2 Readout TD3 Readout TD4 Readout TR1 Readout TR2 Readout Type : Read Only
TEMP READOUT BIT 7 6 5 4 3 2 1 0
- Bank 0 Address 1CHEX - Bank 0 Address 1DHEX - Bank 0 Address 1EHEX - Bank 0 Address 1FHEX - Bank 0 Address 22HEX - Bank 0 Address 20HEX - Bank 0 Address 21HEX
Low bit Readout
Name
Temperature
TD LOW BIT READOUT
BIT
7
6
5
4
3
2
1
0
Name
TD4L
TD3L
TD2L
TD1L
The format of Temperature channel readout is 2’complement. TD channel express temperature using 10-bit data including 1-bit sign bit, 7-bit integer, and 2 bits decimal. TR channel express temperature using 8-bit data including 1-bit sign bit, and 7-bit integer. For TD channel temperature = TDx + TDxL* 0.25 TR channel temperature = TRx
- 49 -
Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
8.10.2.2 Temperature Channel Limitation Registers Location: TD1 Critical TD1 Warning TD2 Critical TD2 Critical Hystersis TD2 Warning TD3 Critical TD3 Warning TD4 Critical TD4 Critical Hystersis TD4 Warning TR1 Critical TR1 Critical Hystersis TR1 Warning TR2 Critical TR2 Warning Type: Reset: Read / Write VSB5V (Pin 7) Rising.
SENSOR CRITICAL TEMPERATURE BIT 7 6 5 4 3 2 1 0
- Bank 0 Address 78HEX - Bank 0 Address 7AHEX - Bank 0 Address 7CHEX - Bank 0 Address 7DHEX - Bank 0 Address 7EHEX - Bank 0 Address 80HEX - Bank 0 Address 82HEX - Bank 0 Address 84HEX - Bank 0 Address 85HEX - Bank 0 Address 86HEX - Bank 0 Address 88HEX - Bank 0 Address 89HEX - Bank 0 Address 8AHEX - Bank 0 Address 8CHEX - Bank 0 Address 8EHEX
TD1 Critical Hystersis - Bank 0 Address 79HEX TD1 Warning Hystersis - Bank 0 Address 7BHEX
TD2 Warning Hystersis - Bank 0 Address 7FHEX TD3 Critical Hystersis - Bank 0 Address 81HEX TD3 Warning Hystersis - Bank 0 Address 83HEX
TD4 Warning Hystersis - Bank 0 Address 87HEX
TR1 Warning Hystersis-Bank 0 Address 8BHEX TR2 Critical Hystersis - Bank 0 Address 8DHEX TR2 Warning Hystersis- Bank 0 Address 8FHEX
Name Reset
Temp Critical Temperature 64HEX (100 C)
- 50 -
W83793G
SENSOR CRITICAL TEMPERATURE HYSTERSIS BIT 7 6 5 4 3 2 1 0
Name Reset
Sensor Critical Temperature Hysteresis 5FHEX (95 C)
SENSOR CRITICAL TEMPERATURE
BIT
7
6
5
4
3
2
1
0
Name Reset
Sensor Warning Temperature 55HEX (85 C)
SENSOR WARNING TEMPERATURE HYSTERSIS
BIT
7
6
5
4
3
2
1
0
Name Reset
Sensor Warning Temperature Hysteresis 50HEX (80 C)
The format of Temperature channel limit is 2’complement, bit 7 is sign bit, range is –128~127.
8.11 Fan Control Registers
All Fan Control/Status register are allocated in Bank 0 and Bank 2. Bank 0 resides common-used control/status registers, and Bank 2 inside has Smart Fan Control setups.
8.11.1 Fan Register Map
8.11.1.1 Common Register Control/Status registers Block All common Fan Control/Status registers are located in Bank 0.
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
MNEMONIC REGISTER NAME TYPE
Fan1CountH/L. | Fan12CountH/L. Fan1LimitH/L. | Fan12LimitH/L. FanCtrl1. FanCtrl2. DefaultSpeed. Fan1Duty. | Fan8Duty. PWM1Prescalar. | PWM8Prescalar. Here listed registers which can read out tachometer values, and their limit registers. All these registers are separated into 2 bytes. Reading tachometer count high byte will lock the corresponding low byte to ensure next reading on low byte will get consistent data with high byte. Due to Fan input 6~12 are multifunction pins, FanInControl provides selection between FanIn functions or other functions. Also here provides Fan Output style(DC/PWM), Duty cycle, and frequency controls. 8.11.1.2 Smart Fan Setup/Status registers Registers of SmartFan setup resides in Bank 0 and Bank 2. Most used step timing control and critical temperature setup are located in Bank 0, all others located in Bank 2. Fan PWM output frequency pre-scalar RW Current Fan output Duty Cycle RW Fan Output style Control Default Fan Speed at power-on RW RW Fan Count Limit high/low Byte RW Fan tachometer readout high/low Byte RO
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W83793G
MNEMONIC REGISTER NAME TYPE
UpTime. DownTime. CriticalTemp. TD1FanSelect. TR2FanSelect. FanCtrlMode. TolTD12.
SmartFan Fan Step Up Time SmartFan Fan Step Down Time All Fan full speed temperature Temperature to Fan mapping relationships in SmartFan mode SmartFan Control Mode Select Hysteresis tolerance of each temperature source
RW RW RW
RW RW RW
TolTR12. Fan1Nonstop. Fan Output Nonstop Duty cycle Fan8Nonstop. Fan1Start. Fan Output Start Duty Cycle Fan8Start. Fan1StopTime. Fan Stop Time from nonstop level to turn off. Fan8StopTime. Smart Fan Mode is activated on corresponding Fan once users define their relationship with temperature input in TempFanSelect. Under SmartFan Mode, user can select Thermal Cruise mode or Smart Fan II mode by assigning FanCtrlMode. TempFanSelect enables users to arbitrarily define the Temperature-to-Fan relationship. For example, one can define Thermistor input 1 as chassis temperature sensor, and Temperature 1(Diode Input 1) as CPU sensor. User can do following manipulation to the Fan1(CPU Fan) and Fan2(System Fan). Assigning TD1FanSelect 03HEX and TR1FanSelect 02HEX, W83793G will associate the system Fan with CPU sensor and Chassis sensor, but CPU Fan only affects by CPU sensor. More descriptions can be found at the register definition section for this issue. Under SmartFan Mode, a specific temperature will be defined in CriticalTemp, when any temperature input detected temperature higher than this will cause all fan to full speed simultaneously. Beside this, in normal use several control parameters can be defined in following graph. RW RW RW
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W83793G
8.11.1.3 Thermal Cruise Mode Registers(Bank 2)
MNEMONIC REGISTER NAME TYPE
TD1Target. Target Temperature of Temperature inputs TR2Target. Thermal Cruise mode is an algorithm to control Fan speed to keep the temperature source around the target temperature. If the temperature source detects temperatures higher or lower than target with TolTemp tolerance, Smart Fan Control will take actions to speed up or lower down the fan to keep the temperature within the tolerance range.
Temperature
RW
TolTemp
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TolTemp
W83793G
The concept is quite simple, when temperature is larger(not include equal) than TargetTemp+TolTemp, Fan will speed up; When temperature is less(not include equal) than TargetTemp-TolTemp, Fan will slow down; Otherwise, Fan keeps its current speed. 8.11.1.4 Smart Fan II Control registers(Bank 2)
MNEMONIC REGISTER NAME TYPE
TD1Level01. Smart Fan II Fan Transition temperature levels TR2Level67. TD1FanLevel0. Smart Fan II Fan Output Levels TR2FanLevel6. Smart Fan II algorithm provides user a mechanism to setup Fan speed via Temperature level relationship. Each temperature source has a corresponding table, and totally six tables are used to control Temperature 1(D1) to Temperature 6 (R2). A table is consisted of 7 temperature levels and 7 fan levels as following. RW RW
TempLevel01
TempLevel12
TempLevel23
TempLevel34
TempLevel45
TempLevel56
While Fan speed jump from one level to another level, there is a hysterisis mechanism to prevent fan from throttling. When speed jump high to another level, temperature need to at specified temperature level, but instead when speed is slow down, it must wait until temperature is lower than specified temperature level minus tolerance.
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TempLevel67
Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
8.11.2 Fan Register Details
8.11.2.1 Fan Tachometer Readout high/low Byte Register(FanCountH/L) The FanCountH/L maintains current count value of corresponding Fan inputs. When VSB 5V power on, it is cleared(00HEX). Effective width of FanCountH/L is 12-bits, FanCountH high nibble is not used. Location : Fan1CountH - Bank 0 Address 23HEX Fan1CountL – Bank 0 Address 24HEX Fan2CountH – Bank 0 Address 25HEX Fan2CountL – Bank 0 Address 26HEX Fan3CountH – Bank 0 Address 27HEX Fan3CountL – Bank 0 Address 28HEX Fan4CountH – Bank 0 Address 29HEX Fan4CountL – Bank 0 Address 2AHEX Fan5CountH – Bank 0 Address 2BHEX Fan5CountL – Bank 0 Address 2CHEX Fan6CountH – Bank 0 Address 2DHEX Fan6CountL – Bank 0 Address 2EHEX Fan7CountH – Bank 0 Address 2FHEX Fan7CountL – Bank 0 Address 30HEX Fan8CountH – Bank 0 Address 31HEX Fan8CountL – Bank 0 Address 32HEX Fan9CountH – Bank 0 Address 33HEX Fan9CountL – Bank 0 Address 34HEX Fan10CountH – Bank 0 Address 35HEX Fan10CountL – Bank 0 Address 36HEX Fan11CountH – Bank 0 Address 37HEX Fan11CountL – Bank 0 Address 38HEX Fan12CountH – Bank 0 Address 39HEX Fan12CountL – Bank 0 Address 3AHEX Type : Reset : Read Only VSB5V(Pin 7) Rising
FAN1COUNTH~FAN12COUNTH BIT 7 6 5 4 3 2 1 0
Name Reset
FanCountH 00HEX
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W83793G
BIT DESCRIPTION
7-0
FanCountH(Fan tachometer readout high byte). The count value high byte of FanIn signal period with 45KHz clock.
FAN1COUNTL~FAN12COUNTL
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
FanCountL 00HEX
DESCRIPTION
7-0
FanCountL(Fan tachometer readout low byte). The count value low byte of FanIn signal period with 45KHz clock.
FAN COUNT CALCULATION
Fan1CountL combined with Fan1CountH forms the 12-bit count value. If reading the Fan1CountH and Fan1CountL successively, W83793G will make these two count value consistent( i.e. The same counting). If user read them in reverse order or other read/write between them, it is possible that the high/low byte may come from different counting and leads to some abnormal reading. Same rules can be applied to other FanCounts. Real RPM(Rotate Per Minute) calculations should follow the formula
FanSpeed ( RPM ) =
1.35 × 10 6 (12 − bitCountValue) × ( FanPoles ) 4
In this formula, 12-bitCountValue represents the values stored in the FanCountH/L, and FanPoles stands for the number of NS poles pair inside the Fan, normally a N-S-N-S Fan(FanPoles = 4) will generate 2 pulses when complete one rotate. Fan tachometer normal operating range is below 4.5KHz(if FanPoles=4, it means 135KRPM), nearly impossible but a Fan rotating faster than this will cause W83793G works abnormally. 8.11.2.2 Fan Count Limit High/Low Byte(FanLimitH/L)
The FanLimitH/L setups the Limit range for Fan in count values, if counter counts value larger than these register indicates, W83793G will show alert in real-time status and may take further actions based on user setups. While reset it is set(FFHEX). Location : Fan1LimitH - Bank 0 Address 90HEX Fan1LimitL – Bank 0 Address 91HEX Fan2LimitH – Bank 0 Address 92HEX Fan2LimitL – Bank 0 Address 93HEX Fan3LimitH – Bank 0 Address 94HEX Fan3LimitL – Bank 0 Address 95HEX
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
Fan4LimitH – Bank 0 Address 96HEX Fan4LimitL – Bank 0 Address 97HEX Fan5LimitH – Bank 0 Address 98HEX Fan5LimitL – Bank 0 Address 99HEX Fan6LimitH – Bank 0 Address 9AHEX Fan6LimitL – Bank 0 Address 9BHEX Fan7LimitH – Bank 0 Address 9CHEX Fan7LimitL – Bank 0 Address 9DHEX Fan8LimitH – Bank 0 Address 9EHEX Fan8LimitL – Bank 0 Address 9FHEX Fan9LimitH – Bank 0 Address A0HEX Fan9LimitL – Bank 0 Address A1HEX Fan10LimitH – Bank 0 Address A2HEX Fan10LimitL – Bank 0 Address A3HEX Fan11LimitH – Bank 0 Address A4HEX Fan11LimitL – Bank 0 Address A5HEX Fan12LimitH – Bank 0 Address A6HEX Fan12LimitL – Bank 0 Address A7HEX Type : Reset : Read / Write VSB5V(Pin 7) Rising.
FAN1LIMITH ~ FAN12LIMITH BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
FanLimitH FFHEX
DESCRIPTION
7-0
FanLimitH(Fan tachometer limit high byte). The limitation of count value high byte of FanIn.
FAN1LIMITL~FAN12LIMITL
BIT
7
6
5
4
3
2
1
0
Name Reset
FanLimitL FFHEX
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W83793G
BIT
DESCRIPTION
7-0
FanLimitL(Fan tachometer readout limit low byte). The limitation count value low byte of FanIn.
8.11.2.3 Fan Output Style Control (FanCtrl) The FanCtrl1/2 decides the Fan output style. There are several output styles available in W83793G, which are OD mode(Open-Drain), OB mode(Ouput-Buffer), and DC mode(DAC output). Default all fans outputs are set to OD mode. Location : FanCtrl1 - Bank 0 Address B0HEX FanCtrl2 – Bank 0 Address B1HEX Type : Read / Write Reset : . VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
FANCTRL1 BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
F8OB 0
F7OB 0
F6OB 0
F5OB 0
DESCRIPTION
F4OB 0
F3OB 0
F2OB 0
F1OB 0
F8OB(Fan output 8 Output Buffer Mode Control). 7 0: Depends on F8DC(CRB1.Bit7), if F8DC=1, Pin 11 output with DC mode. Otherwise output is configured with OD mode. 1: Depends on F8DC(CRB1.Bit7), if F8DC=1, Pin 11 output with DC mode. Otherwise output is configured with OB mode F7OB(Fan output 7 Output Buffer Mode Control). 6 0: Depends on F7DC(CRB1.Bit6), if F7DC=1, Pin 54 output with DC mode. Otherwise output is configured with OD mode. 1: Depends on F7DC(CRB1.Bit6), if F7DC=1, Pin 54 output with DC mode. Otherwise output is configured with OB mode F6OB(Fan output 6 Output Buffer Mode Control). 5 0: Depends on F6DC(CRB1.Bit5), if F6DC=1, Pin 52 output with DC mode. Otherwise output is configured with OD mode. 1: Depends on F6DC(CRB1.Bit5), if F6DC=1, Pin 52 output with DC mode. Otherwise output is configured with OB mode
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W83793G
Continued.
BIT
DESCRIPTION
F5OB(Fan output 5 Output Buffer Mode Control). 4 0: Depends on F5DC(CRB1.Bit4), if F5DC=1, Pin 50 output with DC mode. Otherwise output is configured with OD mode. 1: Depends on F5DC(CRB1.Bit4), if F5DC=1, Pin 50 output with DC mode. Otherwise output is configured with OB mode F4OB(Fan output 4 Output Buffer Mode Control). 3 0: Depends on F4DC(CRB1.Bit3), if F4DC=1, Pin 49 output with DC mode. Otherwise output is configured with OD mode. 1: Depends on F4DC(CRB1.Bit3), if F4DC=1, Pin 49 output with DC mode. Otherwise output is configured with OB mode F3OB(Fan output 3 Output Buffer Mode Control). 2 0: Depends on F3DC(CRB1.Bit2), if F3DC=1, Pin 46 output with DC mode. Otherwise output is configured with OD mode. 1: Depends on F3DC(CRB1.Bit2), if F3DC=1, Pin 46 output with DC mode. Otherwise output is configured with OB mode F2OB(Fan output 2 Output Buffer Mode Control). 1 0: Depends on F2DC(CRB1.Bit1), if F2DC=1, Pin 44 output with DC mode. Otherwise output is configured with OD mode. 1: Depends on F2DC(CRB1.Bit1), if F2DC=1, Pin 44 output with DC mode. Otherwise output is configured with OB mode F1OB(Fan output 1 Output Buffer Mode Control). 0 0: Depends on F1DC(CRB1.Bit0), if F1DC=1, Pin 42 output with DC mode. Otherwise output is configured with OD mode. 1: Depends on F1DC(CRB1.Bit0), if F1DC=1, Pin 42 output with DC mode. Otherwise output is configured with OB mode
FANCTRL2 BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
F8DC 0
F7DC 0
F6DC 0
F5DC 0
DESCRIPTION
F4DC 0
F3DC 0
F2DC 0
F1DC 0
F8DC(Fan output 8 Direct Current Mode Control). 7 0: OD or OB mode on Pin 11. Depend on F8OB(CRB0.Bit7) 1: Pin 11 set as DC mode.
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W83793G
Continued.
BIT
DESCRIPTION
F7DC(Fan output 7 Direct Current Mode Control). 6 0: OD or OB mode on Pin 54. Depend on F7OB(CRB0.Bit6) 1: Pin 54 set as DC mode. F6DC(Fan output 6 Direct Current Mode Control). 5 0: OD or OB mode on Pin 52. Depend on F6OB(CRB0.Bit5) 1: Pin 52 set as DC mode. F5DC(Fan output 5 Direct Current Mode Control). 4 0: OD or OB mode on Pin 50. Depend on F5OB(CRB0.Bit4) 1: Pin 50 set as DC mode. F4DC(Fan output 4 Direct Current Mode Control). 3 0: OD or OB mode on Pin 49. Depend on F4OB(CRB0.Bit3) 1: Pin 49 set as DC mode. F3DC(Fan output 3 Direct Current Mode Control). 2 0: OD or OB mode on Pin 46. Depend on F3OB(CRB0.Bit2) 1: Pin 46 set as DC mode. F2DC(Fan output 2 Direct Current Mode Control). 1 0: OD or OB mode on Pin 44. Depend on F2OB(CRB0.Bit1) 1: Pin 44 set as DC mode. F1DC(Fan output 1 Direct Current Mode Control). 0 0: OD or OB mode on Pin 42. Depend on F1OB(CRB0.Bit0) 1: Pin 42 set as DC mode. 8.11.2.4 Default Fan Speed at Power-on (DefaultSpeed) DefaultSpeed set the initial speed of every fan. When system is turned on, all Fans output will be set a default Duty as this register content. This register’s reset is specially design to be reset by VSB only, so at second system power on, the system will use the lastest setup speed to turn on all Fans. Location : Type : Reset : DefaultSpeed - Bank 0 Address B2HEX Read / Write VSB5V(Pin 7) Rising.
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
DefaultSpeed
BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0 0
DESCRIPTION
DefaultSpeed 30HEX
7-6 5-0
Reserved. DefaultSpeed(Default Fan Speed at Power-on). Specifies The Fan Duty at next power on.
8.11.2.5 Current Fan Output Duty Cycle (FanDuty) FanDuty reflects the current output duty cycle. In manual mode it also can be set user desired duty cycles. But in Smart Fan mode, it is read-only. Location : Fan1Duty - Bank 0 Address B3HEX Fan2Duty - Bank 0 Address B4HEX Fan3Duty - Bank 0 Address B5HEX Fan4Duty - Bank 0 Address B6HEX Fan5Duty - Bank 0 Address B7HEX Fan6Duty - Bank 0 Address B8HEX Fan7Duty - Bank 0 Address B9HEX Fan8Duty - Bank 0 Address BAHEX Type : Read / Write(Only in Manual Mode, make sure 5VDD and Pin 1 CLK is ready) Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
FAN1DUTY ~ FAN8DUTY BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0 0
FanDuty Depend on DefaultSpeed.
DESCRIPTION
7-6 5-0
Reserved. FanDuty(Current Fan output Duty Cycle). Specifies the current Fan output duty cycle. While VDD5V is low, this register is forcing to be zero by hardware.
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W83793G
FanDuty also has a special characteristic; it’s called sequential power-on. This function is used to avoid system current over-load while system power-on and all fans start to spin. W83793G will turn on each fan in sequence and it take 0.1sec to power on all fans.(12.5ms intervals for 8 Fans) 8.11.2.6 Fan PWM Output Frequency Prescalar (PWMPrescalar) PWMPrescalar controls the output frequency in PWM mode. Here a large range of clock can be selected to fit customer needs. Default output frequency is 25KHz. Location : PWM1Prescalar - Bank 0 Address BBHEX PWM2Prescalar - Bank 0 Address BCHEX PWM3Prescalar - Bank 0 Address BDHEX PWM4Prescalar - Bank 0 Address BEHEX PWM5Prescalar - Bank 0 Address BFHEX PWM6Prescalar - Bank 0 Address C0HEX PWM7Prescalar - Bank 0 Address C1HEX PWM8Prescalar - Bank 0 Address C2HEX Type : Read / Write(Only in Manual Mode) Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
PWM1PRESCALAR ~ PWM8PRESCALAR BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
CKSEL 1
Divisor 09HEX
DESCRIPTION
CKSEL(clock source select). 7 6-0 0: 512Hz. 1: 250KHz. Divisor(Clock Divisor). Clock frequency Divisor. The clock source selected by CKSEL will be divided by Divisor and used as a Fan PWM output frequency. There are 2 cases of Divisor depends on CKSEL. If CKSEL equals 1, then output clock is simply equals to 250/(Divisor+1) KHz. If CKSEL equals 0, output clock is 512Hz/MappedDivisor. MappedDivisor depends on Divisor[3:0] and looks like below table. Publication Release Date: Dec. 11, 2006 Revision 1.0
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W83793G
DIVISOR[3:0]
MAPPED DIVISOR
OUTPUT FREQUENCY
DIVISOR[3:0]
MAPPED DIVISOR
OUTPUT FREQUENCY
0000 0001 0010 0011 0100 0101 0110 0111
1 2 3 4 5 6 7 8
512Hz 256Hz 171Hz 128Hz 102Hz 85Hz 73Hz 64Hz
1000 1001 1010 1011 1100 1101 1110 1111
12 16 32 64 128 256 512 1024
43Hz 32Hz 16Hz 8Hz 4Hz 2Hz 1Hz 0.5Hz
8.11.2.7 SmartFan Output Step Up Time (UpTime) UpTime regulates the time interval of fastest Fan speed up a unit. Default setting is 0.6sec. Location : Reset : UpTime - Bank 0 Address C3HEX VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
UPTIME BIT 7 6 5 4 3 2 1 0
Type : Read / Write
Name Reset
BIT
UpTime 06HEX
DESCRIPTION
7-0
UpTime(SmartFan Step Up Time). Unit in 0.1sec. Programmed as the interval of continuous Fan ramping up.
SmartFan mostly control fans smoothly, which means it seldom suddenly add a large duty to fan or decrease a large duty. Instead, most often it increase/decrease duty by 1 LSB one time. The Up Time / Down Time register defines the time interval between successively increase/decrease duty. If this value set too small, Fan will have no time to reflect the speed after tuning the duty and sometimes may cause Fan speed unstable; on the other hand, if set Up Time / Down Time too large, Fan may not act fast enough to dissipate the heat. This register should never set to 0, otherwise will cause Fan Duty abnormal. Only in these cases, fan will suddenly jump large duty. VDD Power – on/off - 64 -
W83793G
Critical Temperature reached Fan Turn off state to Start Fan at NonStop Level to turn off state 8.11.2.8 SmartFan Output Step Down Time (DownTime) Down Time regulates the time interval of fastest Fan speed lowered a unit. Default setting is 0.6sec. Location : Reset : DownTime - Bank 0 Address C4HEXType : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
DOWNTIME BIT 7 6 5 4 3 2 1 0
Read / Write
Name Reset
BIT
DownTime 06HEX
DESCRIPTION
7-0
DownTime(SmartFan Step Down Time). Unit in 0.1sec. Programmed as the interval of continuous Fan ramping Down.
This register should never set to 0, otherwise will cause Fan Duty abnormal. 8.11.2.9 All Fan Full Speed Temperature (CriticalTemp) CriticalTemp defines a system critical temperature while exceeding this temperature may lead to system damage or crash. When W83793G detects any temperature input exceeding CriticalTemp, it will speed all Fans and try to lowering the temperature. Location : CritcalTemp - Bank 0 Address C5HEX Type : Read / Write Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
UPTIME BIT 7 6 5 4 3 2 1 0
Name Reset
Reserved 0
CriticalTemp 50HEX Publication Release Date: Dec. 11, 2006 Revision 1.0
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W83793G
BIT
DESCRIPTION
7 6-0
Reserved. CriticalTemp(All Fan Full Speed Temperature).
8.11.2.10 Temperature to Fan mapping relationships Register (TempFanSelect) The TempFanSelect is responsible for dealing with the relationship between Fan and Temperature source. While reset it is cleared(00HEX). Location : TD1FanSelect - Bank 2 Address 01HEX TD2FanSelect - Bank 2 Address 02HEX TD3FanSelect - Bank 2 Address 03HEX TD4FanSelect - Bank 2 Address 04HEX TR1FanSelect - Bank 2 Address 05HEX TR2FanSelect - Bank 2 Address 06HEX Type : Read / Write Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
TD1FANSELECT ~ TR2FANSELECT BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Fan8 0
Fan7 0
Fan6 0
Fan5 0
Fan4 0
Fan3 0
Fan2 0
Fan1 0
DESCRIPTION
Fan8(Enable Fan8 Smart Fan). 7 0: Fan8 has no relation with this temperature source. 1: Applies SmartFan control on Fan8 and this temperature. Fan7(Enable Fan7 Smart Fan). 6 0: Fan7 has no relation with this temperature source. 1: Applies SmartFan control on Fan7 and this temperature. Fan6(Enable Fan6 Smart Fan). 5 0: Fan6 has no relation with this temperature source. 1: Applies SmartFan control on Fan6 and this temperature.
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W83793G
Continued.
BIT
DESCRIPTION
Fan5(Enable Fan5 Smart Fan). 4 0: Fan5 has no relation with this temperature source. 1: Applies SmartFan control on Fan5 and this temperature. Fan4(Enable Fan4 Smart Fan). 3 0: Fan4 has no relation with this temperature source. 1: Applies SmartFan control on Fan4 and this temperature. Fan3(Enable Fan3 Smart Fan). 2 0: Fan3 has no relation with this temperature source. 1: Applies SmartFan control on Fan3 and this temperature. Fan2(Enable Fan2 Smart Fan). 1 0: Fan2 has no relation with this temperature source. 1: Applies SmartFan control on Fan2 and this temperature. Fan1(Enable Fan1 Smart Fan). 0 0: Fan1 has no relation with this temperature source. 1: Applies SmartFan control on Fan1 and this temperature. Here using an example to explain the concept of TempFanSelect Mapping. Considering this case, TD1FanSelect is set to 86HEX, TD2FanSelect is set to 52HEX, TD3FanSelect is set 20HEX, and other 3 left unset.
We can spilt the six registers bit by bit as above figure, and give it a rotation, this help us to understand the relationship from the point of fan easier. For Fan1 and Fan4 row, all temperature is deasserted, that means Fan1/Fan4 does not have any relationship with temperature, thus they are in manual mode under this setting. For Fan2, it is clear that it has relation with temperature 1 and 2, so it will activate SmartFan control with temperature 1/2 as it input.
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W83793G
Temperature 1 Fan1
The right graph give a picture of how the mapping relationship is made by this setting. In this example, Fan2 retrieves information from Temperature 1 and Temperature 2, and decide the next duty cycle applied to Fan2. But how did it decide to speed up/slow down fan? Basically, W83793G sorting the information comes from each temperature sensor and SmartFan Controls. After sorting the information, W83793G will get something like, TD1 need to speed up fan, and TD2 does not need so fast Fan speed; or TD1 would no more need fast fan, and TD2 hopes to keep current fan speed. And after that, the algorithm will make a decision to control fan by a very simple rule, which can expressed very simply in the following.
Temperature 2
Fan2
Fan3 Temperature 3 Fan4 Temperature 4
Fan5
Temperature 5
Fan6
Temperature 6
Fan7
Fan8
Any Temp request faster Fan??
If TD1 say, “I need faster fan”, and TD2 says, “No fast fan needed”. W83793G will take request of TD1 and start to speed up Fan. In short, W83793G always prefers to pick the most critical request and applies it to the related Fan.
Yes Speed Up
No
Any Temp request f hold current speed??
Yes
Hold current Speed
No
Slow Down
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W83793G
8.11.2.11 SmartFan Control Mode Select Register (FanCtrlMode) There are two SmartFan modes supported with W83793G once SmartFan function enabled (Please refer TempFanSelect to enable SmartFan Function), they are Thermal Cruise mode and SmartFan II mode. While reset it is cleared (00HEX), SmartFan II mode. Location : FanCtrlMode - Bank 2 Address 07HEX Type : Read / Write Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
FANCTRLMODE BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0 0
TR2_MD 0
TR1_MD 0
TD4_MD 0
TD3_MD 0
TD2_MD 0
TD1_MD 0
DESCRIPTION
7-6 5
4
3
2
1
0
Reserved. TR2_MD (Thermistor 2 SmartFan Control Mode) 0: SmartFan II mode. 1: Thermal Cruise mode. TR1_MD (Thermistor 1 SmartFan Control Mode) 0: SmartFan II mode. 1: Thermal Cruise mode. TD4_MD (Thermal Diode 4 SmartFan Control Mode) 0: SmartFan II mode. 1: Thermal Cruise mode. TD3_MD (Thermal Diode 3 SmartFan Control Mode) 0: SmartFan II mode. 1: Thermal Cruise mode. TD2_MD (Thermal Diode 2 SmartFan Control Mode) 0: SmartFan II mode. 1: Thermal Cruise mode. TD1_MD (Thermal Diode 1 SmartFan Control Mode) 0: SmartFan II mode. 1: Thermal Cruise mode.
8.11.2.12 Hysteresis Tolerance of Temperature Register(TolTemp) In SmartFan mode, to avoid temperature unstable causing fan throttling, W83793G uses a hysteresis temperature to separate the speed up/slow down temperature point. While reset it is set to 2℃(22HEX). Location : Publication Release Date: Dec. 11, 2006 Revision 1.0
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W83793G
TolTD12 - Bank 2 Address 08HEX TolTD34 - Bank 2 Address 09HEX TolTR12 - Bank 2 Address 0AHEX Type : Read / Write Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
TOLTD12 BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
TolTD2 2HEX
DESCRIPTION
TolTD1 2HEX
7-4 3-0
TolTD2(TD 2 Tolerance Range). Unit in ℃. TolTD1(TD 1 Tolerance Range). Unit in ℃.
TOLTD34
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
TolTD4 2HEX
DESCRIPTION
TolTD3 2HEX
7-4 3-0
TolTD4(TD 4 Tolerance Range). Unit in ℃. TolTD3(TD 3 Tolerance Range). Unit in ℃.
TOLTR12
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
TolTR2 2HEX
DESCRIPTION
TolTR1 2HEX
7-4 3-0
TolTR2(TR2 Tolerance Range). Unit in ℃. TolTR1(TR1 Tolerance Range). Unit in ℃.
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W83793G
8.11.2.13 Fan Output Nonstop Duty Cycle Register(FanNonStop) Due to bring a fan from stop to work might take some time. The design of FanNonStop is hope to have a minimum duty cycle to keep the fan rotating when system does not require fan help getting ride of heat but still want to keep the fast response time to speed up fan. (Reference to Graph) Location : Fan1NonStop - Bank 2 Address 18HEX Fan2NonStop - Bank 2 Address 19HEX Fan3NonStop - Bank 2 Address 1AHEX Fan4NonStop - Bank 2 Address 1BHEX Fan5NonStop - Bank 2 Address 1CHEX Fan6NonStop - Bank 2 Address 1DHEX Fan7NonStop - Bank 2 Address 1EHEX Fan8NonStop - Bank 2 Address 1FHEX Type : Read / Write Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
FANNONSTOP BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0
FanNonStop 4HEX
DESCRIPTION
7-6 5-0
Reserved. FanNonStop(Fan Output NonStop Duty Cycle).
8.11.2.14 Fan Output Start Duty Cycle Register(FanStart) From still to rotate, Fan usually needs a higher duty cycle to generate enough torque to conquer the restriction force. Thus W83793G include a FanStart to bring the Fan live with the duty specified. (Reference to Graph) Location : Fan1Start - Bank 2 Address 20HEX Fan2Start - Bank 2 Address 21HEX Fan3Start - Bank 2 Address 22HEX Fan4Start - Bank 2 Address 23HEX
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W83793G
Fan5Start - Bank 2 Address 24HEX Fan6Start - Bank 2 Address 25HEX Fan7Start - Bank 2 Address 26HEX Fan8Start - Bank 2 Address 27HEX Type : Read / Write Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
FANSTART BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0
DESCRIPTION
FanStart 8HEX
7-6 5-0
Reserved. FanStart(Fan Output Start Duty Cycle).
8.11.2.15 Fan Output Stop Time Register(FanStopTime) A time interval is specified to tell W83793G when to turn off fan if SmartFan continuously request to slower down Fan, but fan already reached the NonStop Level. Default is 10 sec. (Reference to Graph) Location : Fan1StopTime - Bank 2 Address 28HEX Fan2StopTime - Bank 2 Address 29HEX Fan3StopTime - Bank 2 Address 2AHEX Fan4StopTime - Bank 2 Address 2BHEX Fan5StopTime - Bank 2 Address 2CHEX Fan6StopTime - Bank 2 Address 2DHEX Fan7StopTime - Bank 2 Address 2EHEX Fan8StopTime - Bank 2 Address 2FHEX Type : Read / Write Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
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W83793G
FANSTOPTIME BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
FanStopTime 64HEX
DESCRIPTION
FanStopTime(Fan Stop time from Nonstop level to turn off). 7-0 Unit in 0.1sec. Ranged from 0.1sec to 25.5sec. If set to 0, Fan will never stop. 8.11.2.16 Target Temperature of Temperature Inputs Register(TempTarget) In Thermal Cruise mode, a target temperature is needed to be defined for each temperature source. W83793G will try to tune fan speed to keep the temperature of target device around the target temperature. Default target temperature for diode sensors is 40℃, and 32℃ for thermistor sensors. Location : TD1Target - Bank 2 Address 10HEX TD2Target - Bank 2 Address 11HEX TD3Target - Bank 2 Address 12HEX TD4Target - Bank 2 Address 13HEX TR1Target - Bank 2 Address 14HEX TR2Target - Bank 2 Address 15HEX Type : Read / Write Reset : VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
TD1TARGET ~ TD4TARGET BIT 7 6 5 4 3 2 1 0
Name Reset
Reserved 0
TempTarget 28HEX
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W83793G
BIT
DESCRIPTION
7 6-0
Reserved. TempTarget. (Diode Temperature sensor target temperature). Unit in ℃
TR1TARGET ~ TR2TARGET BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0
TempTarget 20HEX
DESCRIPTION
7 6-0
Reserved. TempTarget. (Thermistor Temperature sensor target temperature). Unit in ℃
See also : TolTemp, FanCtrlMode, Thermal Cruise mode. 8.11.2.17 Smart Fan II Fan Transition Temperature Level Registers (TempLevel) SmartFan II, an algorithm providing a table mapping mechanism to translate temperature information into output Fan duties. The mapping table need user to provide 2 domains for the translation, those are at certain temperature mapping to certain duty. TempLevel(Temperature) and TempFanLevel(Duty Cycle) are used to define the table. There totally are six tables reside in W83793G, one table per temperature channel; 7 entries per table. Therefore here TempLevel will have 42 registers, and another 42 registers for TempFanLevel in this and next section. Location : TD1Level01 - Bank 2 Address 30HEX TD1Level12 - Bank 2 Address 31HEX TD1Level23 - Bank 2 Address 32HEX TD1Level34 - Bank 2 Address 33HEX TD1Level45 - Bank 2 Address 34HEX TD1Level56 - Bank 2 Address 35HEX TD1Level67 - Bank 2 Address 36HEX TD2Level01 - Bank 2 Address 40HEX TD2Level12 - Bank 2 Address 41HEX TD2Level23 - Bank 2 Address 42HEX TD2Level34 - Bank 2 Address 43HEX TD2Level45 - Bank 2 Address 44HEX - 74 -
W83793G
TD2Level56 - Bank 2 Address 45HEX TD2Level67 - Bank 2 Address 46HEX TD3Level01 - Bank 2 Address 50HEX TD3Level12 - Bank 2 Address 51HEX TD3Level23 - Bank 2 Address 52HEX TD3Level34 - Bank 2 Address 53HEX TD3Level45 - Bank 2 Address 54HEX TD3Level56 - Bank 2 Address 55HEX TD3Level67 - Bank 2 Address 56HEX TD4Level01 - Bank 2 Address 60HEX TD4Level12 - Bank 2 Address 61HEX TD4Level23 - Bank 2 Address 62HEX TD4Level34 - Bank 2 Address 63HEX TD4Level45 - Bank 2 Address 64HEX TD4Level56 - Bank 2 Address 65HEX TD4Level67 - Bank 2 Address 66HEX TR1Level01 - Bank 2 Address 70HEX TR1Level12 - Bank 2 Address 71HEX TR1Level23 - Bank 2 Address 72HEX TR1Level34 - Bank 2 Address 73HEX TR1Level45 - Bank 2 Address 74HEX TR1Level56 - Bank 2 Address 75HEX TR1Level67 - Bank 2 Address 76HEX TR2Level01 - Bank 2 Address 80HEX TR2Level12 - Bank 2 Address 81HEX TR2Level23 - Bank 2 Address 82HEX TR2Level34 - Bank 2 Address 83HEX TR2Level45 - Bank 2 Address 84HEX TR2Level56 - Bank 2 Address 85HEX TR2Level67 - Bank 2 Address 86HEX Type : Reset : Read / Write VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
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W83793G
TD1LEVEL01 ~ TR2LEVEL01 BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0
TempLevel01 1EHEX
DESCRIPTION
7 6-0
Reserved. TempLevel01. (Temperature Level between TempFanLevel0 and TempFanLevel1). Unit in ℃
TD1LEVEL12 ~ TR2LEVEL12 BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0
TempLevel12 23HEX
DESCRIPTION
7 6-0
Reserved. TempLevel12. (Temperature Level between TempFanLevel1 and TempFanLevel2). Unit in ℃
TD1LEVEL23 ~ TR2LEVEL23 BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0
TempLevel23 28HEX
DESCRIPTION
7 6-0
Reserved. TempLevel23. (Temperature Level between TempFanLevel2 and TempFanLevel3). Unit in ℃
TD1LEVEL34 ~ TR2LEVEL34 BIT 7 6 5 4 3 2 1 0
Name Reset
Reserved 0
TempLevel34 2DHEX
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W83793G
BIT DESCRIPTION
7 6-0
Reserved. TempLevel34. (Temperature Level between TempFanLevel3 and TempFanLevel4). Unit in ℃
TD1LEVEL45 ~ TR2LEVEL45 BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0
TempLevel45 32HEX
DESCRIPTION
7 6-0
Reserved. TempLevel45. (Temperature Level between TempFanLevel4 and TempFanLevel5). Unit in ℃
TD1LEVEL56 ~ TR2LEVEL56 BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0
TempLevel56 37HEX
DESCRIPTION
7 6-0
Reserved. TempLevel56. (Temperature Level between TempFanLevel5 and TempFanLevel6). Unit in ℃
TD1LEVEL67 ~ TR2LEVEL67 BIT 7 6 5 4 3 2 1 0
Name Reset
Reserved 0
TempLevel67 3CHEX
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W83793G
BIT
DESCRIPTION
7 6-0
Reserved. TempLevel67. (Temperature Level between TempFanLevel6 and TempFanLevel7). Unit in ℃
See also : TolTemp, FanCtrlMode, Smart Fan II mode. 8.11.2.18 Smart Fan II Fan Output Levels Registers (TempFanLevel) Previous section describes one temperature axis of Smart Fan II Table, here introduced Fan Duty axis for the table, TempFanLevel registers. Location : TD1FanLevel0 - Bank 2 Address 38HEX TD1FanLevel1 - Bank 2 Address 39HEX TD1FanLevel2 - Bank 2 Address 3AHEX TD1FanLevel3 - Bank 2 Address 3BHEX TD1FanLevel4 - Bank 2 Address 3CHEX TD1FanLevel5 - Bank 2 Address 3DHEX TD1FanLevel6 - Bank 2 Address 3EHEX TD2FanLevel0 - Bank 2 Address 48HEX TD2FanLevel1 - Bank 2 Address 49HEX TD2FanLevel2 - Bank 2 Address 4AHEX TD2FanLevel3 - Bank 2 Address 4BHEX TD2FanLevel4 - Bank 2 Address 4CHEX TD2FanLevel5 - Bank 2 Address 4DHEX TD2FanLevel6 - Bank 2 Address 4EHEX TD3FanLevel0 - Bank 2 Address 58HEX TD3FanLevel1 - Bank 2 Address 59HEX TD3FanLevel2 - Bank 2 Address 5AHEX TD3FanLevel3 - Bank 2 Address 5BHEX TD3FanLevel4 - Bank 2 Address 5CHEX TD3FanLevel5 - Bank 2 Address 5DHEX TD3FanLevel6 - Bank 2 Address 5EHEX TD4FanLevel0 - Bank 2 Address 68HEX TD4FanLevel1 - Bank 2 Address 69HEX TD4FanLevel2 - Bank 2 Address 6AHEX TD4FanLevel3 - Bank 2 Address 6BHEX - 78 -
W83793G
TD4FanLevel4 - Bank 2 Address 6CHEX TD4FanLevel5 - Bank 2 Address 6DHEX TD4FanLevel6 - Bank 2 Address 6EHEX TR1FanLevel0 - Bank 2 Address 78HEX TR1FanLevel1 - Bank 2 Address 79HEX TR1FanLevel2 - Bank 2 Address 7AHEX TR1FanLevel3 - Bank 2 Address 7BHEX TR1FanLevel4 - Bank 2 Address 7CHEX TR1FanLevel5 - Bank 2 Address 7DHEX TR1FanLevel6 - Bank 2 Address 7EHEX TR2FanLevel0 - Bank 2 Address 88HEX TR2FanLevel1 - Bank 2 Address 89HEX TR2FanLevel2 - Bank 2 Address 8AHEX TR2FanLevel3 - Bank 2 Address 8BHEX TR2FanLevel4 - Bank 2 Address 8CHEX TR2FanLevel5 - Bank 2 Address 8DHEX TR2FanLevel6 - Bank 2 Address 8EHEX Type : Reset : Read / Write VSB5V(Pin 7) Rising, Init Reset(CR40.Bit7) is set, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set, SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
TD1FANLEVEL0 ~ TR2FANLEVEL0 BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0
TempFanLevel0 08HEX
DESCRIPTION
7-6 5-0
Reserved. TempFanLevel0. (Fan Output Level 0).
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W83793G
TD1FANLEVEL1 ~ TR2FANLEVEL1 BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0
TempFanLevel1 0CHEX
DESCRIPTION
7-6 5-0
Reserved. TempFanLevel1. (Fan Output Level 1).
TD1FANLEVEL2 ~ TR2FANLEVEL2
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
Reserved 0
TempFanLevel2 10HEX
DESCRIPTION
7-6 5-0
Reserved. TempFanLevel2. (Fan Output Level 2).
TD1FANLEVEL3 ~ TR2FANLEVEL3
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
Reserved 0
TempFanLevel3 18HEX
DESCRIPTION
7-6 5-0
Reserved. TempFanLevel3. (Fan Output Level 3).
TD1FANLEVEL4 ~ TR2FANLEVEL4
BIT
7
6
5
4
3
2
1
0
Name Reset
Reserved 0
TempFanLevel4 20HEX
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W83793G
BIT
DESCRIPTION
7-6 5-0
Reserved. TempFanLevel4. (Fan Output Level 4).
TD1FANLEVEL5 ~ TR2FANLEVEL5
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
Reserved 0
TempFanLevel5 30HEX
DESCRIPTION
7-6 5-0
Reserved. TempFanLevel5. (Fan Output Level 5).
TD1FANLEVEL6 ~ TR2FANLEVEL6
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
Reserved 0
TempFanLevel6 38HEX
DESCRIPTION
7-6 5-0
Reserved. TempFanLevel6. (Fan Output Level 6).
See also: TolTemp, FanCtrlMode, Smart Fan II mode.
8.12 PECI Control Registers
Intel® new generation CPUs such as Presler begin to support new single wire digital temperature monitor interface which is called Platform Environment Control Interface or PECI. W83793G supports the PECI* version 1.0 for these new generation CPUs. All PECI control registers are allocated in Bank 0. Pin 1, PCLK, is the timing base of PECI control circuit, if PECI function is desired, Pin 1 is required to feed a 48MHz clock.
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W83793G
8.12.1 PECI Register Map
MNEMONIC REGISTER NAME TYPE
AgtConfig Agt1Tcontrol | Agt4Tcontrol ReportStyle
Agent Configuration Register
RW
Tcontrol Register
RW
PECI Report Temperature Style Register
RW
PECIWarning Agt1RelTempH/L | Agt4RelTempH/L
PECI Warning Flag Register
RO
Agent Relative Temperature Registers
RO
Three control registers and 2 status registers are listed here. The detailed operation of PECI host can be referred to below figure.
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W83793G
Everytime W83793G PECI host detects user enable an agent by setting AgtEn, it start to Ping if the client really exist. If not true, it set PECIAbsent flag to inform host; otherwise it continue to issue GetTemp0 or GetTemp1 (when DM1Exist asserted). A three-level fault queue is made to ensure host can get correct temperature and return.
8.12.2 PECI Register Details
8.12.2.1 Agent Configuration Register (AgtConfig) This register commands PECI host to proceed related agents and domains, only agent or domain specified in this register will proceed PECI transactions. It is reset as 00HEX. Location : Type : Reset : AgtConfig - Bank 0 Address D0HEX Read Write VSB5V(Pin 7) Rising, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set.
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W83793G
AGTCONFIG BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Agt4EN 0
Agt3EN 0
Agt2EN 0
Agt1EN 0
Agt4D1 0
Agt3D1 0
Agt2D1 0
Agt1D1 0
DESCRIPTION
Agt4EN( Agent 4 Enable Bit). 7 0BIN: Agent 4 is disabled. 1BIN: Agent 4 enabled. Agt3EN( Agent 3 Enable Bit). 6 0BIN: Agent 3 is disabled. 1BIN: Agent 3 enabled. Agt2EN( Agent 2 Enable Bit). 5 0BIN: Agent 2 is disabled. 1BIN: Agent 2 enabled. Agt1EN( Agent 1 Enable Bit). 4 0BIN: Agent 1 is disabled. 1BIN: Agent 1 enabled. Agt4D1( Agent 4 Domain 1 Enable Bit). 3 0BIN: Agent 4 does not have domain 1. 1BIN: Agent 4 have domain 1. Agt3D1( Agent 3 Domain 1 Enable Bit). 2 0BIN: Agent 3 does not have domain 1. 1BIN: Agent 3 have domain 1. Agt2D1( Agent 2 Domain 1 Enable Bit). 1 0BIN: Agent 2 does not have domain 1. 1BIN: Agent 2 have domain 1. Agt1D1( Agent 1 Domain 1 Enable Bit). 0 0BIN: Agent 1 does not have domain 1. 1BIN: Agent 1 have domain 1. 8.12.2.2 Agent TControl Register (AgtTcontrol) Intel® CPU introduces a Tcontrol concept on temperature management. In Presler generation CPUs, Tcontrol can be read from CPU register by BIOS and refill to W83793G registers. Our default setup is 70℃, which is 10℃ higher than TempLevel67. In later generation CPUs, CPU might only response the Tcontrol value as an offset temperature to PROCHOT# assertion. It is reset as 46HEX.
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W83793G
Location : Agt1TControl - Bank 0 Address D1HEX Agt2TControl - Bank 0 Address D2HEX Agt3TControl - Bank 0 Address D3HEX Agt4TControl - Bank 0 Address D4HEX Type : Reset : Read / Write VSB5V(Pin 7) Rising, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set.
AGT1TCONTROL~AGT4TCONTROL BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Reserved 0 1 0
TControl Temperature 0
DESCRIPTION
0
1
1
0
7 6-0
Reserved. TControl( TControl Temperature Setting). TControl must always be a positive value, negative value will introduce abnormal temperature response.
8.12.2.3 PECI Report Temperature Style Register (ReportStyle) ReportStyle controls which value being loaded into Absolute Temp or Relative Temp. If RtHigh, PECI host will automatically compares the highest temperature domain and load it into Abs/Rel-Temp. If RtHigh = 0, RtDm will return Domain 0 temperature if set 0, return Domain 1 temperature if set 1. It is reset as 00HEX. Location : Type : Reset : ReportStyle - Bank 0 Address D5HEX Read / Write VSB5V(Pin 7) Rising, VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set.
REPORTSTYLE BIT 7 6 5 4 3 2 1 0
Name Reset 0
Reserved 0 0
RtHigh 0
RTD4 0
RTD3 0
RTD2 0
RTD1 0
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W83793G
BIT
DESCRIPTION
7-5 4
Reserved. RtHigh (Return High Temperature). 0BIN: Return domain by RTD selection (RTD1~RTD4). 1BIN: Return highest temperature in the same agent. RtD4 (Agent 4 Return Domain 1 Enable Bit). Only take effect when RtHigh deasserts.
3
0BIN: Agent 4 always return domain 0. 1BIN: Agent 4 always return domain 1. RtD3 (Agent 3 Return Domain 1 Enable Bit). Only take effect when RtHigh deasserts.
2
0BIN: Agent 3 always return domain 0. 1BIN: Agent 3 always return domain 1. RtD2 (Agent 2 Return Domain 1 Enable Bit). Only take effect when RtHigh deasserts.
1
0BIN: Agent 2 always return domain 0. 1BIN: Agent 2 always return domain 1. RtD1 (Agent 1 Return Domain 1 Enable Bit). Only take effect when RtHigh deasserts.
0
0BIN: Agent 1 always return domain 0. 1BIN: Agent 1 always return domain 1.
8.12.2.4 PECI Warning Flag Register (PECIWarning) Few warnings may be generated while PECI protocol applies. First, PECI host may not able to detect a PECI Client (or say, client does not reponse to host Ping() command), in this case PECI issue a flag called Absent to inform users it cannot detect the client. Another case is about the PECI Client return bad FCS in successive 3 time polling, host will issue an Alert flag. It is reset as 00HEX. Location: Type: Reset: PECIWarning - Bank 0 Address D6HEX Read Only VSB5V (Pin 7) Rising, VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set.
PECIWARNING BIT 7 6 5 4 3 2 1 0
Name Reset
Absent4 0
Absent3 0
Absent2 0
Absent1 0
Alert4 0
Alert3 0
Alert2 0
Alert1 0
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W83793G
BIT
DESCRIPTION
Absent4 (PECI Agent 4 Absent Bit). 7 0BIN: Agent 4 is detected. 1BIN: Agent 4 cannot be detected. Absent3 (PECI Agent 3 Absent Bit). 6 0BIN: Agent 3 is detected. 1BIN: Agent 3 cannot be detected. Absent2 (PECI Agent 2 Absent Bit). 5 0BIN: Agent 2 is detected. 1BIN: Agent 2 cannot be detected. Absent1 (PECI Agent 1 Absent Bit). 4 0BIN: Agent 1 is detected. 1BIN: Agent 1 cannot be detected. Alert4 (PECI Agent 4 Alert Bit). 3 0BIN: Agent 4 has good FCS. 1BIN: Agent 4 has bad FCS in last 3 transactions. Alert3 (PECI Agent 3 Alert Bit). 2 0BIN: Agent 3 has good FCS. 1BIN: Agent 3 has bad FCS in last 3 transactions. Alert2 (PECI Agent 2 Alert Bit). 1 0BIN: Agent 2 has good FCS. 1BIN: Agent 2 has bad FCS in last 3 transactions. Alert1 (PECI Agent 1 Alert Bit). 0 0BIN: Agent 1 has good FCS. 1BIN: Agent 1 has bad FCS in last 3 transactions. While PECI is activated, Alert flag will be asserted when corresponding agent return successive 3 time bad FCS. In this case, W83793G will think this agent has some problem in interface, and for safty reason W83793G will turn on the related Fan to full speed in SmartFan mode. The Fan and PECI agent relationship is defined in TempFanSelect registers. 8.12.2.5 Agent Relative Temperature Register (AgtRelTemp) These registers return the raw data retrieved from PECI interface. They may be the error code (range: 8000H~81FFH) or relative temperature to processor defined PROCHOT#. Error code will only update in AgtRelTemp, Absolute Temp will not be updated when error code received. If ReturnHigh mechanism is activated, normal temperature will always return first. In case both 2 domain returns error, return priority will be Overflow error > Underflow Error > Missing diode > General Error. Reset value is 8001HEX due to PECI is default turned off, in PECI, 8001HEX means diode missing. Publication Release Date: Dec. 11, 2006 Revision 1.0
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W83793G
Location: Agt1RelTempH - Bank 0 Address D8HEX Agt1RelTempL - Bank 0 Address D9HEX Agt2RelTempH - Bank 0 Address DAHEX Agt2RelTempL - Bank 0 Address DBHEX Agt3RelTempH - Bank 0 Address DCHEX Agt3RelTempL - Bank 0 Address DDHEX Agt4RelTempH - Bank 0 Address DEHEX Agt4RelTempL - Bank 0 Address DFHEX Type: Reset: Read Only VSB5V (Pin 7) Rising, VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set.
AGT1RELTEMPH/L~AGT4RELTEMPH/L BIT 7 6 5 4 3 2 1 0
Name Reset Name Reset
BIT
Sign 1 0 0 0 0 TEMP_2 0 0 Temperature[1:0]
Temperature[8:2] 0 TEMP_8 0 0 TEMP_16 0 0 TEMP_32 0 0 TEMP_64 1 TEMP_4 0
DESCRIPTION
15 14-6 5 4 3 2 1 0
Sign Bit. In PECI Protocol, this bit should always be 1 to represent a negative temperature. Temperature The integer part of relative temperature. TEMP_2. 0.5℃ unit. TEMP_4. 0.25℃ unit. TEMP_8. 0.125℃ unit. TEMP_16. 0.0625℃ unit. TEMP_32. 0.03125℃ unit. TEMP_64. 0.015625℃ unit.
In some occasion, the PECI interface will return the abnormal states of the PECI bus other than temperature, all these information will be recorded in AgtRelTemp, and in some cases W83793G will also do further processing for alert mechanism. The following describes these code and their effects to W83793G.
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W83793G
ERROR CODE
DESCRIPTION
W83793G HOST OPERATION
8000HEX 8001HEX 8002HEX
General Sensor Error Sensing Device Missing Operational, but temperature is lower than sensor operation range. Operational, but temperature is higher than sensor operation range. Reserved.
No further processing. Force writing back temperature with 0℃ in temperature readouts.(Bank 0 Index 1CHEX ~ 1FHEX) Force writing back temperature with 127℃ in temperature readouts.(Bank 0 Index 1CHEX ~ 1FHEX)
8003HEX 8004HEX
No further operation.
81FFHEX Besides error conditions or bad FCS, normal temperature will be wrote back to Temperature Readouts with the sum of AgtRelTemp and Tcontrol.
8.13 ASF Control Registers
ASF or Alert Standard Format provides remote system abilities to monitor, discover and manage the local platform. All ASF control registers are allocated in Bank 1*. *About the Bank Selection, please reference Bank Select register located at address 00Hex.
8.13.1 ASF Register Map
8.13.1.1 SMBus ARP UDID Control Registers
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W83793G
MNEMONIC
REGISTER NAME
TYPE
UDIDDevCap. UDIDVersion. UDIDVendorH. UDIDVendorL. UDIDDevH. UDIDDevL. UDIDIFH. UDIDIFL. UDIDSubVenH. UDIDSubVenL. UDIDSubDevH. UDIDSubDevL. UDIDSpeID1.
UDID Device Capability Register UDID Version Number Register
RO RO
UDID Vendor ID High/Low Byte Register
RO
UDID Device ID High/Low Byte Register UDID Interface High/Low Byte Register UDID Subsystem Vendor ID High/Low Byte Registers UDID Subsystem Device ID High/Low Byte Registers
RW RW RW RW
UDID Vendor Specific ID Byte 1~4 UDIDSpeID4. RNG1. Random Number Generator Byte 1~4 RNG4. ASFAddr. ASF Assigned Address Register
RW
RO
RO
Before activating ASF, user must go through the ARP (Address Resolution Protocol) to dynamically get a valid address to manipulate ASF commands. In ARP, a very important ID must be defined to distinguish different devices, called UDID (Unique Device Identifier). Registers in this section are used to setup the UDID content. For detailed operation of ARP and UDID, you can refer to SMBus Specification version 2.0 (http://www.smbus.org/specs/smbus20.pdf ) section 5.6 page 34. 8.13.1.2 ASF Sensor Entity Definition Registers In ASF Sensor, each sensor channel has 2 parameters to tell ASF host its related location information on the platform. They are entity Instance and entity ID. In case of user uses the temperature sensor in locations different with default specified, W83793G provides all channel parameter programmable to fit customers’ application.
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W83793G
MNEMONIC REGISTER NAME TYPE
VCA_ENTY. VCB_ENTY. Vtt_ENTY. VDD_ENTY. VSB_ENTY. VBAT_ENTY. VSEN1_ENTY.
VCoreA Entity ID Register VCoreB Entity ID Register Vtt Entity ID Register VDD Entity ID Register VSB Entity ID Register VBAT Entity ID Register
RW RW RW RW RW RW
VSEN1~12VSEN Entity ID Register 12VSEN_ENTY. FAN1_ENTY. FAN1~FAN12 Entity ID Register FAN12_ENTY. TD1_ENTY. TD1~TR2 Entity ID Register TR2_ENTY. CHS_ENTY. Chassis Entity Register
RW
RW RW RW
For details of entity ID, you can refer to Platform Event Trap Format Specification Version 1.0 Table 6 page 13.
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W83793G
MNEMONIC REGISTER NAME TYPE
ENTINS1. ENTINS2. ENTINS3. ENTINS4. ENTINS5. ENTINS6. ENTINS7. ENTINS8. ENTINS9. ENTINS10. ENTINS11. ENTINS12. ENTINS13. ENTINS14. ENTINS15.
VCoreA/VCoreB Entity Instance Register VDD/Vtt Entity Instance Register VBAT/VSB Entity Instance Register VIN1/VIN2 Entity Instance Register VIN3/VIN4 Entity Instance Register FAN1/FAN2 Entity Instance Register FAN3/FAN4 Entity Instance Register FAN5/FAN6 Entity Instance Register FAN7/FAN8 Entity Instance Register FAN9/FAN10 Entity Instance Register FAN11/FAN12 Entity Instance Register TD1/TD2 Entity Instance Register TD3/TD4 Entity Instance Register TR1/TR2 Entity Instance Register Chassis Entity Instance Register
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Entity Instance is a sequential number which help identifies this sensor’s location. Customer can set the sequence at any order they want.
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W83793G
A summary of the entity and entity instance is at following table.
SENSOR IN W83793G EVENT STATUS INDEX EVENT SENSOR TYPE EVENT NUMBER ENTITY ID (PROGRAMMABLE) ENTITY INSTANCE (PROGRAMMABLE)
VCOREA VCOREB Vtt TD1 TD2 TD3 TD4 TR1 TR2 5VDD VSB VBAT VSEN1 VSEN2 3VSEN 12VSEN FAN1 FAN2 FAN3 FAN4 FAN5 FAN6 FAN7 FAN8 FAN9 FAN10 FAN11 FAN12
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh
02h 02h 02h 01h 01h 01h 01h 01h 02h 02h 02h 02h (Voltage) 02h 02h 02h 04h (Fan) 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 05h(Physical Security)
01h 02h 03h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh
03h (Processor)
01h 02h 03h 01h 02h 03h 04h 05h 06h 01h 02h
01h (Temperature) 04h
07h (System Board)
03h 04h 05h 06h 07h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch
Case OPEN 1Ch / Intrusion
23h(System Chassis) 01h
Channels in light-green indicates them could be disabled by multi-function pin selection or control registers.
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W83793G
And according to each channel status, they are expressed in the following terms.
DESCRIPTION STATUS EVENT SENSOR TYPE EVENT TYPE EVENT OFFSET EVENT SEVERITY
TEMPERATURE SENSORS Upper-Critical Going High Upper-Critical Going Low 3h Upper-Non-critical Going Assert High Upper-Non-critical Going Low Lower-Non-critical Going 2h High Deasser Lower-Non-critical Going Low t VOLTAGE SENSORS Generic Over Voltage 3h Problem Normal Voltage 2h Generic Under Voltage 3h Problem FAN SENSORS Normal FAN Speed 2h Generic FAN Failure 3h CASEOPEN/ CASE INTRUSION Case Intruded Case Normal 3h 2h
09h 08h 01h Temperature 01h ThresholdBased 07h 06h 01h 00h 02h 07h 02h 07h 02h 00h 80h
10h Critical 08h Non-critical 01h Monitor
02h Voltage
07h GenericSeverity
10h 01h 10h 01h 10h 10h 01h
04h Fan 05h Physical Security
07h
6Fh Sensor Specific
8.13.1.3 ASF Remote Control Definition Registers ASF function in W83793G also supports the Remote Control. This function enables MIS to remotely power on, power down, or reset while he finds the client computer goes into abnormal.
MNEMONIC REGISTER NAME TYPE
PwrOnOption. PwrOnCmd. PwrOffCmd. RstCmd.
Power On Control Option Register Remote Control Power On Command Register Remote Control Power Down Command Register Remote Control Reset Command Register
RW RW RW RW
Remote Control function in W83793G enables MIS to use side-band of Network Interface Controller to send ASF commands with SMBus, its format looks like
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W83793G
1 S
7 Slave Address Control Device Address
1 Wr 0
1 A 0
8 Command Control Command
1 A 0
8 Write Data Control Value Data
1 A 0
8 PEC CRC Checksum
1 A 0
1 P
‘S’ represents “Start” Cycle of SMBus transaction, ‘Wr’ means “Write” Flag, ‘A’ means “Acknowledge” from W83793G, and ‘P’ indicates a “Stop” Cycle. All letter in shadow means it is a response from W83793G; otherwise it is a host transmitted signal. Last row above shows what is each data meaning, where Control Device Address is the address assigned in the ARP process, Control Command is specified in above registers, and Control Data option is not supported in W83793G, thus with any value in this field W83793G will perform the same action. In Alert Standard Format Specification v2.0, there are two sections describe this. They are Section 5.4 at page 76, and Section 3.2.4.1 at page 33.
8.13.2 ASF Register Details
8.13.2.1 UDID Device Capability Register (UDIDDevCap) SMBus Specification Working Group intends to use device capability to distinguish the arbitration priority of GeneralGetUDID() first. Thus the very first byte the UDID is device capability, because SMBus is a MSB first serial protocol and client sent low will win the arbitration. It is set as C1HEX. Location: Type: Reset: UDIDVersion - Bank 1 Address 20HEX Read Only No Reset.
UDIDDEVCAP BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Address Type 1 1 0 0
Reserved 0 0 0
PEC 1
DESCRIPTION
Address Type. 00BIN: Fixed address device. It’s the highest priority device. 7-6 01BIN: Dynamic and persistent address device. 10BIN: Dynamic and volatile address device. If power-down, the address needs to reassign at next power on. W83793G ASF address will lost while VSB5V not exist. 11BIN: Random number device.
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W83793G
Continued
BIT
DESCRIPTION
5-1 0
Reserved. PEC Suppot. 0: Not known support PEC(Packet Error Code) on this device. 1: PEC is supported on this device.
8.13.2.2 UDID Version Number Register (UDIDVersion) This field defines the version of UDID and Silicon for W83793G. It is 08HEX. Location: Type: Reset: UDIDVersion - Bank 1 Address 21HEX Read Only No Reset
UDIDVERSION BIT 7 6 5 4 3 2 1 0
Name Fixed
BIT
Reserved 0 0 0
UDID Version 0
DESCRIPTION
Silicon Version 1 0 0 0
7-6
Reserved. UDID Version. 000BIN: Reserved. 001BIN: UDID version 1. 010BIN-111BIN: Reserved for future use. Silicon Version. For W83793G silicon version identification use. 000BIN stands for Version A/B.
5-3
2-0
8.13.2.3 UDID Vendor ID High/Low Byte Register (UDIDVendorH/L) This field defines Winbond vendor ID. Default is 1050HEX. Location: Type: Reset: UDIDVendorH - Bank 1 Address 22HEX UDIDVendorL - Bank 1 Address 23HEX Read Only No Reset
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W83793G
UDIDVENDORH BIT 7 6 5 4 3 2 1 0
Name Fixed 0 0 0
Vendor ID High Byte 1
UDIDVENDORL
0
0
0
0
BIT
7
6
5
4
3
2
1
0
Name Fixed
BIT
Vendor ID Low Byte 0 1 0 1 0 0 0 0
DESCRIPTION
15-0
Winbond Vendor ID.
8.13.2.4 UDID Device ID High/Low Byte Register (UDIDDevH/L) This field defines Winbond device ID. Default is 0100HEX. Location: Type: UDIDDevH - Bank 1 Address 24HEX UDIDDevL - Bank 1 Address 25HEX Read Write Init Reset (CR40.Bit7) is set.
UDIDDEVH BIT 7 6 5 4 3 2 1 0
Reset: VSB5V (Pin 7) Rising,
Name Reset 0 0 0
Device ID High Byte 0 0 0 0 1
UDIDDEVL BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Device ID Low Byte 0 0 0 0 0 0 0 0
DESCRIPTION
15-0
Winbond Device ID.
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W83793G
8.13.2.5 UDID Interface High/Low Byte Register (UDIDIFH/L) This field defines SMBus version and supported protocol. It is reset to 0024HEX. Location: UDIDIFH - Bank 1 Address 26HEX UDIDIFL - Bank 1 Address 27HEX Type: Read Write Init Reset (CR40.Bit7) is set.
UDIDIFH BIT 7 6 5 4 3 2 1 0
Reset: VSB5V (Pin 7) Rising,
Name Reset 0 0 0
Reserved 0
UDIDIFL
0
0
0
0
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
Reserved 0
IPMI 0
ASF 1
OEM 0 0
SMBus Version 1 0 0
DESCRIPTION
15-7 6
Reserved. IPMI. This device supports additional interface access capability per IPMI specification. 0: not supported. 1: supported. ASF. This device supports additional interface access capability per ASF specification.
5
0: not supported. 1: supported. OEM. Device supports vendor specific access capability per Subsystem Vendor ID and Subsystem Device ID. 0: not supported. 1: supported. SMBus Version 0HEX: SMBus 1.0, not ARPable. 1HEX: SMBus 1.1, not ARPable. 4HEX: SMBus 2.0.
4
3-0
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W83793G
8.13.2.6 UDID Subsystem Vendor ID High/Low Byte Register (UDIDSubVenH/L) This field defines UDID supporting for Subsystems. If no subsystem is supported, it must specify 0000HEX. It is reset to 0000HEX. Location: UDIDSubVenH - Bank 1 Address 28HEX UDIDSubVenL - Bank 1 Address 29HEX Type: Read Write Init Reset (CR40.Bit7) is set.
UDIDSUBVENH BIT 7 6 5 4 3 2 1 0
Reset: VSB5V (Pin 7) Rising,
Name Reset 0 0
UDID Subsystem Vendor ID High Byte 0 0
UDIDSUBVENL
0
0
0
0
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
UDID Subsystem Vendor ID Low Byte 0 0 0 0 0 0 0 0
DESCRIPTION
15-0
UDID subsystem Vendor.
8.13.2.7 UDID Subsystem Device ID High/Low Byte Register (UDIDSubDevH/L) This field defines UDID supporting for Subsystems. If no subsystem is supported, it must specify 0000HEX. It is reset to 0000HEX. Location: UDIDSubDevH - Bank 1 Address 2AHEX UDIDSubDevL - Bank 1 Address 2BHEX Type: Read Write Init Reset (CR40.Bit7) is set.
UDIDSUBVENH BIT 7 6 5 4 3 2 1 0
Reset: VSB5V (Pin 7) Rising,
Name Reset 0 0
UDID Subsystem Device ID High Byte 0 0 0 0 0 0
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W83793G
UDIDSUBVENL BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
UDID Subsystem Device ID Low Byte 0 0 0 0 0 0 0 0
DESCRIPTION
15-0
UDID subsystem Device ID.
8.13.2.8 UDID Vendor-Specific ID Register (UDIDSpecID1/2/3/4) This field defines unique Vendor-Specific ID for each W83793G. With this field different W83793G will identified on the same SMBus interface, and it is loaded with random number while reset signal received. Location : UDIDSpecID1 - Bank 1 Address 2CHEX UDIDSpecID2 - Bank 1 Address 2DHEX UDIDSpecID3 - Bank 1 Address 2EHEX UDIDSpecID4 - Bank 1 Address 2FHEX Type: Read Write Init Reset (CR40.Bit7) is set, ARP ResetDevice Command.
UDIDSPECID1~UDIDSPECID4 BIT 7 6 5 4 3 2 1 0
Reset: VSB5V (Pin 7) Rising,
Name Reset
BIT
UDID Specific Vendor ID 0 0 0 0 0 0 0 0
DESCRIPTION
31-0
UDID Vendor-Specific ID.
8.13.2.9 Random Number Generator Register (RNG1/2/3/4) W83793G internally generates pseudo random number by using CRC generator and internal clock. Due to internal clock always having little different deviations, different IC and different power-on time will affect the result of random number. It is reset to FFFFHEX. Location: RNG4 - Bank 1 Address 30HEX RNG3 - Bank 1 Address 31HEX RNG2 - Bank 1 Address 32HEX RNG1 - Bank 1 Address 33HEX - 100 -
W83793G
Type: Read Only
Reset: None.
RNG1~RNG4 BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Random Number Code 0 0 0 0 0 0 0 0
DESCRIPTION
31-0
Random Number Code.
8.13.2.10 ASF Assigned Address Register (ASFAddr) After ARP host get related device UDID, it will start to assign each device for later usage. W83793G will record this assigned address and set it as default address for ASF transactions. It is reset to 00HEX. Location: ASFAddr - Bank 1 Address 4FHEX Type: Read Only Init Reset (CR40.Bit7) is set, Reset: VSB5V (Pin 7) Rising,
ASFADDR BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
ASF Address 0 0 0 0 0 0 0 0
DESCRIPTION
31-0
ASF Address. This register will be assigned while ARP AssignAddress command issued.
8.13.2.11 ASF Entity/Instance Registers (ENITIY/ENTINS) W83793G supports various channels which can be reported to host through ASF protocol. Each sensor channel is associated with an entity (or said location on motherboard) and entity instance. Table provides an overall look for these registers. Location: VCA_ENTY VCB_ENTY Vtt_ENTY VDD_ENTY - Bank 1 Address 50HEX - Bank 1 Address 51HEX - Bank 1 Address 52HEX - Bank 1 Address 53HEX Publication Release Date: Dec. 11, 2006 Revision 1.0
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W83793G
VSB_ENTY - Bank 1 Address 54HEX
VBAT_ENTY - Bank 1 Address 55HEX VSEN1_ENTY - Bank 1 Address 56HEX VSEN2_ENTY - Bank 1 Address 57HEX 3VSEN_ENTY - Bank 1 Address 58HEX 12VSEN_ENTY- Bank 1 Address 59HEX FAN1_ENTY FAN2_ENTY FAN3_ENTY FAN4_ENTY FAN5_ENTY FAN6_ENTY FAN7_ENTY FAN8_ENTY FAN9_ENTY - Bank 1 Address 5AHEX - Bank 1 Address 5BHEX - Bank 1 Address 5CHEX - Bank 1 Address 5DHEX - Bank 1 Address 5EHEX - Bank 1 Address 5FHEX - Bank 1 Address 60HEX - Bank 1 Address 61HEX - Bank 1 Address 62HEX
FAN10_ENTY - Bank 1 Address 63HEX FAN11_ENTY - Bank 1 Address 64HEX FAN12_ENTY - Bank 1 Address 65HEX TD1_ENTY TD2_ENTY TD3_ENTY TD4_ENTY TR1_ENTY TR2_ENTY CHS_ENTY ENTINS1 ENTINS2 ENTINS3 ENTINS4 ENTINS5 ENTINS6 ENTINS7 ENTINS8 ENTINS9 - Bank 1 Address 66HEX - Bank 1 Address 67HEX - Bank 1 Address 68HEX - Bank 1 Address 69HEX - Bank 1 Address 6AHEX - Bank 1 Address 6BHEX - Bank 1 Address 6CHEX - Bank 1 Address 70HEX - Bank 1 Address 71HEX - Bank 1 Address 72HEX - Bank 1 Address 73HEX - Bank 1 Address 74HEX - Bank 1 Address 75HEX - Bank 1 Address 76HEX - Bank 1 Address 77HEX - Bank 1 Address 78HEX
ENTINS10 - Bank 1 Address 79HEX ENTINS11 - Bank 1 Address 7AHEX - 102 -
W83793G
ENTINS12 - Bank 1 Address 7BHEX ENTINS13 - Bank 1 Address 7CHEX ENTINS14 - Bank 1 Address 7DHEX ENTINS15 - Bank 1 Address 7EHEX Type: Read / Write Reset: 5VSB (Pin 7) Rising.
VCA_ENTITY BIT 7 6 5 4 3 2 1 0
Name Reset
VCore A Entity ID. 03HEX
VCB_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
VCore B Entity ID. 03HEX
VTT_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
Vtt Entity ID. 03HEX
VDD_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
VDD Entity ID. 07HEX
VSB_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
VSB Entity ID. 07HEX
VBAT_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
VBAT Entity ID. 07HEX
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W83793G
VSEN1_ENTITY BIT 7 6 5 4 3 2 1 0
Name Reset
VSEN1 Entity ID. 07HEX
VSEN2_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
VSEN2 Entity ID. 07HEX
3VSEN_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
3VSEN Entity ID. 07HEX
12VSEN_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
12VSEN Entity ID. 07HEX
FAN1_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN1 Entity ID. 07HEX
FAN2_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN2 Entity ID. 07HEX
FAN3_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN3 Entity ID. 07HEX
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W83793G
FAN4_ENTITY BIT 7 6 5 4 3 2 1 0
Name Reset
FAN4 Entity ID. 07HEX
FAN5_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN5 Entity ID. 07HEX
FAN6_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN6 Entity ID. 07HEX
FAN7_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN7 Entity ID. 07HEX
FAN8_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN8 Entity ID. 07HEX
FAN9_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN9 Entity ID. 07HEX
FAN10_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN10 Entity ID. 07HEX
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W83793G
FAN11_ENTITY BIT 7 6 5 4 3 2 1 0
Name Reset
FAN11 Entity ID. 07HEX
FAN12_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN12 Entity ID. 07HEX
TD1_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
TD1 Entity ID. 07HEX
TD2_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
TD2 Entity ID. 07HEX
TD3_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
TD3 Entity ID. 07HEX
TD4_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
TD4 Entity ID. 07HEX
TR1_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
TR1 Entity ID. 07HEX
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W83793G
TR2_ENTITY BIT 7 6 5 4 3 2 1 0
Name Reset
TR2 Entity ID. 07HEX
CHS_ENTITY
BIT
7
6
5
4
3
2
1
0
Name Reset
Chassis Entity ID. 23HEX
ENTINS1
BIT
7
6
5
4
3
2
1
0
Name Reset
VCoreB Entity Instance 02HEX
ENTINS2
VCoreA Entity Instance 01HEX
BIT
7
6
5
4
3
2
1
0
Name Reset
VDD Entity Instance 01HEX
ENTINS3
Vtt Entity Instance 03HEX
BIT
7
6
5
4
3
2
1
0
Name Reset
VBAT Entity Instance 03HEX
ENTINS4
VSB Entity Instance 02HEX
BIT
7
6
5
4
3
2
1
0
Name Reset
VSEN2 Entity Instance 05HEX
ENTINS5
VSEN1 Entity Instance 04HEX
BIT
7
6
5
4
3
2
1
0
Name Reset
12VSEN Entity Instance 07HEX
3VSEN Entity Instance 06HEX
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W83793G
ENTINS6 BIT 7 6 5 4 3 2 1 0
Name Reset
FAN2 Entity Instance 02HEX
ENTINS7
FAN1 Entity Instance 01HEX
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN4 Entity Instance 04HEX
ENTINS8
FAN3 Entity Instance 03HEX
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN6 Entity Instance 06HEX
ENTINS9
FAN5 Entity Instance 05HEX
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN8 Entity Instance 08HEX
ENTINS10
FAN7 Entity Instance 07HEX
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN10 Entity Instance 0AHEX
ENTINS11
FAN9 Entity Instance 09HEX
BIT
7
6
5
4
3
2
1
0
Name Reset
FAN12 Entity Instance 0CHEX
ENTINS12
FAN11 Entity Instance 0BHEX
BIT
7
6
5
4
3
2
1
0
Name Reset
TD2 Entity Instance 02HEX
TD1 Entity Instance 01HEX
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W83793G
ENTINS13 BIT 7 6 5 4 3 2 1 0
Name Reset
TD4 Entity Instance 04HEX
ENTINS14
TD3 Entity Instance 03HEX
BIT
7
6
5
4
3
2
1
0
Name Reset
TR2 Entity Instance 06HEX
ENTINS15
TR1 Entity Instance 05HEX
BIT
7
6
5
4
3
2
1
0
Name Reset
BIT
Reserved 00HEX
DESCRIPTION
Chassis Entity Instance 01HEX
ENTITY. Entity of each sensor channel. 03HEX: Processor 7-0 07HEX: System Board. 23HEX: Chassis Back Panel Board. For other entity types, please refer to PET Spec. page 13. 8.13.2.12 Power On Control Option Register (PwrOnOption) W83793G supports 2 kinds of power on. One is power on only one time, no matter VDD5V rised or not. The other is W83793G always issues power on cycles until it detects VDD is already power on. Location: PwrOnOption - Bank 1 Address 7FHEX Type: Reset: Read Write VSB5V (Pin 7) Rising.
PWRONOPTION BIT 7 6 5 4 3 2 1 0
Name Reset 0 0 0
Winbond Test Modes 0 0 0 0
PWR1T 0
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W83793G
BIT
DESCRIPTION
7-1
Winbond Test Mode. Test modes for production. Winbond strongly suggest customer do not use these registers in case of causing system malfunction. PWR1T (Power on One Time). 0: always issue power on cycles (PWRBTN_N assert 0.1sec every 1sec) until VDD power on. 1: Only issue 1 time power on cycle.
0
8.13.2.13 Power On Command Register (PwrOnCmd) ASF Remote Control Command supports Remote Power On features, here defines the Power on commands accepted by W83793G. Location: PwrOnCmd - Bank 1 Address 80HEX Type: Read Write Reset: VSB5V (Pin 7) Rising.
PWRONCMD BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Remote Power On Command 11HEX
DESCRIPTION
7-0
Remote Power On Command.
8.13.2.14 Power Down Command Register (PwrOffCmd) ASF Remote Control Command supports Remote Power Down features, here defines the Power off commands accepted by W83793G. Location: PwrOffCmd - Bank 1 Address 81HEX Type: Reset: Read Write VSB5V (Pin 7) Rising.
PWROFFCMD BIT 7 6 5 4 3 2 1 0
Name Reset
Remote Power Off Command 12HEX
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W83793G
BIT
DESCRIPTION
7-0
Remote Power Off Command.
8.13.2.15 Reset Command Register (Rst Cmd) ASF Remote Control Command supports Remote Reset features, here defines the Reset commands accepted by W83793G. Location: RstCmd - Bank 1 Address 82HEX Type: Read Write Reset: VSB5V (Pin 7) Rising.
RSTCMD BIT 7 6 5 4 3 2 1 0
Name Reset
BIT
Remote Reset Command 10HEX
DESCRIPTION
7-0
Remote Reset Command.
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W83793G
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage Input Voltage Operating Temperature Storage Temperature
-0.5 to 7.0 -0.5 to VDD+0.5 0 to +70 -55 to +150
V V °C °C
9.2
DC Characteristics
5VSB =5V ± 5%, VSS = 0V)
TYP. MAX. UNIT CONDITIONS PARAMETER SYM. MIN.
(Ta = 0° C to 70° C, 5VDD = 5V ± 10%,
OUT/OD12 – Output buffer or Open-drain output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA, OB mode 5VDD = 5 V 5VDD = 5 V 5VDD = 5 V IOL = 12 mA VIN = VDD VIN = 0V 5VDD = 5 V 5VDD = 5 V 5VDD = 5 V IOL = 12 mA VIN = VDD VIN = 0V IOL = 12 mA IOH = -12 mA
IN/ODB12v1sB - bi-directional pin with sink capability of 12 mA and schmitt-trigger level input Input Low Voltage Input High Voltage Hysteresis Output Low Voltage Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Hysteresis Output Low Voltage Input High Leakage Input Low Leakage Output Low Voltage Output High Voltage VIL VIH VTH VOL ILIH ILIL VIL VIH VTH VOL ILIH ILIL VOL VOH 2.4 2.0 1.2 0.4 +10 -10 0.4 0.6 0.2 0.4 +10 -10 0.8 0.4 V V V V µA µA V V V V µA µA V V
IN/ODB12tsB - TTL level bi-directional pin with sink capability of 12 mA and schmitt-trigger level input
OUTB12B - TTL level output pin with source-sink capability of 12 mA
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W83793G
DC Characteristics, continued.
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
ODB12B - Open-drain output pin with sink capability of 12 mA Output Low Voltage AOUT – Analog output N.A. INBV1SB - VID input pin for INTELTM VRM10.0, and VRM11 design Input Low Voltage Input High Voltage INtV2SB - VID input pin for AMDTM VRM design Input Low Voltage Input High Voltage for INTELTM PECI Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Hysterisis INBtsB Input Low Voltage Input High Voltage Hysteresis Input High Leakage Input Low Leakage VIL VIH VOL VOH VHys VIL VIH VTH ILIH ILIL 2.0 1.2 +10 -10 0.75Vtt 0.1Vtt 0.8 0.275Vtt 0.55Vtt 0.5Vtt 0.725Vtt 0.25Vtt V V V V V V V V µA µA 5VDD = 5 V 5VDD = 5 V 5VDD = 5 V VIN = VDD VIN = 0 V VIL VIH 1.4 0.8 V V VIL VIH 0.6 0.4 V V VOL 0.4 V IOL = 12 mA
IN/OBV3B – Bi-direction pin with source capability of 6 mA and sink capability of 1 mA
TTL level Schmitt-triggered input pin
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W83793G
9.3
9.3.1
AC Characteristics
Access Interface
t SCL t t R R
SCL
t HD;SDA
t SU;DAT t SU;STO
SDA IN
VALID DATA
t HD;DAT
SDA OUT Serial Bus Timing Diagram
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time SCL and SDA rise time SCL and SDA fall time
t SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tR tF
-
10 4.7 4.7 150 270 1.0 300
uS uS uS nS nS uS nS
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W83793G
9.3.2 Dynamic Vcore Limit Setting
If dynamic VID function enable, Vcore channel high/low limit will change in accordance with VID table. When VIDIN value change, internal VIDCHG signal will set until VIDIN value has stabled more than 1ms. New Vcore high/low limit will set at falling edge of VIDCHG and Vcore channel will enable monitor at the same time.
VIDIN
VIDCHG
Vcore High/Low limit
Vcore Disable Monitor ~1ms
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
9.3.3 Power On Reset The power-on reset threshold is 4.3V (typical). When Vcc crosses this threshold, the internal reset signal will be asserted for 3uS. During this time period, W83793G is in the reset state. When the internal reset signal is de-asserted, W83793G is in the operating state.
In the operating state, if Vcc drops below 4.0V and then rises above 4.3V, the internal reset signal will be asserted immediately. Fig 1 illustrates the reset mechanism.
5V VSB 4.3V 4.0V
0V
5.0V 4.3V Internal Reset Signal
Figure 1.
3us
3us
10.
ORDER INFORMATION
PART NO. PACKAGE REMARKS
W83793G
SSOP56
Pb-free Package
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W83793G
11. APPENDIX
11.1 Register Summary
BANK 0 INDEX REGISTER NAME INDEX REGISTER NAME
BANK 0 ADDRESS 00-1F
00HEX 01HEX 02HEX 03HEX 04HEX 05HEX 06HEX 07HEX 08HEX 09HEX 0AHEX 0BHEX 0CHEX 0DHEX 0EHEX 0FHEX 20HEX 21HEX 22HEX 23HEX 24HEX 25HEX 26HEX 27HEX 2AHEX 2BHEX 2CHEX
Bank Selection Watch Dog Lock Watch Dog Enable Watch Dog Status Watch Dog Timer VIDA Input Value VIDB Input Value VIDA Latch VIDB Latch VCore High Tolerance VCore Low Tolerance I C Address Sensor 1/2 Address Winbond Vendor ID Winbond Chip ID Winbond Device ID TR1 Readout TR2 Readout Temp Low Bit Readout Fan1 Count High Byte Fan1 Count Low Byte Fan2 Count High Byte Fan2 Count Low Byte Fan3 Count High Byte Fan4 Count Low Byte Fan5 Count High Byte Fan5 Count Low Byte
2
10HEX 11HEX 12HEX 13HEX 14HEX 15HEX 16HEX 17HEX 18HEX 19HEX 1AHEX 1BHEX 1CHEX 1DHEX 1EHEX 1FHEX
BANK 0 ADDRESS 20-3F
VCore A Readout VCore B Readout Vtt Readout VSEN1 Readout VSEN2 Readout 3VSEN Readout 12VSEN Readout 5VDD Readout 5VSB Readout VBAT Readout VIN Low Bit TD1 Readout TD2 Readout TD3 Readout TD4 Readout Fan7 Count Low Byte Fan8 Count High Byte Fan8 Count Low Byte Fan9 Count High Byte Fan9 Count Low Byte Fan10 Count High Byte Fan10 Count Low Byte Fan11 Count High Byte Fan12 Count Low Byte
30HEX 31HEX 32HEX 33HEX 34HEX 35HEX 36HEX 37HEX 3AHEX 3BHEX 3CHEX
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W83793G
Register Summary, continued.
INDEX
REGISTER NAME
INDEX
REGISTER NAME
2DHEX 2EHEX 2FHEX 40HEX 41HEX 42HEX 43HEX 44HEX 45HEX 46HEX 47HEX 48HEX 49HEX 4AHEX 4BHEX 4CHEX 4DHEX 4EHEX 4FHEX 60HEX 61HEX 62HEX 63HEX 64HEX 65HEX 66HEX 67HEX 68HEX 69HEX 6AHEX
Fan6 Count High Byte Fan6 Count Low Byte Fan7 Count High Byte Configuration Interrupt Status 1 Interrupt Status 2 Interrupt Status 3 Interrupt Status 4 Interrupt Status 5 Interrupt Mask 1 Interrupt Mask 2 Interrupt Mask 3 Interrupt Mask 4 Interrupt Mask 5 Real Time Status 1 Real Time Status 2 Real Time Status 3 Real Time Status 4 Real Time Status 5 VCoreA High Limit VCoreA Low Limit VCoreB High Limit VCoreB Low Limit Vtt High Limit Vtt Low Limit
3DHEX 3EHEX 3FHEX
BANK 0 ADDRESS 40-5F
50HEX 51HEX 52HEX 53HEX 54HEX 55HEX 56HEX 57HEX 58HEX 59HEX 5AHEX 5BHEX 5CHEX 5DHEX 5EHEX 5FHEX
BANK 0 ADDRESS 60-7F
SMI/IRQ Control OVT Control OVT/Beep Global Enable Beep Control 1 Beep Control 2 Beep Control 3 Beep Control 4 Beep Control 5 Multi-Function Pin Control VID Control TD1 Configuration TD2 Configuration FanIn Control FanIn Redirection TD Mode Select TR Mode Select 12VSEN High Limit 12VSEN Low Limit 5VDD High Limit 5VDD Low Limit 5VSB High Limit 5VSB Low Limit VBAT High Limit VBAT Low Limit TD1 Critical TD1 Critical Hysterisis TD1 Warning
70HEX 71HEX 72HEX 73HEX 74HEX 75HEX 76HEX 77HEX
High Limit Low Bit Low Limit Low Bit VSEN1 High Limit
78HEX 79HEX 7AHEX
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W83793G
Register Summary, continued.
INDEX
REGISTER NAME
INDEX
REGISTER NAME
6BHEX 6CHEX 6DHEX 6EHEX 6FHEX 80HEX 81HEX 82HEX 83HEX 84HEX 85HEX 86HEX 87HEX 88HEX 89HEX 8AHEX 8BHEX 8CHEX 8DHEX 8EHEX 8FHEX A0HEX A1HEX A2HEX A3HEX A4HEX A5HEX A6HEX A7HEX A8HEX
VSEN1 Low Limit VSEN2 High Limit VSEN2 Low Limit 3VSEN High Limit 3VSEN Low Limit TD3 Critical TD3 Critical Hysterisis TD3 Warning TD3 Warning Hysterisis TD4 Critical TD4 Critical Hysterisis TD4 Warning TD4 Warning Hysterisis TR1 Critical TR1 Critical Hysterisis TR1 Warning TR1 Warning Hysterisis TR2 Critical TR2 Critical Hysterisis TR2 Warning TR2 Warning Hysterisis Fan9 Limit High Byte Fan9 Limit Low Byte Fan10 Limit High Byte Fan10 Limit Low Byte Fan11 Limit High Byte Fan11 Limit Low Byte Fan12 Limit High Byte Fan12 Limit Low Byte TD1 Temperature Offset
7BHEX 7CHEX 7DHEX 7EHEX 7FHEX
BANK 0 ADDRESS 80-9F
TD1 Warning Hysterisis TD2 Critical TD2 Critical Hysterisis TD2 Warning TD2 Warning Hysterisis Fan1 Limit High Byte Fan1 Limit Low Byte Fan2 Limit High Byte Fan2 Limit Low Byte Fan3 Limit High Byte Fan3 Limit Low Byte Fan4 Limit High Byte Fan4 Limit Low Byte Fan5 Limit High Byte Fan5 Limit Low Byte Fan6 Limit High Byte Fan6 Limit Low Byte Fan7 Limit High Byte Fan7 Limit Low Byte Fan8 Limit High Byte Fan8 Limit Low Byte Fan Output Style 1 Fan Output Style 2 Fan Default Speed Fan1 Duty Fan2 Duty Fan3 Duty Fan4 Duty Fan5 Duty Fan6 Duty Publication Release Date: Dec. 11, 2006 Revision 1.0
90HEX 91HEX 92HEX 93HEX 94HEX 95HEX 96HEX 97HEX 98HEX 99HEX 9AHEX 9BHEX 9CHEX 9DHEX 9EHEX 9FHEX B0HEX B1HEX B2HEX B3HEX B4HEX B5HEX B6HEX B7HEX B8HEX
BANK 0 ADDRESS A0-BF
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W83793G
Register Summary, continued.
INDEX
REGISTER NAME
INDEX
REGISTER NAME
A9HEX AAHEX ABHEX ACHEX ADHEX AEHEX AFHEX C0HEX C1HEX C2HEX C3HEX C4HEX C5HEX D0HEX D1HEX D2HEX D3HEX D4HEX
TD2 Temperature Offset TD3 Temperature Offset TD4 Temperature Offset TR1 Temperature Offset TR2 Temperature Offset
B9HEX BAHEX BBHEX BCHEX BDHEX BEHEX BFHEX
Fan7 Duty Fan8 Duty Fan1 Output Prescalar Fan2 Output Prescalar Fan3 Output Prescalar Fan4 Output Prescalar Fan5 Output Prescalar PECI Return Domain PECI Warning Flags PECI Agent1 RelTempH PECI Agent1 RelTempL PECI Agent2 RelTempH PECI Agent2 RelTempL PECI Agent3 RelTempH PECI Agent3 RelTempL PECI Agent4 RelTempH PECI Agent4 RelTempL
BANK 0 ADDRESS C0-DF
Fan6 Output Prescalar Fan7 Output Prescalar Fan8 Output Prescalar Step Up Time Step Down Time Critical Temperature PECI Agent Configure PECI Agent1 Tcontrol PECI Agent2 Tcontrol PECI Agent3 Tcontrol PECI Agent4 Tcontrol
D5HEX D6HEX D7HEX D8HEX D9HEX DAHEX DBHEX DCHEX DDHEX DEHEX DFHEX
BANK 1
INDEX
REGISTER NAME
INDEX
REGISTER NAME
BANK 1 ADDRESS 00-1F
00HEX 0DHEX 20HEX 21HEX 22HEX 23HEX 24HEX 25HEX
Bank Select Winbond Vendor ID UDID Device Capability UDID Version Number UDID Vendor ID High UDID Vendor ID Low UDID Device ID High UDID Device ID Low
0EHEX 0FHEX
BANK 1 ADDRESS 20-33
Winbond Chip ID Winbond Device ID UDID SubDevice ID High UDID SubDevice ID Low UDID Specific Vendor ID1 UDID Specific Vendor ID2 UDID Specific Vendor ID3 UDID Specific Vendor ID4
2AHEX 2BHEX 2CHEX 2DHEX 2EHEX 2FHEX
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W83793G
Bank 1, continued.
INDEX
REGISTER NAME
INDEX
REGISTER NAME
26HEX 27HEX 28HEX 29HEX 40HEX 50HEX 51HEX 52HEX 53HEX 54HEX 55HEX 56HEX 57HEX 58HEX 59HEX 5AHEX 5BHEX 5CHEX 5DHEX 5EHEX 5FHEX 70HEX 71HEX 72HEX 73HEX 74HEX 75HEX 76HEX 77HEX
UDID Interface High Byte UDID Interface Low Byte UDID SubVendor ID High UDID SubVendor ID Low ARP Assigned Address
30HEX 31HEX 32HEX 33HEX
BANK 1 ADDRESS 40
Random Number 1 Random Number 2 Random Number 3 Random Number 4
BANK 1 ADDRESS 50-6F
VCoreA Entity ID VCoreB Entity ID Vtt Entity ID VDD Entity ID VSB5V Entity ID VBAT Entity ID VSEN1 Entity ID VSEN2 Entity ID 3VSEN Entity ID 12VSEN Entity ID Fan1 Entity ID Fan2 Entity ID Fan3 Entity ID Fan4 Entity ID Fan5 Entity ID Fan6 Entity ID VCoreA/VCoreB EntityID VDD/Vtt EntityID VBAT/VSB EntityID VCoreA/VCoreB EntityID VSEN1/VSEN2 EntityID 12VSEN/3VSEN EntityID Fan1/2 EntityID Fan3/4 EntityID
60HEX 61HEX 62HEX 63HEX 64HEX 65HEX 66HEX 67HEX 68HEX 69HEX 6AHEX 6BHEX 6CHEX 6DHEX 6EHEX 6FHEX
BANK 1 ADDRESS 70-8F
Fan7 Entity ID Fan8 Entity ID Fan9 Entity ID Fan10 Entity ID Fan11 Entity ID Fan12 Entity ID TD1 Entity ID TD2 Entity ID TD3 Entity ID TD4 Entity ID TR1 Entity ID TR2 Entity ID Chassis Entity ID
80HEX 81HEX 82HEX 83HEX 84HEX 85HEX 86HEX 87HEX
Remote PowerOn Command Remote Power Off Command Remote Reset Command
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
Bank 1, continued.
INDEX
REGISTER NAME
INDEX
REGISTER NAME
78HEX 79HEX 7AHEX 7BHEX 7CHEX 7DHEX 7EHEX 7FHEX
Fan5/6 EntityID Fan7/8 EntityID Fan9/10 EntityID Fan11/12 EntityID TD1/2 EntityID TD3/4 EntityID Chassis EntityID Power On Option
88HEX 89HEX 8AHEX 8BHEX 8CHEX 8DHEX 8EHEX 8FHEX
BANK 2
INDEX
REGISTER NAME
INDEX
REGISTER NAME
BANK 2 ADDRESS 00-1F
00HEX 01HEX 02HEX 03HEX 04HEX 05HEX 06HEX 07HEX 08HEX 09HEX 0AHEX 0BHEX 0CHEX 0DHEX 0EHEX 0FHEX 20HEX 21HEX 22HEX 23HEX
Bank Select TD1 Fan Mapping Select TD2 Fan Mapping Select TD3 Fan Mapping Select TD4 Fan Mapping Select TR1 Fan Mapping Select TR2 Fan Mapping Select Fan Control Mode Select TD1/2 Temp Tolerance TD3/4 Temp Tolerance TR1/2 Temp Tolerance
10HEX 11HEX 12HEX 13HEX 14HEX 15HEX 16HEX 17HEX 18HEX 19HEX 1AHEX 1BHEX 1CHEX
TD1 Target Temperature TD2 Target Temperature TD3 Target Temperature TD4 Target Temperature TR1 Target Temperature TR2 Target Temperature
Fan1 Nonstop Duty Cycle Fan2 Nonstop Duty Cycle Fan3 Nonstop Duty Cycle Fan4 Nonstop Duty Cycle Fan5 Nonstop Duty Cycle Fan6 Nonstop Duty Cycle Fan7 Nonstop Duty Cycle Fan8 Nonstop Duty Cycle TD1 Temp Level01 TD1 Temp Level12 TD1 Temp Level23 TD1 Temp Level34
Winbond Vendor ID Winbond Chip ID Winbond Device ID Fan1 Start Duty Cycle Fan2 Start Duty Cycle Fan3 Start Duty Cycle Fan4 Start Duty Cycle
1DHEX 1EHEX 1FHEX
BANK 2 ADDRESS 20-3F
30HEX 31HEX 32HEX 33HEX - 122 -
W83793G
Bank 2, continued.
INDEX
REGISTER NAME
INDEX
REGISTER NAME
24HEX 25HEX 26HEX 27HEX 28HEX 29HEX 2AHEX 2BHEX 2CHEX 2DHEX 2EHEX 2FHEX 40HEX 41HEX 42HEX 43HEX 44HEX 45HEX 46HEX 47HEX 48HEX 49HEX 4AHEX 4BHEX 4CHEX 4DHEX 4EHEX 4FHEX 60HEX 61HEX
Fan5 Start Duty Cycle Fan6 Start Duty Cycle Fan7 Start Duty Cycle Fan8 Start Duty Cycle Fan1 Stop Time Fan2 Stop Time Fan3 Stop Time Fan4 Stop Time Fan5 Stop Time Fan6 Stop Time Fan7 Stop Time Fan8 Stop Time TD2 Temp Level01 TD2 Temp Level12 TD2 Temp Level23 TD2 Temp Level34 TD2 Temp Level45 TD2 Temp Level56 TD2 Temp Level67 TD2 Fan Level0 TD2 Fan Level1 TD2 Fan Level2 TD2 Fan Level3 TD2 Fan Level4 TD2 Fan Level5 TD2 Fan Level6
34HEX 35HEX 36HEX 37HEX 38HEX 39HEX 3AHEX 3BHEX 3CHEX 3DHEX 3EHEX 3FHEX
BANK 2 ADDRESS 40-5F
TD1 Temp Level45 TD1 Temp Level56 TD1 Temp Level67 TD1 Fan Level0 TD1 Fan Level1 TD1 Fan Level2 TD1 Fan Level3 TD1 Fan Level4 TD1 Fan Level5 TD1 Fan Level6
50HEX 51HEX 52HEX 53HEX 54HEX 55HEX 56HEX 57HEX 58HEX 59HEX 5AHEX 5BHEX 5CHEX 5DHEX 5EHEX 5FHEX
BANK 2 ADDRESS 60-7F
TD3 Temp Level01 TD3 Temp Level12 TD3 Temp Level23 TD3 Temp Level34 TD3 Temp Level45 TD3 Temp Level56 TD3 Temp Level67 TD3 Fan Level0 TD3 Fan Level1 TD3 Fan Level2 TD3 Fan Level3 TD3 Fan Level4 TD3 Fan Level5 TD3 Fan Level6
TD4 Temp Level01 TD4 Temp Level12
70HEX 71HEX
TR1 Temp Level01 TR1 Temp Level12 Publication Release Date: Dec. 11, 2006 Revision 1.0
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W83793G
Bank 1, continued.
INDEX
REGISTER NAME
INDEX
REGISTER NAME
62HEX 63HEX 64HEX 65HEX 66HEX 67HEX 68HEX 69HEX 6AHEX 6BHEX 6CHEX 6DHEX 6EHEX 6FHEX 80HEX 81HEX 82HEX 83HEX 84HEX 85HEX 86HEX 87HEX
TD4 Temp Level23 TD4 Temp Level34 TD4 Temp Level45 TD4 Temp Level56 TD4 Temp Level67 TD4 Fan Level0 TD4 Fan Level1 TD4 Fan Level2 TD4 Fan Level3 TD4 Fan Level4 TD4 Fan Level5 TD4 Fan Level6
72HEX 73HEX 74HEX 75HEX 76HEX 77HEX 78HEX 79HEX 7AHEX 7BHEX 7CHEX 7DHEX 7EHEX 7FHEX
BANK 2 ADDRESS 80-8F
TR1 Temp Level23 TR1 Temp Level34 TR1 Temp Level45 TR1 Temp Level56 TR1 Temp Level67 TR1 Fan Level0 TR1 Fan Level1 TR1 Fan Level2 TR1 Fan Level3 TR1 Fan Level4 TR1 Fan Level5 TR1 Fan Level6
TR2 Temp Level01 TR2 Temp Level12 TR2 Temp Level23 TR2 Temp Level34 TR2 Temp Level45 TR2 Temp Level56 TR2 Temp Level67
88HEX 89HEX 8AHEX 8BHEX 8CHEX 8DHEX 8EHEX 8FHEX
TR2 Fan Level0 TR2 Fan Level1 TR2 Fan Level2 TR2 Fan Level3 TR2 Fan Level4 TR2 Fan Level5 TR2 Fan Level6
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W83793G
12. THE TOP MARKING
W83793R 28201234 606GCUB
Left First Line Second Line Third Line
Winbond Logo. IC part number: W83793R; R means SSOP, leaded package. Serial number Tracking Code: 6 6 06 G C UB Week: 06 Assembly house ID; G means Greatek; A means ASE; O means OSE IC version Mask version 06 G B UB for Package information Package is made in 2006
W83793G 28201234 606GCUB
Left First Line Second Line Third Line
Winbond Logo. IC part number: W83793G; G means Pb-free package. Serial number Tracking Code: 6 6 06 G C UB Week: 06 Assembly house ID; G means Greatek; A means ASE; O means OSE IC version Mask version 06 G B UB for Package information Package is made in 2006
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Publication Release Date: Dec. 11, 2006 Revision 1.0
W83793G
13. PACKAGE DRAWING AND DIMENSIONS
(56-pin SSOP 300mil)
.035 .045
.045 .055 0.40/0.50 DIA
SYMBOL
DIMENSION IN MM
DIMENSION IN INCH
E
END VIEW
HE
A A1 A2 b c D HE E e L L1 Y θ
MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0.13 0.25 0.005 0.720 0.400 0.292 0.020 0.024 18.2 18.42 18.54 9 10.16 10.31 10.41 7.42 0.51 0.61 7.52 0.64 0.81 1.40 7.59 0.76 1.02 0.08 8
MAX. 0.110 0.016 0.092 0.0135 0.010
TOP VIEW
SEE DETAIL "A"
c
D
θ
A2
A
Y SEATING PLANE e b
SIDE VIEW A1 PARTING LINE
0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 8
c
0
0
θ
L L1
DETAIL"A"
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W83793G
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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Publication Release Date: Dec. 11, 2006 Revision 1.0
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