W83977ATG

W83977ATF W83977ATG WINBOND I/O W83977ATF/W83977ATG W83977ATF Data Sheet Revision History PAGES DATES VERSION VERSION ON WEB 1 2 3 4 5 6 7 8 9 10 n.a. 53,54,58,63,64,65 , 69,138.1,139 1,2,3,20,45,53,63, 65,99,103,150 112 192 n.a. 08/25/97 11/17/97 04/01/98 05/14/98 09/22/98 05/02/06 0.50 0.51 0.52 0.53 0.54 0.6 A1 A2 A3 First published. Register correction Typo correction and data calibrated spec. revision; configuration register programming method. Modify ordering information and top marking. Add lead-free package version MAIN CONTENTS -I- Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Table of Contents1. 2. 3. 4. GENERAL DESCRIPTION .............................................................................................................. 1 FEATURES...................................................................................................................................... 2 PIN CONFIGURATION.................................................................................................................... 5 PIN DESCRIPTION ......................................................................................................................... 6 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5. 5.1 Host Interface ........................................................................................................................ 6 General Purpose I/O Port...................................................................................................... 9 Serial Port Interface............................................................................................................. 10 Infrared Interface ................................................................................................................. 11 Multi-Mode Parallel Port ...................................................................................................... 11 FDC Interface ...................................................................................................................... 15 KBC Interface ...................................................................................................................... 17 POWER PINS...................................................................................................................... 17 ACPI Interface ..................................................................................................................... 17 W83977ATF/ATG FDC ....................................................................................................... 18 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 AT interface .......................................................................................................................... 18 FIFO (Data) .......................................................................................................................... 18 Data Separator ..................................................................................................................... 19 Write Precompensation ........................................................................................................ 19 Perpendicular Recording Mode ............................................................................................ 19 FDC Core ............................................................................................................................. 20 FDC Commands................................................................................................................... 20 Status Register A (SA Register) (Read base address + 0)................................................... 29 Status Register B (SB Register) (Read base address + 1)................................................... 31 Digital Output Register (DO Register) (Write base address + 2) .......................................... 33 Tape Drive Register (TD Register) (Read base address + 3)............................................... 33 Main Status Register (MS Register) (Read base address + 4)............................................. 34 Data Rate Register (DR Register) (Write base address + 4) ................................................ 34 FIFO Register (R/W base address + 5) ................................................................................ 36 Digital Input Register (DI Register) (Read base address + 7)............................................... 38 Configuration Control Register (CC Register) (Write base address + 7) .............................. 39 FDC FUNCTIONAL DESCRIPTION.............................................................................................. 18 5.2 Register Descriptions .......................................................................................................... 29 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 6. UART PORT .................................................................................................................................. 41 6.1 6.2 Universal Asynchronous Receiver/Transmitter (UART A, UART B)................................... 41 Register Address................................................................................................................. 41 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 UART Control Register (UCR) (Read/Write) ........................................................................ 41 UART Status Register (USR) (Read/Write) .......................................................................... 43 Handshake Control Register (HCR) (Read/Write) ................................................................ 44 Handshake Status Register (HSR) (Read/Write).................................................................. 45 UART FIFO Control Register (UFR) (Write only).................................................................. 46 - II - W83977ATF/W83977ATG 6.2.6 6.2.7 6.2.8 6.2.9 Interrupt Status Register (ISR) (Read only) .......................................................................... 47 Interrupt Control Register (ICR) (Read/Write) ...................................................................... 48 Programmable Baud Generator (BLL/BHL) (Read/Write)..................................................... 48 User-defined Register (UDR) (Read/Write) .......................................................................... 49 7. INFRARED (IR) PORT .................................................................................................................. 50 7.1 7.2 IR Register Description ....................................................................................................... 50 Set0-Legacy/Advanced IR Control and Status Registers ................................................... 51 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) ..................... 51 Set0.Reg1 - Interrupt Control Register (ICR)........................................................................ 52 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR) ........................ 53 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): ....................................... 57 Set0.Reg4 - Handshake Control Register (HCR) ................................................................. 57 Set0.Reg5 - IR Status Register (USR) ................................................................................. 59 Set0.Reg6 - Reserved .......................................................................................................... 60 Set0.Reg7 - User Defined Register (UDR/AUDR) ................................................................ 60 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ............................................................. 61 Set1.Reg 2~7 ....................................................................................................................... 61 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) ................................................ 62 Reg2 - Advanced IR Control Register 1 (ADCR1) ................................................................ 62 Reg3 - Sets Select Register (SSR)....................................................................................... 63 Reg4 - Advanced IR Control Register 2 (ADCR2) ................................................................ 64 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only) ...................................................... 65 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only).......................................................... 66 Reg0 - Advanced IR ID (AUID)............................................................................................. 66 Reg1 - Mapped IR Control Register (MP_UCR) ................................................................... 66 Reg2 - Mapped IR FIFO Control Register (MP_UFR) .......................................................... 67 Reg3 - Sets Select Register (SSR)....................................................................................... 67 Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH) ........................................................... 67 Set4.Reg2 - Infrared Mode Select (IR_MSL) ........................................................................ 67 Set4.Reg3 - Set Select Register (SSR) ................................................................................ 68 Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH) ................................................. 68 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH) .................................................... 69 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL) ............... 69 Set5.Reg2 - Flow Control Mode Operation (FC_MD) ........................................................... 69 Set5.Reg3 - Sets Select Register (SSR) .............................................................................. 70 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)........................................................... 70 Set5.Reg5 - Frame Status FIFO Register (FS_FO) ............................................................. 71 7.3 Set1 - Legacy Baud Rate Divisor Register.......................................................................... 61 7.3.1 7.3.2 7.4 Set2 - Interrupt Status or IR FIFO Control Register (ISR/UFR) .......................................... 62 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.5 Set3 - Version ID and Mapped Control Registers............................................................... 66 7.5.1 7.5.2 7.5.3 7.5.4 7.6 Set4 - TX/RX/Timer counter registers and IR control registers. ......................................... 67 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.7 Set 5 - Flow control and IR control and Frame Status FIFO registers................................ 69 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 - III - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 7.7.6 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number (LST_NU).......................................................................................................................................... 72 7.8 Set6 - IR Physical Layer Control Registers......................................................................... 72 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2)......................................................... 72 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width............................................................ 73 Set6.Reg2 - SIR Pulse Width ............................................................................................... 74 Set6.Reg3 - Set Select Register........................................................................................... 74 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU) ............................... 74 4.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC) ........................................ 75 Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC) ............................................. 77 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG)................................................... 78 Set7.Reg3 - Sets Select Register (SSR) .............................................................................. 79 Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1) ............................................. 80 Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2) ............................................. 80 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3) ............................................. 81 Set7.Reg7 - Infrared Module Control Register (IRM_CR) .................................................... 81 7.9 Set7 - Remote control and IR module selection registers................................................... 75 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.9.6 7.9.7 7.9.8 8. PARALLEL PORT.......................................................................................................................... 83 8.1 8.2 Printer Interface Logic ......................................................................................................... 83 Enhanced Parallel Port (EPP) ............................................................................................. 84 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 Data Swapper....................................................................................................................... 85 Printer Status Buffer ............................................................................................................. 85 Printer Control Latch and Printer Control Swapper............................................................... 86 EPP Address Port ................................................................................................................ 86 EPP Data Port 0-3 ................................................................................................................ 87 Bit Map of Parallel Port and EPP Registers.......................................................................... 87 EPP Pin Descriptions ........................................................................................................... 88 EPP Operation ..................................................................................................................... 88 ECP Register and Mode Definitions ..................................................................................... 89 Data and ecpAFifo Port ........................................................................................................ 90 Device Status Register (DSR) .............................................................................................. 90 Device Control Register (DCR)............................................................................................. 91 cFifo (Parallel Port Data FIFO) Mode = 010 ......................................................................... 91 ecpDFifo (ECP Data FIFO) Mode = 011............................................................................... 92 tFifo (Test FIFO Mode) Mode = 110 ..................................................................................... 92 cnfgA (Configuration Register A) Mode = 111 ...................................................................... 92 cnfgB (Configuration Register B) Mode = 111 ...................................................................... 92 ecr (Extended Control Register) Mode = all.......................................................................... 93 Bit Map of ECP Port Registers ............................................................................................. 94 ECP Pin Descriptions ........................................................................................................... 95 ECP Operation ..................................................................................................................... 96 FIFO Operation .................................................................................................................... 96 DMA Transfers ..................................................................................................................... 97 8.3 Extended Capabilities Parallel (ECP) Port .......................................................................... 89 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 8.3.15 - IV - W83977ATF/W83977ATG 8.3.16 Programmed I/O (NON-DMA) Mode..................................................................................... 97 8.4 8.5 9. 9.1 9.2 9.3 9.4 9.5 Extension FDD Mode (EXTFDD) ........................................................................................ 97 Extension 2FDD Mode (EXT2FDD) .................................................................................... 97 Output Buffer ....................................................................................................................... 98 Input Buffer .......................................................................................................................... 98 Status Register .................................................................................................................... 99 Commands .......................................................................................................................... 99 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC ................................... 101 9.5.1 9.5.2 KB Control Register (Logic Device 5, CR-F0)..................................................................... 101 Port 92 Control Register (Default Value = 0x24) ................................................................ 102 KEYBOARD CONTROLLER ......................................................................................................... 98 10. GENERAL PURPOSE I/O ........................................................................................................... 103 10.1 Basic I/O functions ............................................................................................................ 105 10.2 Alternate I/O Functions...................................................................................................... 107 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 Interrupt Steering................................................................................................................ 107 Watch Dog Timer Output.................................................................................................... 108 Power LED ......................................................................................................................... 108 General Purpose Address Decoder.................................................................................... 108 General Purpose Write Strobe ........................................................................................... 108 11. PLUG AND PLAY CONFIGURATION......................................................................................... 109 11.1 Compatible PnP................................................................................................................. 109 11.1.1 11.1.2 11.1.3 Extended Function Registers.............................................................................................. 109 Extended Functions Enable Registers (EFERs) ................................................................. 110 Extended Function Index Registers (EFIRs), Extended Function Data Registers (EFDRs) 110 11.2 Configuration Sequence.................................................................................................... 110 12. ACPI REGISTERS FEATURES .................................................................................................. 112 12.1 SMI to SCI/SCI to SMI and Bus Master ............................................................................ 113 12.2 Power Management Timer ................................................................................................ 114 12.3 ACPI Registers (ACPIRs).................................................................................................. 115 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.3.9 12.3.10 12.3.11 12.3.12 Power Management 1 Status Register 1 (PM1STS1) ........................................................ 115 Power Management 1 Status Register 2 (PM1STS2) ........................................................ 116 Power Management 1 Enable Register 1(PM1EN1)........................................................... 117 Power Management 1 Enable Register 2 (PM1EN2).......................................................... 117 Power Management 1 Control Register 1 (PM1CTL1) ....................................................... 118 Power Management 1 Control Register 2 (PM1CTL2) ....................................................... 118 Power Management 1 Control Register 3 (PM1CTL3) ....................................................... 119 Power Management 1 Control Register 4 (PM1CTL4) ....................................................... 119 Power Management 1 Timer 1 (PM1TMR1) ....................................................................... 120 Power Management 1 Timer 2 (PM1TMR2) ....................................................................... 120 Power Management 1 Timer 3 (PM1TMR3) ....................................................................... 121 Power Management 1 Timer 4 (PM1TMR4) ....................................................................... 121 -V- Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 12.3.13 12.3.14 12.3.15 12.3.16 12.3.17 12.3.18 12.3.19 12.3.20 12.3.21 General Purpose Event 0 Status Register 1 (GP0STS1) ................................................... 122 General Purpose Event 0 Status Register 2 (GP0STS2) ................................................... 122 General Purpose Event 0 Enable Register 1 (GP0EN1) .................................................... 123 General Purpose Event 0 Enable Register 2 (GP0EN2) .................................................... 124 General Purpose Event 1 Status Register 1 (GP1STS1) ................................................... 124 General Purpose Event 1 Status Register 2 (GP1STS2) ................................................... 125 General Purpose Event 1 Enable Register 1 (GP1EN1) .................................................... 125 General Purpose Event 1 Enable Register 2 (GP1EN2) .................................................... 126 Bit Map Configuration Registers ......................................................................................... 127 13. SERIAL IRQ................................................................................................................................. 128 13.1 Start Frame........................................................................................................................ 129 13.2 IRQ/Data Frame ................................................................................................................ 129 13.3 Stop Frame........................................................................................................................ 130 13.4 Reset and Initialization ...................................................................................................... 130 14. CONFIGURATION REGISTER ................................................................................................... 131 14.1 Chip (Global) Control Register .......................................................................................... 131 14.2 Logical Device 0 (FDC) ..................................................................................................... 136 14.3 Logical Device 1 (Parallel Port) ......................................................................................... 140 14.4 Logical Device 2 (UART A)¢) ............................................................................................ 141 14.5 Logical Device 3 (UART B) ............................................................................................... 141 14.6 Logical Device 5 (KBC) ..................................................................................................... 142 14.7 Logical Device 6 (IR) ......................................................................................................... 143 14.8 Logical Device 7 (GP I/O Port I) ........................................................................................ 144 14.9 Logical Device 8 (GP I/O Port II) ....................................................................................... 148 14.10 Logical Device 9 (GP I/O Port III) ...................................................................................... 152 14.11 Logical Device A (ACPI).................................................................................................... 155 15. SPECIFICATIONS....................................................................................................................... 162 15.1 Absolute Maximum Ratings............................................................................................... 162 15.2 DC CHARACTERISTICS .................................................................................................. 162 15.3 AC Characteristics............................................................................................................. 166 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 15.3.6 15.3.7 15.3.8 15.3.9 15.3.10 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. ...................................................... 166 UART/Parallel Port ............................................................................................................. 167 Parallel Port Mode Parameters........................................................................................... 168 EPP Data or Address Read Cycle Timing Parameters....................................................... 168 EPP Data or Address Write Cycle Timing Parameters ....................................................... 169 Parallel Port FIFO Timing Parameters................................................................................ 170 ECP Parallel Port Forward Timing Parameters .................................................................. 170 ECP Parallel Port Reverse Timing Parameters .................................................................. 170 KBC Timing Parameters..................................................................................................... 171 GPIO Timing Parameters ................................................................................................... 172 16. TIMING WAVEFORMS................................................................................................................ 173 - VI - W83977ATF/W83977ATG 16.1 FDC ................................................................................................................................... 173 16.2 UART/Parallel.................................................................................................................... 174 16.2.1 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 16.3.8 16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 16.4.6 16.4.7 Modem Control Timing ....................................................................................................... 175 Parallel Port Timing ............................................................................................................ 176 EPP Data or Address Read Cycle (EPP Version 1.9) ........................................................ 177 EPP Data or Address Write Cycle (EPP Version 1.9)......................................................... 178 EPP Data or Address Read Cycle (EPP Version 1.7) ........................................................ 179 EPP Data or Address Write Cycle (EPP Version 1.7)......................................................... 180 Parallel Port FIFO Timing ................................................................................................... 180 ECP Parallel Port Forward Timing...................................................................................... 181 ECP Parallel Port Reverse Timing...................................................................................... 181 Write Cycle Timing ............................................................................................................. 182 Read Cycle Timing ............................................................................................................. 182 Send Data to K/B................................................................................................................ 182 Receive Data from K/B ....................................................................................................... 183 Input Clock ......................................................................................................................... 183 Send Data to Mouse........................................................................................................... 183 Receive Data from Mouse .................................................................................................. 183 16.3 Parallel Port ....................................................................................................................... 176 16.4 KBC ................................................................................................................................... 182 16.5 GPIO Write Timing Diagram.............................................................................................. 184 16.6 Master Reset (MR) Timing ................................................................................................ 184 17. APPLICATION CIRCUITS ........................................................................................................... 185 17.1 Parallel Port Extension FDD.............................................................................................. 185 17.2 Parallel Port Extension 2FDD............................................................................................ 186 17.3 Four FDD Mode................................................................................................................. 186 18. ORDERING INFORMATION ....................................................................................................... 187 19. HOW TO READ THE TOP MARKING ........................................................................................ 188 20. PACKAGE DIMENSIONS............................................................................................................ 189 - VII - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 1. GENERAL DESCRIPTION W83977ATF/ATG is an evolving product from Winbond's most popular I/O chip W83877F --- which integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, configurable plugand-play registers for the whole chip --- plus additional powerful features: ACPI, 8042 keyboard controller with PS/2 mouse support, 23 general purpose I/O ports, full 16-bit address decoding, OnNow keyboard wake-up, OnNow mouse wake-up, and OnNow CIR wake-up. In addition, W83977ATF/ATG provides IR functions: IrDA 1.1 (MIR for 1.152M bps or FIR for 4M bps) and TV remote IR (Consumer IR, supporting NEC, RC-5, extended RC-5, and RECS-80 protocols). The disk drive adapter functions of W83977ATF/ATG include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto W83977ATF/ATG greatly reduces the number of components required for interfacing with floppy disk drives. W83977ATF/ATG supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. W83977ATF/ATG provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps which support higher speed modems. W83977ATF/ATG provides independent 3rd UART(32-byte FIFO) dedicated for the IR function. W83977ATF/ATG supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature TM demand of Windows 95 , which makes system resource allocation more efficient than ever. W83977ATF/ATG provides functions that comply with ACPI (Advanced Configuration and Power Interface), which includes support of legacy and ACPI power management through SMI or SCI function pins. W83977ATF/ATG also has auto power management to reduce power consumption. The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable TM ROM and a 256-Byte RAM bank. Keyboard BIOS firmware is available with optional AMIKEY -2, TM Phoenix MultiKey/42 , or customer code. W83977ATF/ATG provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. W83977ATF/ATG is made to fully comply with Microsoft PC97 Hardware Design Guide. IRQs, DMAs, and I/O space resource are flexible to adjust to meet ISA PnP requirement. Moreover, W83977ATF/ATG is made to meet the specification of PC97's requirement in the power management: ACPI and DPM (Device Power Management). Another benefit is that W83977ATF/ATG has the same pin assignment as W83977AF, W83977F, and W83977TF. This makes the design very flexible. -1- Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 2. FEATURES General • Plug & Play 1.0A compatible • Support 13 IRQs, 4 DMA channels, full 16-bit address decoding • Capable of ISA Bus IRQ Sharing • Compliant with Microsoft PC97 Hardware Design Guide • Support DPM (Device Power Management), ACPI • Report ACPI status interrupt by SCI signal issued from any of the 13 IQRs pins or GPIO xx • Programmable configuration settings • Single 24/48 Mhz clock input FDC • Compatible with IBM PC AT disk drive systems • Variable write pre-compensation with track selectable capability • Support vertical recording format • DMA enable logic • 16-byte data FIFOs • Support floppy disk drives and tape drives • Detects all overrun and underrun conditions • Built-in address mark detection circuit to simplify the read electronics • FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) • Support up to four 3.5-inch or 5.25-inch floppy disk drives • Completely compatible with industry standard 82077 • 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate • Support 3-mode FDD, and its Win95 driver UART • Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs • MIDI compatible • Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop bits generation • Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation • Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz by 1 to (216-1) • Maximum baud rate up to 921k bps for 14.769 Mhz and 1.5M bps for 24 Mhz -2- W83977ATF/W83977ATG Infrared • Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps • Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps • Support IrDA version 1.1 MIR (1.152M bps) and FIR (4M bps) protocol --- Single DMA channel for transmitter or receiver --- 3rd UART with 32-byte FIFO is supported in both TX/RX transmission --- 8-byte status FIFO is supported to store received frame status (such as overrun CRC error, etc.) • Support auto-config SIR and FIR Parallel Port • Compatible with IBM parallel port • Support PS/2 compatible bi-directional parallel port • Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification • Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification • Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port • Enhanced printer port back-drive current protection Keyboard Controller • 8042 based with optional F/W from AMIKKEY TM -2, Phoenix MultiKey/42 TM or customer code with 2K bytes of programmable ROM, and 256 bytes of RAM • Asynchronous Access to Two Data Registers and One status Register • Software compatibility with the 8042 and PC87911 microcontrollers • Support PS/2 mouse • Support port 92 • Support both interrupt and polling modes • Fast Gate A20 and Hardware Keyboard Reset • 8 Bit Timer/ Counter • Support binary and BCD arithmetic • 6MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency General Purpose I/O Ports • 23 programmable general purpose I/O ports; 1 dedicate, 22 optional • General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer output, power LED output, infrared I/O pins, general purpose address decoder, KBC control I/O pins -3- Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG OnNow Funtions • Keyboard wake-up by programmable keys (patent pending) • Mouse wake-up by programmable buttons (patent pending) • CIR wake-up by programmable keys (patent pending) Package • 128-pin PQFP -4- W83977ATF/W83977ATG 3. PIN CONFIGURATION II RR QQ 11 21 I RI I I I QR R R R 1 QQQ Q 0134 5 / /P PA AN NS SW WO IU NT ,, IIII GG R R R RA V A A A A V A PPV Q Q Q Q1 S 1 1 1 1 C 1 A A A A A A A A A A 2 2 S 6 7 8 95 S 4 3 2 1 C0 9 8 7 6 5 4 3 2 1 0 3 2 B / S M I, G GMK P PCC 22LL 1 0KK / R I B / R I A 11 199 9 9 99999 9 88 8888 88 8877 777777 7 766666 00 098 7 6 54321 0 98 7654 32 1098 765432 1 098765 21 0 IRQ14/GP14 IRQ15/GP15 IOR IOW AEN IOCHRDY D0 D1 D2 D3 D4 D5 VCC D6 D7 MR DACK0/GP16 VSS SCI/DRQ0/GP17 DACK1 DRQ1 DACK2 DRQ2 DACK3 DRQ3 TC 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 1 111 1 1 1 1 1 22 22 2 222 2 2 3 33 3 3 33 33 1 2 34 5 67 8 90 1 234 5 6 7 8 9 01 23 4 567 8 9 0 12 3 4 56 78 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 VBAT XTAL1 VSS XTAL2 MDATA KDATA KBLOCK/GP13 KBRST/GP12 GA20/GP11 VCC DCDB SOUTB/PEN48 SINB DTRB RTSB DSRB CTSB DCDA SOUTA/PENKBC SINA DTRA/PNPCSV RTSA/HEFRAS DSRA CTSA CIRRX/GP24 IRRXH/IRSL0 C L K I N D R V D E N 0 D/ / / / / / / / R D H R W T WW S VS E DP R E D T DK A A A E ECDT K P NH A 0 1G , G P 1 0 , / S C I //// D MD D I OS S RBAB / / S P V B / PP V P P P PP P / / / / / M I L E C U A DD S D D D D D D S I E A S O NC C S C 7 6 S 5 4 3 2 1 0 L N R F T I I RD B A DT YK E NT X I R R X I R T X -5- Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 4. PIN DESCRIPTION Note: Please refer to Section 12.2 DC CHARACTERISTICS for details. I/O6t I/O8t I/O8 I/O12t I/O12 I/O16u - TTL level bi-directional pin with 6 mA source-sink capability - TTL level bi-directional pin with 8 mA source-sink capability - CMOS level bi-directional pin with 8 mA source-sink capability - TTL level bi-directional pin with 12 mA source-sink capability - CMOS level bi-directional pin with 12 mA source-sink capability - CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal I/OD16u pull-up resistor I/O24t - TTL level bi-directional pin with 24 mA source-sink capability OUT8t - TTL level output pin with 8 mA source-sink capability OUT12t - TTL level output pin with 12 mA source-sink capability OD12 OD24 INt INc INcu INcs INts INtsu - Open-drain output pin with 12 mA sink capability - Open-drain output pin with 24 mA sink capability - TTL level input pin - CMOS level input pin - CMOS level input pin with internal pull-up resitor - CMOS level Schmitt-triggered input pin - TTL level Schmitt-triggered input pin - TTL level Schmitt-triggered input pin with internal pull-up resistor 4.1 Host Interface PIN 74-84 86-89 91 109114 116117 105 106 107 108 118 SYMBOL A0−A10 A11-A14 A15 D0−D5 D6−D7 I/O INt INt INt I/O12t I/O12t INts INts INts OD24 INts FUNCTION System address bus bits 0-10. System address bus bits 11-14. System address bus bit 15. System data bus bits 0-5. System data bus bits 6-7. CPU I/O read signal. CPU I/O write signal. System address bus enable. In EPP Mode, this pin is the IO Channel Ready output to extend the host read/write cycle. Master Reset; Active high; MR is low during normal operations. IOR IOW AEN IOCHRDY MR -6- W83977ATF/W83977ATG Host Interface, continued SYMBOL PIN 119 I/O INtsu I/O12t I/O12t FUNCTION DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00, default) General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01) Alternate function from GP16: Watch dog timer output. KBC P15 I/O port. (CR2C bit 5_4 = 10) DMA Channel 0 request signal. (CR2C bit 7_6 = 00, default) General purpose I/O port 1bit 7. (CR2C bit 7_6 = 01) Alternate Function from GP17: Power LED output. KBC P14 I/O port. (CR2C bit 7_6 = 10) System Control Interrupt.(CR2C bit 7_6 = 11) In the ACPI power management mode, SCI is driven low by the power management events. DACK0 GP16 (WDTO) P15 DRQ0 GP17 (PLEDO) P14 121 OUT12t I/O12t I/O12t OD12 SCI DACK1 DRQ1 122 123 124 125 126 127 128 99 INts OUT12t INts OUT12t INts OUT12t INts OUT12t I/O12t DMA Channel 1 Acknowledge signal. DMA Channel 1 request signal. DMA Channel 2 Acknowledge signal. DMA Channel 2 request signal. DMA Channel 3 Acknowledge signal. DMA Channel 3 request signal. Terminal Count. When active, this pin indicates termination of a DMA transfer. Interrupt request 1. (Logical device 9, CRF1 bit 2 = 0) General purpose I/O port 3 bit 0. (Logical device 9, CRF1 bit 2 = 1) Interrupt request 3. (Logical device 9, CRF1 bit 2 = 0) General purpose I/O port 3 bit 1. (Logical device 9, CRF1 bit 2 = 1) Interrupt request 4. (Logical device 9, CRF1 bit 2 = 0) General purpose I/O port 3 bit 2. (Logical device 9, CRF1 bit 2 = 1) Interrupt request 5. (Logical device 9, CRF1 bit 2 = 0) General purpose I/O port 3 bit 3. (Logical device 9, CRF1 bit 2 = 1) Interrupt request 6. (Logical device 9, CRF1 bit 2 = 0) General purpose I/O port 3 bit 4. (Logical device 9, CRF1 bit 2 = 1) DACK2 DRQ2 DACK3 DRQ3 TC IRQ1 IRQ1 IRQ3 GP31 IRQ4 GP32 IRQ5 GP33 IRQ6 GP34 98 OUT12t I/O12t 97 OUT12t I/O12t 96 OUT12t I/O12t 95 OUT12t I/O12t -7- Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Host Interface, continued SYMBOL IRQ7 GP35 IRQ8 GP36 IRQ9 GP37 IRQ10 SERIRQ IRQ11 PCICLK IRQ12 GP26 IRQ14 GP14 ( GPACS ) (P17) PLEDO IRQ15 GP15 ( GPAWE ) (P12) WDT CLKIN PIN 94 I/O OUT12t I/O12t FUNCTION Interrupt request 7. (Logical device 9, CRF1 bit 2 = 0) General purpose I/O port 3 bit 5. (Logical device 9, CRF1 bit 2 = 1) Interrupt request 8. (Logical device 9, CRF1 bit 2 = 0) General purpose I/O port 3 bit 6. (Logical device 9, CRF1 bit 2 = 1) Interrupt request 9. (Logical device 9, CRF1 bit 2 = 0) General purpose I/O port 3 bit 7. (Logical device 9, CRF1 bit 2 = 1) Interrupt request 10. (Logical device 9, CRF1 bit 2 = 0) Serial IRQ input/output. (Logical device 9, CRF1 bit 2 = 1) Interrupt request 11. (Logical device 9, CRF1 bit 2 = 0) PCI clock input. (Logical device 9, CRF1 bit 2 = 1) Interrupt request 12. (Logical device 9, CRF1 bit 2 = 0) General purpose I/O port 2 bit 6. (Logical device 9, CRF1 bit 2 = 1) Interrupt request 14. (CR2C bit 1_0 = 00, default) General purpose I/O port 1 bit 4. (CR2C bit 1_0 = 01) Alternate Function 1 from GP14: General purpose address decode output. Alternate Function 2 from GP14: KBC P17 I/O port. 93 OUT12t I/O12t 92 OUT12t I/O12t 100 101 102 OUT12t I/O12t OUT12t INt OUT12t I/O12t 103 OUT12t I/O12t OUT12t 104 OUT12t I/O12t Power LED output. (CR2C bit 1_0 = 10) Interrupt request 15.(CR2C bit 3_2 = 00, default) General purpose I/O port 1 bit 5. (CR2C bit 3_2 = 01) Alternate Function 1 from GP15: General purpose address write enable output. Alternate Function 2 from GP15: KBC P12 I/O port. OUT12t 1 INt Watch-Dog timer output. (CR2C bit 3_2 = 10) 24 or 48 MHz clock input, selectable through CR24 bit 6. -8- W83977ATF/W83977ATG 4.2 GP20 (KBRST) General Purpose I/O Port PIN 69 70 SYMBOL I/O I/O12t OD12 FUNCTION General purpose I/O port 2 bit 0. Alternate Function from GP20: Keyboard reset. (KBC P20) System Management Interrupt. (CR2B bit 4_3 = 00, default) In the legacy power management mode, SMI is driven low by the power managenment events. SMI GP21 (P13) P16 I/O12t I/O12t 72 OD12 I/O12t 73 IN12t I/O12t General purpose I/O port 2 bit 1. (CR2B bit 4_3 = 01) Alternate Function from GP21: KBC P13 I/O port. KBC P16 I/O port. (CR2B bit 4_3 = 10) Panel Switch output. (CR2B bit 5 = 0, default) General purpose I/O port 2 bit 2. (CR2B bit 5 = 1) Alternate Function from GP22: KBC P14 I/O port. Panel Switch input. (CR2B bit 7_6 = 00, default) General purpose I/O port 2 bit 3. (CR2B bit 7_6 = 01) Alternate Function from GP23: KBC P15 I/O port. PANSWOUT GP22 (P14) PANSWIN GP23 (P15) GP24 (P16) P13 CIRRX GP25 (GA20) IRRXH IRSL0 40 I/O12t I/O12t INt General purpose I/O port 2 bit 4. (CR2A bit 5_4 = 01) Alternate Function from GP24: KBC P16 I/O port. KBC P13 I/O port. (CR2A bit 5_4 = 10) Consumer IR receiving input. (CR2A bit 5_4 = 00) General purpose I/O port 2 bit 5. (CR2A bit 3_2 = 10) Alternate Function from GP25: GATE A20. (KBC P21) FIR receiving input. (CR2A bit 3_2 = 00) IR module select 0. (CR2A bit 3_2 = 01) 39 I/O12 INt OUT12t -9- Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 4.3 Serial Port Interface PIN 41 48 42 49 43 I/O8t INt SYMBOL I/O INt FUNCTION Clear To Send. This is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 kΩ is recommended if intends to pull up. (select 370H as configuration I/O port′s address) CTSA CTSB DSRA DSRB RTSA HEFRAS RTSB DTRA PNPCSV 50 44 I/O8t I/O8t UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. UART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as PNPCSV , which provides the power-on value for CR24 bit 0 ( PNPCSV ). A 4.7 kΩ is recommended if intends to pull up. (clear the default value of FDC, UARTs, and PRT) DTRB SINA SINB SOUTA PENKBC 51 45, 52 46 I/O8t INt I/O8t UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Serial Input. It is used to receive serial data through the communication link. UART A Serial Output. It is used to transmit serial data out to the communication link. During power-on reset, this pin is pulled down internally and is defined as PENKBC, which provides the power-on value for CR24 bit 2 (ENKBC). A 4.7 kΩ resistor is recommended if intends to pull up. (enable KBC) SOUTB PEN48 53 I/O8t UART B Serial Output. During power-on reset, this pin is pulled down internally and is defined as PEN48, which provides the power-on value for CR24 bit 6 (EN48). A 4.7 kΩ resistor is recommended if intends to pull up. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. DCDA DCDB RIA RIB 47 54 65 66 INt INt - 10 - W83977ATF/W83977ATG 4.4 IRRX IRTX Infrared Interface PIN 37 38 SYMBOL I/O INcs OUT12t Infrared Receiver input. Infrared Transmitter Output. FUNCTION 4.5 Multi-Mode Parallel Port PIN 18 The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL SLCT I/O INt FUNCTION PRINTER MODE: SLCT An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WE2 This pin is for Extension FDD B; its function is the same as the WE pin of FDC. OD12 OD12 PE 19 INt EXTENSION 2FDD MODE: WE2 This pin is for Extension FDD A and B; its function is the same as the WE pin of FDC. PRINTER MODE: PE An active high input on this pin indicates that the printer has detected the end of the paper. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WD2 This pin is for Extension FDD B; its function is the same as the WD pin of FDC. OD12 OD12 EXTENSION 2FDD MODE: WD2 This pin is for Extension FDD A and B; its function is the same as the WD pin of FDC. PRINTER MODE: BUSY An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. BUSY 21 INt OD12 EXTENSION FDD MODE: MOB2 This pin is for Extension FDD B; its function is the same as the MOB pin of FDC. OD12 EXTENSION 2FDD MODE: MOB2 This pin is for Extension FDD A and B; its function is the same as the MOB pin of FDC. - 11 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Multi-Mode Parallel Port, continued SYMBOL PIN 22 I/O INt PRINTER MODE: ACK FUNCTION ACK An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: DSB2 This pin is for the Extension FDD B; its functions is the same as the DSB pin of FDC. EXTENSION 2FDD MODE: DSB2 This pin is for Extension FDD A and B; its function is the same as the DSB pin of FDC. PRINTER MODE: ERR An active low input on this pin indicates that the printer has encountered an error condition. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD12 OD12 EXTENSION FDD MODE: HEAD2 This pin is for Extension FDD B; its function is the same as the HEAD pin of FDC. EXTENSION 2FDD MODE: HEAD2 This pin is for Extension FDD A and B; its function is the same as the HEAD pin of FDC. OD12 ERR 34 INt SLIN 32 OD12 PRINTER MODE: SLIN Output line for detection of printer selection. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: STEP2 This pin is for Extension FDD B; its function is the same as the STEP pin of FDC. OD12 EXTENSION 2FDD MODE: STEP2 This pin is for Extension FDD A and B; its function is the same as the STEP pin of FDC. - 12 - W83977ATF/W83977ATG Multi-Mode Parallel Port, continued SYMBOL PIN 33 I/O OD12 FUNCTION PRINTER MODE: INIT Output line for the printer initialization. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DIR2 This pin is for Extension FDD B; its function is the same as the DIR pin of FDC. INIT OD12 OD12 EXTENSION 2FDD MODE: DIR2 This pin is for Extension FDD A and B; its function is the same as the DIR pin of FDC. PRINTER MODE: AFD An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. PRINTER MODE: STB An active low output is used to latch the parallel data into the printer. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD0 Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: INDEX2 This pin is for Extension FDD B; its function is the same as the INDEX pin of FDC. It is pulled high internally. AFD 35 OD12 OD12 OD12 STB 36 OD12 PD0 31 I/O24t INt INt EXTENSION 2FDD MODE: INDEX2 This pin is for Extension FDD A and B; its function is the same as the INDEX pin of FDC. It is pulled high internally. - 13 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Multi-Mode Parallel Port, continued SYMBOL PD1 PIN 30 I/O I/O24t PRINTER MODE: PD1 FUNCTION Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. INt EXTENSION FDD MODE: TRAK02 This pin is for Extension FDD B; its function is the same as the TRAK0 pin of FDC. It is pulled high internally. INt EXTENSION. 2FDD MODE: TRAK02 This pin is for Extension FDD A and B; its function is the same as the TRAK0 pin of FDC. It is pulled high internally. PD2 29 I/O24t PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. INt EXTENSION FDD MODE: WP2 This pin is for Extension FDD B; its function is the same as the WP pin of FDC. It is pulled high internally. INt EXTENSION. 2FDD MODE: WP2 This pin is for Extension FDD A and B; its function is the same as the WP pin of FDC. It is pulled high internally. PD3 28 I/O24t PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: RDATA2 This pin is for Extension FDD B; its function is the same as the RDATA pin of FDC. It is pulled high internally. INt INt EXTENSION 2FDD MODE: RDATA2 This pin is for Extension FDD A and B; its function is the same as the RDATA pin of FDC. It is pulled high internally. PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PD4 27 I/O24t INt EXTENSION FDD MODE: DSKCHG2 This pin is for Extension FDD B; the function of this pin is the same as the DSKCHG pin of FDC. It is pulled high internally. INt EXTENSION 2FDD MODE: DSKCHG2 This pin is for Extension FDD A and B; this function of this pin is the same as the DSKCHG pin of FDC. It is pulled high internally. - 14 - W83977ATF/W83977ATG Multi-Mode Parallel Port, continued SYMBOL PD5 PIN 26 I/O I/O24t FUNCTION PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. PD6 24 I/O24t - OD24 EXTENSION. 2FDD MODE: MOA2 This pin is for Extension FDD A; its function is the same as the MOA pin of FDC. PD7 23 I/O24t PRINTER MODE: PD7 Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD24 EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: DSA2 This pin is for Extension FDD A; its function is the same as the DSA pin of FDC. 4.6 FDC Interface PIN 2 3 SYMBOL DRVDEN0 DRVDEN1 GP10 (IRQIN1) P12 I/O OD24 OD24 IO24t IO24t OD12 Drive Density Select bit 0. FUNCTION Drive Density Select bit 1. (CR2A bit 1_0 = 00, default) General purpose I/O port 1 bit 0. (CR2A bit 1_0 = 01) Alternate Function from GP10: Interrupt channel input. KBC P12 I/O port. (CR2A bit 1_0 = 10) System Control Interrupt. (CR2A bit 1_0 = 11) In the ACPI power management mode, SCI is driven low by the power management events. SCI HEAD 5 OD24 Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Write enable. An open drain output. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. WE WD 9 10 OD24 OD24 - 15 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG FDC Interface, continued SYMBOL PIN 11 12 I/O OD24 OD24 FUNCTION Step output pulses. This active low open drain output produces a pulse to move the head to another track. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion STEP DIR MOB DSA DSB MOA DSKCHG 13 14 15 16 4 OD24 OD24 OD24 OD24 INcs Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by a 1 K　resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). The read data input signal from the FDD. This input pin is pulled up internally by a 1 K　 resistor. The resistor can be disabled by bit 7 of L0CRF0 (FIPURDWN). RDATA 6 INcs WP 7 INcs Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 K　 resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 K　 resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 K　 resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). TRAK0 8 INcs INDEX 17 INcs - 16 - W83977ATF/W83977ATG 4.7 KBC Interface PIN 59 60 67 68 56 SYMBOL KDATA MDATA KCLK MCLK GA20 GP11 (IRQIN2) KBRST GP12 (WDTO) KBLOCK GP13 I/O I/O16u I/O16u I/O16u I/O16u I/O12t I/O12t Keyboard Data. PS2 Mouse Data. Keyboard Clock. PS2 Mouse Clock. FUNCTION KBC GATE A20 (P21) Output. (CR2A bit 6 = 0, default) General purpose I/O port 1 bit 1. (CR2A bit 6 = 1) Alternate Function from GP11: Interrupt channel input. W83C45 Keyboard Reset (P20) Output. (CR2A bit 7 = 0, default) General purpose I/O port 1 bit 2. (CR2A bit 7 = 1) Alternate Function 1 from GP12: Watchdog timer output. W83C45 KINH (P17) Input. (CR2B bit 0 = 0, default) General purpose I/O port 1 bit 3. (CR2B bit 0 = 1) 57 I/O12t I/O12t 58 INts I/O16t 4.8 VCC VSB GND POWER PINS PIN 20, 55, 85, 115 71 25, 62, 90, 120 SYMBOL FUNCTION +5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. Ground. 4.9 ACPI Interface PIN 64 63 61 SYMBOL VBAT XTAL1 XTAL2 I/O NA INC O8t Battery voltage input. 32.768Khz Clock Input. 32.768Khz Clock Output. FUNCTION - 17 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 5. FDC FUNCTIONAL DESCRIPTION 5.1 W83977ATF/ATG FDC The floppy disk controller of W83977ATF/ATG integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to 2 M bits/sec data rate. The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core. 5.1.1 AT interface The interface consists of the standard asynchronous signals: RD , WR , A0-A3, IRQ, DMA control, and a data bus. The address lines select between the configuration registers, the FIFO and control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2 register sets are a superset of the registers found in a PC/AT. 5.1.2 FIFO (Data) The FIFO is 16 bytes in size and has programmable threshold values. All command parameter information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the CONFIGURE command. The advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following tables give several examples of the delays with a FIFO. The data are based upon the following formula: THRESHOLD # × (1/DATA/RATE) *8 - 1.5 μS = DELAY FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte MAXIMUM DELAY TO SERVICING AT 500K BPS Data Rate 1 × 16 μS - 1.5 μS = 14.5 μS 2 × 16 μS - 1.5 μS = 30.5 μS 8 × 16 μS - 1.5 μS = 6.5 μS 15 × 16 μS - 1.5 μS = 238.5 μS FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 1 × 8 μS - 1.5 μS = 6.5 μS 2 × 8 μS - 1.5 μS = 14.5 μS 8 × 8 μS - 1.5 μS = 62.5 μS 15 × 8 μS - 1.5 μS = 118.5 μS - 18 - W83977ATF/W83977ATG At the start of a command the FIFO is always disabled, and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred. An overrun and underrun will terminate the current command and the data transfer. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK and addresses need not be valid. Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed by the FDC based only on DACK . This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above operation is performed by using the new VERIFY command. No DMA operation is needed. 5.1.3 Data Separator The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The synchronized clock, called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates the read data into clock and data bytes. The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. Ideally, the DDS circuit cycles once every 12 clock cycles. Any data pulse input will be synchronized and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed. A digital integrator is used to keep track of the speed changes in the input data stream. 5.1.4 Write Precompensation The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive. The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits. 5.1.5 Perpendicular Recording Mode The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into the same area. FDCs with perpendicular recording drives can read standard 3.5" floppy disks, and can also read and write perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive. A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. - 19 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 5.1.6 FDC Core W83977ATF/ATG FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. Execution The controller performs the specified operation. Result After the operation is completed, status information and other housekeeping information is provided to the microprocessor. 5.1.7 FDC Commands Command Symbol Descriptions: C: Cylinder number 0 - 256 D: Data Pattern DIR: Step Direction DIR = 0, step out DIR = 1, step in DS0: Disk Drive Select 0 DS1: Disk Drive Select 1 DTL: Data Length EC: Enable Count EOT: End of Track EFIFO: Enable FIFO EIS: Enable Implied Seek EOT: End of track FIFOTHR: FIFO Threshold GAP: Gap length selection GPL: Gap Length H: Head number HDS: Head number select HLT: Head Load Time HUT: Head Unload Time LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset MFM: MFM or FM Mode MT: Multitrack N: The number of data bytes written in a sector NCN: New Cylinder Number ND: Non-DMA Mode OW: Overwritten - 20 - W83977ATF/W83977ATG PCN: POLL: PRETRK: R: RCN: R/W: SC: SK: SRT: ST0: ST1: ST2: ST3: WG: (1) Read Data PHASE Command Present Cylinder Number Polling Disable Precompensation Start Track Number Record Relative Cylinder Number Read/Write Sector/per cylinder Skip deleted data address mark Step Rate Time Status Register 0 Status Register 1 Status Register 2 Status Register 3 Write gate alters timing of WE R/W W W W W W W W W W 0 D7 0 D6 SK 0 D5 0 0 D4 0 0 D3 1 D2 1 D1 0 D0 REMARKS Command codes Sector ID information prior to command execution MT MFM HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------ Data transfer between the FDD and system Status information after command execution Sector ID information after command execution - 21 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG (2) Read Deleted Data PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W W W W W W W W W MT 0 MFM SK 0 1 1 0 0 0 0 0 0 HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Command codes Sector ID information prior to command execution Execution Result R R R R R R R R/W D7 -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------D6 D5 D4 D3 D2 D1 D0 Data transfer between the FDD and system Status information after command execution Sector ID information after command execution (3) Read A Track PHASE REMARKS Command W W W W W W W W W 0 0 MFM 0 0 0 0 1 0 0 0 0 0 HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Command codes Sector ID information prior to command execution Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------ Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after command execution Sector ID information after command execution - 22 - W83977ATF/W83977ATG (4) Read ID PHASE Command Execution R/W W W 0 0 D7 0 D6 0 0 D5 0 0 D4 1 0 D3 0 D2 1 D1 0 D0 REMARKS Command codes The first correct ID information on the cylinder is stored in Data Register MFM HDS DS1 DS0 Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------ Status information after command execution Disk status after the command has been completed (5) Verify PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W W W W W W W W MT MFM SK EC 0 0 1 0 0 0 1 1 0 Command codes Sector ID information prior to command execution HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL/SC ------------------- Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------ No data transfer takes place Status information after command execution Sector ID information after command execution - 23 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG (6) Version PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command Result (7) Write Data PHASE W R 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Command code Enhanced controller R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W W W W W W W W W MT MFM 0 0 0 0 0 0 0 0 1 0 1 Command codes Sector ID information prior to Command execution HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------ Data transfer between the FDD and system Status information after Command execution Sector ID information after Command execution - 24 - W83977ATF/W83977ATG (8) Write Deleted Data PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W W W W W W W W W MT MFM 0 0 0 0 0 0 1 0 0 0 1 Command codes Sector ID information prior to command execution HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL ----------------------- Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------ Data transfer between the FDD and system Status information after command execution Sector ID information after command execution - 25 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG (9) Format A Track PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W W W W W W 0 0 MFM 0 0 0 0 0 1 0 1 0 1 Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters HDS DS1 DS0 ---------------------- N -------------------------------------------- SC ------------------------------------------- GPL ------------------------------------------ D --------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined ------------------- Execution for Each Sector Repeat: Result W W W W R R R R R R R Status information after command execution (10) Recalibrate PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command Execution W W 0 0 0 0 0 0 0 0 0 0 1 0 1 1 Command codes Head retracted to Track 0 Interrupt DS1 DS0 (11) Sense Interrupt Status PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command Result W R R 0 0 0 0 1 0 0 0 Command code Status information at the end of each seek operation ---------------- ST0 ---------------------------------------- PCN ------------------------- - 26 - W83977ATF/W83977ATG (12) Specify PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W W W 0 0 0 0 0 0 1 1 Command codes | ---------SRT ----------- | --------- HUT ---------- | |------------ HLT ----------------------------------| ND (13) Seek PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W W W 0 0 0 0 0 0 0 0 1 0 1 1 1 Command codes HDS DS1 DS0 Head positioned over proper cylinder on diskette -------------------- NCN ----------------------- Execution R (14) Configure PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W W W W 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 Configure information EIS EFIFO POLL | ------ FIFOTHR ----| Internal registers written | --------------------PRETRK ----------------------- | Execution (15) Relative Seek PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W W W 1 0 DIR 0 0 0 0 0 1 0 1 1 1 Command codes HDS DS1 DS0 | -------------------- RCN ---------------------------- | - 27 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG (16) Dumpreg PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command Result W R R R R R R R R R R 0 0 0 0 1 1 1 0 Registers placed in FIFO ----------------------- PCN-Drive 0------------------------------------------ PCN-Drive 1 ----------------------------------------- PCN-Drive 2------------------------------------------ PCN-Drive 3 --------------------------SRT ------------------ | --------- HUT ------------------ HLT -----------------------------------| ND ------------------------ SC/EOT ---------------------LOCK 0 D3 D2 D1 D0 GAP WG 0 EIS EFIFO POLL | ------ FIFOTHR ------------------------------PRETRK ------------------------- (17) Perpendicular Mode PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W W 0 OW 0 0 0 D3 1 D2 0 D1 0 1 0 Command Code D0 GAP WG (18) Lock PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command Result W R LOCK 0 0 0 0 0 1 LOCK 0 0 1 0 0 0 0 0 Command Code (19) Sense Drive Status PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command Result W W R 0 0 0 0 0 0 0 0 0 0 1 0 0 Command Code Status information about disk drive HDS DS1 DS0 ---------------- ST3 ------------------------- (20) Invalid PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W ------------- Invalid Codes ----------------- Invalid codes (no operation- FDC goes to standby state) ST0 = 80H Result R -------------------- ST0 ---------------------- - 28 - W83977ATF/W83977ATG 5.2 Register Descriptions There are several status, data, and control registers in W83977ATF/ATG. These registers are defined below: ADDRESS OFFSET READ REGISTER WRITE base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 SA REGISTER SB REGISTER TD REGISTER MS REGISTER DT (FIFO) REGISTER DI REGISTER DO REGISTER TD REGISTER DR REGISTER DT (FIFO) REGISTER CC REGISTER 5.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows: 7 6 5 4 3 2 1 0 DIR WP INDEX HEAD TRAK0 STEP DRV2 INIT PENDING INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRV2 (Bit 6): 0 1 A second drive has been installed A second drive has not been installed STEP (Bit 5): This bit indicates the complement of STEP output. TRAK0 (Bit 4): This bit indicates the value of TRAK0 input. - 29 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG HEAD (Bit 3): This bit indicates the complement of HEAD output. 0 1 side 0 side 1 INDEX (Bit 2): This bit indicates the value of INDEX output. WP (Bit 1): 0 1 disk is write-protected disk is not write-protected DIR (Bit 0) This bit indicates the direction of head movement. 0 1 outward direction inward direction In PS/2 Model 30 mode, the bit definitions for this register are as follows: 7 6 5 4 3 2 1 0 DIR WP INDEX HEAD TRAK0 STEP F/F DRQ INIT PENDING INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0 input. - 30 - W83977ATF/W83977ATG HEAD (Bit 3): This bit indicates the value of HEAD output. 0 1 side 1 side 0 INDEX (Bit 2): This bit indicates the complement of INDEX output. WP (Bit 1): 0 1 disk is not write-protected disk is write-protected DIR (Bit 0) This bit indicates the direction of head movement. 0 1 inward direction outward direction 5.2.2 Status Register B (SB Register) (Read base address + 1) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows: 7 1 6 1 MOT EN A MOT EN B WE RDATA Toggle WDATA Toggle Drive SEL0 5 4 3 2 1 0 Drive SEL0 (Bit 5): This bit indicates the status of DO REGISTER bit 0 (drive select bit 0). WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD output pin. RDATA Toggle (Bit 3): This bit changes state at every rising edge of the RDATA output pin. WE (Bit 2): This bit indicates the complement of the WE output pin. - 31 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG MOT EN B (Bit 1) This bit indicates the complement of the MOB output pin. MOT EN A (Bit 0) This bit indicates the complement of the MOA output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows: 7 6 5 4 3 2 1 0 DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2 DRV2 (Bit 7): 0 1 A second drive has been installed A second drive has not been installed DSB (Bit 6): This bit indicates the status of DSB output pin. DSA (Bit 5): This bit indicates the status of DSA output pin. WD F/F (Bit 4): This bit indicates the complement of the latched WD output pin at every rising edge of the WD output pin. RDATA F/F(Bit 3): This bit indicates the complement of the latched RDATA output pin. WE F/F (Bit 2): This bit indicates the complement of latched WE output pin. DSD (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected - 32 - W83977ATF/W83977ATG 5.2.3 Digital Output Register (DO Register) (Write base address + 2) The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are as follows: 7 6 5 4 3 2 1-0 Drive Select: 00 select drive A 01 select drive B 10 select drive C 11 select drive D Floppy Disk Controller Reset Active low resets FDC DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A. Motor A on when active high Motor Enable B. Motor B on when active high Motor Enable C. Motor C on when active high Motor Enable D. Motor D on when active high 5.2.4 Tape Drive Register (TD Register) (Read base address + 3) This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as follows: 7 X 6 X 5 X 4 X 3 X 2 X Tape sel 0 Tape sel 1 1 0 If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows: 7 6 5 4 3 2 1 0 Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 - 33 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of CR8 bit 3, 2. Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive selected in the DO REGISTER. Floppy Boot drive 1, 0 (Bit 3, 2): These two bits reflect the value of CR8 bit 1, 0. Tape Sel 1, Tape Sel 0 (Bit 1, 0): These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive. TAPE SEL 1 TAPE SEL 0 DRIVE SELECTED 0 0 1 1 0 1 0 1 None 1 2 3 5.2.5 Main Status Register (MS Register) (Read base address + 4) The Main Status Register is used to control the flow of data between the microprocessor and the controller. The bit definitions for this register are as follows: 7 6 5 4 3 2 1 0 FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode. FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode. FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode. FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode. FDC Busy, (CB). A read or write command is in the process when CB = HIGH. Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the execution phase in non-DMA mode. Transition to LOW state indicates execution phase has ended. DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor. 5.2.6 Data Rate Register (DR Register) (Write base address + 4) The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER. - 34 - W83977ATF/W83977ATG 7 6 5 0 DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET 4 3 2 1 0 S/W RESET (Bit 7): This bit is the software reset bit. POWER-DOWN (Bit 6): 0 FDC in normal mode 1 FDC in power-down mode PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the precompensation values for the combination of these bits. PRECOMP PRECOMPENSATION DELAY 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 250K - 1 Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) 2 Mbps Tape drive Default Delays 20.8 nS 41.17 nS 62.5nS 83.3 nS 104.2 nS 125.00 nS 0.00 nS (disabled) DATA RATE DEFAULT PRECOMPENSATION DELAYS 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S 125 nS 125 nS 125 nS 41.67nS 20.8 nS - 35 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control. 00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1 01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0 10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0 11 1 MB/S (MFM), Illegal (FM), RWC = 1 The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as well as setting 10 to DRT1 and DRT0 bits, which are two of the Configure Register CRF4 or CRF5 bits in logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for individual data rates setting. 5.2.7 FIFO Register (R/W base address + 5) The Data Register consists of four status registers in a stack, with only one register presented to the data bus at a time. This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In W83977ATF/ATG, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. Status Register 0 (ST0) 7-6 5 4 3 2 1-0 US1, US0 Drive Select: 00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected HD Head address: 1 Head selected 0 Head selected NR Not Ready: 1 Drive is not ready 0 Drive is ready EC Equipment Check: 1 When a fault signal is received from the FDD or the track 0 signal fails to occur after 77 step pulses 0 No error SE Seek end: 1 seek end 0 seek error IC Interrupt Code: 00 Normal termination of command 01 Abnormal termination of command 10 Invalid command issue 11 Abnormal termination because the ready signal from FDD changed state during command executio - 36 - W83977ATF/W83977ATG Status Register 1 (ST1) 7 6 5 4 3 2 1 0 Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data. Not used. This bit is always 0. OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer. DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field. Not used. This bit is always 0. EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder. Status Register 2 (ST2) 7 6 5 4 3 2 1 0 MD (Missing Address Mark in Data Field). 1 If the FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 No error BC (Bad Cylinder) 1 Bad Cylinder 0 No error SN (Scan Not satisfied) 1 During execution of the Scan command 0 No error SH (Scan Equal Hit) 1 During execution of the Scan command, if the equal condition is satisfied 0 No error WC (Wrong Cylinder) 1 Indicates wrong Cylinder DD (Data error in the Data field) 1 If the FDC detects a CRC error in the data field 0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0 Status Register 3 (ST3) 7 6 5 4 3 2 1 0 US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault - 37 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 5.2.8 Digital Input Register (DI Register) (Read base address + 7) The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of DSKCHG , while other bits of the data bus remain in tri-state. Bit definitions are as follows: 7 6 5 4 3 2 1 0 xxxxxxx for hard disk controller x Reservedreadthe this register, these bits are in tri-stat During a of DSKCHG In the PS/2 mode, the bit definitions are as follows: 7 6 1 5 1 4 1 3 1 HIGH DENS DRATE0 DRATE1 2 1 0 DSKCHG DSKCHG (Bit 7): This bit indicates the complement of the DSKCHG input. Bit 6-3: These bits are always a logic 1 during a read. DRATE1 DRATE0 (Bit 2, 1): These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings corresponding to the individual data rates. HIGH DENS (Bit 0): 0 1 500 KB/S or 1 MB/S data rate (high density FDD) 250 KB/S or 300 KB/S data rate - 38 - W83977ATF/W83977ATG In the PS/2 Model 30 mode, the bit definitions are as follows: 7 6 0 5 0 4 0 DRATE0 DRATE1 NOPREC DMAEN 3 2 1 0 DSKCHG DSKCHG (Bit 7): This bit indicates the status of DSKCHG input. Bit 6-4: These bits are always a logic 1 during a read. DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3. NOPREC (Bit 2): This bit indicates the value of CC REGISTER NOPREC bit. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. 5.2.9 Configuration Control Register (CC Register) (Write base address + 7) This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows: 7 6 5 4 3 2 1 0 x x x x x x DRATE0 DRATE1 X: Reserved Bit 7-2: Reserved. These bits should be set to 0. - 39 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. In the PS/2 Model 30 mode, the bit definitions are as follows: 7 X 6 X 5 X 4 X 3 X DRATE0 DRATE1 NOPREC X: Reserved 2 1 0 Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. - 40 - W83977ATF/W83977ATG 6. UART PORT 6.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B) The UARTs are used to convert parallel data into serial format on the transmit side and, convert serial data to parallel format on the receiver side. The serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (fivebit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also include complete modem control capability and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16byte FIFOs for both receive and transmit mode. 6.2 6.2.1 Register Address UART Control Register (UCR) (Read/Write) The UART Control Register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection. 7 6 5 4 3 2 1 0 Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format) from the divisor latches of the baudrate generator during a read or write operation. When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control Register can be accessed. Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is affected by this bit; the transmitter is not affected. Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1, (1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check. - 41 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG TABLE 6-1 UART Register Bit Map BIT NUMBER REGISTER ADDRESS BASE +0 BDLAB = 0 0 RBR RX Data Bit 0 TBR TX Data Bit 0 ICR 1 RX Data Bit 1 TX Data Bit 1 2 RX Data Bit 2 TX Data Bit 2 USR Interrupt Enable (EUSRI) Interrupt Status Bit (1) XMIT FIFO Reset 3 RX Data Bit 3 TX Data Bit 3 HSR Interrupt Enable (EHSRI) Interrupt Status Bit (2)** DMA Mode Select 4 RX Data Bit 4 TX Data Bit 4 0 5 RX Data Bit 5 TX Data Bit 5 0 6 RX Data Bit 6 TX Data Bit 6 0 7 RX Data Bit 7 TX Data Bit 7 0 Receiver Buffer Register (Read Only) Transmitter Buffer Register (Write Only) Interrupt Control Register +0 BDLAB = 0 +1 BDLAB = 0 RBR Data TBR Ready Empty Interrupt Interrupt Enable Enable (ERDRI) (ETBREI) "0" if Interrupt Pending FIFO Enable Interrupt Status Bit (0) RCVR FIFO Reset +2 Interrupt Status Register (Read Only) UART FIFO Control Register (Write Only) UART Control Register ISR 0 0 FIFOs Enabled ** FIFOs Enabled ** RX Interrupt Active Level (MSB) Baudrate Divisor Latch Access Bit (BDLAB) 0 +2 UFR Reserved Reversed RX Interrupt Active Level (LSB) Set Silence Enable (SSE) 0 +3 UCR Data Length Select Bit 0 (DLS0) Data Terminal Ready (DTR) Data Length Select Bit 1 (DLS1) Request to Send (RTS) Overrun Error (OER) DSR Toggling (TDSR) Bit 1 Bit 1 Multiple Stop Bits Enable (MSBE) Loopback RI Input Parity Bit Error (PBER) RI Falling Edge (FERI) Bit 2 Bit 2 Parity Bit Enable (PBE) IRQ Enable Even Parity Enable (EPE) Internal Loopback Enable Silent Byte Detected (SBD) Clear to Send (CTS) Bit 4 Bit 4 Parity Bit Fixed Enable PBFE) 0 +4 Handshake Control Register HCR +5 UART Status USR RBR Data Register Ready (RDR) No Stop Bit Error (NSER) DCD Toggling (TDCD) Bit 3 Bit 3 TBR Empty (TBRE) Data Set Ready (DSR) Bit 5 Bit 5 TSR Empty (TSRE) Ring Indicator (RI) Bit 6 Bit 6 RX FIFO Error Indication (RFEI) ** Data Carrier Detect (DCD) Bit 7 Bit 7 +6 Handshake Status Register HSR CTS Toggling (TCTS) Bit 0 Bit 0 +7 +0 User Defined UDR Register Baudrate Low BLL BDLAB = 1 Divisor Latch Baudrate BDLAB = 1 Divisor Latch High +1 BHL Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 *: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode. - 42 - W83977ATF/W83977ATG Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit is reset, an odd number of logic 1's are sent or checked. Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as the transmitter will be detected. Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or received. (1) If MSBE is set to a logical 0, one stop bit is sent and checked. (2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and checked. (3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and checked. Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character. TABLE 6-2 WORD LENGTH DEFINITION DLS1 DLS0 DATA LENGTH 0 0 1 1 0 1 0 1 5 bits 6 bits 7 bits 8 bits 6.2.2 UART Status Register (USR) (Read/Write) This 8-bit register provides information about the status of the data transfer during communication. 7 6 5 4 3 2 1 0 RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in the FIFO. - 43 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In 16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other than in these two cases, this bit will be reset to a logical 0. Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO. Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next received data before they were read by the CPU. In 16550 mode, it indicates the same condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0. Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0. 6.2.3 Handshake Control Register (HCR) (Read/Write) This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART. 7 0 6 0 5 0 4 3 2 1 0 Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable - 44 - W83977ATF/W83977ATG Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as follows: (1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the TSR. (2) Modem output pins are set to their inactive state. (3) Modem input pins are isolated from the communication link and connect internally as DTR (bit 0 of HCR) → DSR , RTS ( bit 1 of HCR) → CTS , Loopback RI input ( bit 2 of HCR) → RI and IRQ enable ( bit 3 of HCR) → DCD . Aside from the above connections, the UART operates normally. This method allows the CPU to test the UART in a convenient way. Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this bit is internally connected to the modem control input DCD . Bit 2: This bit is used only in the diagnostic mode. connected to the modem control input RI . Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS . Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . In the diagnostic mode this bit is internally 6.2.4 Handshake Status Register (HSR) (Read/Write) This register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins. 7 6 5 4 3 2 1 0 CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback mode. Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode. Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback mode. Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback mode. Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU. - 45 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read by the CPU. Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU. Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read. 6.2.5 UART FIFO Control Register (UFR) (Write only) This register is used to control the FIFO functions of the UART. 7 6 5 4 3 2 1 0 FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB) Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO. TABLE 6-3 FIFO TRIGGER LEVEL BIT 7 BIT 6 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 0 0 1 1 Bit 4, 5: Reserved 0 1 0 1 01 04 08 14 Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR bit 0 = 1. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed. - 46 - W83977ATF/W83977ATG 6.2.6 Interrupt Status Register (ISR) (Read only) This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits. 7 6 5 0 4 0 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled 3 2 1 0 Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1. Bit 5, 4: These two bits are always logic 0. Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a timeout interrupt is pending. Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to a logical 0. TABLE 6-4 INTERRUPT CONTROL FUNCTION ISR Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT SET AND FUNCTION Interrupt priority First Second Interrupt Type UART Receive Status RBR Data Ready Interrupt Source No Interrupt pending 1. OER = 1 2. PBER =1 3. NSER = 1 4. SBD = 1 1. RBR data ready 2. FIFO interrupt active level reached Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty Clear Interrupt Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 0 Second FIFO Data Timeout 0 0 1 0 Third TBR Empty 1. Write data into TBR 2. Read ISR (if priority is third) 2. TDSR = 1 4. TDCD = 1 Read HSR 0 0 0 0 Fourth Handshake status 1. TCTS = 1 3. FERI = 1 ** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1. - 47 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 6.2.7 Interrupt Control Register (ICR) (Read/Write) This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1. 7 0 6 0 5 0 4 0 RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) 3 2 1 0 Bit 7-4: These four bits are always logic 0. Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt. Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt. Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt. Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt. 6.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) 16 Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2 -1. The output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. The table in the next page illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed mode, the data transmission rate can be as high as 1.5M bps. - 48 - W83977ATF/W83977ATG 6.2.9 User-defined Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user. TABLE 6-5 BAUD RATE TABLE BAUD RATE FROM DIFFERENT PRE-DIVIDER Pre-Div: 13 1.8461M Hz 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 Pre-Div:1.625 14.769M Hz 400 600 880 1076 1200 2400 4800 9600 14400 16000 19200 28800 38400 57600 76800 153600 307200 460800 921600 Pre-Div: 1.0 24M Hz 650 975 1430 1478.5 1950 3900 7800 15600 23400 26000 31200 46800 62400 93600 124800 249600 499200 748800 1497600 Decimal divisor used to generate 16X clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 Error Percentage between desired and actual ** ** 0.18% 0.099% ** ** ** ** ** 0.53% ** ** ** ** ** ** ** ** ** ** The percentage error for all baud rates, except where indicated otherwise, is 0.16%. Note. Pre-Divisor is determined by CRF0 of UART A and B. - 49 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 7. INFRARED (IR) PORT The Infrared (IR) function provides a point-to-point (or multi-point to multi-point) wireless communication which can operate under various transmission protocols including IrDA 1.0 SIR, IrDA 1.1 MIR (1.152 Mbps), IrDA 1.1 FIR (4 Mbps), SHARP ASK-IR, and remote control (NEC, RC-5, advanced RC-5, and RECS-80 protocol). 7.1 IR Register Description When bank select enable bit (ENBNKSEL, the bit 0 in CRF0 of logic device 6) is set, legacy IR will be switched to Advanced IR, and eight Register Sets can then be accessible. These Register Sets control enhanced IR, SIR, MIR, or FIR. Also, a superior traditional SIR function can be used with enhanced features such as 32-byte transmitter/receiver FIFOs, non-encoding IRQ identify status register, and automatic flow control. The MIR/FIR and remote control registers are also defined in these Register Sets. Structure of these Register Sets is as shown below. Reg 7 Reg 6 Reg 5 Reg 4 BDL/SSR Reg 2 Reg 1 Reg 0 Set 0 Set 1 Set 2 Set 3 Set 4 Set 5 Set 6 Set 7 All in one Reg to Select SSR *Set 0, 1 are legacy/Advanced UART Registers *Set 2~7 are Advanced UART Registers Each of these register sets has a common register, namely Sets Select Register (SSR), in order to switch to another register set. The summary description of these Sets is given below. - 50 - W83977ATF/W83977ATG SET SETS DESCRIPTION 0 1 2 3 4 5 6 7 Legacy/Advanced IR Control and Status Registers. Legacy Baud Rate Divisor Register. Advanced IR Control and Status Registers. Version ID and Mapped Control Registers. Transmitter/Receiver/Timer Counter Registers and IR Control Registers. Flow Control and IR Control and Frame Status FIFO Registers. IR Physical Layer Control Registers Remote Control and IR front-end Module Selection Registers. 7.2 Set0-Legacy/Advanced IR Control and Status Registers ADDRESS OFFSET REGISTER NAME REGISTER DESCRIPTION 0 1 2 3 4 5 6 7 RBR/TBR ICR ISR/UFR UCR/SSR HCR USR HSR UDR/ESCR Receiver/Transmitter Buffer Registers Interrupt Control Register Interrupt Status or IR FIFO Control Register IR Control or Sets Select Register Handshake Control Register IR Status Register Handshake Status Register User Defined Register 7.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) Receiver Buffer Register is read only and Transmitter Buffer Register is write only. When operating in the PIO mode, the port is used to Receive/Transmit 8-bit data. When function as a legacy IR, this port only supports PIO mode. If set in the advanced IR mode and configured as MIR/FIR/Remote IR, this port can support DMA transmission. Two DMA channels can be used simultaneously, one for TX DMA and the other for RX DMA. Therefore, single DMA channel is also supported when the bit of D_CHSW (DMA Channel Swap, in Set2.Reg2.Bit3) is set and the TX/RX DMA channel is swapped. Note that two DMA channels can be defined in configure register CR2A, which selects DMA channel or disables DMA channel. If only RX DMA channel is enabled while TX DMA channel is disabled, then the single DMA channel will be selected. - 51 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 7.2.2 Set0.Reg1 - Interrupt Control Register (ICR) B7 0 ETMRI MODE Legacy IR Advanced IR B6 0 EFSFI B5 0 ETXTHI B4 0 EDMAI B3 0 0 B2 EUSRI EUSRI/ TXURI B1 ETBREI ETBREI B0 ERDRI ERBRI The advanced IR functions including Advanced SIR/ASK-IR, MIR, FIR, or Remote IR are described below. Bit 7: Legacy IR Mode: Not used. A read will return 0. Advanced IR Mode: ETMRI - Enable Timer Interrupt A write to 1 will enable timer interrupt. Bit 6: Legacy IR Mode: Not used. A read will return 0. MIR, FIR mode: EFSFI - Enable Frame Status FIFO Interrupt A write to 1 will enable frame status FIFO interrupt. Advanced SIR/ASK-IR, Remote IR: Not used. Bit 5: Legacy IR Mode: Not used. A read will return 0. Advanced SIR/ASK-IR, MIR, FIR, Remote IR: ETXTHI - Enable Transmitter Threshold Interrupt A write to 1 will enable transmitter threshold interrupt. Bit 4: Legacy IR Mode: Not used. A read will return 0. MIR, FIR, Remote IR: EDMAI - Enable DMA Interrupt. A write to 1 will enable DMA interrupt. Bit 3: Reserved. A read will return 0. - 52 - W83977ATF/W83977ATG Bit 2: Legacy IR Mode: EUSRI - Enable USR (IR Status Register) Interrupt A write to 1 will enable IR status register interrupt. Advanced SIR/ASK-IR: EUSRI - Enable USR (IR Status Register) Interrupt A write to 1 will enable IR status register interrupt. MIR, FIR, Remote Controller: EHSRI/ETXURI - Enable USR Interrupt or Enable Transmitter Underrun Interrupt A write to 1 will enable USR interrupt or enable transmitter underrun interrupt. Bit 1: Bit 0: ETBREI - Enable TBR (Transmitter Buffer Register) Empty Interrupt A write to 1 will enable the transmitter buffer register empty interrupt. ERBRI - Enable RBR (Receiver Buffer Register) Interrupt A write to 1 will enable receiver buffer register interrupt. 7.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR) Interrupt Status Register (Read Only) MODE Legacy IR Advanced IR Reset Value B7 FIFO Enable TMR_I 0 B6 FIFO Enable FSF_I 0 B5 0 TXTH_I 1 B4 0 DMA_I 0 B3 IID2 HS_I 0 B2 IID1 USR_I/ FEND_I 0 B1 IID0 TXEMP_I 1 B0 IP RXTH_I 0 Legacy IR: This register reflects the Legacy IR interrupt status, which is encoded by different interrupt sources into 3 bits. Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1. Bit 5, 4: These two bits are always logical 0. Bit 3: When not in FIFO mode, this bit is always 0. In FIFO mode, both bit 3 and 2 are set to logical 1 when a time-out interrupt is pending. Bit 2, 1: These bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to logical 0. - 53 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG TABLE: INTERRUPT CONTROL FUNCTION ISR Bit 3 0 0 0 Bit 2 0 1 1 Bit 1 0 1 0 Bit 0 1 0 0 First Second Interrupt priority - INTERRUPT SET AND FUNCTION Interrupt Type IR Receive Status RBR Data Ready FIFO Data Time-out Interrupt Source No Interrupt pending 1. OER = 1 2. PBER =1 3. NSER = 1 4. SBD = 1 1. RBR data ready 2. FIFO interrupt active level reached Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR Clear Interrupt - 1 1 0 0 Second 0 0 1 0 Third TBR Empty 1. Write data into TBR 2. Read ISR (if priority is third) ** Bit 3 of ISR is enabled when bit 0 of UFR is a logical 1. Advanced IR: Bit 7: TMR_I - Timer Interrupt. Set to 1 when timer counts to logical 0. This bit is valid when: (1) the timer registers are defined in Set4.Reg0 and Set4.Reg1; (2) EN_TMR(Enable Timer, in Set4.Reg2.Bit0) is set to 1; (3) ENTMR_I (Enable Timer Interrupt, in Set0.Reg1.Bit7) is set to 1. Bit 6: MIR, FIR modes: FSF_I - Frame Status FIFO Interrupt. Set to 1 when Frame Status FIFO is equal or larger than the threshold level or Frame Status FIFO time-out occurs. Cleared to 0 when Frame Status FIFO is below the threshold level. Advanced SIR/ASK-IR, Remote IR modes: Not used. Bit 5: TXTH_I - Transmitter Threshold Interrupt. Set to 1 if the TBR (Transmitter Buffer Register) FIFO is below the threshold level. Cleared to 0 if the TBR (Transmitter Buffer Register) FIFO is above the threshold level. Bit 4: MIR, FIR, Remote IR Modes: DMA_I - DMA Interrupt. Set to 1 if the DMA controller 8237A sends a TC (Terminal Count) to I/O device which might be a Transmitter TC or a Receiver TC. Cleared to 0 when this register is read. Bit 3: HS_I - Handshake Status Interrupt. Set to 1 when the Handshake Status Register has a toggle. Cleared to 0 when Handshake Status Register (HSR) is read. Note that in all IR modes including SIR, ASKIR, MIR, FIR, and Remote Control IR, this bit defaults to be inactive unless IR Handshake Status Enable (IRHS_EN) is set to 1. - 54 - W83977ATF/W83977ATG Bit 2: Advanced SIR/ASK-IR modes: USR_I - IR Status Interrupt. Set to 1 when overrun error, parity error, stop bit error, or silent byte error is detected and registered in the IR Status Register (USR). Cleared to 0 when USR is read. MIR, FIR modes: FEND_I - Frame End Interrupt. Set to 1 when (1) a frame has a grace end to be detected where the frame signal is defined in the physical layer of IrDA version 1.1; (2) abort signal or illegal signal has been detected during receiving valid data. Cleared to 0 when this register is read. Remote Controller Mode: Not used. Bit 1: TXEMP_I - Transmitter Empty. Set to 1 when transmitter (or, say, FIFO + Transmitter) is empty. Cleared to 0 when this register is read. Bit 0: RXTH_I - Receiver Threshold Interrupt. Set to 1 when (1) the Receiver Buffer Register (RBR) is equal or larger than the threshold level; or (2) RBR time-out occurs if the receiver buffer register has valid data and is below the threshold level. Cleared to 0 when RBR is less than threshold level after reading RBR. IR FIFO Control Register (UFR): MODE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Legacy IR RXFTL1 (MSB) Advanced RXFTL1 IR (MSB) Reset Value RXFTL0 (LSB) RXFTL0 (LSB) 0 0 TXFTL1 (MSB) 0 0 TXFTL0 (LSB) 0 0 0 0 TXF_RST RXF_RST EN_FIFO TXF_RST RXF_RST EN_FIFO 0 0 0 0 Legacy IR: This register is used to control FIFO functions of the IR. Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes and there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify CPU to read the data from FIFO. - 55 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG TABLE: FIFO TRIGGER LEVEL BIT 7 BIT 6 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 0 0 1 1 Bit 4, 5: Reserved 0 1 0 1 01 04 08 14 Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR bit 0 = 1. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to its initial state. This bit will be cleared to logical 0 by itself after being set to logical 1. Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit will be cleared to a logical 0 by itself after being set to logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the IR. This bit should be set to logical 1 before other bits of UFR can be programmed. Advanced IR: Bit 7, 6: RXFTL1, 0 - Receiver FIFO Threshold Level Its definition is the same as Legacy IR. RXTH_I becomes 1 when the Receiver FIFO Threshold Level is equal to or larger than the defined value shown as follow. RXFTL1, 0 (BIT 7, 6) RX FIFO THRESHOLD LEVEL (FIFO SIZE: 16-BYTE) RX FIFO THRESHOLD LEVEL (FIFO SIZE: 32-BYTE) 00 01 10 11 1 4 8 14 1 4 16 26 Note that the FIFO Size is selectable in SET2.Reg4. Bit 5, 4: TXFTL1, 0 - Transmitter FIFO Threshold Level TXTH_I (Transmitter Threshold Level Interrupt) is set to 1 when the Transmitter Threshold Level is less than the programmed value shown below. - 56 - W83977ATF/W83977ATG TXFTL1, 0 (BIT 5, 4) TX FIFO THRESHOLD LEVEL (FIFO SIZE: 16-BYTE) TX FIFO THRESHOLD LEVEL (FIFO SIZE: 32-BYTE) 00 01 10 11 Bit 3 ~0 Same as in Legacy IR Mode 1 3 9 13 1 7 17 25 7.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): These two registers share the same address. In all Register Sets, Set Select Register (SSR) can be programmed to select a desired Set, but IR Control Register can only be programmed in Set 0 and Set 1. In other words, writing to Reg3 in Sets other than Set 0 and Set 1 will not affect IR Control Register. The mapping of entry Set and programming value is shown below. SSR BITS SELECTED 7 0 1 1 1 1 1 1 1 6 ¡Ñ 5 ¡Ñ 4 ¡Ñ 3 ¡Ñ 2 ¡Ñ 1 ¡Ñ 0 ¡Ñ Hex Value ¡Ð ¡Ð Set Set 0 Set1 Set 2 Set 3 Set 4 Set 5 Set 6 Set 7 Any combination except those used in SET 2~7 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 7.2.5 Set0.Reg4 - Handshake Control Register (HCR) B7 B6 B5 B4 B3 B2 B1 B0 MODE Legacy IR Reset Value 0 0 0 1 0 1 XLOOP 0 EN_IRQ TX_WT 0 0 EN_DMA 0 0 0 0 0 0 0 Advanced IR AD_MD2 AD_MD1 AD_MD0 SIR_PLS - 57 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Legacy IR Register: This register controls the pins of IR used for handshaking with peripherals such as modem, and controls the diagnostic mode of IR. Bit 4: When this bit is set to logical 1, the legacy IR enters diagnostic mode by an internal loopback: IRTX is forced to logical 0, and IRRX is isolated from the communication link instead of the TSR. Bit 3: The legacy IR interrupt output is enabled by setting this bit to logic 1. Advanced IR Register: Bit 7~5 Advanced SIR/ASK-IR, MIR, FIR, Remote Controller Modes: AD_MD2~0 - Advanced IR/Infrared Mode Select. These registers are active when Advanced IR Select (ADV_SL, in Set2.Reg2.Bit0) is set to 1. Operational mode selection is defined as follows. When backward operation occurs, these registers will be reset to 0 and fall back to legacy IR mode. AD_MD2~0 (BIT 7, 6, 5) SELECTED MODE 000 001 010 011 100 101 110 111 Bit 4: Reserved Low speed MIR (0.576M bps) Advanced ASK-IR Advanced SIR High Speed MIR (1.152M bps) FIR (4M bps) Consumer IR Reserved Bit 3: MIR, FIR Modes: SIR_PLS - Send Infrared Pulse Writing 1 to this bit will send a 2 μ s long infrared pulse after physical frame end. This is to signal to SIR that the high speed infrared is still in. This bit will be auto cleared by hardware. Other Modes: Not used. MIR, FIR modes: TX_WT - Transmission Waiting If this bit is set to 1, the transmitter will wait for TX FIFO to reach threshold level or transmitter time-out before it begins to transmit data; this prevents short queues of data bytes from transmitting prematurely. This is to avoid Underrun. Other Modes: Not used. - 58 - W83977ATF/W83977ATG Bit 2: MIR, FIR modes: EN_DMA - Enable DMA Enable DMA function for transmitting or receiving. Before using this, the DMA channel should be selected first. If only RX DMA channel is set and TX DMA channel is disabled, then the single DMA channel is used. In the single channel system, the bit of D_CHSW (DMA channel swap, in Set 2.Reg2.Bit3) will determine if it is RX_DMA or TX_DMA channel. Other modes: Not used. Bit 1, 0: RTS, DTR Functional definitions are the same as in legacy IR mode. 7.2.6 Set0.Reg5 - IR Status Register (USR) B7 RFEI LB_INFR 0 MODE Legacy IR Advanced IR Reset Value B6 TSRE TSRE 0 B5 TBRE TBRE 0 B4 SBD MX_LEX 0 B3 NSER PHY_ERR 0 B2 PBER CRC_ERR 0 B1 OER OER 0 B0 RDR RDR 0 Legacy IR Register: These registers are defined the same as previous description. Advanced IR Register: MIR, FIR Modes: LB_INFR - Last Byte In Frame End Set to 1 when last byte of a frame is in the bottom of FIFO. This bit separates one frame from another when RX FIFO has more than one frame. Bit 6, 5: Same as legacy IR description. Bit 4: MIR, FIR modes: MX_LEX - Maximum Frame Length Exceed Set to 1 when the length of a frame from the receiver has exceeded the programmed frame length defined in SET4.Reg6 and Reg5. If this bit is set to 1, the receiver will not receive any data to RX FIFO. Bit 3: MIR, FIR modes: PHY_ERR - Physical Layer Error Set to 1 when an illegal data symbol is received. The illegal data symbol is defined in physical layer of IrDA version 1.1. When this bit is set to 1, the decoder of receiver will be aborted and a frame end signal is set to 1. Bit 2: MIR, FIR Modes: CRC_ERR - CRC Error Set to 1 when an attached CRC is erroneous. Bit 1, 0: OER - Overrun Error, RDR - RBR Data Ready Definitions are the same as legacy IR. Bit 7: - 59 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 7.2.7 7.2.8 Set0.Reg6 - Reserved Set0.Reg7 - User Defined Register (UDR/AUDR) BIT 7 Bit 7 FLC_ACT 0 MODE Legacy IR Advanced IR Reset Value BIT 6 Bit 6 UNDRN 0 BIT 5 Bit 5 RX_BSY/ RX_IP 0 BIT 4 Bit 4 LST_FE/ RX_PD 0 BIT 3 Bit 3 S_FEND 0 BIT 2 Bit 2 0 0 BIT 1 Bit 1 LB_SF 0 BIT 0 Bit 0 RX_TO 0 Legacy IR Register: This is a temporary register that can be accessed and defined by the user. Advanced IR Register: Bit 7 MIR, FIR Modes: FLC_ACT - Flow Control Active Set to 1 when the flow control occurs. Cleared to 0 when this register is read. Note that this will be affected by Set5.Reg2 which controls the SIR mode switches to MIR/FIR mode or MIR/FIR mode operated in DMA function switches to SIR mode. Bit 6 MIR, FIR Modes: UNDRN - Underrun Set to 1 when transmitter is empty and S_FEND (bit 3 of this register) is not set in PIO mode or no TC (Terminal Count) in DMA mode. Cleared to 0 after a write to 1. Bit 5 MIR, FIR Modes: RX_BSY - Receiver Busy Set to 1 when receiver is busy or active in process. Remote IR mode: RX_IP - Receiver in Process Set to 1 when receiver is in process. Bit 4: MIR, FIR modes: LST_FE - Lost Frame End Set to 1 when a frame end in a entire frame is lost. Cleared to 0 when this register is read. Remote IR Modes: RX_PD - Receiver Pulse Detected Set to 1 when one or more remote pulses are detected. Cleared to 0 when this register is read. Bit 3 MIR, FIR Modes: S_FEND - Set a Frame End Set to 1 when trying to terminate the frame, that is, the procedure od PIO command is An Entire Frame = Write Frame Data (First) + Write S_FEND (Last) This bit should be set to 1, if used in PIO mode, to avoid transmitter underrun. Note that setting S_FEND to 1 is equivalent to TC (Terminal Count) in DMA mode. Therefore, this bit should be set to 0 in DMA mode. Bit 2: Reserved. - 60 - W83977ATF/W83977ATG Bit 1: Bit 0: MIR, FIR Modes: LB_SF - Last Byte Stay in FIFO A 1 in this bit indicates one or more frame ends remain in receiver FIFO. MIR, FIR, Remote IR Modes: RX_TO - Receiver FIFO or Frame Status FIFO time-out Set to 1 when receiver FIFO or frame status FIFO time-out occurs 7.3 Set1 - Legacy Baud Rate Divisor Register REGISTER NAME BLL BHL ISR/UFR UCR/SSR HCR USR HSR UDR/ESCR ADDRESS OFFSET 0 1 2 3 4 5 6 7 REGISTER DESCRIPTION Baud Rate Divisor Latch (Low Byte) Baud Rate Divisor Latch (High Byte) Interrupt Status or IR FIFO Control Register IR Control or Sets Select Register Handshake Control Register IR Status Register Handshake Status Register User Defined Register 7.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) These two registers of BLL and BHL are baud rate divisor latch in the legacy SIR/ASK-IR mode. Accessing these registers in Advanced IR mode will cause backward operation, that is, UART will fall back to legacy SIR mode and clear some register values as shown in the following table. SET & REGISTER ADVANCED MODE DIS_BACK=¡Ñ LEGACY MODE DIS_BACK=0 Set 0.Reg 4 Set 2.Reg 2 Set 4.Reg 3 Bit 7~5 Bit 0, 5, 7 Bit 2, 3 Bit 5, 7 - Note that DIS_BACK=1 (Disable Backward operation) in legacy SIR/ASK-IR mode will not affect any register which is meaningful in legacy SIR/ASK-IR. 7.3.2 Set1.Reg 2~7 These registers are defined the same as Set 0 registers. - 61 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 7.4 Set2 - Interrupt Status or IR FIFO Control Register (ISR/UFR) REGISTER NAME REGISTER DESCRIPTION These registers are only used in advanced modes. ADDRESS OFFSET 0 1 2 3 4 5 6 7 ABLL ABHL ADCR1 SSR ADCR2 Reserved TXFDTH RXFDTH Advanced Baud Rate Divisor Latch (Low Byte) Advanced Baud Rate Divisor Latch (High Byte) Advanced IR Control Register 1 Sets Select Register Advanced IR Control Register 2 Transmitter FIFO Depth Receiver FIFO Depth 7.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) These two registers are the same as legacy IR baud rate divisor latch in SET 1.Reg0~1. In advanced SIR/ASK-IR mode, the user should program these registers to set baud rate. This is to prevent backward operations from occurring. 7.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1) BIT 7 BR_OUT 0 MODE Advanced IR Reset Value BIT 6 0 BIT 5 EN_LOUT 0 BIT 4 ALOOP 0 BIT 3 D_CHSW 0 BIT 2 DMATHL 0 BIT 1 DMA_F 0 BIT 0 ADV_SL 0 Bit 7: BR_OUT - Baud Rate Clock Output When written to 1, the programmed baud rate clock will be output to DTR pin. This bit is only used to test baud rate divisor. Bit 6: Bit 5: Reserved, write 0. EN_LOUT - Enable Loopback Output A write to 1 will enable transmitter to output data to IRTX pin when loopback operation occurs. Internal data can be verified through an output pin by setting this bit. - 62 - W83977ATF/W83977ATG Bit 4: Bit 3: ALOOP - All Mode Loopback A write to 1 will enable loopback in all modes. D_CHSW - DMA TX/RX Channel Swap If only one DMA channel operates in MIR/FIR mode, then the DMA channel can be swapped. D_CHSW 0 1 DMA Channel Selected Receiver (Default) Transmitter A write to 1 will enable output data when ALOOP=1. Bit 2: DMATHL - DMA Threshold Level Set DMA threshold level as shown in the following table. DMATHL TX FIFO THRESHOLD 16-BYTE 32-BYTE RX FIFO THRESHOLD (16/32-BYTE) 0 1 Bit 1: DMA_F - DMA Fairness DMA_F 0 1 Bit 0: 13 23 13 7 4 10 Function Description DMA request (DREQ) is forced inactive after 10.5us No effect DMA request. ADV_SL - Advanced Mode Select A write to 1 selects advanced mode. 7.4.3 Reg3 - Sets Select Register (SSR) BIT 7 SSR7 1 Reading this register returns E0H. Writing a value selects Register Set. REG. SSR Refault Value BIT 6 SSR6 1 BIT 5 SSR5 1 BIT 4 SSR4 0 BIT 3 SSR3 0 BIT 2 SSR2 0 BIT 1 SRR1 0 BIT 0 SRR0 0 - 63 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 7.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2) BIT 7 DIS_BACK 0 MODE Advanced IR Reset Value BIT 6 0 BIT 5 PR_DIV1 0 BIT 4 PR_DIV0 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 TXFSZ0 0 RX_FSZ1 RX_FSZ0 TX_FSZ1 Bit 7: DIS_BACK - Disable Backward Operation A write to 1 disables backward legacy IR mode. When operating in legacy SIR/ASK-IR mode, this bit should be set to 1 to avoid backward operation. Bit 6: Bit 5, 4: Reserved, write 0. PR_DIV1~0 - Pre-Divisor 1~0. These bits select pre-divisor for external input clock 24M Hz. The clock goes through the pre-divisor, then input to baud rate divisor of IR. PR_DIV1~0 00 01 10 11 PRE-DIVISOR 13.0 1.625 6.5 1 MAX. BAUD RATE 115.2K bps 921.6K bps 230.4K bps 1.5M bps Bit 3, 2: RX_FSZ1~0 - Receiver FIFO Size 1~0 These bits setup receiver FIFO size when FIFO is enable. RX_FSZ1~0 00 01 1X RX FIFO SIZE 16-Byte 32-Byte Reserved Bit 1, 0: TX_FSZ1~0 - Transmitter FIFO Size 1~0 These bits setup transmitter FIFO size when FIFO is enable. TX_FSZ1~0 00 01 1X TX FIFO SIZE 16-Byte 32-Byte Reserved - 64 - W83977ATF/W83977ATG TABLE: SIR Baud Rate BAUD RATE FROM DIFFERENT PRE-DIVIDER Pre-Div: 13 1.8461M Hz 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 Pre-Div:1.625 14.769M Hz 400 600 880 1076 1200 2400 4800 9600 14400 16000 19200 28800 38400 57600 76800 153600 307200 460800 921600 Pre-Div: 1.0 24M Hz 650 975 1430 1478.5 1950 3900 7800 15600 23400 26000 31200 46800 62400 93600 124800 249600 499200 748800 1497600 Decimal divisor used to generate 16X clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 Error Percentage between desired and actual ** ** 0.18% 0.099% ** ** ** ** ** 0.53% ** ** ** ** ** ** ** ** ** ** The percentage error for all baud rates, except where indicated otherwise, is 0.16%. 7.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only) BIT 7 0 0 MODE Advanced IR Reset Value BIT 6 0 0 BIT 5 TXFD5 0 BIT 4 TXFD4 0 BIT 3 TXFD3 0 BIT 2 TXFD2 0 BIT 1 TXFD1 0 BIT 0 TXFD1 0 Bit 7~6: Bit 5~0: Reserved, Read 0. Reading these bits returns the current transmitter FIFO depth, that is, the number of bytes left in the transmitter FIFO. - 65 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 7.4.6 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MODE Advanced IR Reset Value 0 0 0 0 RXFD5 0 RXFD4 0 RXFD3 0 RXFD2 0 RXFD1 0 RXFD1 0 Bit 7~6: Bit 5~0: Reserved, Read 0. Reading these bits returns the current receiver FIFO depth, that is, the number of bytes left in the receiver FIFO. 7.5 Set3 - Version ID and Mapped Control Registers ADDRESS OFFSET 0 1 2 3 4 5 6 7 REGISTER NAME AUID MP_UCR MP_UFR SSR Reversed Reserved Reserved Reserved REGISTER DESCRIPTION Advanced IR ID Mapped IR Control Register Mapped IR FIFO Control Register Sets Select Register - 7.5.1 Reg0 - Advanced IR ID (AUID) BIT 7 SSR7 0 This register is read only. It stores advanced IR version ID. Reading it returns 1XH. REG. SSR Default Value BIT 6 SSR6 0 BIT 5 SSR5 0 BIT 4 SSR4 1 BIT 3 SSR3 X BIT 2 SSR2 X BIT 1 SRR1 X BIT 0 SRR0 X 7.5.2 Reg1 - Mapped IR Control Register (MP_UCR) BIT 7 SSR7 0 This register is read only. Reading this register returns IR Control Register value of Set 0. REG. SSR Default Value BIT 6 SSR6 0 BIT 5 SSR5 0 BIT 4 SSR4 0 BIT 3 SSR3 0 BIT 2 SSR2 0 BIT 1 SRR1 0 BIT 0 SRR0 0 - 66 - W83977ATF/W83977ATG 7.5.3 0. Reg2 - Mapped IR FIFO Control Register (MP_UFR) This register is read only. Reading this register returns IR FIFO Control Register (UFR) value of SET REG. SSR Default Value BIT 7 SSR7 0 BIT 6 SSR6 0 BIT 5 SSR5 0 BIT 4 SSR4 0 BIT 3 SSR3 0 BIT 2 SSR2 0 BIT 1 SRR1 0 BIT 0 SRR0 0 7.5.4 Reg3 - Sets Select Register (SSR) BIT 7 SSR7 1 Reading this register returns E4H. Writing a value selects a Register Set. REG. SSR Default Value BIT 6 SSR6 1 BIT 5 SSR5 1 BIT 4 SSR4 0 BIT 3 SSR3 0 BIT 2 SSR2 1 BIT 1 SRR1 0 BIT 0 SRR0 0 7.6 Set4 - TX/RX/Timer counter registers and IR control registers. ADDRESS OFFSET 0 1 2 3 4 5 6 7 REGISTER NAME TMRL TMRH IR_MSL SSR TFRLL TFRLH RFRLL RFRLH REGISTER DESCRIPTION Timer Value Low Byte Timer Value High Byte Infrared Mode Select Sets Select Register Transmitter Frame Length Low Byte Transmitter Frame Length High Byte Receiver Frame Length Low Byte Receiver Frame Length High Byte 7.6.1 Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH) This is a 12-bit timer whose resolution is 1ms, that is, the maximum programmable time is 212-1 ms. The timer is a down-counter and starts counting down when EN_TMR (Enable Timer) of Set4.Reg2 is set to 1. When the timer counts down to zero and EN_TMR=1, the TMR_I is set to 1 and a new initial value will be loaded into counter. 7.6.2 Set4.Reg2 - Infrared Mode Select (IR_MSL) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MODE Advanced IR Reset Value 0 0 0 0 IR_MSL1 0 IR_MSL0 0 TMR_TST 0 EN_TMR 0 - 67 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Bit 7~4: Reserved, write to 0. Bit 3, 2: IR_MSL1, 0 - Infrared Mode Select Select legacy IR, SIR, or ASK-IR mode. Note that in legacy SIR/ASK-IR user should set DIS_BACK=1 to avoid backward when programming baud rate. IR_MSL1, 0 00 01 10 11 OPERATION MODE SELECTED Legacy IR CIR Legacy ASK-IR Legacy SIR Bit 1: TMR_TST - Timer Test When set to 1, reading the TMRL/TMRH returns the programmed values of TMRL/TMRH instead of the value of down counter. This bit is for testing timer register. Bit 0: EN_TMR - Enable Timer A write to 1 will enable the timer. 7.6.3 Set4.Reg3 - Set Select Register (SSR) BIT 7 SSR7 1 Reading this register returns E8H. Writing this register selects Register Set. REG. SSR Default Value BIT 6 SSR6 1 BIT 5 SSR5 1 BIT 4 SSR4 1 BIT 3 SSR3 1 BIT 2 SSR2 0 BIT 1 SRR1 0 BIT 0 SRR0 0 7.6.4 Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH) REG. BIT 7 bit 7 0 - BIT 6 bit 6 0 - BIT 5 bit 5 0 - BIT 4 bit 4 0 bit 12 0 BIT 3 bit3 0 bit 11 0 BIT 2 bit 2 0 bit 10 0 BIT 1 bit 1 0 bit 9 0 BIT 0 bit 0 0 bit 8 0 TFRLL Reset Value TFRLH Reset Value These are combined to be a 13-bit register. Writing these registers programs the transmitter frame length of a package. These registers are only valid when APM=1 (automatic package mode, Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame length if the transmitted data is larger than the programmed frame length. When these registers are read, they will return the number of bytes which is not transmitted from a frame length programmed. - 68 - W83977ATF/W83977ATG 7.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH) REG. RFRLL Reset Value RFRLH Reset Value BIT 7 bit 7 0 - BIT 6 bit 6 0 - BIT 5 bit 5 0 - BIT 4 bit 4 0 bit 12 0 BIT 3 bit 3 0 bit 11 0 BIT 2 bit 2 0 bit 10 0 BIT 1 bit 1 0 bit 9 0 BIT 0 bit 0 0 bit 8 0 These are combined to be a 13-bit register and up counter. The length of receiver frame will be limited to the programmed frame length. If the received frame length is larger than the programmed receiver frame length, the bit of MX_LEX (Maximum Length Exceed) will be set to 1. Simultaneously, the receiver will not receive any more data to RX FIFO until the next start flag of the next frame, which is defined in the physical layer IrDA 1.1. Reading these registers returns the number of received data bytes of a frame from the receiver. 7.7 Set 5 - Flow control and IR control and Frame Status FIFO registers ADDRESS OFFSET 0 1 2 3 4 5 6 7 REGISTER NAME FCBLL FCBHL FC_MD SSR IRCFG1 FS_FO RFRLFL RFRLFH REGISTER DESCRIPTION Flow Control Baud Rate Divisor Latch Register (Low Byte) Flow Control Baud Rate Divisor Latch Register (High Byte) Flow Control Mode Operation Sets Select Register Infrared Configure Register Frame Status FIFO Register Receiver Frame Length FIFO Low Byte Receiver Frame Length FIFO High Byte 7.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL) If flow control is enforced when UART switches mode from MIR/FIR to SIR, then the pre-programmed baud rate of FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL). 7.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD) BIT 7 FC_MD2 0 These registers control flow control mode operation as shown in the following table. REG. FC_MD Reset Value BIT 6 FC_MD1 0 BIT 5 FC_MD0 0 BIT 4 0 BIT 3 FC_DSW 0 BIT 2 EN_FD 0 BIT 1 EN_BRFC 0 BIT 0 EN_FC 0 - 69 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Bit 7~5 FC_MD2 - Flow Control Mode When flow control is enforced, these bits will be loaded into AD_MD2~0 of advanced HSR (Handshake Status Register). These three bits are defined as same as AD_MD2~0. Reserved, write 0. FC_DSW - Flow Control DMA Channel Swap A write to 1 allows user to swap DMA channel for transmitter or receiver when flow control is enforced. FC_DSW 0 1 Next Mode After Flow Control Occurred Receiver Channel Transmitter Channel Bit 4: Bit 3: Bit 2: Bit 1: EN_FD - Enable Flow DMA Control A write to 1 enables UART to use DMA channel when flow control is enforced. EN_BRFC - Enable Baud Rate Flow Control A write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in Set5.Reg1~0) to be loaded into advanced baud rate divisor latch (ADBLL/ADBHL, in Set2.Reg1~0). EN_FC - Enable Flow Control A write to 1 enables flow control function and bit 7~1 of this register. Bit 0: 7.7.3 Set5.Reg3 - Sets Select Register (SSR) BIT 7 SSR7 1 Writing this register selects Register Set. Reading this register returns ECH. REG. SSR Default Value BIT 6 SSR6 1 BIT 5 SSR5 1 BIT 4 SSR4 0 BIT 3 SSR3 1 BIT 2 SSR2 1 BIT 1 SRR1 0 BIT 0 SRR0 0 7.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1) REG. BIT 7 0 BIT 6 FSF_TH 0 BIT 5 FEND_M 0 BIT 4 AUX_RX 0 BIT 3 0 BIT 2 0 BIT 1 IRHSSL 0 BIT 0 IR_FULL 0 IRCFG1 Reset Value Bit 7: Bit 6: Reserved, write 0. FSF_TH - Frame Status FIFO Threshold Set this bit to determine the frame status FIFO threshold level and to generate the FSF_I. The threshold level values are defined as follows. FSF_TH 0 1 STATUS FIFO THRESHOLD LEVEL 2 4 - 70 - W83977ATF/W83977ATG Bit 5: FEND_MD - Frame End Mode A write to 1 enables hardware to split data stream into equal length frame automatically as defined in Set4.Reg4 and Set4.Reg5, i.e., TFRLL/TFRLH. Bit 4: Bit 3~2: Bit 1: AUX_RX - Auxiliary Receiver Pin A write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5) Reserved, write 0. IRHSSL - Infrared Handshake Status Select When set to 0, the HSR (Handshake Status Register) operates the same as defined in IR mode. A write to 1 will disable HSR, and reading HSR returns 30H. Bit 0: IR_FULL - Infrared Full Duplex Operation When set to 0, IR module operates in half duplex. A write to 1 makes IR module operate in full duplex. 7.7.5 Set5.Reg5 - Frame Status FIFO Register (FS_FO) BIT 7 FSFDR 0 This register shows the bottom byte of frame status FIFO. REG. FS_FO Reset Value BIT 6 LST_FR 0 BIT 5 0 BIT 4 MX_LEX 0 BIT 3 0 BIT 2 0 BIT 1 RX_OV 0 BIT 0 FSF_OV 0 PHY_ERR CRC_ERR Bit 7: Bit 6: Bit 5: Bit 4: FSFDR - Frame Status FIFO Data Ready Indicates that a data byte is valid in frame status FIFO bottom. LST_FR - Lost Frame Set to 1 when one or more frames have been lost. Reserved. MX_LEX - Maximum Frame Length Exceed Set to 1 when incoming data exceeds programmed maximum frame length defined in Set4.Reg6 and Set4.Reg7. This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status FIFO Data Ready). Bit 3: PHY_ERR - Physical Error When receiving data, any physical layer error as defined in IrDA 1.1 will set this bit to 1. This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status FIFO Data Ready). Bit 2: CRC_ERR - CRC Error Set to 1 when a bad CRC is received in a frame. This CRC belongs to physical layer as defined in IrDA 1.1. This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status FIFO Data Ready). Bit 1: Bit 0: RX_OV - Received Data Overrun Set to 1 when receiver FIFO overruns. FSF_OV - Frame Status FIFO Overrun Set to 1 When frame status FIFO overruns. - 71 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 7.7.6 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number (LST_NU) REG. RFLFL/ LST_NU Reset Value RFLFH Reset Value BIT 7 Bit 7 0 0 BIT 6 Bit 6 0 0 BIT 5 Bit 5 0 0 BIT 4 Bit 4 0 Bit 12 0 BIT 3 Bit 3 0 Bit 11 0 BIT 2 Bit 2 0 Bit 10 0 BIT 1 Bit 1 0 Bit 9 0 BIT 0 Bit 0 0 Bit 8 0 Receiver Frame Length FIFO (RFLFL/RFLFH): These are combined to be a 13-bit register. Reading these registers returns received byte count for the frame. When read, the register of RFLFH will pop-up another frame status and frame length if FSFDR=1 (Set5.Reg4.Bit7). Lost Frame Number (LST_NU): When LST_FR=1 (Set5.Reg4.Bit6), Reg6 stands for LST_NU which is a 8-bit register holding the number of frames lost in succession. 7.8 Set6 - IR Physical Layer Control Registers REGISTER NAME IR_CFG2 MIR_PW SIR_PW SSR HIR_FNU Reserved Reserved Reserved ADDRESS OFFSET 0 1 2 3 4 5 6 7 REGISTER DESCRIPTION Infrared Configure Register 2 MIR (1.152M bps or 0.576M bps) Pulse Width SIR Pulse Width Sets Select Register High Speed Infrared Flag Number - 7.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2) BIT 7 SHMD_N 0 This register controls ASK-IR, MIR, FIR operations. REG. IR_CFG2 Reset Value BIT 6 SHDM_N 0 BIT 5 FIR_CRC 1 BIT 4 MIR_CRC 0 BIT 3 0 BIT 2 INV_CRC 0 BIT 1 DIS_CRC 0 BIT 0 0 Bit 7: SHMD_N - ASK-IR Modulation Disable SHMD_N 0 1 Modulation Mode IRTX modulate 500K Hz Square Wave Re-rout IRTX - 72 - W83977ATF/W83977ATG Bit 6: SHDM_N - ASK-IR Demodulation Disable SHDM_N 0 1 FIR_CRC - FIR (4M bps) CRC Type FIR_CRC Demodulation Mode Demodulation 500K Hz Re-rout IRRX CRC Type Bit 5: Bit 4: 0 16-bit CRC 1 32-bit CRC Note that the 16/32-bit CRC are defined in IrDA 1.1 physical layer. MIR_CRC - MIR (1.152M/0.576M bps) CRC Type MIR_CRC CRC Type 0 1 16-bit CRC 32-bit CRC Bit 2: Bit 1: Bit 0: INV_CRC - Inverting CRC When set to 1, the CRC is inversely output in physical layer. DIS_CRC - Disable CRC When set to 1, the transmitter does not transmit CRC in physical layer. Reserved, write 1. 7.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width REG. BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 M_PW4 0 BIT 3 M_PW3 1 BIT 2 M_PW2 0 BIT 1 M_PW1 1 BIT 0 M_PW0 0 MIR_PW Reset Value This 5-bit register sets MIR output pulse width. M_PW4~0 MIR PULSE WIDTH (1.152M BPS) MIR OUTPUT WIDTH (0.576M BPS) 00000 00001 00010 ... 0 ns 20.83 ns 41.66 (==20.83*2) ns ... 0 ns 41.66 ns 83.32 (==41.66*2) ns ... k10 ... 20.83*k10 ns ... 41.66*k10 ns ... 11111 645 ns 1290 ns - 73 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 7.8.3 Set6.Reg2 - SIR Pulse Width BIT 7 0 REG. SIR_PW Reset Value BIT 6 0 BIT 5 0 BIT 4 S_PW4 0 BIT 3 S_PW3 0 BIT 2 S_PW2 0 BIT 1 S_PW1 0 BIT 0 S_PW0 0 This 5-bit register sets SIR output pulse width. S_PW4~0 SIR OUTPUT PULSE WIDTH 00000 01101 Others 3/16 bit time of IR 1.6 us 1.6 us 7.8.4 Set6.Reg3 - Set Select Register BIT 7 SSR7 1 Select Register Set by writing a set number to this register. Reading this register returns F0H. REG. SSR Default Value BIT 6 SSR6 1 BIT 5 SSR5 1 BIT 4 SSR4 1 BIT 3 SSR3 0 BIT 2 SSR2 0 BIT 1 SRR1 0 BIT 0 SRR0 0 7.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU) BIT 7 M_FG3 0 REG. HIR_FNU Reset Value BIT 6 M_FG2 0 BIT 5 M_FG1 1 BIT 4 M_FG0 0 BIT 3 F_FL3 1 BIT 2 F_FL2 0 BIT 1 F_FL1 1 BIT 0 F_FL0 0 Bit 7~4: M_FG3~0 - MIR beginning Flag Number These bits define the number of transmitter Start Flag of MIR. Note that the number of MIR start flag should be equal or more than two which is defined in IrDA 1.1 physical layer. The default value is 2. M_FG3~0 0000 0001 0010 0011 0100 0101 0110 0111 BEGINNING FLAG NUMBER Reserved 1 2 (Default) 3 4 5 6 8 M_FG3~0 1000 1001 1010 1011 1100 1101 1110 1111 BEGINNING FLAG NUMBER 10 12 16 20 24 28 32 Reserved - 74 - W83977ATF/W83977ATG Bit 3~0: F_FG3~0 - FIR Beginning Flag Number These bits define the number of transmitter Preamble Flag in FIR. Note that the number of FIR start flag should be equal to sixteen which is defined in IrDA 1.1 physical layer. The default value is 16. M_FG3~0 0000 0001 0010 0011 0100 0101 0110 0111 BEGINNING FLAG NUMBER Reserved 1 2 3 4 5 6 8 M_FG3~0 1000 1001 1010 1011 1100 1101 1110 1111 BEGINNING FLAG NUMBER 10 12 16 (Default) 20 24 28 32 Reserved 7.9 Set7 - Remote control and IR module selection registers REGISTER NAME RIR_RXC RIR_TXC RIR_CFG SSR IRM_SL1 IRM_SL2 IRM_SL3 IRM_CR ADDRESS OFFSET 0 1 2 3 4 5 6 7 REGISTER DESCRIPTION Remote Infrared Receiver Control Remote Infrared Transmitter Control Remote Infrared Config Register Sets Select Register Infrared Module (Front End) Select 1 Infrared Module Select 2 Infrared Module Select 3 Infrared Module Control Register 7.9.1 4.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC) BIT 7 RX_FR2 0 REG. RIR_RXC Default Value BIT 6 RX_FR1 0 BIT 5 RX_FR0 1 BIT 4 RX_FSL4 0 BIT 3 RX_FSL3 1 BIT 2 RX_FSL2 0 BIT 1 RX_FSL1 0 BIT 0 RX_FSL0 1 This register defines frequency range of receiver of remote IR. - 75 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Bit 7~5: RX_FR2~0 - Receiver Frequency Range 2~0. These bits select the input frequency range of the receiver. It is implemented through a band pass filter, i.e., only the input signals whose frequency lies in the range defined in this register will be received. Bit 4~0: RX_FSL4~0 - Receiver Frequency Select 4~0. Selects the operation frequency of receiver. Table: Low Frequency range select of receiver. RX_FR2~0 (LOW FREQUENCY) 001 RX_FSL4~0 00010 00011 00100 00101 00110 00111 01000 01001 01011 01100 01101 01111 10000 10010 10011 10101 10111 11010 11011 11101 Min. 26.1 28.2 29.4 30.0 31.4 32.1 32.8 33.6* 34.4 36.2 37.2 38.2 40.3 41.5 42.8 44.1 45.5 48.7 50.4 54.3 Max. 29.6 32.0 33.3 34.0 35.6 36.4 37.2 38.1* 39.0 41.0 42.1 43.2 45.7 47.1 48.5 50.0 51.6 55.2 57.1 61.5 Min. 24.7 26.7 27.8 28.4 29.6 30.3 31.0 31.7 32.5 34.2 35.1 36.0 38.1 39.2 40.4 41.7 43.0 46.0 47.6 51.3 010 Max. 31.7 34.3 35.7 36.5 38.1 39.0 39.8 40.8 41.8 44.0 45.1 46.3 49.0 50.4 51.9 53.6 55.3 59.1 61.2 65.9 Min. 23.4 25.3 26.3 26.9 28.1 28.7 29.4 30.1 30.8 32.4 33.2 34.1 36.1 37.2 38.3 39.5 40.7 43.6 45.1 48.6 011 Max. 34.2 36.9 38.4 39.3 41.0 42.0 42.9 44.0 45.0 47.3 48.6 49.9 52n.7 54.3 56.0 57.7 59.6 63.7 65.9 71.0 Note that those unassigned combinations are reserved. - 76 - W83977ATF/W83977ATG Table: High Frequency range select of receiver RX_FR2~0 (HIGH FREQUENCY) 001 RX_FSL4~0 00011 01000 01011 Note that those unassigned combinations are reserved. Min. 355.6 380.1 410.3 Max. 457.1 489.8 527.4 Table: SHARP ASK-IR receiver frequency range select. RX_FSL4~0 (SHARP ASK-IR) RX_FR2~0 - 001 480.0* 533.3* 010 457.1 564.7 011 436.4 600.0 100 417.4 640.0 101 400.0 685.6 110 384.0 738.5 Note that those unassigned combinations are reserved. 7.9.2 Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC) BIT 7 TX_PW2 0 REG. RIR_TXC Default Value BIT 6 TX_PW1 1 BIT 5 TX_PW0 1 BIT 4 TX_FSL4 0 BIT 3 TX_FSL3 1 BIT 2 TX_FSL2 0 BIT 1 TX_FSL1 0 BIT 0 TX_FSL0 1 This Register defines the transmitter frequency and pulse width of remote IR. Bit 7~5: TX_PW2~0 - Transmitter Pulse Width 2~ 0. Select the transmission pulse width. TX_PW2~0 LOW FREQUENCY HIGH FREQUENCY 010 011 100 101 Note that those unassigned combinations are reserved. 6 μs 7 μs 9 μs 10.6 μ s 0.7 μ s 0.8 μ s 0.9 μ s 1.0 μ s Bit 4~0: TX_FSL4~0 - Transmitter Frequency Select 4~0. Select the transmission frequency. - 77 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Table: Low frequency selected. TX_FSL4~0 LOW FREQUENCY 00011 00100 ... 11101 Note that those unassigned combinations are reserved. 30K Hz 31K HZ ... 56K Hz Table: High frequency selected. TX_FSL4~0 HIGH FREQUENCY 00011 01000 01011 Note that those unassigned combinations are reserved. 400K Hz 450K Hz 480K Hz 7.9.3 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG) BIT 7 P_PNB 0 REG. RIR_CFG Default Value BIT 6 SMP_M 0 BIT 5 RXCFS 0 BIT 4 0 BIT 3 TX_CFS 0 BIT 2 RX_DM 0 BIT 1 TX_MM1 0 BIT 0 TX_MM0 0 Bit 7: P_PNB: Programming Pulse Number Coding. Write a 1 to select programming pulse number coding. The code format is defined as follows. (Number of bits) - 1 B7 B6 B5 B4 B3 B2 B1 B0 Bit value - 78 - W83977ATF/W83977ATG If the bit value is set to 0, the high pulse will be transmitted/received. If the bit value is set to 1, then no energy will be transmitted/received. Bit 6: SMP_M - Sampling Mode. To select receiver sampling mode. When set to 0 then uses T-period sampling, that the T-period is programmed IR baud rate. When set to 1, programmed baud rate will be used to do oversampling. Bit 5: RXCFS - Receiver Carry Frequency Select RXCFS 0 1 Bit 4: Bit 3: Reserved, write 0. TX_CFS - Transmitter Carry Frequency Select. Select low speed or high speed transmitter carry frequency. TX_FCS 0 1 Bit 2: RX_DM - Receiver Demodulation Mode. RX_DM 0 1 Bit 1~0: Demodulation Mode Enable internal decoder Disable internal decoder Selected Frequency 30K ~ 56K Hz 400K ~ 480K Hz Selected Frequency 30K ~ 56K Hz 400K ~ 480K Hz TX_MM1~0 - Transmitter Modulation Mode 1~0 TX_MM1~0 00 01 10 11 TX Modulation Mode Continuously send pulse for logic 0 8 pulses for logic 0 and no pulse for logic 1. 6 pulses for logic 0 and no pulse for logic 1 Reserved. 7.9.4 Set7.Reg3 - Sets Select Register (SSR) BIT 7 Bit 7 1 REG. SSR Default Value BIT 6 Bit 6 1 BIT 5 Bit 5 1 BIT 4 Bit 4 1 BIT 3 Bit 3 0 BIT 2 Bit 2 1 BIT 1 Bit 1 0 BIT 0 Bit 0 0 Reading this register returns F4H. Select Register Set by writing a set number to this register. - 79 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 7.9.5 Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1) BIT 7 IR_MSP 0 REG. IRM_SL1 Default Value BIT 6 SIR_SL2 0 BIT 5 SIR_SL1 0 BIT 4 SIR_SL0 0 BIT 3 0 BIT 2 AIR_SL2 0 BIT 1 AIR_SL1 0 BIT 0 AIR_SL0 0 Bit 7: IR_MSP - IR Mode Select Pulse When set to 1, the transmitter (IRTX) will send a 64 μs pulse to setup a special IR frontend operational mode. When IR front-end module uses mode select pin (MD) and transmitter IR pulse (IRTX) to switch between high speed IR (such as FIR or MIR) and low speed IR (SIR or ASK-IR), this bit should be used. Bit 6~4: SIR_SL2~0 - SIR (Serial IR) mode select. These bits are used to program the operational mode of the SIR front-end module. These values of SIR_SL2~0 will be automatically loaded to pins of IR_SL2~0, respectively, when (1) AM_FMT=1 (Automatic Format, in Set7.Reg7.Bit7); (2) the mode of Advanced IR is set to SIR (AD_MD2~0, in Set0.Reg4.Bit7~0). Bit 3: Bit 2~0: Reserved, write 0. AIR_SL2~0 - ASK-IR Mode Select. These bits setup the operational mode of ASK-IR front-end module when AM_FMT=1 and AD_MD2~0 are configured to ASK-IR mode. These values will be automatically loaded to IR_SL2~0, respectively. 7.9.6 Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2) BIT 7 0 REG. IRM_SL2 Default Value BIT 6 FIR_SL2 0 BIT 5 FIR_SL1 0 BIT 4 FIR_SL0 0 BIT 3 0 BIT 2 MIR_SL2 0 BIT 1 MIR_SL1 0 BIT 0 MIR_SL0 0 Bit 7: Bit 6~4: Reserved, write 0. FIR_SL2~0 - FIR mode select. These bits setup the operational mode of FIR front-end module when AM_FMT=1 and AD_MD2~0 are configured to FIR mode. These values will be automatically loaded to IR_SL2~0, respectively. Bit 3: Bit 2~0: Reserved, write 0. MIR_SL2~0 - MIR Mode Select. These bits setup the MIR operational mode when AM_FMT=1 and AD_MD2~0 are configured to MIR mode. These values will be automatically loaded to IR_SL2~0, respectively. - 80 - W83977ATF/W83977ATG 7.9.7 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3) BIT 7 0 REG. IRM_SL3 Default Value BIT 6 LRC_SL2 0 BIT 5 LRC_SL1 0 BIT 4 LRC_SL0 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0 HRC_SL2 HRC_SL1 HRC_SL0 Bit 7: Bit 6~4: Reserved, write 0. LRC_SL2~0 - Low Speed Remote IR mode select. These bits setup the operational mode of low speed remote IR front-end module when AM_FMT=1 and AD_MD2~0 are configured to Remote IR mode. These values will be automatically loaded to IR_SL2~0, respectively. Bit 3: Bit 2~0: Reserved, write 0. HRC_SL2~0 - High Speed Remote IR Mode Select. These bits setup the operational mode of high speed remote IR front-end module when AM_FMT=1 and .AD_MD2~0 are configured to Remote IR mode. These values will be automatically loaded to IR_SL2~0, respectively. 7.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR) BIT 7 AM_FMT 0 REG. IRM_CR Default Value BIT 6 IRX_MSL 0 BIT 5 IRSL0D 0 BIT 4 RXINV 0 BIT 3 TXINV 0 BIT 2 0 BIT 1 0 BIT 0 0 Bit 7: Bit 6: Bit 5: AM_FMT - Automatic Format A write to 1 will enable automatic format IR front-end module. These bits will affect the output of IR_SL2~0 which is referred by IR front-end module selection (Set7.Reg4~6) IRX_MSL - IR Receiver Module Select Select the receiver input path from the IR front end module if IR module has a separated high speed and low speed receiver path. If the IR module has only one receiving path, then this bit should be set to 0. IRX_MSL Receiver Pin selected IRRX (Low/High Speed) 0 IRRXH (High Speed) 1 IRSL0D - Direction of IRSL0 Pin Select function for IRRXH or IRSL0 because they share common pin and have different input/output direction. IRSL0_D Function 0 1 IRRXH (I/P) IRSL0 (O/P) - 81 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Table: IR receiver input pin selection IRSL0D 0 0 0 0 1 1 1 1 IRX_MSL 0 0 1 1 0 0 1 1 AUX_RX 0 1 X X 0 1 X X HIGH SPEED IR X X 0 1 X X 0 1 SELECTED IR PIN IRRX IRRXH IRRX IRRXH IRRX Reserved IRRX Reserved Note: that (1) AUX_RX is defined in Set5.Reg4.Bit4, (2) high speed IR includes MIR (1.152M or 0.576M bps) and FIR (4M bps), (3) IRRX is the input of the low speed or high speed IR receiver, IRRXH is the input of the high speed IR receiver. Bit 4: Bit 3: Bit 2~0: RXINV - Receiving Signal Invert A write to 1 will Invert the receiving signal. TXINV - Transmitting Signal Invert A write to 1 will Invert the transmitting signal. Reserved, write 0. - 82 - W83977ATF/W83977ATG 8. PARALLEL PORT 8.1 Printer Interface Logic The parallel port of the W83977ATF/ATG makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. W83977ATF/ATG supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port. Refer to the configuration registers for more information on disabling, power-down, and on selecting the mode of operation. Table 8-1-1 and table 8-1-2 show the pin definitions for different modes of the parallel port. TABLE 8-1-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 Notes: PIN NUMBER OF W83977ATF 36 31-26, 24-23 22 21 19 18 35 34 33 32 PIN ATTRIBUTE O I/O I I I I O I O O SPP EPP ECP nSTB PD nACK BUSY PE SLCT nAFD nERR nINIT nSLIN nWrite PD Intr nWait PE Select nDStrb nError nInit nAStrb nSTB, HostClk2 PD nACK, PeriphClk2 BUSY, PeriphAck2 PEerror, nAckReverse2 SLCT, Xflag2 nAFD, HostAck2 nFault1, nPeriphRequest2 nINIT1, nReverseRqst2 nSLIN1 , ECPMode2 n : Active Low 1. Compatible Mode 2. High Speed Mode 3. For more information, refer to the IEEE 1284 standard. - 83 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG TABLE 8-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR PIN NUMBER OF W83977ATF PIN ATTRIBUTE SPP PIN ATTRIBUTE EXT2FD D PIN ATTRIBUTE EXTFDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 36 31 30 29 28 27 26 24 23 22 21 19 18 35 34 33 32 O I/O I/O I/O I/O I/O I/O I/O I/O I I I I O I O O nSTB PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nAFD nERR nINIT nSLIN --I I I I I --OD OD OD OD OD OD OD OD OD OD --INDEX2 TRAK02 WP2 RDATA 2 DSKCHG2 --I I I I I ------OD OD OD OD OD OD OD OD --INDEX2 TRAK02 WP2 RDATA 2 DSKCHG2 --MOA 2 DSA 2 DSB2 MOB2 WD2 WE2 RWC2 HEAD2 ------DSB2 MOB2 WD2 WE2 RWC2 HEAD2 DIR2 STEP2 DIR2 STEP2 8.2 Enhanced Parallel Port (EPP) A2 A1 A0 REGISTER NOTE TABLE 8-2 PRINTER MODE AND EPP REGISTER ADDRESS 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 1 0 0 1 0 1 0 1 Data port (R/W) Printer status buffer (Read) Printer control latch (Write) Printer control swapper (Read) EPP address port (R/W) EPP data port 0 (R/W) EPP data port 1 (R/W) EPP data port 2 (R/W) EPP data port 2 (R/W) 1 1 1 1 2 2 2 2 2 Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode. - 84 - W83977ATF/W83977ATG 8.2.1 Data Swapper The system microprocessor can read the contents of the printer's data latch by reading the data swapper. 8.2.2 Printer Status Buffer The system microprocessor can read the printer status by reading the address of the printer status buffer. The bit definitions are as follows: 7 6 5 4 3 2 1 1 1 TMOUT ERROR SLCT PE ACK BUSY 0 Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print head is changing position, or during an error state. When this signal is active, the printer is busy and cannot accept data. Bit 6: This bit represents the current state of the printer's ACK signal. A 0 means the printer has received a character and is ready to accept another. Normally, this signal will be active for approximately 5 microseconds before BUSY stops. Bit 5: Logical 1 means the printer has detected the end of paper. Bit 4: Logical 1 means the printer is selected. Bit 3: Logical 0 means the printer has encountered an error condition. Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register. Bit 0: This bit is valid in EPP mode only. It indicates that a 10 μS time-out has occurred on the EPP bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect. - 85 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 8.2.3 Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows: 7 1 6 1 STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR 5 4 3 2 1 0 Bit 7, 6: These two bits are a logic one during a read. They can be written. Bit 5: Direction control bit When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at zero. Bit 4: A 1 in this position allows an interrupt to occur when ACK changes from low to high. Bit 3: A 1 in this bit position selects the printer. Bit 2: A 0 starts the printer (50 microsecond pulse, minimum). Bit 1: A 1 causes the printer to line-feed after a line is printed. Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse. 8.2.4 EPP Address Port 7 6 5 4 3 2 1 0 The address port is available only in EPP mode. Bit definitions are as follows: PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW causes an EPP address write cycle to be performed, and the trailing edge of IOW latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read during a read operation. The leading edge of IOR causes an EPP address read cycle to be performed and the data to be output to the host CPU. - 86 - W83977ATF/W83977ATG 8.2.5 EPP Data Port 0-3 7 6 5 4 3 2 1 0 These four registers are available only in EPP mode. Bit definitions of each data port are as follows: PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW causes an EPP data write cycle to be performed, and the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of IOR causes an EPP read cycle to be performed and the data to be output to the host CPU. 8.2.6 Bit Map of Parallel Port and EPP Registers REGISTER 7 PD7 6 PD6 5 PD5 PE 1 DIR PD5 PD5 PD5 PD5 PD5 4 PD4 SLCT IRQEN IRQ PD4 PD4 PD4 PD4 PD4 3 PD3 2 PD2 1 1 PD1 1 0 PD0 TMOUT Data Port (R/W) Status Buffer (Read) Control Swapper (Read) Control Latch (Write) EPP Address Port R/W) EPP Data Port 0 (R/W) EPP Data Port 1 (R/W) EPP Data Port 2 (R/W) EPP Data Port 3 (R/W) BUSY 1 1 PD7 PD7 PD7 PD7 PD7 ACK 1 1 PD6 PD6 PD6 PD6 PD6 ERROR SLIN SLIN PD3 PD3 PD3 PD3 PD3 INIT INIT PD2 PD2 PD2 PD2 PD2 AUTOFD AUTOFD PD1 PD1 PD1 PD1 PD1 STROBE STROBE PD0 PD0 PD0 PD0 PD0 - 87 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 8.2.7 nWrite PD Intr nWait PE Select nDStrb nError nInits nAStrb EPP Pin Descriptions TYPE O I/O I I I I O I O O EPP NAME EPP DESCRIPTION Denotes an address or data read or write operation. Bi-directional EPP address and data bus. Used by peripheral device to interrupt the host. Inactive to acknowledge that data transfer is completed. Active to indicate that the device is ready for the next transfer. Paper end; same as SPP mode. Printer selected status; same as SPP mode. This signal is active low. It denotes a data read or write operation. Error; same as SPP mode. This signal is active low. When it is active, the EPP device is reset to its initial operating mode. This signal is active low. It denotes an address read or write operation. 8.2.8 EPP Operation When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or address cycle is currently being executed. In this condition all output signals are set by the SPP Control Port and the direction is controlled by DIR of the Control Port. A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 μS have elapsed from the start of the EPP cycle to the time WAIT is deasserted. The current EPP cycle is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0. 8.2.8.1 EPP Operation The EPP operates on a two-phase cycle. First, the host selects the register within the device for subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed asynchronously. 8.2.8.2 EPP Version 1.9 Operation The EPP read/write operation can be completed under the following conditions: a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally and will be completed when nWait goes inactive high. b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to active low, at which time it will start as described above. 8.2.8.3 EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high. - 88 - W83977ATF/W83977ATG 8.3 Extended Capabilities Parallel (ECP) Port This port is software and hardware compatible with existing parallel ports, so it may be used as a standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) directions. Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The ECP port supports run-length-encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. 8.3.1 ECP Register and Mode Definitions NAME ADDRESS Base+000h Base+000h Base+001h Base+002h Base+400h Base+400h Base+400h Base+400h Base+401h Base+402h I/O R/W R/W R R/W R/W R/W R/W R R/W R/W ECP MODES 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr Note: The base addresses are specified by CR60 & CR61, which are determined by configuration register or hardware setting. MODE 000 001 010 011 100 101 110 111 SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode DESCRIPTION EPP mode (If this option is enabled in the CRF0 to select ECP/EPP mode) Reserved Test mode Configuration mode Note: The mode selection bits are bit 7-5 of the Extended Control Register. - 89 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 8.3.2 Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0-PD7 are read and output to the host. The bit definitions are as follows: 7 6 5 4 3 2 1 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Mode 011 (ECP FIFO-Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is defined only for the forward direction. The bit definitions are as follows: 7 6 5 4 3 2 1 0 Address or RLE Address/RLE 8.3.3 Device Status Register (DSR) These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows: 7 6 5 4 3 2 1 1 1 0 1 nFault Select PError nAck nBusy - 90 - W83977ATF/W83977ATG Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logic one during a read. 8.3.4 Device Control Register (DCR) 7 1 6 1 strobe autofd nInit SelectIn ackIntEn Direction 5 4 3 2 1 0 The bit definitions are as follows: Bit 6, 7: These two bits are logic one during a read and cannot be written. Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is valid in all other modes. 0 the parallel port is in output mode. 1 the parallel port is in input mode. Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt requests from the parallel port to the CPU due to a low to high transition on the ACK input. Bit 3: This bit is inverted and output to the SLIN output. 0 The printer is not selected. 1 The printer is selected. Bit 2: This bit is output to the INIT output. Bit 1: This bit is inverted and output to the AFD output. Bit 0: This bit is inverted and output to the STB output. 8.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned. - 91 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 8.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system. 8.3.7 tFifo (Test FIFO Mode) Mode = 110 Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be displayed on the parallel port data lines. 8.3.8 cnfgA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation. 8.3.9 cnfgB (Configuration Register B) Mode = 111 The bit definitions are as follows: 7 6 5 4 3 2 1 1 1 0 1 IRQx 0 IRQx 1 IRQx 2 intrValue compress Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts. - 92 - W83977ATF/W83977ATG Bit 5-3: Reflect the IRQ resource assigned for ECP port. cnfgB[5:3] 000 001 010 011 100 101 110 111 IRQ resource reflect other IRQ resources selected by PnP register (default) IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 IRQ5 Bit 2-0: These five bits are at high level during a read and can be written. 8.3.10 ecr (Extended Control Register) Mode = all This register controls the extended ECP parallel port functions. The bit definitions are follows: 7 6 5 4 3 2 1 0 empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Bit 7-5: These bits are read/write and select the mode. 000 001 Standard Parallel Port mode. The FIFO is reset in this mode. PS/2 Parallel Port mode. This is the same as 000 except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel port protocol. This mode is useful only when direction is 0. ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and auto transmitted to the peripheral using ECP Protocol. When the direction is 1 (reverse direction), bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected. Reserved. Test Mode. The FIFO may be written and read in this mode, but the data will not be transmitted on the parallel port. Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. Publication Release Date: May 2006 Revision 0.6 010 011 100 101 110 111 - 93 - W83977ATF/W83977ATG Bit 4: Read/Write (Valid only in ECP Mode) 1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt), an interrupt will be generated and this bit is written from a 1 to 0. Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally. Bit 2: Read/Write 1 Disables DMA and all of the service interrupts. 0 Enables one of the following cases of interrupts. When one of the service interrupts has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt. (a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached. (b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the FIFO. (c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be read from the FIFO. Bit 1: Read only 0 The FIFO has at least 1 free byte. 1 The FIFO cannot accept another byte or the FIFO is completely full. Bit 0: Read only 0 The FIFO contains at least 1 byte of data. 1 The FIFO is completely empty. 8.3.11 Bit Map of ECP Port Registers D7 data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO. D6 PD6 nAck 1 D5 PD5 PError Directio D4 PD4 Select ackIntEn D3 PD3 nFault SelectIn D2 PD2 1 nInit D1 PD1 1 autofd D0 PD0 NOTE 2 PD7 Addr/RLE Address or RLE field 1 strobe nBusy 1 1 1 2 2 2 Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 compress 0 intrValue MODE 0 1 1 1 nErrIntrEn 0 1 dmaEn 0 1 serviceIntr 0 1 full 0 1 empty - 94 - W83977ATF/W83977ATG 8.3.12 ECP Pin Descriptions NAME nStrobe (HostClk) PD nAck (PeriphClk) Busy (PeriphAck) TYPE O I/O I I DESCRIPTION The nStrobe registers data or address into the slave on the asserting edge during write operations. This signal handshakes with Busy. These signals contain address or data or RLE data. This signal indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. It indicates whether the data lines contain ECP command information or data in the reverse direction. When in reverse direction, normal data are transferred when Busy (PeriphAck) is high and an 8-bit command is transferred when it is low. This signal is used to acknowledge a change in the direction of the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when it is asserted. This signal indicates whether the data lines contain ECP address or data in the forward direction. When in forward direction, normal data are transferred when nAutoFd (HostAck) is high and an 8-bit command is transferred when it is low. Generates an error interrupt when it is asserted. This signal is valid only in the forward direction. The peripheral is permitted (but not required) to drive this pin low to request a reverse transfer during ECP Mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode. PError (nAckReverse) I Select (Xflag) nAutoFd (HostAck) I O nFault (nPeriphRequest) I nInit (nReverseRequest) O nSelectIn (ECPMode) O - 95 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 8.3.13 ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The following are required: (a) Set direction = 0, enabling the drivers. (b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state. (c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. (d) Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively. 8.3.13.1 Mode Switching Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010). If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can be changed only in mode 001. When in extended forward mode, the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. 8.3.13.2 Command/Data ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck is low. The most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address. In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. 8.3.13.3 Data Compression The W83977ATF/ATG supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. 8.3.14 FIFO Operation The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled. - 96 - W83977ATF/W83977ATG 8.3.15 DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the DMA. 8.3.16 Programmed I/O (NON-DMA) Mode The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and serviceIntr = 0 in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. 8.4 Extension FDD Mode (EXTFDD) In this mode, W83977ATF/ATG changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 8-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOB and DSB will be forced to inactive state. (2) Pins DSKCHG , RDATA , WP , TRAK0 , INDEX will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive. 8.5 Extension 2FDD Mode (EXT2FDD) In this mode, W83977ATF/ATG changes the printer interface pins to FDC input/output pins, allowing the user to install two external floppy disk drives through the DB-25 printer connector to replace internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table8-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOA , DSA , MOB , and DSB will be forced to inactive state. (2) Pins DSKCHG , RDATA , WP , TRAK0 , and INDEX will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive. - 97 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 9. KEYBOARD CONTROLLER The KBC (8042 with licensed KB BIOS) circuit of W83977ATF/ATG is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM®-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. Then, the controller will assert an interrupt to the system when data are placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledgement is received for the previous data byte. P24 P25 P21 KINH P17 P20 P27 KIRQ MIRQ GATEA20 KBRST KDAT KCLK MCLK 8042 GP I/O PINS Multiplex I/O PINS P12~P16 P10 P26 T0 P23 T1 P22 P11 MDAT Keyboard and Mouse Interface 9.1 Output Buffer The output buffer is an 8-bit read-only register at I/O address 60H (Default, PnP programmable I/O address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. The output buffer can only be read when the output buffer full bit in the register is "1". 9.2 Input Buffer The input buffer is an 8-bit write-only register at I/O address 60H or 64H (Default, PnP programmable I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written to I/O address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte) through the controller's input buffer only if the input buffer full bit in the status register is “0”. - 98 - W83977ATF/W83977ATG 9.3 Status Register The status register is an 8-bit read-only register at I/O address 64H (Default, PnP programmable I/O address LD5-CR62 and LD5-CR63), that holds information about the status of the keyboard controller and interface. It may be read at any time. BIT BIT FUNCTION DESCRIPTION 0 1 2 Output Buffer Full Input Buffer Full System Flag 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. It defaults to 0 after a power-on reset. 0: Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) 3 4 5 6 7 Command/Data Inhibit Switch Auxiliary Device Output Buffer General Purpose Timeout Parity Error 9.4 Commands COMMAND FUNCTION 20h 60h Read Command Byte of Keyboard Controller Write Command Byte of Keyboard Controller BIT 7 6 5 4 3 2 1 0 Reserved IBM Keyboard Translate Mode Disable Auxiliary Device Disable Keyboard Reserve System Flag Enable Auxiliary Interrupt Enable Keyboard Interrupt BIT DEFINITION - 99 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Commands, continued COMMAND FUNCTION A4h Test Password Returns 0Fah if Password is loaded Returns 0F1h if Password is not loaded A5h A6h A7h A8h A9h Load Password Load Password until a "0" is received from the system Enable Password Enable the checking of keystrokes for a match with the password Disable Auxiliary Device Interface Enable Auxiliary Device Interface Interface Test BIT 00 01 02 03 04 BIT DEFINITION No Error Detected Auxiliary Device "Clock" line is stuck low Auxiliary Device "Clock" line is stuck high Auxiliary Device "Data" line is stuck low Auxiliary Device "Data" line is stuck low AAh ABh Self-test Returns 055h if self test succeeds Interface Test BIT 00 01 02 03 04 BIT DEFINITION No Error Detected Keyboard "Clock" line is stuck low Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low Keyboard "Data" line is stuck high ADh AEh C0h C1h C2h D0h D1h Disable Keyboard Interface Enable Keyboard Interface Read Input Port(P1) and send data to the system Continuously puts the lower four bits of Port1 into STATUS register Continuously puts the upper four bits of Port1 into STATUS register Send Port2 value to the system Only set/reset GateA20 line based on the system data bit 1 - 100 - W83977ATF/W83977ATG Commands, continued COMMAND FUNCTION D2h D3h D4h E0h FXh Send data back to the system as if it came from Keyboard Send data back to the system as if it came from Auxiliary Device Output next received byte of data from system to Auxiliary Device Reports the status of the test inputs Pulse only RC(the reset line) low for 6μS if Command byte is even 9.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control logic is controlled by LD5-CRF0 as follows: 9.5.1 BIT KB Control Register (Logic Device 5, CR-F0) 7 KCLKS1 6 KCLKS0 5 Reserved 4 Reserved 3 Reserved 2 P92EN 1 HGA20 0 HKBRST NAME KCLKS1, KCLKS0 This 2 bits are for the KBC clock rate selection. =00 =01 =10 =11 P92EN (Port 92 Enable) KBC clock input is 6 Mhz KBC clock input is 8 Mhz KBC clock input is 12 Mhz KBC clock input is 16 Mhz A "1" on this bit enables Port 92 to control GATEA20 and KBRESET. A "0" on this bit disables Port 92 functions. HGA20 (Hardware GATE A20) A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal. A "0" on this bit disables hardware GATEA20 control logic function. HKBRST (Hardware Keyboard Reset) A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal. A "0" on this bit disable hardware KB RESET control logic function. When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears GATE A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears KBRESET depending on the received data bit 0. When the KBC receives a "FE" command, the KBRESET is pulse low for 6μS (Min.) with 14μS (Min.) delay. - 101 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG GATEA20 and KBRESET are controlled by either the software control or the hardware control logic and they are mutually exclusive. Then, GATEA20 and KBRESET are merged along with Port92 when P92EN bit is set. 9.5.2 BIT Port 92 Control Register (Default Value = 0x24) 7 6 5 4 3 2 1 0 NAME Res. (0) Res. (0) Res. (1) Res. (0) Res. (0) Res. (1) SGA20 PLKBRST SGA20 (Special GATE A20 Control) A "1" on this bit drives GATE A20 signal to high. A "0" on this bit drives GATE A20 signal to low. PLKBRST (Pull-Low KBRESET) A "1" on this bit causes KBRESET to drive low for 6μS (Min.) with 14μS (Min.) delay. Before issuing another keyboard reset command, the bit must be cleared. - 102 - W83977ATF/W83977ATG 10. GENERAL PURPOSE I/O W83977ATF/ATG provides 23 Input/Output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. These 23 GP I/O ports are divided into three groups; the first group contains 8 ports, the second group contains only 7 ports, and the third group contains 8 ports. Each port in the first group corresponds to a configuration register in logical device 7, the second group in logical device 8, and the third group in logical device 9. Users can select these I/O ports functions by independently programming the configuration registers. Figure 7.1, 7.2, and 7.3 show the GP I/O port's structure of logical device 7, 8, and 9 respectively. Right after Power-on reset, those ports default to perform basic I/O functions. Figure 10.1 - 103 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Figure 10.2 Figure 10.3 - 104 - W83977ATF/W83977ATG 10.1 Basic I/O functions The Basic I/O functions of W83977ATF/ATG provide several I/O operations, including driving a logic value to output port, latching a logic value from input port, inverting the input/output logic value, and steering Common Interrupt (only available in the second group of the GP I/O port). Common Interrupt is the ORed function of all interrupt channels in the second group of the GP I/O ports, and it also connects to a 1ms debounce filter which can reject a noise of 1 ms pulse width or less. There are three 8-bit registers (GP1, GP2, and GP3) which are directly connected to those GP I/O ports. Each GP I/O port is represented as a bit in one of three 8-bit registers. Only 6 bits of GP2 are implemented. Table 10.1.1 shows their combinations of Basic I/O functions, and Table 10.1.2 shows the register bit assignments of GP1, GP2, and GP3. Table 10.1.1 I/O BIT 0 = OUTPUT 1 = INPUT 0 0 0 0 1 1 1 1 ENABLE INT BIT 0 = DISABLE 1 = ENABLE 0 0 1 1 0 0 1 1 POLARITY BIT 0 = NON INVERT 1 = INVERT 0 1 0 1 0 1 0 1 BASIC I/O OPERATIONS Basic non-inverting output Basic inverting output Non-inverted output bit value of GP2 drive to Common Interrupt Inverted output bit value of GP2 drive to Common Interrupt Basic non-inverting input Basic inverting input Non-inverted input drive to Common Interrupt Inverted input drive to Common Interrupt - 105 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Table 10.1.2 GP I/O PORT ACCESSED REGISTER REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 GP1 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 GP2 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 0 BIT 1 BIT 2 BIT 3 GP3 BIT 4 BIT 5 BIT 6 BIT 7 GP I/O PORT GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP30 GP31 GP32 GP33 GP34 GP35 GP36 GP37 - 106 - W83977ATF/W83977ATG 10.2 Alternate I/O Functions W83977ATF/ATG provides several alternate functions which are scattered among the GP I/O ports. Table 10.2.1 shows their assignments. Polarity bit can also be set to alter their polarity. Table 10.2.1 GP I/O PORT GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP30 GP31 GP32 GP33 GP34 Interrupt Steering Interrupt Steering Watch Dog Timer Output/IRRX input Power LED output/IRTX output General Purpose Address Decoder/Keyboard Inhibit(P17) General Purpose Write Strobe/ 8042 P12 Watch Dog Timer Output Power LED output Keyboard Reset (8042 P20) 8042 P13 8042 P14 8042 P15 8042 P16 GATE A20 (8042 P21) Interrupt Steering Interrupt Steering General Purpose Address Decoder General Purpose Address Decoder Watch Dog Timer Output ALTERNATE FUNCTION 10.2.1 Interrupt Steering GP10, GP11, GP30, and GP31 can be programmed to map their own interrupt channels. The selection of IRQ channel can be done in configuration registers CR70 and CR72 of logical device 7 and logical device 9. Each interrupt channel also has its own 1 ms debounce filter that is used to reject any noise whose width is equal to or less than 1 ms. - 107 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 10.2.2 Watch Dog Timer Output Watch Dog Timer contains a one minute resolution down counter, CRF2 of Logical Device 8, and two watch Dog control registers, WDT_CTRL0 and WDT_CTRL1 of Logical Device 8. The down counter can be programmed within the range from 1 to 255 minutes. Writing any new non-zero value to CRF2 or reset signal coming from a Mouse interrupt or Keyboard interrupt (CRF2 also contains non-zero value) will cause the Watch Dog Timer to reload and start to count down from the new value. As the counter reaches zero, (1) Watch Dog Timer time-out occurs and the bit 0 of WDT_CTRL1 will be set to logic 1; (2) Watch Dog interrupt output is asserted if the interrupt is enable in CR72 of logical device 8; and (3) Power LED starts to toggle output if the bit 3 of WDT_CTRL0 is enabled. WDT_CTRL1 also can be accessed through GP2 I/O base address + 1. 10.2.3 Power LED The Power LED function provides 1 Hertz rate toggle pulse output with 50 percent duty cycle. Table 10.2.2 shows how to enable Power LED. Table 10.2.2 WDT_CTRL1 BIT[1] 1 0 0 0 WDT_CTRL0 BIT[3] X 0 1 1 WDT_CTRL1 BIT[0] X X 0 1 POWER LED STATE 1 Hertz Toggle pulse Continuous high or low * Continuous high or low * 1 Hertz Toggle pulse * Note: Continuous high or low depends on the polarity bit of GP13 or GP17 configuration registers. 10.2.4 General Purpose Address Decoder General Purpose Address Decoder provides two addresses decode as AEN equal to logic 0. The address base is stored at CR62, CR63 of logical device 7 for GP14 and at CR62-65 of logical device 9 for GP32 and GP33. The decoding output is normally active low. Users can alter its polarity through the polarity bit of the GP14, GP32, and GP33's configuration register. 10.2.5 General Purpose Write Strobe General Purpose Write Strobe is an address decoder that performs like General Purpose Address Decoder, but it has to be qualified by IOW and AEN. Its output is normally active low. Users can alter its polarity through the polarity bit of the GP15's configuration register. - 108 - W83977ATF/W83977ATG 11. PLUG AND PLAY CONFIGURATION W83977ATF/ATG uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83977ATF/ATG, there are nine Logical Devices (from Logical Device 0 to Logical Device A, with the exception of logical device 4 for compatibility) which correspond to ten individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), KBC (logical device 5), IR (logical device 6), GPIO1 (logical device 7), GPIO2 (logical device 8), GPIO3 (logical device 9), and ACPI ((logical device A). Each Logical Device has its own configuration registers (above CR30). Host can access those registers by writing an appropriate logical device number into logical device select register at CR7. 11.1 Compatible PnP 11.1.1 Extended Function Registers In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS (CR26 bit 6) can be used to select one of these two methods of entering the Extended Function mode as follows: HEFRAS 0 1 ADDRESS AND VALUE write 87h to the location 3F0h twice write 87h to the location 370h twice After Power-on reset, the value on RTSA (pin 43) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 3F0h or 370h). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Functions Index Register (I/O port address 3F0h or 370h same as Extended Functions Enable Register) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 3F1h or 371h). After programming of the configuration register is finished, an additional value (AAh) should be written to EFERs to exit the Extended Function mode, to prevent unintentional access to those configuration registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. Publication Release Date: May 2006 Revision 0.6 - 109 - W83977ATF/W83977ATG 11.1.2 Extended Functions Enable Registers (EFERs) After a power-on reset, W83977ATF/ATG enters the default operating mode. Before W83977ATF/ATG enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 3F0h or 370h (as described in previous section). 11.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers (EFDRs) After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 3F0h or 370h on PC/AT systems; the EFDRs are read/write registers with port address 3F1h or 371h on PC/AT systems. 11.2 Configuration Sequence To program W83977ATF/ATG configuration registers, the following configuration sequence must be followed: (1). Enter the extended function mode (2). Configure the configuration registers (3). Exit the extended function mode Enter the extended function mode To place the chip into the extended function mode, two successive writes of 0x87 must be applied to Extended Function Enable Registers (EFERs, i.e. 3F0h or 370h). Configurate the configuration registers The chip selects the logical device and activates the desired logical devices through Extended Function Index Register (EFIR) and Extended Function Data Register (EFDR). EFIR is located at the same address as EFER, and EFDR is located at address (EFIR+1). First, write the Logical Device Number (i.e., 0x07) to the EFIR and then write the number of the desired logical device to the EFDR. If accessing the Chip (Global) Control Registers, this step is not required. Secondly, write the address of the desired configuration register within the logical device to the EFIR and then write (or read) the desired configuration register through EFDR. Exit the extended function mode To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the extended function mode, it is in the normal running mode and is ready to enter the configuration mode. - 110 - W83977ATF/W83977ATG Software programming example The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 3F0h, so EFIR is located at 3F0h and EFDR is located at 3F1h. If HEFRAS (CR26 bit 6) is set, 3F0h can be directly replaced by 370h and 3F1h replaced by 371h. ;----------------------------------------------------------------------------------; Enter the extended function mode, interruptible double-write | ;----------------------------------------------------------------------------------MOV DX, 3F0H MOV AL, 87H OUT DX, AL OUT DX, AL ;----------------------------------------------------------------------------; Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV DX, 3F0H MOV AL, 07H OUT DX, AL ; point to Logical Device Number Reg. MOV DX, 3F1H MOV AL, 01H OUT DX, AL ; select logical device 1 ; MOV DX, 3F0H MOV AL, F0H OUT DX, AL ; select CRF0 MOV DX, 3F1H MOV AL, 3CH OUT DX, AL ; update CRF0 with value 3CH ;-----------------------------------------; Exit extended function mode | ;-----------------------------------------MOV DX, 3F0H MOV AL, AAH OUT DX, AL - 111 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 12. ACPI REGISTERS FEATURES W83977ATF/ATG supports both ACPI and legacy power managements. The switch logic of the power management block generates an SMI interrupt in the legacy mode and an SCI interrupt in the ACPI mode. For the legacy mode, the SMI_EN bit is used. If it is set, it routes the power management events to the SMI interrupt logic. For the ACPI mode, the SCI_EN bit is used. If it is set, it routes the power management events to the SCI interrupt logic. The SMI_EN bit is located in the configuration register block of logical device A and the SCI_EN bit is located in the PM1 register block. See the following figure for illustration. IRQs from SCI to SMI IRQs 0 1 SCI_EN SMI_EN SMI Logic SMI output Logic SMI PM Timer from SMI to SCI Bus Master SCI SCI output Logic SCI Logic IRQs SCI WAK_STS Device Idle Timers Device Trap Global STBY Timer Sleep/Wake State machine Clock Control The SMI interrupt is routed to pin SMI , which is dedicated for the SMI interrupt output. Another way to output the SMI interrupt is to route to pin IRQSER, which is the signal pin in the Serial IRQ mode. The SCI interrupt can be routed to pin SCI , which is dedicated for the SCI function. Or it can be routed to one interrupt request pin, which is selected through CR70 bit3-0 of logical device A. Another way is to output the SCI interrupt to pin IRQSER if Serial IRQ mode is enabled. - 112 - W83977ATF/W83977ATG 12.1 SMI to SCI/SCI to SMI and Bus Master The following figure illustrates the process of generating an interrupt from SMI to SCI or from SCI to SMI . clear from SMI to SCI BIOS_RLS GBL_EN clear from SCI to SMI GBL_RLS BIOS_EN clear Bus Master SCI BM_CNTPL BM_RLD set set set GBL_STS To SCI Logic BIOS_STS To SMI Logic BM_STS To SCI Logic : Status bit : Enable bit For the BIOS software to raise an event to the ACPI software, BIOS_RLS, GBL_EN, and GBL_STS bits are involved. GBL_EN is the enable bit and the GBL_STS is the status bit. Both are controlled by the ACPI software. If BIOS_RLS is set by the BIOS software and GBL_EN is set by the ACPI software, an SCI interrupt is raised. Writing a 1 to BIOS_RLS sets it to logic 1 and also sets GBL_STS to logic 1. Writing a 0 to BIOS_RLS has no effect. Writing a 1 to GBL_STS clears it to logic 0 and also clears BIOS_RLS to logic 0. Writing a 0 to GBL_STS has no effect. For the ACPI software to raise an event to the BIOS software, GBL_RLS, BIOS_EN, and BIOS_STS bits are involved. BIOS_EN is the enable bit and the BIOS_STS is the status bit. Both are controlled by the BIOS software. If GBL_RLS is set by the ACPI software and BIOS_EN is set by the BIOS software, a SMI is raised. Writing a 1 to GBL_RLS sets it to logic 1 and also sets BIOS_STS to logic Publication Release Date: May 2006 Revision 0.6 - 113 - W83977ATF/W83977ATG 1. Writing a 0 to GBL_RLS has no effect. Writing a 1 to BIOS_STS clears it to logic 0 and also clears GBL_RLS to logic 0. Writing a 0 to BIOS_STS has no effect. For the bus master to raise an event to the ACPI software, BM_CNTRL, BM_RLD, and BM_STS bits are involved. Both BM_RLD and BM_STS are controlled by the ACPI software. If BM_CNTRL is set by the BIOS software and BM_RLD is set by the ACPI software, an SCI interrupt is raised. Writing a 1 to BM_CNTRL sets it to logic 1 and also sets BM_STS to logic 1. Writing a 0 to BM_CNTRL has no effect. Writing a 1 to BM_STS clears it to logic 0 and also clears BM_CNTRL to logic 0. Writing a 0 to BM_STS has no effect. 12.2 Power Management Timer In the ACPI specification, a power management timer is required. The power management timer is a 24-bit fixed rate free running up-count timer that runs off a 3.579545MHZ clock. The power management timer corresponds to status bit (TMR_STS) and enable bit (TMR_EN). The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. Three registers are used to read the timer value which are located in the PM1 register block. The power management timer has one enable bit (TMR_ON) to turn it on or off. The TMR_ON is located in GPE register block. If it is cleared to 0, the power management timer function will not work. There are no timer reset requirements, except that the timer should function after power-up. See the following figure for illustration. TMR_ON 3.579545 MHz 24 bit counter Bits (23-0) 24 TMR_STS To SCI Logic TMR_EN TMR_VAL - 114 - W83977ATF/W83977ATG 12.3 ACPI Registers (ACPIRs) The ACPI register model consists of the fixed register blocks that perform the ACPI functuions. A register block may be an event register block which deals with ACPI events or a control register block which deals with control features. The order in the event register block is a status register followed by an enable register. Each event register, if implemented, contains two registers: a status register and an enable register, of 16 bits wide each. The status register indicates which event triggers the ACPI System Control Interrupt ( SCI ). When the hardware event occurs, the corresponding status bit will be set. However, the corresponding enable bit is also required to be set before an SCI interrupt can be raised. If the enable bit is not set, the software can examine the state of the hardware event by reading the status bit without generating an SCI interrupt. Any status bit, unless otherwise noted, can only be set by specific hardware events. It is cleared by writing a 1 to its bit position, and writing a 0 has no effect. Except for some special status bits, every status bit has a corresponding enable bit on the same bit position in the enable register. Those status bits which have no corresponding enable bit are read for special purpose. Reversed or unimplemented enable bits always return zero, and writing to these bits should have no effect. The control bit in the control register provides some special control functions over hardware events, or some special control over SCI event. Reserved or unimplemented control bits always return zero, and writing to those bits should have no effect. Table 12-1 lists the PM1 register block and the registers within it. The base address of PM1 register block is named as PM1a_EVT_BLK in the ACPI specification and is specified in CR60, CR61 of logical device A. Table 12-2 lists the GPE register block and the register within it. The base address of general-purpose event block GPE0 is named as GPE0_BLK in the ACPI specification and is specified in CR62, CR63 of logical device A. The base address of general-purpose event block GPE1 is named as GPE1_BLK in the ACPI specification and is specified in CR64, CR65 of logical device A. 12.3.1 Power Management 1 Status Register 1 (PM1STS1) Register Location: Default Value: Attribute: Size: System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 TMR_STS Reserved Reserved Reserved BM_STS GBL_STS Reserved Reserved - 115 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG BIT NAME DESCRIPTION 0 TMR_STS This bit is the timer carry status bit. This bit is set anytime the bit 23 of the 24-bit counter changes (whenever the MSB changes from low to high or high to low). When TMR_EN and TMR_STS are set, a power management event is raised. This bit is only set by hardware and can only be cleared by writing a 1 to this bit position. Writing a 0 has no effect. Reserved. This is the bus master status bit. Writing a 1 to BM_CNTRL also sets BM_STS. Writing a 1 clears this bit and also clears BM_CNTRL. Writing a 0 has no effect. This is the global status bit. This bit is set when the BIOS wants the attention of the SCI handler. BIOS sets this bit by setting BIOS_RLS and can only be cleared by writing a 1 to this bit position. Writing a 1 to this bit position also clears BIOS_RLS. Writing a 0 has no effect. Reserved. These bits always return zeros. 1-3 4 Reserved BM_STS 5 GBL_STS 6-7 Reserved 12.3.2 Power Management 1 Status Register 2 (PM1STS2) Register Location: Default Value: Attribute: Size: + 1H System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved WAK_STS BIT NAME DESCRIPTION 0-6 7 Reserved WAK_STS Reserved. This bit is set when the system is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working state. This bit is only set by hardware and is cleared by writing a 1 to this bit position, or by the sleeping/working state machine automatically when the global standby timer expires. Writing a 0 has no effect. When the WAK_STS is cleared and all devices are in sleeping state, the whole chip enters the sleeping state. - 116 - W83977ATF/W83977ATG 12.3.3 Power Management 1 Enable Register 1(PM1EN1) Register Location: Default Value: Attribute: Size: + 2H System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 TMR_EN Reserved Reserved Reserved GBL_EN Reserved Reserved Reserved BIT NAME DESCRIPTION 0 TMR_EN This is the timer carry interrupt enable bit. When this bit is set, an SCI event is generated whenever the TMR_STS bit is set. When this bit is reset, no interrupt is generated even when the TMR_STS bit is set. Reserved. These bits always return a value of zero. The global enable bit. When both the GBL_EN bit and the GBL_STS bit are set, an SCI interrupt is raised. Reserved. 1-4 5 6-7 Reserved GBL_EN Reserved 12.3.4 Power Management 1 Enable Register 2 (PM1EN2) Register Location: Default Value: Attribute: Size: + 3H System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT NAME DESCRIPTION 0-7 Reserved Reserved. These bits always return zeros. - 117 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 12.3.5 Power Management 1 Control Register 1 (PM1CTL1) Register Location: + 4H System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 6 5 4 3 2 1 0 SCI_EN BM_RLD GBL_RLD Reserved Reserved Reserved Reserved Reserved BIT NAME DESCRIPTION 0 SCI_EN Selects whether the power management event triggers a SCI or an SMI interrupt. When this bit is set, the power management events will generate an SCI interrupt. When this bit is reset and SMI_EN bit is set, the power management events will generate an SMI interrupt. This is the bus master reload enable bit. If this bit is set and BM_CNTRL is set, an SCI interrupt is raised. The global release bit. This bit is used by the ACPI software to raise an event to the BIOS software. The BIOS software has a corresponding enable and status bit to control its ability to receive the ACPI event. Setting GBL_RLS sets BIOS_STS, and it generates an SMI interrupt if BIOS_EN is also set. Reserved. These bits always return zeros. 1 2 BM_RLD GBL_RLS 3-7 Reserved 12.3.6 Power Management 1 Control Register 2 (PM1CTL2) Register Location: + 5H System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT NAME DESCRIPTION 0-7 Reserved Reserved. These bits always return zeros. - 118 - W83977ATF/W83977ATG 12.3.7 Power Management 1 Control Register 3 (PM1CTL3) Register Location: Default Value: Attribute: Size: + 6H System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT NAME DESCRIPTION 0-7 Reserved Reserved. These bits always return zeros. 12.3.8 Power Management 1 Control Register 4 (PM1CTL4) Register Location: Default Value: Attribute: Size: + 7H System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT NAME DESCRIPTION 0-7 Reserved Reserved. These bits always return zeros. - 119 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 12.3.9 Power Management 1 Timer 1 (PM1TMR1) Register Location: + 8H System I/O Space Default Value: 00h Attribute: Read only Size: 8 bits 7 6 5 4 3 2 1 0 TMR_VAL0 TMR_VAL1 TMR_VAL2 TMR_VAL3 TMR_VAL4 TMR_VAL5 TMR_VAL6 TMR_VAL7 BIT 0-7 NAME TMR_VAL DESCRIPTION This read-only field returns the running count of the power management timer. This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in the working state. The timer is reset and then continues counting until the CLKIN input to the chip is stopped. If the clock is restarted without an MR reset, then the counter will resume counting from where it stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. 12.3.10 Power Management 1 Timer 2 (PM1TMR2) Register Location: + 9H System I/O Space Default Value: 00h Attribute: Read only Size: 8 bits 7 6 5 4 3 2 1 0 TMR_VAL8 TMR_VAL9 TMR_VAL10 TMR_VAL11 TMR_VAL12 TMR_VAL13 TMR_VAL14 TMR_VAL15 BIT 0-7 NAME TMR_VAL DESCRIPTION This read-only field returns the running count of the power management timer. This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in the working state. The timer is reset and then continues counting until the CLKIN input to the chip is stopped. If the clock is restarted without an MR reset, then the counter will resume counting from where it stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. - 120 - W83977ATF/W83977ATG 12.3.11 Power Management 1 Timer 3 (PM1TMR3) Register Location: Default Value: Attribute: Size: + AH System I/O Space 00h Read only 8 bits 7 6 5 4 3 2 1 0 TMR_VAL16 TMR_VAL17 TMR_VAL18 TMR_VAL19 TMR_VAL20 TMR_VAL21 TMR_VAL22 TMR_VAL23 BIT 0-7 NAME TMR_VAL DESCRIPTION This read-only field returns the running count of the power management timer. This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in the working state. The timer is reset and then continues counting until the CLKIN input to the chip is stopped. If the clock is restarted without an MR reset, then the counter will resume counting from where it stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. 12.3.12 Power Management 1 Timer 4 (PM1TMR4) Register Location: Default Value: Attribute: Size: + BH System I/O Space 00h Read only 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT 0-7 NAME Reserved DESCRIPTION Reserved. These bits always return zeros. - 121 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 12.3.13 General Purpose Event 0 Status Register 1 (GP0STS1) Register Location: Default Value: Attribute: Size: System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 URBSCISTS URASCISTS FDCSCISTS PRTSCISTS KBCSCISTS MOUSCISTS IRSCISTS Reserved These bits indicate the status of the SCI input, which is set when the device's IRQ is raised. If the corresponding enable bit in the SCI interrupt enable register (in GP0EN1) is set, an SCI interrupt is raised and routed to the output pin. Writing a 1 clears the bit, and writing a 0 has no effect. If the bit is not cleared, new IRQ to the SCI logic input is ignored and no SCI interrupt will be raised. BIT 0 1 2 3 4 5 6 7 NAME URBSCISTS URASCISTS FDCSCISTS PRTSCISTS KBCSCISTS MOUSCISTS IRSCISTS Reserved DESCRIPTION UART B SCI status, which is set by the UART B IRQ. UART A SCI status, which is set by the UART A IRQ. FDC SCI status, which is set by the FDC IRQ. PRT SCI status, which is set by the printer port IRQ. KBC SCI status, which is set by the KBC IRQ. MOUSE SCI status, which is set by the MOUSE IRQ. IR SCI status, which is set by the IR IRQ. Reserved. 12.3.14 General Purpose Event 0 Status Register 2 (GP0STS2) Register Location: Default Value: Attribute: Size: + 1H System I/O Space 00h Read/write 8 bits - 122 - W83977ATF/W83977ATG 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT 0-7 NAME Reserved DESCRIPTION Reserved. These bits always return zeros. 12.3.15 General Purpose Event 0 Enable Register 1 (GP0EN1) Register Location: + 2H System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 6 5 4 3 2 1 0 URBSCIEN URASCIEN FDCSCIEN PRTSCIEN KBCSCIEN MOUSCIEN IRSCIEN Reserved These bits are used to enable the device's IRQ sources into the SCI logic. The SCI logic output for the IRQs is as follows: SCI logic output = (URBSCIEN and URBSCISTS) or (URASCIEN and URASCISTS) or (FDCSCIEN and FDCSCISTS) or (PRTSCIEN and PRTSCISTS) or (KBCSCIEN and KBCSCISTS) or (MOUSCIEN and MOUSCISTS) or (IRSCIEN and IRSCISTS) BIT 0 1 2 3 4 5 6 7 NAME URBSCIEN URASCIEN FDCSCIEN PRTSCIEN KBCSCIEN MOUSCIEN IRSCIEN Reserved DESCRIPTION UART B SCI enable, which controls the UART B IRQ. UART A SCI enable, which controls the UART A IRQ. FDC SCI enable, which controls the FDC IRQ. Printer port SCI enable, which controls the printer port IRQ. KBC SCI enable, which controls the KBC IRQ. MOUSE SCI enable, which controls the MOUSE IRQ. IR SCI enable, which controls the IR IRQ. Reserved. - 123 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 12.3.16 General Purpose Event 0 Enable Register 2 (GP0EN2) Register Location: Default Value: Attribute: Size: + 3H System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT 0-7 NAME Reserved DESCRIPTION Reserved. These bits always return zeros. 12.3.17 General Purpose Event 1 Status Register 1 (GP1STS1) Register Location: Default Value: Attribute: Size: System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 BIOS_STS Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT 0 NAME BIOS_STS DESCRIPTION The BIOS status bit. This bit is set when GBL_RLS is set. If BIOS_EN is set, setting GBL_RLS will raise an SMI event. Writing a 1 to its bit location clears BIOS_STS and also clears GBL_RLS. Writing a 0 has no effect. 1-7 Reserved Reserved. - 124 - W83977ATF/W83977ATG 12.3.18 General Purpose Event 1 Status Register 2 (GP1STS2) Register Location: Default Value: Attribute: Size: + 1H System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT 0-7 NAME Reserved DESCRIPTION Reserved. These bits always return zeros. 12.3.19 General Purpose Event 1 Enable Register 1 (GP1EN1) Register Location: Default Value: Attribute: Size: + 2H System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 BIOS_EN TMR_ON Reserved Reserved Reserved Reserved Reserved Reserved BIT 0 NAME BIOS_EN DESCRIPTION This bit raises the SMI event. When this bit is set and the ACPI software writes a 1 to the GBL_RLS bit, an SMI event is raised on the SMI logic output. This bit is used to turn on the power management timer. 1 = timer on; 0 = timer off. Reserved. 1 2-7 TMR_ON Reserved - 125 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 12.3.20 General Purpose Event 1 Enable Register 2 (GP1EN2) Register Location: Default Value: Attribute: Size: + 3H System I/O Space 00h Read/write 8 bits 7 6 5 4 3 2 1 0 BIOS_RLS BM_CNTRL Reserved Reserved Reserved Reserved Reserved Reserved BIT 0 NAME BIOS_RLS DESCRIPTION The BIOS release bit. This bit is used by the BIOS software to raise an event to the ACPI software. The ACPI software has a corresponding enable and status bit to control its ability to receive the ACPI event. Setting BIOS_RLS sets GBL_STS, and it generates an SCI interrupt if GBL_EN is also set. Writing a 1 to its bit position sets this bit and also sets the BM_STS bit. Writing a 0 has no effect. This bit is cleared by writing a 1 to the GBL_STS bit. 1 BM_CNTRL This bit is used to set the BM_STS bit and if the BM_RLD bit is also set, then an SCI interrupt is generated. Writing a 1 sets BM_CNTRL to 1 and also sets BM_STS. Writing a 0 has no effect. Writing a 1 to BM_STS clears BM_STS and also clears BM_CNTRL. Reserved. 2-7 Reserved - 126 - W83977ATF/W83977ATG 12.3.21 Bit Map Configuration Registers Table 12-1: Bit Map of PM1 Register Block Register Address PowerOn Reset Value PM1STS1 PM1STS2 PM1EN1 PM1EN2 PM1CTL1 PM1CTL2 PM1CTL3 PM1CTL4 PM1TMR1 PM1TMR2 PM1TMR3 PM1TMR4 +1H +2H +3H +4H +5H +6H +7H +8H +9H +AH +BH 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 WAK_STS 0 0 0 0 0 0 TMR_VAL 7 TMR_VAL 15 TMR_VAL 23 0 0 0 0 0 0 0 0 0 TMR_VAL 6 TMR_VAL 14 TMR_VAL 22 0 GBL_STS 0 GBL_EN 0 0 0 0 0 TMR_VAL 5 TMR_VAL 13 TMR_VAL 21 0 BM_STS 0 0 0 0 0 0 0 TMR_VAL 4 TMR_VAL 12 TMR_VAL 20 0 0 0 0 0 0 0 0 0 TMR_VAL 3 TMR_VAL 11 TMR_VAL 19 0 0 0 0 0 GBL_RLS 0 0 0 0 0 0 0 BM_RLD 0 0 0 TMR_STS 0 TMR_EN 0 SCI_EN 0 0 0 TMR_VAL0 TMR_VAL8 TMR_VAL16 0 D7 D6 D5 D4 D3 D2 D1 D0 TMR_VAL TMR_VAL1 2 TMR_VAL TMR_VAL9 10 TMR_VAL TMR_VAL1 18 7 0 Table 12-2: Bit Map of GPE Register Block Register Address PowerOn Reset Value GP0STS1 GP0STS2 GP0EN1 GP0EN2 GP1STS1 GP1STS2 GP1EN1 GP1EN2 +1H +2H +3H +1H +2H +3H 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOUSCISTS KBCSCIST S 0 MOUSCIEN 0 0 0 0 0 0 KBCSCIEN 0 0 0 0 0 PRTSCISTS 0 PRTSCIEN 0 0 0 0 0 FDCSCISTS 0 FDCSCIEN 0 0 0 0 0 URASCISTS 0 URASCIEN 0 0 0 TMR_ON BM_CNTRL URBSCISTS 0 URBSCIEN 0 BIOS_STS 0 BIOS_EN BIOS_RLS D7 D6 D5 D4 D3 D2 D1 D0 - 127 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 13. SERIAL IRQ W83977ATF/ATG supports a Serial IRQ scheme. This allows a signal line to be used to report the legacy ISA interrupt requests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is transferred on the IRQSER signal, one cycle consisting of three frame types: a start frame, several IRQ/Data frames, and one Stop frame. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI System, Version 6.0. Timing Diagrams for IRQSER Cycle Start Frame timing with source sampled a low pulse on IRQ1 SL or H PCICLK IRQSER START FRAME H R T S IRQ0 FRAME R T IRQ1 FRAME S R T S IRQ2 FRAME R T 1 START Drive Source H=Host Control IRQ1 Host Controller SL=Slave Control R=Recovery None IRQ1 T=Turn-around None S=Sample 1. Start Frame pulse can be 4-8 clocks wide. Stop Frame Timing with Host using 17 IRQSER sampling period IRQ14 FRAME S PCICLK IRQSER 1 STOP 3 START R T S IRQ15 FRAME R T S IOCHCK FRAME R T 2 I STOP FRAME H R T NEXT CYCLE Drive None H=Host Control IRQ15 R=Recovery None T=Turn-around Host Controller S=Sample I=Idle 1. Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. 2. There may be none, one or more Idle states during the Stop Frame. 3. The next IRQSER cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stip Frame. - 128 - W83977ATF/W83977ATG 13.1 Start Frame There are two modes of operation for the IRQSER Start frame: Quiet mode and Continuous mode. In the Quiet mode, the peripheral drives the SERIRQ signal active low for one clock, and then tristates it. This brings all the states machines of the peripherals from idle to active states. The host controller will then take over driving IRQSER signal low in the next clock, and will continue driving the IRQSER low for programmable 3 to 7 clock periods. This makes the total number of clocks low for 4 to 8 clock periods. After these clocks, the host controller will drive the IRQSER high for one clock and then tri-states it. In the Continuous mode, only the host controller initiates the START frame to update IRQ/Data line information. The host controller drives the IRQSER signal low for 4 to 8 clock periods. Upon a reset, the IRQSER signal is defaulted to the Continuous mode for the host controller to initiate the first Start frame. 13.2 IRQ/Data Frame Once the start frame has been initiated, all the peripherals must start counting frames based on the rising edge of the start pulse. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase, the peripheral drives SERIRQ low if the corresponding IRQ is active. If the corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the peripheral device drives the IRQSER high. During the Turn-around phase, the peripheral device leaves the IRQSER tri-stated. The IRQ/Data Frame has a number of specific order, as shown in Table 13-1. Table 13-1 IRQSER Sampling periods IRQ/DATA FRAME 1 2 3 4 5 6 7 8 9 10 11 12 13 SIGNAL SAMPLED IRQ0 IRQ1 # OF CLOCKS PAST START 2 5 8 11 14 17 20 23 26 29 32 35 38 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 - 129 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Continued. IRQ/DATA FRAME 14 15 16 17 18 19 20 21 32:22 SIGNAL SAMPLED IRQ13 IRQ14 IRQ15 # OF CLOCKS PAST START 41 44 47 50 53 56 59 62 95 IOCHCK INTA INTB INTC INTD Unassigned 13.3 Stop Frame After all IRQ/Data Frames have completed, the host controller will terminate IRQSER by a Stop frame. Only the host controller can initiate the Stop frame by driving IRQSER low for 2 or 3 clocks. If the Stop Frame is low for 2 clocks, the next IRQSER cycle's Sample mode is the Quiet mode. If the Stop Frame is low for 3 clocks, the next IRQSER cycle's Sample mode is the Continuous mode. 13.4 Reset and Initialization After MR reset, IRQSER Slaves are put into the Continuous (Idle) mode. The Host Controller is responsible for starting the initial IRQSER Cycle to collect the system's IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent IRQSER cycles. It's the Host Controller's responsibility to provide the default values to 8259's and other system logic before the first IRQSER cycle is performed. For IRQSER system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (Idle) mode first. This is to guarantee IRQSER bus in the Idle state before the system configuration changes. - 130 - W83977ATF/W83977ATG 14. CONFIGURATION REGISTER 14.1 Chip (Global) Control Register CR02 (Default 0x00) Bit 7 - 1 : Reserved. Bit 0 : SWRST --> Soft Reset. CR07 Bit 7 - 0 CR20 Bit 7 - 0 CR21 Bit 7 - 0 : LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0 : DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x97 (read only). : DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 = 0x74 (read only). CR22 (Default 0xff) Bit 7 - 6 : Reserved. Bit 5 : URBPWD =0 Power down =1 No Power down Bit 4 : URAPWD =0 Power down =1 No Power down Bit 3 : PRTPWD =0 Power down =1 No Power down Bit 2 : IRPWD =0 Power down =1 No Power down Bit 1 : Reserved. Bit 0 : FDCPWD =0 Power down =1 No Power down CR23 (Default 0xFE) Bit 7 - 1 : Reserved. Bit 0 : IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down mode immediately. - 131 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG CR24 (Default 0b1s000s0s) Bit 7 : EN16SA =0 12 bit Address Qualification =1 16 bit Address Qualification Bit 6 : EN48 =0 The clock input on Pin 1 should be 24 Mhz. =1 The clock input on Pin 1 should be 48 Mhz. The corresponding power-on setting pin is SOUTB (pin 53). Bit 5 - 3 : Reserved. Bit 2 : ENKBC =0 KBC is disabled after hardware reset. =1 KBC is enabled after hardware reset. This bit is read only, and set/reset by power-on setting pin. The corresponding poweron setting pin is SOUTA (pin 46). Bit 1 : Reserved Bit 0 : PNPCSV =0 =1 The Compatible PnP address select registers have default values. The Compatible PnP address select registers have no default value. When trying to make a change to this bit, new value of PNPCSV must be complementary to the old one to make an effective change. For example, the user must set PNPCSV to 0 first and then reset it to 1 to reset these PnP registers if the present value of PNPCSV is 1. The corresponding power-on setting pin is NDTRA (pin 44). CR25 (Default 0x00) Bit 7 - 6 : Reserved Bit 5 : URBTRI Bit 4 : URATRI Bit 3 : PRTTRI Bit 2 : IRTRI Bit 1 : Reserved Bit 0 : FDCTRI. CR26 (Default 0b0s000000) Bit 7 : SEL4FDD =0 Select two FDD mode. =1 Select four FDD mode. - 132 - W83977ATF/W83977ATG Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 : HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is NRTSA (pin 43). HEFRAS Address and Value =0 Write 87h to the location 3F0h twice. =1 Write 87h to the location 370h twice. : LOCKREG =0 Enable R/W Configuration Registers. =1 Disable R/W Configuration Registers. : DSIRLGRQ =0 Enable IR legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ =1 Disable IR legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ : DSFDLGRQ =0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective on selecting IRQ =1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective on selecting IRQ : DSPRLGRQ =0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ =1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective on selecting IRQ : DSUALGRQ =0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ =1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ : DSUBLGRQ =0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ =1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ CR28 (Default 0x00) Bit 7 - 5 : Reserved. Bit 4 : IRQ Sharing selection. =0 Disable IRQ Sharing =1 Enable IRQ Sharing Bit 3 :Reserved - 133 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Bit 2 - 0 : PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode CR2A (Default 0x00) Bit 7 : PIN57S =0 KBRST =1 GP12 Bit 6 : PIN56S =0 GA20 =1 GP11 Bit 5 - 4 : PIN40S1, PIN40S0 = 00 CIRRX = 01 GP24 = 10 8042 P13 = 11 Reserved Bit 3 - 2 : PIN39S1, PIN39S0 = 00 IRRXH = 01 IRSL0 = 10 GP25 =11 Reserved Bit 1 - 0 : PIN3S1, PIN3S0 = 00 DRVDEN1 = 01 GP10 = 10 8042 P12 = 11 SCI CR2B (Default 0x00) Bit 7 - 6 : PIN73S1, PIN73S0 = 00 = 01 = 10 = 11 PANSWIN GP23 Reserved Reserved - 134 - W83977ATF/W83977ATG Bit 5 : PIN72S PANSWOUT =0 =1 GP22 : PIN70S1, PIN70S0 SMI = 00 = 01 GP21 = 10 8042 P16 = 11 Reserved : Reserved. : PIN58S =0 KBLOCK =1 GP13 Bit 4 - 3 Bit 2 - 1 Bit 0 CR2C (Default 0x00) Bit 7 - 6 : PIN121S1, PIN121S0 = 00 DRQ0 = 01 GP17 = 10 8042 P14 Bit 5 - 4 Bit 3 - 2 Bit 1 - 0 SCI = 11 : PIN119S1, PIN119S0 = 00 NDACK0 = 01 GP16 = 10 8042 P15 = 11 Reserved : PIN104S1, PIN104S0 = 00 IRQ15 = 01 GP15 = 10 WDTO = 11 Reserved : PIN103S1, PIN103S0 = 00 IRQ14 = 01 GP14 = 10 PLEDO = 11 Reserved CR2D (Default 0x00) Test Modes: Reserved for Winbond. - 135 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG CR2E (Default 0x00) Test Modes: Reserved for Winbond. CR2F (Default 0x00) Test Modes: Reserved for Winbond. 14.2 Logical Device 0 (FDC) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 Bit 0: : Reserved. = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 Bit 3 - 0 : Reserved. : These bits select IRQ resource for FDC. CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit 7 - 3 Bit 2 - 0 : Reserved. : These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04 - 0x07 No DMA active CRF0 (Default 0x0E) FDD Mode Register Bit 7 : FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. =0 =1 The internal pull-up resistors of FDC are turned on.(Default) The internal pull-up resistors of FDC are turned off. - 136 - W83977ATF/W83977ATG Bit 6 : INTVERTZ This bit determines the polarity of all FDD interface signals. =0 =1 FDD interface signals are active low. FDD interface signals are active high. Bit 5 : DRV2EN (PS2 mode only) When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A. Bit 4 : Swap Drive 0, 1 Mode =0 =1 No Swap (Default) Drive and Motor sel 0 and 1 are swapped. AT Mode (Default) (Reserved) PS/2 Model 30 Burst Mode is enabled Non-Burst Mode (Default) Normal Floppy Mode (Default) Enhanced 3-mode FDD Bit 3 - 2 : Interface Mode = 11 = 10 = 01 = 00 Bit 1 : FDC DMA Mode =0 =1 Bit 0 : Floppy Mode =0 =1 CRF1 (Default 0x00) Bit 7 - 6 : Boot Floppy = 00 = 01 = 10 = 11 FDD A FDD B FDD C FDD D Bit 5, 4 Bit 3 - 2 : Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. : Density Select = 00 = 01 = 10 = 11 Normal (Default) Normal 1 ( Forced to logic 1) 0 ( Forced to logic 0) - 137 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Bit 1 : DISFDDWR =0 =1 Enable FDD write. Disable FDD write (forces pins WE, WD stay high). Normal, use WP to determine whether the FDD is write protected or not. FDD is always write-protected. Bit 0 : SWWP =0 =1 CRF2 (Default 0xFF) Bit 7 - 6 Bit 5 - 4 Bit 3 - 2 Bit 1,0 : FDD D Drive Type : FDD C Drive Type : FDD B Drive Type : FDD A Drive Type When FDD is in enhanced 3-mode (CRF0.bit0=1),these bits determine SELDEN value in TABLE A of CRF4 and CRF5 as follows. DTYPE1 0 0 0 0 0 1 1 Note: X means don't care. DPYTE0 0 0 0 0 1 0 1 DRATE1 1 0 0 1 X X 0 DRATE0 1 0 1 0 X X 1 SELDEN 1 1 0 0 0 1 0 CRF4 (Default 0x00) FDD0 Selection: Bit 7 : Reserved. Bit 6 : Precomp. Disable. =1 =0 Disable FDC Precompensation. Enable FDC Precompensation. Bit 5 Bit 4 - 3 : Reserved. : DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A). = 00 = 01 = 10 = 11 Select Regular drives and 2.88 format Specifical application 2 Meg Tape Reserved - 138 - W83977ATF/W83977ATG Bit 2 Bit 1,0 : Reserved. : DMOD0, DMOD1: Drive Model select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. TABLE A DRIVE RATE TABLE SELECT DRTS1 DRTS0 DATA RATE DRATE1 DRATE0 SELECTED DATA RATE MFM FM SELDEN CRF0 BIT 0=0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K --250K 150K 125K --250K 250K 125K --250K --125K 1 1 0 0 1 1 0 0 1 1 0 0 Note: Refer to CRF2 for SELDEN value in the cases when CRF0, bit0=1. TABLE B DMOD0 DMOD1 DRVDEN0(PIN 2) DRVDEN1(PIN 3) DRIVE TYPE 0 0 1 1 0 1 0 1 SELDEN DRATE1 SELDEN DRATE0 DRATE0 DRATE0 DRATE0 DRATE1 4/2/1 MB 3.5”“ 2/1 MB 5.25” 2/1.6/1 MB 3.5” (3-MODE) - 139 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 14.3 Logical Device 1 (Parallel Port) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 Bit 0: : Reserved. =1 =0 Activates the logical device. Logical device is inactive. CR60, CR 61 (Default 0x03, 0x78 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Parallel Port I/O base address. [0x100:0xFFC] on 4 byte boundary (EPP not supported) or [0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base address is on 8 byte boundary). CR70 (Default 0x07 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 Bit [3:0] : Reserved. : These bits select IRQ resource for Parallel Port. CR74 (Default 0x04) Bit 7 - 3 Bit 2 - 0 : Reserved. : These bits select DRQ resource for Parallel Port. 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04 - 0x07= No DMA active CRF0 (Default 0x3F) Bit 7 : PP Interrupt Type: Not valid when the parallel port is in the printer Mode (100) or the standard & Bidirectional Mode (000). =1 Pulsed Low, released to high-Z. =0 IRQ follows nACK when parallel port in EPP Mode or [Printer, SPP, EPP] under ECP. Bit [6:3] Bit 2 - 0 : ECP FIFO Threshold. : Parallel Port Mode = 100 Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode - 140 - W83977ATF/W83977ATG = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode. 14.4 Logical Device 2 (UART A)¢) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 Bit 0 : Reserved. =1 =0 Activates the logical device. Logical device is inactive. CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 Bit 3 - 0 : Reserved. : These bits select IRQ resource for Serial Port 1. CRF0 (Default 0x00) Bit 7 - 2 Bit 1 - 0 : Reserved. : SUACLKB1, SUACLKB0 = 00 = 01 = 10 = 11 UART A clock source is 1.8462 Mhz (24MHz/13) UART A clock source is 2 Mhz (24MHz/12) UART A clock source is 24 Mhz (24MHz/1) UART A clock source is 14.769 Mhz (24MHz/1.625) 14.5 Logical Device 3 (UART B) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 Bit 0 : Reserved. =1 =0 Activates the logical device. Logical device is inactive. CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary. - 141 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 Bit [3:0] : Reserved. These bits select IRQ resource for Serial Port 2. CRF0 (Default 0x00) Bit 7 - 2 Bit 1 - 0 : Reserved. : SUBCLKB1, SUBCLKB0 = 00 = 01 = 10 = 11 UART B clock source is 1.8462 Mhz (24MHz/13) UART B clock source is 2 Mhz (24MHz/12) UART B clock source is 24 Mhz (24MHz/1) UART B clock source is 14.769 Mhz (24MHz/1.625) 14.6 Logical Device 5 (KBC) CR30 (Default 0x01 if PENKBC= 1 during POR, default 0x00 otherwise) Bit 7 - 1 Bit 0 : Reserved. =1 =0 Activates the logical device. Logical device is inactive. CR60, CR 61 (Default 0x00, 0x60 if PENKBC= 1 during POR, default 0x00 otherwise) These two registers select the first KBC I/O base address [0x100:0xFFF] on 1 byte boundary. CR62, CR 63 (Default 0x00, 0x64 if PENKBC= 1 during POR, default 0x00 otherwise) These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundary. CR70 (Default 0x01 if PENKBC= 1 during POR, default 0x00 otherwise) Bit 7 - 4 Bit [3:0] : Reserved. : These bits select IRQ resource for KINT (keyboard). CR72 (Default 0x0C if PENKBC= 1 during POR, default 0x00 otherwise) Bit 7 - 4 Bit [3:0] : Reserved. : These bits select IRQ resource for MINT (PS2 Mouse) CRF0 (Default 0x83) Bit 7 - 6 : KBC clock rate selection = 00 = 01 = 10 = 11 Select 6MHz as KBC clock input. Select 8MHz as KBC clock input. Select 12Mhz as KBC clock input. Select 16Mhz as KBC clock input. - 142 - W83977ATF/W83977ATG Bit 5 - 3 Bit 2 Bit 1 Bit 0 : Reserved. =0 =1 =0 =1 =0 =1 Port 92 disable. Port 92 enable. Gate20 software control. Gate20 hardware speed up. KBRST software control. KBRST hardware speed up. 14.7 Logical Device 6 (IR) CR30 (Default 0x00) Bit 7 - 1 Bit 0 : Reserved. =1 =0 Activates the logical device. Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select IR I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x00) Bit 7 - 4 : Reserved. Bit [3:0] :These bits select IRQ resource for IR CR74 (Default 0x04) Bit 7-3 : Reserved. Bit 2-0 : These bits select DRQ resource for RX of UART C. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04-0x07 No DMA active CR75 (Default 0x04) Bit 7-3 : Reserved. Bit 2-0 : These bits select DRQ resource for TX of UART C. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04-0x07 No DMA active - 143 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG CRF0 (Default 0x00) Bit 7 - 4 : Reserved. Bit 3 : RXW4C =0 No reception delay when SIR is changed from TX mode to RX mode. =1 Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode to RX mode. Bit 2 : TXW4C =0 No transmission delay when SIR is changed from RX mode to TX mode. =1 Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX mode to TX mode. Bit 1 : APEDCRC =0 No append hardware CRC value as data in FIR/MIR mode. =1 Append hardware CRC value as data in FIR/MIR mode. Bit 0 : ENBNKSEL; Bank select enable =0 Disable IR Bank selection. =1 Enable IR Bank selection. 14.8 Logical Device 7 (GP I/O Port I) CR30 (Default 0x00) Bit 7 - 1 Bit 0 : Reserved. =1 =0 Activates the logical device. Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select GP1 I/O base address [0x100:0xFFF] on 1 byte boundary. CR62, CR 63 (Default 0x00, 0x00) These two registers select GP14 alternate function Primary I/O base address [0x100:0xFFE] on 2 byte boundary; they are available as you set GP14 to be an alternate function (General Purpose Address Decode). CR64, CR 65 (Default 0x00, 0x00) These two registers select GP15 alternate function Primary I/O base address [0x100:0xFFF] on 1 byte boundary; they are available as you set GP15 to be an alternate function (General Purpose Write Decode). CR70 (Default 0x00) Bit 7 - 4 Bit 3 - 0 : Reserved. : These bits select IRQ resource for GP10 as you set GP10 to be an alternate function (Interrupt Steering). - 144 - W83977ATF/W83977ATG CR72 (Default 0x00) Bit 7 - 4 Bit 3 - 0 : Reserved. : These bits select IRQ resource for GP11 as you set GP11 to be an alternate function (Interrupt Steering). CRE0 (GP10, Default 0x01) Bit 7 - 5 Bit 4 : Reserved. : IRQ Filter Select =1 =0 Debounce Filter Enabled Debounce Filter Bypassed Select Alternate Function: Interrupt Steering. Select Basic I/O Function. Bit 3 : Select Function. =1 =0 Bit 2 Bit 1 : Reserved. : Polarity. =1 =0 Invert. No Invert. Input. Output. Bit 0 : In/Out selection. =1 =0 CRE1 (GP11, Default 0x01) Bit 7 - 5 Bit 4 : Reserved. : IRQ Filter Select =1 =0 Debounce Filter Enabled Debounce Filter Bypassed Select Alternate Function: Interrupt Steering. Select Basic I/O Function. Bit 3 : Select Function. =1 =0 Bit 2 Bit 1 : Reserved. : Polarity. =1 =0 Invert. No Invert. Input. Output. Bit 0 : In/Out selection. =1 =0 - 145 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG CRE2 (GP12, Default 0x01) Bit 7 - 5 Bit 4 - 3 : Reserved. : Select Function. = 00 = 01 = 10 = 11 Select Basic I/O function. Select 1st alternate function: Watch Dog Timer Output. Reserved Reserved Bit 2 Bit 1 Bit 0 : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRE3 (GP13, Default 0x01) Bit 7 - 5 Bit 4 - 3 : Reserved. : Select Function. = 00 = 01 = 10 = 11 Select Basic I/O function. Select 1st alternate function: Power LED output. Reserved Reserved Bit 2 Bit 1 Bit 0 : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRE4 (GP14, Default 0x01) Bit 7 - 5 Bit 4 - 3 : Reserved. : Select Function. = 00 = 01 when = 10 = 11 Select Basic I/O function. Select 1st alternate function: General Purpose Address Decoder(Active Low Bit 1= 0, Decode two byte address). Select 2nd alternate function: Keyboard Inhibit (P17). Reserved Bit 2 Bit 1 Bit 0 : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRE5 (GP15, Default 0x01) Bit 7 - 5 Bit 4 - 3 : Reserved. : Select Function. = 00 Select Basic I/O function. - 146 - W83977ATF/W83977ATG = 01 = 10 = 11 Bit 2 Bit 1 Bit 0 General Purpose Write Strobe (Active Low when Bit 1 = 0). 8042 P12. Reserved : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRE6 (GP16, Default 0x01) Bit 7 - 5 Bit 4 - 3 : Reserved. : Select Function. = 00 = 01 = 1x Select Basic I/O function. Select 1st alternate function: Watch Dog Timer Output. Reserved Bit 2 Bit 1 Bit 0 : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRE7 (GP17, Default 0x01) Bit 7 - 4 Bit 4 - 3 : Reserved. : Select Function. = 00 = 01 = 1x Select Basic I/O function. Select 1st alternate function: Power LED output. Please refer to TABLE C Reserved Bit 2 Bit 1 Bit 0 TABLE C : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output WDT_CTRL1* BIT[1]* 1 0 0 0 WDT_CTRL0* BIT[3] X 0 1 1 WDT_CTRL1 BIT[0] X X 0 1 POWER LED STATE 1 Hertz Toggle pulse Continuous high or low* Continuous high or low* 1 Hertz Toggle pulse *Note: 1). Regarding to the contents of WDT_CTR1 and WDT_CTRL0, please refer to CRF3 and CRF4 in Logic Device 8. 2). Continuous high or low depends on the polarity bit of GP13 or GP17 configure registers. - 147 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG CRF1 (Default 0x00) General Purpose Read/Write Enable* Bit 7 - 2 Bit 1 Bit 0 : Reserved =1 =0 =1 =0 Enable General Purpose Write Strobe Disable General Purpose Write Strobe Enable General Purpose Address Decode Disable General Purpose Address Decode *Note: If the logical device's activate bit is not set then bit 0 and 1 have no effect. 14.9 Logical Device 8 (GP I/O Port II) CR30 (Default 0x00) Bit 7 - 1 : Reserved. Bit 0 =1 Activates the logical device. =0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select GP2 & Watch Dog I/O base address [0x100:0xFFE] on 2 byte boundary. I/O base address + 1: Watch Dog I/O base address. CR70 (Default 0x00) Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resource for Common IRQ of GP20~GP26 at Logic Device 8. CR72 (Default 0x00) Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resource for Watch Dog. CRE8 (GP20, Default 0x01) Bit 7 - 5 Bit 4 - 3 : Reserved. : Select Function. = 00 = 01 = 10 = 11 Select basic I/O function Reserved Select alternate function: Keyboard Reset (connected to KBC P20) Reserved Enable Common IRQ Disable Common IRQ Bit 2 : Int En =1 =0 Bit 1 Bit 0 : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output - 148 - W83977ATF/W83977ATG CRE9 (GP21, Default 0x01) Bit 7 - 5 Bit 4 - 3 : Reserved : Select Function. = 00 = 01 = 10 = 11 Select Basic I/O function Reserved Select 2nd alternate function: Keyboard P13 I/O Reserved Bit 2 : Int En =1 =0 Enable Common IRQ Disable Common IRQ Bit 1 Bit 0 : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CREA (GP22, Default 0x01) Bit 7 - 5 Bit 4 - 3 Bit 2 Bit 1 Bit 0 : Reserved. : Select Function. = 00 Select Basic I/O function. = 01 Reserved = 10 Select 2nd alternate function: Keyboard P14 I/O. = 11 Reserved : Int En =1 Enable Common IRQ =0 Disable Common IRQ : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output¡@¡@ CREB (GP23, Default 0x01) Bit 7 - 5 Bit 4 - 3 Bit 2 Bit 1 Bit 0 : Reserved. : Select Function. = 00 Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function: Keyboard P15 I/O = 11 Reserved : Int En =1 Enable Common IRQ =0 Disable Common IRQ : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output Publication Release Date: May 2006 Revision 0.6 - 149 - W83977ATF/W83977ATG CREC (GP24, Default 0x01) Bit 7 - 5 Bit 4 - 3 : Reserved. : Select Function. = 00 = 01 = 10 = 11 Select Basic I/O function Reserved Select 2nd alternate function: Keyboard P16 I/O Reserved Enable Common IRQ Disable Common IRQ Bit 2 : Int En =1 =0 Bit 1 Bit 0 : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRED (GP25, Default 0x01) Bit 7 - 4 Bit 3 : Reserved. : Select Function. =1 =0 Select alternate function: GATE A20 (Connect to KBC P21). Select basic I/O function Enable Common IRQ Disable Common IRQ Bit 2 : Int En =1 =0 Bit 1 Bit 0 : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CREE (GP26, Default 0x01) Bit 7 - 3 Bit 2 : Reserved. : Int En =1 =0 Enable Common IRQ Disable Common IRQ Bit 1 Bit 0 : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRF0 (Default 0x00) Debounce Filter Enable or Disable for General Purpose I/O Combined Interrupt. The Debounce Filter can reject a pulse with 1ms width or less. Bit 7 - 4 Bit 3 : Reserved : GP Common IRQ Filter Select - 150 - W83977ATF/W83977ATG =1 =0 Bit 2 - 0 Debounce Filter Enabled Debounce Filter Bypassed : Reserved CRF1 (Reserved) CRF2 (Default 0x00) Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start to count down. If the Bit2 and Bit 1 are set, any Mouse Interrupt or Keyboard Interrupt will also cause reloading of the non-zero value to Watch Dog Counter and count down. Reading this register can not access Watch Dog Timer Time-out value, but can access the current value in Watch Dog Counter. Bit 7 - 0 = 0x00 Time-out Disable = 0x01 Time-out occurs after 1 minute = 0x02 Time-out occurs after 2 minutes = 0x03 Time-out occurs after 3 minutes ................................................ = 0xFF Time-out occurs after 255 minutes CRF3 (WDT_CTRL0, Default 0x00) Watch Dog Timer Control Register #0 Bit 7 - 4 Bit 3 : Reserved : When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output. =1 =0 Enable Disable Watch Dog Timer is reset upon a Mouse interrupt Watch Dog Timer is not affected by Mouse interrupt Watch Dog Timer is reset upon a Keyboard interrupt Watch Dog Timer is not affected by Keyboard interrupt Bit 2 : Mouse interrupt reset Enable or Disable =1 =0 Bit 1 : Keyboard interrupt reset Enable or Disable =1 =0 Bit 0 : Reserved. CRF4 (WDT_CTRL1, Default 0x00) Watch Dog Timer Control Register #1 Bit 7 - 4 Bit 3 : Reserved : Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W* =1 =0 Enable Disable Publication Release Date: May 2006 Revision 0.6 - 151 - W83977ATF/W83977ATG Bit 2 Bit 1 : Force Watch Dog Timer Time-out, Write only* =1 =1 =0 Bit 0 =1 =0 Force Watch Dog Timer time-out event; this bit is self-clearing. Enable Disable Watch Dog Timer time-out occurred. Watch Dog Timer counting : Enable Power LED 1Hz rate toggle pulse with 50% duty cycle , R/W : Watch Dog Timer Status, R/W *Note: 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us. 2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then connect to set the Bit 0(Watch Dog Timer Status). The ORed signal is self-clearing. 14.10 Logical Device 9 (GP I/O Port III) CR30 (Default 0x00) Bit 7 - 1 Bit 0 : Reserved. =1 =0 Activates the logical device. Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select GP3 I/O base address [0x100:0xFFF] on 1 byte boundary. CR62, CR 63 (Default 0x00, 0x00) These two registers select GP32 alternate function Primary I/O base address [0x100:0xFFE] on 2byte boundary; they are available as you set GP32 to be an alternate function (General Purpose Address Decode). CR64, CR 65 (Default 0x00, 0x00) These two registers select GP33 alternate function Primary I/O base address [0x100:0xFFF] on 2byte boundary; they are available as you set GP33 to be an alternate function (General Purpose Address Decode). CR70 (Default 0x00) Bit 7 - 4 Bit 3 - 0 : Reserved. : These bits select IRQ resource for GP30 as you set GP30 to be an alternate function (Interrupt Steering). CR72 (Default 0x00) Bit 7 - 4 Bit 3 - 0 : Reserved. : These bits select IRQ resource for GP31 as you set GP31 to be an alternate function (Interrupt Steering). - 152 - W83977ATF/W83977ATG CRE0 (GP30, Default 0x01) Bit 7 - 5 Bit 4 : Reserved. : IRQ Filter Select =1 =0 Debounce Filter Enabled. Debounce Filter Bypassed. Select Alternate Function: Interrupt Steering. Select Basic I/O Function. Bit 3 : Select Function. =1 =0 Bit 2 Bit 1 : Reserved. : Polarity. =1 =0 Invert. No Invert. Input. Output. Bit 0 : In/Out selection. =1 =0 CRE1 (GP31, Default 0x01) Bit 7 - 5 Bit 4 : Reserved. : IRQ Filter Select =1 =0 Debounce Filter Enabled Debounce Filter Bypassed Select Alternate Function: Interrupt Steering. Select Basic I/O Function. Bit 3 : Select Function. =1 =0 Bit 2 Bit 1 : Reserved. : Polarity. =1 =0 Invert. No Invert. Input. Output. Bit 0 : In/Out selection. =1 =0 CRE2 (GP32, Default 0x01) Bit 7 - 4 Bit 3 : Reserved. : Select Function. =1 =0 Select Alternate Function: General Purpose Address Decode. Select Basic I/O Function. Publication Release Date: May 2006 Revision 0.6 - 153 - W83977ATF/W83977ATG Bit 2 Bit 1 Bit 0 : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRE3 (GP33, Default 0x01) Bit 7 - 4 Bit 3 : Reserved. : Select Function. =1 =0 Select Alternate Function: General Purpose Address Decode. Select Basic I/O Function. Bit 2 Bit 1 Bit 0 : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRE4 (GP34, Default 0x01) Bit 7 - 4 Bit 3 : Reserved. : Select Function. =1 =0 Select Alternate Function: Watch Dog Timer output. Select Basic I/O Function. Bit 2 Bit 1 Bit 0 : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRE5 (GP35, Default 0x01) Bit 7 - 2 Bit 1 Bit 0 : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRE6 (GP36, Default 0x01) Bit 7 - 2 Bit 1 Bit 0 : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output CRE7 (GP37, Default 0x01) Bit 7 - 2 Bit 1 Bit 0 : Reserved. : Polarity: 1: Invert, 0: No Invert : In/Out: 1: Input, 0: Output - 154 - W83977ATF/W83977ATG CRF1 (Default 0x00) Bit 7 - 3 Bit 2 : Reserved : SERIRQ =0 =1 The IRQ system is in normal mode. The IRQ system is in serial IRQ mode. Enable GP33 General Purpose Address Decode. Disable GP33 General Purpose Address Decode. Enable GP32 General Purpose Address Decode. Disable GP32 General Purpose Address Decode. Bit 1 Bit 0 =1 =0 =1 =0 *Note: If the logical device's activate bit is not set then bit 0 and 1 have no effect. 14.11 Logical Device A (ACPI) CR30 (Default 0x00) Bit 7 - 1 Bit 0 : Reserved. =1 =0 Activates the logical device. Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select PM1 register block base address [0x100:0xFFF] on 16-byte boundary. CR62, CR 63 (Default 0x00, 0x00) These two registers select GPE0 register block base address [0x100:0xFFF] on 4-byte boundary. CR64, CR 65 (Default 0x00, 0x00) These two registers select GPE1 register block base address [0x100:0xFFF] on 4-byte boundary. CR70 (Default 0x00) Bit 7 - 4 Bit 3 - 0 : Reserved. : These bits select IRQ resource for SCI . CRE0 (Default 0x00) Bit 7 : DIS-PANSWIN. Disable panel switch input to turn system power supply on. =0 =1 PANSWIN is wire-ANDed and connected to PANSWOUT . PANSWIN is blocked and can not affect PANSWOUT . Bit 6 : ENKBWAKEUP. Enable Keyboard to wake-up system via PANSWOUT . =0 =1 Disable Keyboard wake-up function. Enable Keyboard wake-up function. - 155 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Bit 5 : ENMSWAKEUP. Enable Mouse to wake-up system via PANSWOUT . =0 =1 Bit 4 =0 =1 Bit 3 =0 =1 Bit 2 =0 =1 Bit 1 =0 =1 4 Bit 0 =0 =1 Disable Mouse wake-up function. Enable Mouse wake-up function. Select click on Mouse Left-button twice to wake the system up. Select click on Mouse right-button twice to wake the system up. Disable CIR wake-up function. Enable CIR wake-up function. Keyboard/Mouse ports are not swapped. Keyboard/Mouse ports are swapped. Just clicking Mouse left/right-button twice can wake the system up. Any character received from Mouse can wake the system up (the setting of Bit is ignored). Only predetermined specific key combination can wake up the system. Any character received from Keyboard can wake up the system. : MSRKEY. Select Mouse Left/Right Botton to wake-up system via PANSWOUT . : CIRKEY. Select CIR wake-up system via PANSWOUT . : KB/MS Swap. Enable Keyboard/Mouse port-swap. : MSXKEY. Enable any character received from Mouse to wake-up the system. : KBXKEY. Enable any character received from Keyboard to wake-up the system. CRE1 (Default 0x00) Keyboard Wake-up Index Register This register is used to indicate which Keyboard Wake-up Shift register or Predetermined key Register is to be read/written via CRE2. The range of Keyboard wake-up index register is 0x00-0x19, and the range of CIR wake-up index range register is 0x20-0x2F. CRE2 Keyboard Wake-up Data Register This register holds the value of wake-up key register indicated by CRE1. This register can be read/write. CRE3 (Read only) Keyboard/Mouse Wake-up Status Register Bit 7-4 Bit 3 Bit 2 Bit 1 Bit 2 : Reserved. : CIR_STS. The Panel switch event is caused by CIR wake-up event. This bit is cleared by reading this register : PANSW_STS. The Panel switch event is caused by PANSWIN . This bit is cleared by reading this register. : Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is cleared by reading this register. : Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is cleared by reading this register. - 156 - W83977ATF/W83977ATG CRE4 This Register is reserved for test. CRE5 (Default 0x00) Bit 7 Bit 6-0 : Reserved. : Compared Code Length. When the compared codes are storage in the data register, these data length should be written to this register. CRE6 (Default 0x00) Bit 7-6 Bit 5-0 : Reserved. : CIR Baud Rate Dividor. The clock base of CIR is 32KHz, so that the baud rate is 32KHZ divided by (CIR Baud Rate Divisor+1). CRE7 (Default 0x00) Bit 7-3 Bit 2 Bit 1 Bit 0 : Reserved. : Reset CIR Power-On function. After used CIR power-on, the software should be write logical 1 to restart CIR power-on function. : Invert RX Data, When set 1, invert received data. : Enable Demodulation. When set 1, enable received signal to demodulation. When set 0, disable CRF0 (Default 0x00) Bit 7 : CHIPPME. Chip level power management enable. =0 =1 disable the ACPI/Legacy and the auto power management functions enable the ACPI/Legacy and the auto power management functions. disable the auto power management function. enable the auto power management function provided CRF0.bit7 (CHIPPME) is also set to 1. Bit 6 : IRPME. IR power management enable. =0 =1 Bit 5 - 4 Bit 3 : Reserved. Return zero when read. : PRTPME. Printer port power management enable. =0 =1 is disable the auto power management functions. enable the auto power management functions provided CRF0.bit7 (CHIPPME) also set to 1. disable the auto power management functions. enable the auto power management functions provided CRF0.bit7 (CHIPPME) also set to 1. disable the auto power management functions. Publication Release Date: May 2006 Revision 0.6 Bit 2 : FDCPME. FDC power management enable. =0 =1 is Bit 1 : URAPME. UART A power management enable. =0 - 157 - W83977ATF/W83977ATG =1 is Bit 0 =0 =1 is CRF1 (Default 0x00) enable the auto power management functions provided CRF0.bit7 (CHIPPME) also set to 1. disable the auto power management functions. enable the auto power management functions provided CRF0.bit7 (CHIPPME) also set to 1. : URBPME. UART B power management enable. These bits indicate that the individual device's idle timer expires due to no I/O access, no IRQ, and no external input to the device. These 5 bits are controlled by the IR, printer port, FDC, UART A, and UART B power down machines individually. Writing a 1 clears this bit, and writing a 0 has no effect. Note that the user is not supposed to change the status while the power management function is enabled. Bit 7 Bit 6 : Reserved. Return zero when read. : IRIDLSTS. IR idle status =0 =1 IR is now in the working state. IR is now in the sleeping state due to no IR access, no IRQ, the receiver is now waiting for a start bit, and the transmitter shift register is now empty in a preset expiry time period. Bit 5 - 4 Bit 3 Bit 2 Bit 1 Bit 0 : Reserved. Return zero when read. : PRTIDLSTS. Printer port idle status. =0 printer port is now in the working state. =1 printer port is now in the sleeping state due to no printer port access, no IRQ, no DMA acknowledge, and no transition on BUSY, ACK , PE, SLCT, and ERR pins in a preset expiry time period. : FDCIDLSTS. FDC idle status. =0 FDC is now in the working state. =1 FDC is now in the sleeping state due to no FDC access, no IRQ, no DMA acknowledge, and no enabling of the motor enable bits in the DOR register in a preset expiry time period : URAIDLSTS. UART A idle status. =0 UART A is now in the working state. =1 UART A is now in the sleeping state due to no UART A access, no IRQ, the receiver is now waiting for a start bit, the transmitter shift register is now empty, and no transition on MODEM control input lines in a preset expiry time period. : URBIDLSTS. UART B idle status. =0 UART B is now in the working state. =1 UART B is now in the sleeping state due to no UART A access, no IRQ, the receiver is now waiting for a start bit, the transmitter shift register is now empty, and no transition on MODEM control input lines in a preset expiry time period. - 158 - W83977ATF/W83977ATG CRF2 (Default 0x00) These bits indicate that the individual device wakes up due to any I/O access, IRQ, and external input to the device. The device's idle timer reloads the preset expiry depending on which device wakes up. These 5 bits are controlled by IR, the printer port, FDC, UART A, and UART B power down machines respectively. Writing a 1 clears this bit, and writing a 0 has no effect. Note that the user is not supposed to change the status while power management function is enabled. Bit 7 Bit 6 : Reserved. Return zero when read. : IRTRAPSTS. IR trap status. =0 =1 IR is now in the sleeping state. IR is now in the working state due to any IR access, any IRQ, the receiver begins receiving a start bit, and the transmitter shift register begins transmitting a start bit. Bit 5 - 4 Bit 3 : Reserved. Return zero when read. : PRTTRAPSTS. Printer port trap status. =0 =1 and Bit 2 =0 =1 the printer port is now in the sleeping state. the printer port is now in the working state due to any printer port access, any IRQ, any DMA acknowledge, and any transition on BUSY, ACK , PE, SLCT, ERR pins. FDC is now in the sleeping state. : FDCTRAPSTS. FDC trap status. FDC is now in the working state due to any FDC access, any IRQ, any DMA acknowledge, and any enabling of the motor enable bits in the DOR register. Bit 1 : URATRAPSTS. UART A trap status. =0 =1 UART A is now in the sleeping state. UART A is now in the working state due to any UART A access, any IRQ, the receiver begins receiving a start bit, the transmitter shift register begins transmitting a start bit, and any transition on MODEM control input lines. UART B is now in the sleeping state. UART B is now in the working state due to any UART B access, any IRQ, the receiver begins receiving a start bit, the transmitter shift register begins transmitting a start bit, and any transition on MODEM control input lines. Bit 0 : URBTRAPSTS. UART B trap status. =0 =1 CRF3 (Default 0x00) These bits indicate the IRQ status of the individual device. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. Bit 7 Bit 6 Bit 5 : Reserved. Return zero when read. : IRIRQSTS. IR IRQ status. : MOUIRQSTS. MOUSE IRQ status. Publication Release Date: May 2006 Revision 0.6 - 159 - W83977ATF/W83977ATG Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 : KBCIRQSTS. KBC IRQ status. : PRTIRQSTS. Printer port IRQ status. : FDCIRQSTS. FDC IRQ status. : URAIRQSTS. UART A IRQ status. : URBIRQSTS. UART B IRQ status. CRF4 (Default 0x00) Reserved. Return zero when read. CRF5 (Default 0x00) Reserved. Return zero when read. CRF6 (Default 0x00) These bits enable the generation of an SMI interrupt due to any IRQ of the devices. These 4 bits control the printer port, FDC, UART A, and UART B SMI logics respectively. The SMI logic output for the IRQs is as follows: SMI logic output = (URBIRQEN and URBIRQSTS) or (URAIRQEN and URAIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (PRTIRQEN and PRTIRQSTS) or (KBCIRQEN and KBCIRQSTS) or (MOUIRQEN and MOUIRQSTS) or (IRIRQEN and IRIRQSTS) Bit 7 Bit 6 : Reserved. Return zero when read. : IRIRQEN. =0 =1 Bit 5 =0 =1 Bit 4 =0 =1 Bit 3 =0 =1 Bit 2 =0 =1 disable the generation of an SMI interrupt due to IR's IRQ. enable the generation of an SMI interrupt due to IR's IRQ. disable the generation of an SMI interrupt due to MOUSE's IRQ. enable the generation of an SMI interrupt due to MOUSE's IRQ. disable the generation of an SMI interrupt due to KBC's IRQ. enable the generation of an SMI interrupt due to KBC's IRQ. disable the generation of an SMI interrupt due to printer port's IRQ. enable the generation of an SMI interrupt due to printer port's IRQ. disable the generation of an SMI interrupt due to FDC's IRQ. enable the generation of an SMI interrupt due to FDC's IRQ. - 160 - : MOUIRQEN. : KBCIRQEN. : PRTIRQEN. : FDCIRQEN. W83977ATF/W83977ATG Bit 1 : URAIRQEN. =0 =1 Bit 0 =0 =1 disable the generation of an SMI interrupt due to UART A's IRQ. enable the generation of an SMI interrupt due to UART A's IRQ. disable the generation of an SMI interrupt due to UART B's IRQ. enable the generation of an SMI interrupt due to UART B's IRQ. : URBIRQEN. CRF7 (Default 0x00) Bit 7 - 2 Bit 1 : Reserved. Return zero when read. : FSLEEP. This bit selects the fast expiry time of individual devices. =0 =1 1 second 8 milli-seconds Bit 0 : SMI_EN. This bit is the SMI output pin enable bit. When an SMI event is raised on the output of the SMI logic, setting this bit enables the SMI interrupt to be generated on the pin SMI . If this bit is cleared, only the IRQ status bit in CRF3 is set and no SMI interrupt is generated on the pin SMI . =0 =1 Disable SMI Enable SMI CRFE, FF (Default 0x00) Reserved. Reserved for Winbond test. - 161 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 15. SPECIFICATIONS 15.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage Input Voltage Battery Voltage VBAT Operating Temperature Storage Temperature RATING -0.5 to 7.0 -0.5 to VDD+0.5 4.0 to 1.8 0 to +70 -55 to +150 UNIT V V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 15.2 DC CHARACTERISTICS (Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V) PARAMETER Battery Quiescent Current Stand-by Power Supply Quiescent Current SYM. IBAT IBAT MIN. TYP. MAX. 2.4 2.0 UNIT uA mA CONDITIONS VBAT = 2.5 V VSB = 5.0 V, All ACPI pins are not connected. I/O8t - TTL level bi-directional pin with source-sink capability of 8 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V μA μA IOL = 8 mA IOH = - 8 mA VIN = VDD VIN = 0V I/O6t - TTL level bi-directional pin with source-sink capability of 6 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V μA μA IOL = 6 mA IOH = - 6 mA VIN = VDD VIN = 0V - 162 - W83977ATF/W83977ATG DC CHARACTERISTICS, continued PARAMETER Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage SYM. VIL VIH VOL VOH ILIH ILIL MIN. TYP. MAX. 0.3xVDD UNIT V V V V μA μA CONDITIONS I/O12 - CMOS level bi-directional pin with source-sink capability of 12 mA 0.7xVDD 0.4 3.5 + 10 - 10 IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V I/O16u - CMOS level bi-directional pin with source-sink capability of 16 mA, with internal pullup resistor Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 3.5 + 10 - 10 0.7xVDD 0.4 0.3xVDD V V V V μA μA IOL = 16 mA IOH = - 16 mA VIN = VDD VIN = 0V I/OD16u - CMOS level Open-Drain pin with source-sink capability of 16 mA, with internal pullup resistor Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 3.5 + 10 - 10 0.7xVDD 0.4 0.3xVDD V V V V μA μA IOL = 16 mA IOH = - 16 mA VIN = VDD VIN = 0V I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 2.0 0.8 0.4 + 10 - 10 V V V V μA μA IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V - 163 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/O24t - TTL level bi-directional pin with source-sink capability of 24 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output Low Voltage Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INc VIL VIH VOL VOH ILIH ILIL VOL VOH VOL VOH VOL VOL VIL VIH ILIH ILIL VIL VIH ILIH ILIL VtVt+ VTH ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 0.7×VDD 2.0 2.4 2.4 2.4 2.0 0.8 0.4 + 10 - 10 0.4 V V V V μA μA IOL = 24 mA IOH = - 24 mA VIN = VDD VIN = 0V IOL = 8 mA IOH = - 8 mA IOL = 12 mA IOH = -12 mA IOL = 12 mA IOL = 24 mA OUT8t - TTL level output pin with source-sink capability of 8 mA V V OUT12t - TTL level output pin with source-sink capability of 12 mA 0.4 V V OD12 - Open-drain output pin with sink capability of 12 mA 0.4 0.4 0.8 +10 -10 0.3×VDD +10 -10 1.7 3.8 V V V V μA μA OD24 - Open-drain output pin with sink capability of 24 mA INt - TTL level input pin VIN = VDD VIN = 0 V - CMOS level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage V V μA μA V VIN = VDD VIN = 0 V VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V V V +10 -10 μA μA - 164 - W83977ATF/W83977ATG DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS INcs - CMOS level Schmitt-triggered input pin INcu - CMOS level input pin with internal pull-up resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INts VIL VIH ILIH ILIL VtVt+ VTH ILIH ILIL VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.5 1.6 0.5 0.8 2.0 1.2 0.7xVDD 0.7xVDD +10 -10 1.1 2.4 +10 -10 1.1 2.4 +10 -10 V V μA μA VIN = VDD VIN = 0 V VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V - TTL level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage INtsu V V V μA μA - TTL level Schmitt-triggered input pin with internal pull-up resistor Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage V V V μA μA - 165 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 15.3 AC Characteristics 15.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. PARAMETER SA9-SA0, AEN, DACK , CS , setup time to IOR ¡õ SA9-SA0, AEN, DACK , hold time for IOR ¡ô SYM. TAR TAR TRR TFD TDH TDF TRI TAW TWA TWW TDW TWD TWI TMCY TAM TMA TAA TMR TMW TMRW TTC TRST TEST CONDITIONS MIN. 25 0 80 TYP. (NOTE 1) MAX. UNIT nS nS nS IOR width Data access time from IOR ¡õ Data hold from IOR ¡õ SD to from IOR ¡ô IRQ delay from IOR ¡ô SA9-SA0, AEN, DACK , setup time to IOW ¡õ SA9-SA0, AEN, DACK , hold time for IOW ¡ô CL = 100 pf CL = 100 pf CL = 100 pf 10 10 80 nS nS 50 360/570 /675 nS nS nS nS nS nS nS 25 0 60 60 0 360/570 /675 27 50 0 260/430 /510 0 0 6/12 /20/24 135/220 /260 1.8/3/3.5 IOW width Data setup time to IOW ¡ô Data hold time from IOW ¡ô IRQ delay from IOW ¡ô DRQ cycle time DRQ delay time DACK ¡õ DRQ to DACK delay nS μS nS nS nS nS nS μS nS μS DACK width IOR delay from DRQ IOW delay from DRQ IOW or IOR response time from DRQ TC width RESET width - 166 - W83977ATF/W83977ATG AC Characteristics, FDC continued PARAMETER SYM. TIDX TDST TSTD TSTP TSC TWDD TWPC TEST CONDITIONS MIN. 0.5/0.9 /1.0 1.0/1.6 /2.0 24/40/48 6.8/11.5 /13.8 Note 2 100/185 /225 100/138 /225 TYP. (NOTE 1) MAX. UNIT μS μS μS INDEX width DIR setup time to STEP DIR hold time from STEP STEP pulse width STEP cycle width WD pulse width Write precompensation 7/11.7 /14 Note 2 125/210 /250 125/210 /250 7.2/11.9 /14.2 Note 2 150/235 /275 150/235 /275 μS μS μS μS Notes:1. Typical values for T = 25° C and normal supply voltage. 2. Programmable from 2 mS through 32 mS in 2 mS increments. 15.3.2 UART/Parallel Port PARAMETER Delay from Stop to Set Interrupt Delay from IOR Reset Interrupt Delay from Initial IRQ Reset to Transmit Start Delay from to Reset interrupt Delay from Initial IOW to interrupt Delay from Stop to Set Interrupt Delay from IOR to Reset Interrupt Delay from IOR to Output Set Interrupt Delay from Modem Input Reset Interrupt Delay from IOR Interrupt Active Delay Interrupt Inactive Delay Baud Divisor SYMBOL TSINT TRINT TIRS THR TSI TSTI TIR TMWO TSIM TRIM TIAD TIID N TEST CONDITIONS MIN. 9/16 MAX. UNIT Baud Rate 100 pf Loading 1/16 100 pf Loading 9/16 1 8/16 175 16/16 1/2 μS Baud Rate nS Baud Rate Baud Rate nS nS nS nS nS nS 100 pF Loading 100 pF Loading 250 200 250 250 100 pF Loading 100 pF Loading 100 pF Loading 25 30 216-1 - 167 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 15.3.3 Parallel Port Mode Parameters PARAMETER PD0-7, INDEX , STROBE , AUTOFD Delay from SYM. t1 t2 t3 t4 t5 MIN. TYP. MAX. 100 60 105 UNIT nS nS nS nS nS IOW IRQ Delay from ACK , nFAULT IRQ Delay from IOW IRQ Active Low in ECP and EPP Modes 200 300 105 ERROR Active to IRQ Active 15.3.4 EPP Data or Address Read Cycle Timing Parameters PARAMETER Ax Valid to IOR Asserted IOCHRDY Deasserted to IOR Deasserted SYM. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 MIN. 40 0 10 40 0 0 0 0 60 0 0 0 60 0 60 0 0 60 1 0 0 0 60 10 0 0 MAX. UNIT nS nS IOR Deasserted to Ax Valid IOR Deasserted to IOW or IOR Asserted IOR Asserted to IOCHRDY Asserted PD Valid to SD Valid 10 nS 24 75 40 85 160 nS nS μS nS nS nS nS IOR Deasserted to SD Hi-Z (Hold Time) SD Valid to IOCHRDY Deasserted WAIT Deasserted to IOCHRDY Deasserted PD Hi-Z to PDBIR Set WRITE Deasserted to IOR Asserted WAIT Asserted to WRITE Deasserted Deasserted to WRITE Modified 185 190 50 180 nS nS nS nS nS nS IOR Asserted to PD Hi-Z WAIT Asserted to PD Hi-Z Command Asserted to PD Valid Command Deasserted to PD Hi-Z WAIT Deasserted to PD Drive WRITE Deasserted to Command PBDIR Set to Command PD Hi-Z to Command Asserted Asserted to Command Asserted 190 nS nS 20 30 195 180 12 nS nS nS nS nS nS μS WAIT Deasserted to Command Deasserted Time out PD Valid to WAIT Deasserted PD Hi-Z to WAIT Deasserted - 168 - W83977ATF/W83977ATG 15.3.5 EPP Data or Address Write Cycle Timing Parameters PARAMETER Ax Valid to IOW Asserted SD Valid to Asserted SYM. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 MIN. 40 10 10 0 10 40 0 60 0 0 60 60 0 0 10 5 60 60 0 10 0 0 MAX. UNIT nS nS nS nS nS nS IOW Deasserted to Ax Invalid WAIT Deasserted to IOCHRDY Deasserted Command Asserted to WAIT Deasserted IOW Deasserted to IOW or IOR Asserted IOCHRDY Deasserted to IOW Deasserted 24 160 70 nS nS nS nS WAIT Asserted to Command Asserted IOW Asserted to WAIT Asserted PBDIR Low to WRITE Asserted WAIT Asserted to WRITE Asserted WAIT Asserted to WRITE Change IOW Asserted to PD Valid WAIT Asserted to PD Invalid PD Invalid to Command Asserted 185 185 50 nS nS nS nS nS IOW to Command Asserted WAIT Asserted to Command Asserted WAIT Deasserted to Command Deasserted Command Asserted to WAIT Deasserted Time out Command Deasserted to WAIT Asserted 35 210 190 10 12 nS nS nS μS μS nS nS IOW Deasserted to WRITE Deasserted and PD invalid - 169 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 15.3.6 Parallel Port FIFO Timing Parameters PARAMETER DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive BUSY Inactive to PD Inactive BUSY Inactive to nSTROBE Active nSTROBE Active to BUSY Active SYMBOL t1 t2 t3 t4 t5 t6 MIN. 600 600 450 80 680 MAX. UNIT nS nS nS nS nS 500 nS 15.3.7 ECP Parallel Port Forward Timing Parameters PARAMETER nAUTOFD Valid to nSTROBE Asserted PD Valid to nSTROBE Asserted BUSY Deasserted to nAUTOFD Changed BUSY Deasserted to PD Changed nSTROBE Deasserted to BUSY Deasserted BUSY Deasserted to nSTROBE Asserted nSTROBE Asserted to BUSY Asserted BUSY Asserted to nSTROBE Deasserted SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 MIN. 0 0 80 80 0 80 0 80 MAX. 60 60 180 180 200 180 UNIT nS nS nS nS nS nS nS nS 15.3.8 ECP Parallel Port Reverse Timing Parameters PARAMETER PD Valid to nACK Asserted nAUTOFD Deasserted to PD Changed nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted nACK Deasserted to nAUTOFD Asserted PD Changed to nAUTOFD Deasserted SYMBOL t1 t2 t3 t4 t5 t6 MIN. 0 0 0 0 80 80 MAX. UNIT nS nS nS nS 200 200 nS nS - 170 - W83977ATF/W83977ATG 15.3.9 KBC Timing Parameters NO. DESCRIPTION MIN. MAX. UNIT T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 Address Setup Time from WRB Address Setup Time from RDB WRB Strobe Width RDB Strobe Width Address Hold Time from WRB Address Hold Time from RDB Data Setup Time Data Hold Time Gate Delay Time from WRB RDB to Drive Data Delay RDB to Floating Data Delay Data Valid After Clock Falling (SEND) K/B Clock Period K/B Clock Pulse Width Data Valid Before Clock Falling (RECEIVE) K/B ACK After Finish Receiving RC Fast Reset Pulse Delay (8 Mhz) RC Pulse Width (8 Mhz) Transmit Timeout Data Valid Hold Time Input Clock Period (6−12 Mhz) Duration of CLK inactive Duration of CLK active Time from inactive CLK transition, used to time when the auxiliary device sample DATA Time of inhibit mode Time from rising edge of CLK to DATA transition Duration of CLK inactive Duration of CLK active Time from DATA transition to falling edge of CLK 0 0 20 20 0 0 50 0 10 0 20 10 4 20 2 6 2 0 83 30 30 5 100 5 30 30 5 167 50 50 25 300 T28-5 50 50 25 3 30 40 20 4 nS nS nS nS nS nS nS nS nS nS nS μS μS μS μS μS μS μS mS μS nS μS μS μS μS μS μS μS μS - 171 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 15.3.10 GPIO Timing Parameters SYMBOL tWGO tSWP PARAMETER Write data to GPIO update SWITCH pulse width MIN. 16 MAX. 300(Note 1) UNIT ns msec Note: Refer to Microprocessor Interface Timing for Read Timing. - 172 - W83977ATF/W83977ATG 16. TIMING WAVEFORMS 16.1 FDC Processor Read Operation SA0-SA9 AEN CS DACK IOR TFD TDF D0-D7 TR IRQ TIDX TIDX INDEX TAR TRR TDH TRA WD Write Date TWDD Index Processor Write Operation SA0-SA9 AEN DACK IOW TWD D0-D7 TAW TWW TWA TC Terminal Count TTC Reset RESET TDW IRQ TWI TRST DMA Operation Drive Seek operation DRQ TAM TMCY DIR DACK IOW or IOR TMA TMRW TAA TDST STEP TSTP TSTD TMW (IOW) TMR (IOR) TSC - 173 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 16.2 UART/Parallel Receiver Timing SIN (RECEIVER INPUT DATA) STAR DATA BITS (5-8) PARITY STOP TSINT TRINT IRQ3 or IRQ4 IOR (READ RECEIVER BUFFER REGISTER) Transmitter Timing SERIAL OUT (SOUT) THRS IRQ3 or IRQ4 THR IOW (WRITE THR) THR TSI TIR IOR (READ TIR) STAR DATA (5-8) PARITY STOP (1-2) STAR TSTI - 174 - W83977ATF/W83977ATG 16.2.1 Modem Control Timing MODEM Control Timing IOW (WRITE MCR) RTS,DTR → │ │ │ │ │ │ │ │ CTS,DSR DCD IRQ3 or IRQ4 IOR (READ MSR) RI │ │ │ │ ? ← TMWO │ │ │ → │ │ │ │ │ │ │ │ ←TMWO → │← TSIM │ │ │ │ │ → │ │ │ │ → ←TRIM │ │ │ ←TSIM → ←TRIM TSIM │ ←→ │ │ │ │ │ │ ? │ │ │ ││ │ │ │ │ │ │ │ │ │ │ │ Printer Interrupt Timing │ │ │ │ │ │ │ │ │ │ │ ACK → IRQ7 │ │ │ │ │ ← TLAD → │ │ │ │ │ ←TLID - 175 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 16.3 Parallel Port 16.3.1 Parallel Port Timing IOW t1 INIT, STROBE AUTOFD, SLCTIN PD ACK t2 IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) t5 t2 IRQ t4 t3 t4 - 176 - W83977ATF/W83977ATG 16.3.2 EPP Data or Address Read Cycle (EPP Version 1.9) t3 A IOR t1 t6 SD t8 t5 IOCHRDY t10 t9 t2 t7 t4 t13 t14 WRITE t16 t17 PD t21 ADDRSTB DATASTB t22 t23 t25 t24 t15 t18 t19 t20 t26 t27 t28 WAIT - 177 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 16.3.3 EPP Data or Address Write Cycle (EPP Version 1.9) t3 t4 A10-A0 SD t1 IOW IOCHRDY t9 t10 t11 t13 t15 t16 t17 t2 t7 t8 t5 t6 WRITE PD t12 t14 DATAST ADDRSTB t18 t19 t20 t21 WAIT PBDIR t22 - 178 - W83977ATF/W83977ATG 16.3.4 EPP Data or Address Read Cycle (EPP Version 1.7) t3 A IOR t1 t6 t7 SD t8 t5 IOCHRDY t10 t9 t2 t4 t13 t14 WRITE t16 t17 PD t21 ADDRSTB DATASTB t22 t23 t25 t24 t15 t18 t19 t20 t26 t27 t28 WAIT - 179 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 16.3.5 EPP Data or Address Write Cycle (EPP Version 1.7) t3 t4 A10-A0 SD t1 IOW IOCHRDY t9 t10 t11 t13 t15 t16 t17 t2 t7 t8 t5 t6 WRITE PD t22 t22 DATAST ADDRSTB t18 t19 t20 WAIT 16.3.6 Parallel Port FIFO Timing t4 t3 PD t1 nSTROBE >| t2 > t5 >| >| >| t6 BUSY >| - 180 - W83977ATF/W83977ATG 16.3.7 ECP Parallel Port Forward Timing t3 nAUTOFD t4 PD t1 t2 t6 nSTROBE t5 BUSY t7 t5 t8 16.3.8 ECP Parallel Port Reverse Timing t2 PD t1 t3 nACK t5 nAUTOFD t6 t5 t4 - 181 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 16.4 KBC 16.4.1 Write Cycle Timing A2, CSB T1 T3 ACTIVE T7 T8 T5 WRB D0~D7 GA20 OUTPUT PORT FAST RESET PULSE RC FE COMMAND DATA IN T9 T17 T18 16.4.2 Read Cycle Timing A2,CSB AEN T2 T4 T6 RDB ACTIVE T10 T11 DATA OUT D0-D7 16.4.3 Send Data to K/B CLOCK (KCLK) SERIAL DATA (KDAT) T12 START D0 D1 D2 T14 D3 T13 D4 T19 D5 D6 D7 P STOP T16 - 182 - W83977ATF/W83977ATG 16.4.4 Receive Data from K/B CLOCK (KCLK) T15 T14 D0 D1 D2 D3 D4 T13 D5 D6 D7 P SERIAL DATA (T1) START T20 STOP 16.4.5 Input Clock CLOCK CLOCK T21 16.4.6 Send Data to Mouse MCLK T25 T22 T23 T24 MDAT START Bit D0 D1 D2 D3 D4 D5 D6 D7 P STOP Bit 16.4.7 Receive Data from Mouse MCLK T29 T26 T27 T28 MDAT START D0 D1 D2 D3 D4 D5 D6 D7 P STOP Bit - 183 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 16.5 GPIO Write Timing Diagram A0-A15 IOW D0-7 GPIO10-17 GPIO20-25 PREVIOUS STATE VALID VALID VALID tWGO 16.6 Master Reset (MR) Timing Vcc tVMR MR - 184 - W83977ATF/W83977ATG 17. APPLICATION CIRCUITS 17.1 Parallel Port Extension FDD JP13 WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK PD7 PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 JP 13A DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSB2 IDX2 RWC2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 EXT FDC PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram - 185 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 17.2 Parallel Port Extension 2FDD JP13 WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK DSA2/PD7 MOA2/PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 JP 13A DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSA2 DSB2 MOA2 IDX2 RWC2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 EXT FDC PRINTER PORT Parallel Port Extension 2FDD Connection Diagram 17.3 Four FDD Mode W83977ATF DSA DSB MOA MOB G2 A2 B2 74LS139 G1 A1 B1 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 7407(2) DSA DSB DSC DSD MOA MOB MOC MOD - 186 - W83977ATF/W83977ATG 18. ORDERING INFORMATION PART NO. KBC FIRMWARE REMARKS W83977ATF-AW W83977ATG-AW AMIKEY AMIKEY TM TM -2 -2 Lead-free package - 187 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG 19. HOW TO READ THE TOP MARKING The top marking of W83977ATF-AW inbond W 83977ATF-AW © A M. MEGA. 87-96 7 19AC27039520 1st line: Winbond logo 2nd line: the type number: W83977ATF-AW 3rd line: the source of KBC F/W -- American Megatrends Incorporated TM 4th line: Tracking code 719 A B 2 7039530 719: packages made in '97, week 19 A: assembly house ID; A means ASE, S means SPIL C: IC revision; B means version B, C means version C 2: wafers manufactured in Winbond FAB 2 7039530: wafer production series lot number The top marking of W83977ATG-AW inbond W 83977ATG-AW © A M. MEGA. 87-96 719AC27039520 1st line: Winbond logo 2nd line: the type number: W83977ATG-AW; G means lead-free package. 3rd line: the source of KBC F/W -- American Megatrends Incorporated TM 4th line: Tracking code 719 A B 2 7039530 719: packages made in '97, week 19 A: assembly house ID; A means ASE, S means SPIL C: IC revision; B means version B, C means version C 2: wafers manufactured in Winbond FAB 2 7039530: wafer production series lot number - 188 - W83977ATF/W83977ATG 20. PACKAGE DIMENSIONS (128-pin QFP) HE E 102 65 Symbol Dimension in mm Dimension in inch Min 0.25 2.57 0.10 0.10 13.90 19.90 Nom 0.35 2.72 0.20 0.15 14.00 20.00 0.50 Max 0.45 2.87 0.30 0.20 14.10 20.10 Min 0.010 0.101 0.004 0.004 0.547 0.783 Nom 0.014 0.107 0.008 0.006 0.551 0.787 0.020 Max 0.018 0.113 0.012 0.008 0.555 0.791 103 64 D HD 128 39 1 e b 38 A1 A2 b c D E e HD HE L L1 y 0 c 17.00 23.00 0.65 17.20 23.20 0.80 1.60 17.40 23.40 0.95 0.669 0.905 0.025 0.677 0.913 0.031 0.063 0.685 0.921 0.037 0.08 0 7 0 0.003 7 Note: 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec. A A2 See Detail F Seating Plane A1 L L1 Detail F y 5. PCB layout please use the "mm". - 189 - Publication Release Date: May 2006 Revision 0.6 W83977ATF/W83977ATG Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 190 -