W86L387D

W 86L387D Winbond Host Interface Memory StickTM Bridge W86L387D Data Sheet Revision History Pages 1 2 3 4 5 6 7 8 9 10 Dates 07/2001 08/2002 Version 0.50 0.60 Version on Web First published. Main Contents Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W86L387D PRELIMINARY TABLE OF CONTENT 1. General Description ...........................................................................................................................1 2. Features...............................................................................................................................................1 3. Pin Configuration ...............................................................................................................................2 4. Pin Descriptions .................................................................................................................................3 5. Block Diagram ....................................................................................................................................5 6. Registers .............................................................................................................................................6 6.1 Register Map .............................................................................................................................6 7. Functional Description ......................................................................................................................7 7.1 Host Interface ............................................................................................................................7 7.2 DMA Access ............................................................................................................................11 8. Electrical Characteristics ................................................................................................................13 8.1 Maximum Ratings*...................................................................................................................13 8.2 Recommended Operating Conditions .....................................................................................13 8.3 Power Supply Characteristics..................................................................................................13 8.4. Digital Characteristics .............................................................................................................14 8.5. Timing Characteristics ............................................................................................................14 9. How To Read The Top Marking.......................................................................................................19 10. Package Dimensions .....................................................................................................................20 11. Reference Schematic .....................................................................................................................21 -I- Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 1. GENERAL DESCRIPTION The W86L387D is a Memory StickTM host interface bridge used between host microprocessor and Memory StickTM. The data width of host microprocessor can be 8-bit or 16-bit. W86L387D can support synchronous or asynchronous type of host interface. It also supports DMA or Interrupt type of transfer mode to improve data transfer performance between host microprocessor and Memory StickTM. W86L387D is fit for most of IA devices, such as PDA, Cellular Phone, DSC, and MP3 player. 2. FEATURES • • • • • • • • • Compliant with Sony Memory StickTM spec. Version 1.3 Support two types of host microprocessor interface access--synchronous and asynchronous mode DMA and Interrupt transfer mode supported Host microprocessor data bus can be 8-bit or 16-bit Built-in crystal driver circuit, support external oscillator or crystal clock input Extra 8 programmable GPIO supported Wide range of clock input up to 20Mhz 3.3V opereation 48-pin LQFP package Ordering Information Part Number W86L387D Package Type 48-PIN LQFP Production Flow Commercial, 0oC to +70oC The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation All trademarks and brand names belong to their respective owners -1- Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 3. PIN CONFIGURATION XDAKN/XASN XDRQN/XRDYN XWRHN/XBE0 XWRLN/XBE1 XRDN/XRWN XCSN HCKI PO3 PO2 A2 A1 XTYP D15/A0 D14 VSS VDD D13 D12 D11 D10 D9 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 39 40 41 42 43 44 45 46 47 48 1 D8 2 D7 3 D6 4 D5 5 D4 6 VSS 7 D3 8 D2 23 22 21 20 19 18 17 16 15 14 13 9 10 11 12 D1 D0 XINTN RSTN VSS A3 PO1 PO0 PI3 PI2 PI1 PI0 VDD VSS MS3 MS2 MS1 XTO XTI Fig.3-1 W86L387D Pin Assignment. -2- Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 4. PIN DESCRIPTIONS Pin 15 16 17 13 14 28 35 36:38 40 Name MS1 MS2 MS3 XTI XTO HCKI XCSN A[3:1] D15/A0 Type DO DO/DI DO DI DO DI DI DI DI/DO Description Memory stick connect pin #1 Memory stick connect pin #2 Memory stick connect pin #3 From 3.58MHz to 20MHz Clock driver input signal, can be used as external clock input. Clock driver output signal. Host clock input. Only used in Type2. Chip select input pin, active low. Address input pins. Data bus D15 pin, D[15:8] is the high byte of the data bus, D15 also used as A0 when 8-bit Host data size. In 8-bit mode, internal register high byte (D15:8) will accessed at data bus [7:0] when A0 = 1, low byte (D7:0) will accessed at data bus [7:0] when A0 = 0. 41 44:48 1:5 7:10 33 D14 D[13:9] D[8:4] D[3:0] XWRHN/ XBE0 DI/DO DI/DO DI/DO DI/DO DI Data bus D14 pin. Data bus [13:9] pins. Data bus [8:4] pins, D[7:0] is the low byte of the data bus. Data bus [3:0] pins. Type 1: High byte (D15 to D8) write control pin, active low. Type 2: High byte (D15 to D8) data valid pin, active low. 34 XWRLN/ XBE1 DI Type 1: Low byte (D7 to D0) write control pin, active low. Type 2: Low byte (D7 to D0) data valid pin, active low. MS Interface: Crystal Driver: Host Interface: -3- Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 4. Pin Descriptions, continued Pin 32 Name XRDN/ XRWN Type DI Type 1: Description Read control pin, active low. Type 2: Read write control pin, 1: read 0: write 11 30 XINTN XDAKN/ XASN DO DI Interrupt request pin, active low. Type 1: DMA transfer acknowledge pin, active low. Type 2: Bus access cycle start pin, active low. 29 XDRQN/ XRDYN DO Type 1: DMA transfer request pin, active low. Type 2: Bus cycle complete pin, active low. 39 XTYP DI Host interface type 2 select pin, 0 : type 1 mode. 1 : type 2 mode. GP I/O Port: 23:20 27:24 Other: 12 Power: 19,43 6,18, 31,42 Type: DP is Power, DI is Digital Input, DO is Digital Output. VDD x2 VSS x4 DP DP Power supply 3.3V (2 pins). Ground (4 pins). RSTN DI Reset input, hardware reset input, active low. PI[3:0] PO[3:0] DI DO 4-bit parallel port input signal. 4-bit parallel port output signal. -4- Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 5. BLOCK DIAGRAM HCKI XTYP2 RSTN VDD VSS XCSN A[3:1] XASN XRDYN XWRLN/XBE1 XWRHN/XBE0 XRDN/XRDWRN A0 D[15:0]/ D[7:0] XDRQN XDAKN XINTN Address Decode Read /Write Controller Host I/F Type Select Parallel Port Registers PI[3:0] PO[3:0] Register File MS Access Circuit MS1 MS3 Data Packing Circuit 8 Byte FIFO 8 Byte FIFO Serial to Parallel MS2 Parallel to Serial Crystal Driver DMA Circuit Interrupt Circuit XTI XTO Fig. 5-1 Block Diagram of W86L387D -5- Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 6. REGISTERS 6.1 Register Map The register in the W86L387D is consisted of command, status, control, received/transmit data buffer, interrupt, DMA and parallel port registers and READY register in Host interface type 2, these registers are listed as follows: Addr A[3:1] 000 Register Name (note 1) Command Reg. (R/W) 0 001 Status Reg. (RO) 0 001 Control Reg. (R/W) 0 B1 5 B1 4 B1 3 B1 2 B1 1 B1 0 Content (note 2) B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 PID code 0 0 0 0 0 0 0 1 0 0 Data size 0 0 0 0 0 0 0 - Status 1 - Control 0 0 0 0 1 0 1 010 Receive Data Buffer (R/O) 0 0 0 0 0 0 Receive data buffer 0 0 0 0 0 0 0 0 0 0 010 Transmit Data Buffer (WO) X X X X X X Transmit data buffer X X X 0 0 0 PI[3:0] X X X X X PO[3:0] X X X 0 F 0 PIEN[3:0] 0 0 0 0 POEN[3:0] 0 0 0 0 0 Interrupt control X X X X X X X - 011 Interrupt Status Reg. (RO) 1 0 0 - Interrupt status 0 - 011 Interrupt Control Reg. (R/W) Parallel Port Data Reg. ([15:12]RO, [11:8]R/W) Parallel Port Control Reg. (R/W) Ready Control Reg. (R/W) - 100 100 101 111 Data Size Reg. (R/W) - - - - - - - - 0 0 0 0 0 0 0 8bit 0 Note 1: R/W means the register can be read and write. RO means the register is read only. WO means the register is write only. Note 2: The data bit in the content is the initial value during hardware reset. 0: the bit value is 0. 1: the bit value is 1. X: the bit value is unknown. -: Undefined bit in the register and the value will read 0. -6- Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 7. FUNCTIONAL DESCRIPTION 7.1 Host Interface The Host interface type may be type 1 or type 2 and the data size of the data bus may be 16-bit or 8-bit. Host Interface Type 1: The Host interface type 1 is selected when XTYP pin is low. The data size of the CPU data bus may be 16-bit or 8-bit. Figure 7-1 shows the timing of 16-bit CPU read and write in type 1, figure 7-2 and 7-3 show the timing of CPU 8-bit data bus read and write in type 1. A[3:1] D[15:0] XCSN XRDN XWRHN XWRLN DO[15:0] DI[15:0] Fig. 7-1 16-bit Read and Write Access in Host I/F Type 1. -7- Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY A[3:1] A0(D15) D[7:0] XCSN XRDN Register bit [15:8] will be read. Register bit [7:0] will be read. DO[15:8] DO[7:0] Fig. 7-2 CPU 8-bit Data Bus Read Access in Host I/F Type 1. A[3:1] A0(D15) D[7:0] XCSN XWRLN Register bit [15:8] will be write. Register bit [7:0] will be write. DI[15:8] DI[7:0] Fig. 7-3 CPU 8-bit Data Bus Write Access in Host I/F Type 1. -8- Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY The data is located at bit [7:0] when the data size of Host CPU is 8-bit, the address bit 0 (A0) = 1 is to access the register data bit [15:8], A0 = 0 to access data bit [7:0]. Host Interface Type 2: The Host interface type 2 is selected when XTYP pin is high. The data size of the CPU data bus may be 16-bit or 8-bit and the access cycle may be in 3-cycle or 3-cycle. Figure 7-4 shows the timing of 16-bit CPU read write in type 2 and the access cycle is 3-cycle access, figure 7-5 shows the timing of 16-bit CPU read write in type 2 and the access cycle is 2-cycle access. HCKI A[3:1] D[15:0] XCSN XASN XRDYN XRWN XBE[1:0] Read cycle Write cycle DO[15:0] DI[15:0] Fig. 7-4 16-bit Read and Write Access in Host I/F Type 2, 3-Cycle Access. -9- Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY HCKI A[3:1] D[15:0] XCSN XASN XRDYN XRWN XBE[1:0] Read cycle Write cycle DO[15:0] DI[15:0] Fig. 7-5 16-bit Read and Write Access in Host I/F Type 2, 2-Cycle Access. - 10 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 7.2 DMA Access DMA request XDRQN is used to notify the Host that the Host should write data to the transmit data buffer or read data from the receive data buffer in data write to the card or data read from the card. During data transmit to the card, the XDRQN will active if the data write command has been transfer to the card and the transmit data buffer have not enough data to transmit to the card. The XDRQN will not active if the transmit data buffer have enough data to transmit to the card. During data receive from the card, the XDRQN will active if the data read command has been transfer to the card and the data have been received in the receive data buffer. The XDRQN will not active if the data read command has been executed completely and the receive data buffer is read out. There are two types of DMA acknowledge waveform, the first type is configured if DAKEN = low, XDAKN is ignore and XDRQN will inactive after each access receive or transmit data buffer, the XDRQN will re-active after four clock later. Figure 7-6 shows the waveform of DMA access receive data buffer in DAKN = low. The second type is configured if DAKEN = high, XDAKN is used to count the transfer count of the data buffer, XDRQN will hold at active state until the data has been transferred completely. Figure 7-7 is the waveform of DMA access transmit data buffer in DAKN = high. System clock A[3:1] D[15:0] XCSN XRDN XDRQN XDAKN 010 010 Fig. 7-6 DMA Access Receive Data Buffer (DAKEN = low). - 11 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY System clock A[3:1] D[15:0] XCSN XWRHN XWRLN XDRQN XDAKN 010 010 Fig. 7-7 DMA Access Transmit Data Buffer (DAKEN = high). - 12 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 8. ELECTRICAL CHARACTERISTICS 8.1 Maximum Ratings* Parameter 1 Supply Voltage with respect to VVSS 2 Current at any pin other than supplies 3 Storage Temperature * Exceeding these values may cause permanent damage. Tst Symbol VVDD Rating -0.3 to 6 0 to 10 -65 to 150 Units V mA ℃ 8.2 Recommended Operating Conditions Characteristics 1 Operation Voltage (referenced to VSS pin). 2 Operation Voltage (referenced to VSS pin) (Note) 3 Clock Frequency at XTI pin 4 Operation Temperature Note: Clock frequency not guaranteed up to 20MHz. Symbol VVDD VVDD fXTL Top Rating 3.0 to 3.6 2.7to 3.0 20 0 to 70 Unit V V MHz ℃ 8.3 Power Supply Characteristics Parameter 1 Standby Supply Current 2 Operating Supply Current 3 Operating Supply Current Condition Power Supply (VVDD = 3.3V) Symbol IQ IVDD IVDD Min Typ‡ 2 4.7 3.5 Max 10 6 Units Test uA Test 1 mA Test 2 mA Test 3 ‡: Typical figure are at VDIVDD = 3.3V and temperature = 25 ℃ and are for design aid only, not guaranteed and not subject to production testing. Test 1: All input pins are VVDD or VVSS, configured as power down mode, output without loading and no clock input on the XTI and HCKI pins. Test 2: 20 MHz external clock input on the XTI pin, output without loading. Test 3: 20 MHz crystal connected at XTI and XTO pins, output without loading. - 13 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 8.4. Digital Characteristics Parameter 1 Output High Voltage 2 Output Low Voltage 3 Output High Voltage at CLK output 4 Output Low Voltage at CLK output 5 High Level Input Voltage 6 Low Level Input Voltage 7 Input Current 8 Input Capacitance Condition 2mA load 2mA sink 3mA load 3mA sink Symbol VOH VOL VOH VOL VIH VIL Iin Cin 10 0.7 0.3 1 0.9 0.1 Min 0.9 0.1 Typ‡ Max Units Notes VDD VDD VDD VDD VDD VDD uA pF 1 1 ‡: Typical figure are at VDVDD = 3.3V and temperature = 25 ℃ and are for design aid only, not guaranteed and not subject to production testing. Notes: 1: All output pins except CLK output. 8.5. Timing Characteristics Parameter Clock (figure 8-1) 1 XTI 2 XTI high pulse width 3 XTI low pulse width 4 XTI rise time 5 XTI fall time 5 XTO delay time 6 XTI crystal driver 7 HCLK frequency 8 HCLK high pulse width 9 HCLK low pulse width 10 HCLK rise time 11 HCLK fall time fXTI tXTIwh tXTIwl tXTIr tXTIf tXTOd fXTI fHCLK tHCLKwh tHCLKwl tHCLKI tHCLKf 1 10 10 3.58 1 10 10 20 5 5 5 20 30 5 5 MHz nS nS nS nS nS MHz MHz nS nS nS nS 1 1 1 1 1 2 3 Symbol Min Typ Max Units Notes - 14 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 8.5. Timing Characteristics,continued Parameter Reset 1 RSTN Host Interface at Type 1 (figure 8-2, 8-3) 1 Access time 2 Address setup time 3 Address hold time 4 D[15:0] output delay time 5 D[15:0] output hold time 6 D[15:0] input setup time 7 D[15:0] input hold time 8 DMA request delay time 9 DMA request hold time Host Interface at Type 2 (figure 8-4) 1 Input signals setup time 2 Input signals hold time 3 Address setup time 4 Address hold time 5 XRDYN delay time 6 XRDYN hold time 7 D[15:0] output delay time 8 D[15:0] output hold time 9 D[15:0] input setup time 10 D[15:0] input hold time Interrupt (figure 8-3) 1 Interrupt delay time Serial Interface Signals (figure 8-5) 1 MS1 output delay 2 MS2 output delay time 3 MS2 input setup time 4 MS2 input hold time Symbol tRST tacc tAsu tAh tDod tDoh tDsu tDh tDRQd tDRQh tIF2su tIF2h tA2su tA2h tRDYd tRDYh tDod tDoh tDsu tDh tINTd tMS1d tMS2d tMS2su tMS2h Min 4 100 10 5 10 10 5 5 10 5 10 5 5 10 10 5 0 10 5 Typ - Max 30 20 20 30 20 5 30 - Units cycle nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS Notes 4 5,6 5,7 8 9 2 2 10 10 2 2 5 5 2 2 - 15 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY Note 1: External clock input. Note 2: 20 pF output loading. Note 3: Crystal driver. Note 4: Minimum active pulse width of (XCSN and XRDN) or (XCSN and XWRHN and XWRLN). Note 5: 40 pF output loading. Note 6: From the last active signal of XCSN or XRDN. Note 7: From the first in-active signal of XCSN or XRDN. Note 8: To the first in-active signal of XCSN, XWRHN or XWRLN, XWRHN or XWRLN related to the D[15:8] or D[7:0]. Note 9: From the first in-active signal of XCSN, XWRHN or XWRLN, XWRHN or XWRLN related to the D[15:8] or D[7:0]. Note 10: XCSN, XASN, XRWN and XBE[1:0] signals. XTI tXTOd tXTIwh tXTIf tXTIwl tXTIr XTO HCKI tHCKIr tHCKIwh tHCKIf tHCKIwl Fig. 8-1 Timing Characteristic of XTI, XTO and HCKI. - 16 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY A[3:1] tAsu tAh DO[15:0] DI[15:0] D[15:0] tDod tDoh tDsu tDh XCSN XRDN tacc XWRHN XWRLN tacc Fig. 8-2 Host Access Timing Characteristic in Host I/F Type 1. XTO tDRQd XDRQN tDRQh XDAKN tINTd XINTN Fig. 8-3 DMA and Interrupt Timing Characteristic. - 17 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY HCKI XCSN,XASN, XRWN,XBE[1:0] tIF2su tIF2h tA2su tA2h A[3:1] tRDYd tRDYh XRDYN tDsu tDh DI tDod tDoh DO Fig. 8-4 Host Interface Type 2 Timing Characteristic. XTO tMS1d tMS1d MS1 tMS2su tMS2h MS2 (input) tMS2d tMS2d MS2 (output) Fig. 8-5 Serial Interface Timing Characteristic. - 18 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 9. HOW TO READ THE TOP MARKING The top marking of W86L387D SMART@IO W86L387D 118GA01ASA 1st line: Winbond logo and SMART@IO Mark 2nd line: Part number of W86L387D 3rd line: Tracking code 118 G A 01A SA 118: packages made in '01, week 18 G: assembly house ID; A means ASE, O means OSE, G means GR A: IC revision; A means version A, B means version B 01A: for internal use SA: for internal use - 19 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 10. PACKAGE DIMENSIONS 48-LQFP(7x7x1.4mm footprint 2.0mm) H 36 25 24 37 H 48 13 1 12 θ Controlling dimension : Millimeters Symbol Dimension in inch Dimension in mm Min Nom Max 0.002 0.004 0.053 0.055 0.006 0.008 0.004 0.006 0.272 0.276 0.272 0.276 0.014 0.350 0.350 0.018 0.006 0.057 0.010 0.008 0.280 0.280 0.358 0.358 0.030 Min Nom Max 0.05 1.35 0.15 0.10 6.90 6.90 0.35 8.90 8.90 0.45 0.10 1.40 0.20 0.15 7.00 7.00 0.50 9.00 9.00 0.60 1.00 0.15 1.45 0.25 0.20 7.10 7.10 0.65 9.10 9.10 0.75 A A1 A2 b c D E e HD HE L L1 Y 0 0.020 0.026 0.354 0.354 0.024 0.039 0.004 0.10 0 7 0 7 - 20 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY 11. REFERENCE SCHEMATIC VCC33 VCC33 A[1..3] D[0..15] U1 VDD VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15/A0 A1 A2 A3 VSS VSS VSS VSS W86L387D D Q1 NDS352P RSTN XTYP XTI XTO HCKI 12 39 13 14 28 11 35 32 34 33 29 30 15 16 17 20 21 22 23 24 25 26 27 MS1 MS2 MS3 MS_CD MS_CD RESET XTYP1 XTI XTO HCKI XINT NCS5 NOE NWE NWEH R2 0 R5 10K R12 MS_PWEN 10K D D 19 43 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A1 A2 A3 10 9 8 7 5 4 3 2 1 48 47 46 45 44 41 40 38 37 36 6 18 31 42 + C1 10uF + C2 0.1u XINT XCSN XRDN/XRDWRN XWRLN/XBELN XWRHN/XBEHN XDRQN/XRDY XDAKN/XAS MS1 MS2 MS3 PI0 PI1 PI2 PI3 PO0 PO1 PO2 PO3 R13 0 NWE R14 R15 R16 R17 D D CON1 10K 10K 10K 10K R20 R21 R22 R25 47 47 47 47 1 2 3 4 5 6 7 8 9 10 11 VSS MS1 VCC MS2 Reserved MS_CD $PIN3 MS3 VCC VSS Case Card Scoket D LED_INS LED_RW MS_PWEN A[1..3] XTO RESET XTI Q2 XINT NCS5 NOE 20MHz C14 30p C15 30p NWE D[0..15] RESET XINT NCS5 NOE NWE To Intel StrongARM interface D D VCC33 VCC33 VCC33 R30 330 R31 330 + C3 0.1u + C4 0.1u + C5 10u + C7 0.1u + C8 0.1u + C9 0.1u + C10 0.1u D D D1 LED_INS D2 LED_RW LED_INS LED_RW Size Date: WINBOND ELECTRONICS CORP_ Document Number W86L387D Reference Schematic (for StrongARM) Thursday, July 05, 2001 Sheet 1 of 1 inbond Rev 1.1 - 21 - Publication Release Date: July 2001 Revision 0.50 W86L387D PRELIMINARY H eadquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, M in-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. - 22 - Publication Release Date: July 2001 Revision 0.50