W89C982

Preliminary W89C982AF INTEGRATED MULTIPLE REPEATER II GENERAL DESCRIPTION................................................................................................................. 2 FEATURES........................................................................................................................................ 2 ORDERING INFORMATION.............................................................................................................. 2 SYSTEM DIAGRAM .......................................................................................................................... 3 PIN CONFIGURATION ...................................................................................................................... 3 PIN DESCRIPTION ........................................................................................................................... 4 BLOCK DIAGRAM ............................................................................................................................. 8 FUNCTIONAL DESCRIPTION ........................................................................................................... 8 AUI Interface and Twisted Pair Line Transceiver ..........................................................................................8 Link Test Function.........................................................................................................................................8 Automatic Polarity Reversal Function ...........................................................................................................9 Port Partition/Reconnection Logic.................................................................................................................9 Port Status Direct Report Function ...............................................................................................................9 Initial State After Reset ...............................................................................................................................11 Management Logic and Management Interface .........................................................................................11 IMPR II Programmable Options..................................................................................................................15 The IMPR II Kernel Logic............................................................................................................................15 Inter-IMPR II Interface.................................................................................................................................16 ABSOLUTE MAXIMUM RATINGS ................................................................................................... 17 DC CHARACTERISTICS ................................................................................................................. 17 AC CHARACTERISTICS ................................................................................................................. 19 System Clock Timing..................................................................................................................................19 Reset Timing...............................................................................................................................................19 Management Bus Clock Timing..................................................................................................................20 Management Bus Carrier Sense Timing.....................................................................................................20 Inter-IMPR II Interface Input Timing ............................................................................................................21 Inter-IMPR II Interface Output Timing .........................................................................................................22 Inter-IMPR II Interface Collision Timing.......................................................................................................23 Inter-IMPR II Interface to AUI/TP Port Timing.............................................................................................23 Output Driver Timing...................................................................................................................................24 Repetition Timing (part 1) ...........................................................................................................................24 Repetition Timing (part 2) ...........................................................................................................................25 Link Test Timing..........................................................................................................................................26 PACKAGE DIMENSIONS ................................................................................................................ 28 -1- Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF GENERAL DESCRIPTION The Integrated Multiple Port Repeater II (IMPR II) implements the repeater functions specified by section 9 of the IEEE 802.3 standard and twisted pair line transceiver functions conforming to the 10BASE-T standard. The IMPR II provides eight Twisted Pair (TP) Line Transceiver Ports and an Attachment Unit Interface (AUI) port. Each Twisted Pair (TP) Line Transceiver Port can connect to an Ethernet segment through a twisted pair line. The AUI port can connect to a thick Ethernet segment by means of a 50-meter AUI cable. The IMPR II provides an AUI/TP port status direct report function, which uses the ten port status pins and two select pins to indicate collisions, port link/activity, partition, polarity, and network utilization. The inter-IMPR II interface includes signals for connecting more than one IMPR II to increase the total number of hub ports. The manageable functions of the repeater and twisted pair line transceiver in the IMPR II can be accessed through a serial interface. FEATURES • • • • • • • • • • • • • Functions conform to IEEE 802.3 section 9 specifications Single 5V power supply CMOS process for lower power dissipation Twisted-Pair (TP) line media interface compatible with 10 BASE-T specifications Differential interface compatible with AUI specifications Port status direct report function Asynchronous Inter-IMPR II interface for large hub applications Serial management interface allows for network management and makes port status information accessible AUI and TP port carrier sense signals observable through a port activity monitor port Internal main state machine performs fragment extension, packet repetition, and collision handling functions Internal jabber lockup protection state machine monitors the length of each input packet to prevent transmission of excessively large packets Separate partition state machine for each TP port and AUI port can isolate ports when an excessive number of collisions occur and reconnect them using certain algorithms On-chip PLL, Manchester encoder/decoder, and FIFO ORDERING INFORMATION TYPE NO. W89C982AF PACKAGE 100-pin QFP -2- Preliminary W89C982AF SYSTEM DIAGRAM Inter-IMPR II Interface Mngrmnt Controller IMPR II Mngrmnt Bus Preequalizer Port status direct report AUI Twisted-pair Media PIN CONFIGURATION T P D7 DR 4P -T TTTT PP PP 6543 T P 2 RR DD 77 +- DD TTV 77s +-s DD DDV 77D +-D D D D D DD D D D D T TDDTT DDV T TV 66665555 D4 4s +- +- +- + - D+- s D D 4 + R RRR VV R P PPPs DP T TTTs DT RD6RD6+ RD5RD5+ RD4RD4+ AVDD RD3RD3+ RD2RD2+ RD1RD1+ AVss RD0RD0+ DIDI+ CICI+ 877777777776666666666555555555 09876543 2109876 543210 9876543 21 81 50 82 49 83 48 84 47 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 46 45 44 43 42 TP1RPT TP0RPT AUIRPT XCOLRPT ICRS IDAT IDCLK DVss IJAM DV DD ICOL IBEN RST TEST DVss X2 X1 DV DD PCRS STR W89C982AF 41 40 39 38 37 36 35 34 33 32 31 1111111111 222 22222223 12345678901 23456789012 34567890 PD D DDV DDV DD L OOT T s DD DT T L - + 0 0 s 0 0 D1 1 V +++Ds Ds DD DD 11 +DD TT 22 +D D 2 + D V D D V D D MM MMM D D DT T s DD1 0 SCS V 2 D3 3 s 3 3 I LOs ++Ks P L L V -3- Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF PIN DESCRIPTION NETWORK INTERFACE PINS NAME DO+ DONO. 4 3 I/O O DESCRIPTION AUI Transmit Output: Differential line driver that sends differential signal to Medium Attached Unit (MAU). These pins require a 270 ohm pull-down resistor to GND. AUI Receive Input: Differential receiver that receives the AUI-compliant receive signal from MAU. AUI Collision Input: Differential receiver that receives the AUI-compliant collision signal from MAU. Data Positive: Transmit data driver positive that transmits data on the twisted pair line. The driver will source or sink 32 mA. The driver is low during idle. Data Negative: Transmit data driver negative that transmits inverted data on the twisted pair line. The driver will source or sink 32 mA. Driver is low during idle. Delayed Data Positive: Transmit data driver positive that transmits delayed inverted data on the twisted pair line. The driver will source or sink 32 mA. Driver is low during idle. Delayed Data Negative: Transmit data driver negative that transmits delayed data on the twisted pair line. The driver will source or sink 32 mA. Low during idle. Twisted Pair Line Receive Positive: Positive data from the twisted pair line are received by the internal receiver through this pin. Twisted Pair Line Receive Negative: Negative data from the twisted pair line are received by the internal receiver through this pin. INTER-IMPR II INTERFACE PINS ICRS DI+ DICI+ CIDT0+ to DT7+ DT0to DT7DD0+ to DD7+ DD0to DD7RD0+ to RD7+ RD0to RD7- 98, 97 I 100, 99 I 5, 11, 15, 20, 63, 68, 72, 78 6, 12, 16, 21, 62, 67, 71, 77 8, 13, 17, 23, 60, 66, 70, 75 9, 14, 18, 24, 59, 65, 69, 74 96, 93, 91, 89, 86, 84, 82, 80 95, 92, 90, 88, 85, 83, 81, 79 O O O O I I 46 O Inter-IMPR II Carrier Output: The inter-IMPR II carrier (an active low on this pin) will be present when the IMPR II is repeating packets. The IMPR IIs output this signal to the interface of inter-IMPR II for retransmitting valid packets or propogating network collision messages to other IMPR IIs. -4- Preliminary W89C982AF Continued INTER-IMPR II INTERFACE PINS NAME IBEN NO. 39 I/O I DESCRIPTION Inter-IMPR II interface Enable: IBEN is driven by HUB integrator. The integrator will drive the IBEN low if there is only one IMPR II which outputs ICRS to the inter-IMPR II interface. The IMPR II that asserts ICRS will be allowed to transmit valid messages to the IMPR II integrator when IBEN is low. Inter-IMPR II Collision: ICOL will be driven low when more than one IMPR II simultaneously output ICRS to the IMPR II integrator. The IMPR II will not transmit any data to the IMPR II integrator when ICOL is low. On this situation the collision messages will still be sent to all ports of the IMPR II. Inter-IMPR II Data Clock: IDCLK will drive a 10 MHz clock output when ICRS is asserted and IBEN is driven. If ICRS is not asserted and IBEN is driven, IDCLK will be driven by the IDCLK signal of another IMPR II. If a dumb hub is used, i.e., no IBEN is present, this pin is in high impedance. This pin is synchronous to IDAT data. Inter-IMPR II Data: The IMPR II sends/receives valid packets or inter-port collision messages to/from other IMPR IIs through the IDAT pin in NRZ format. IDAT is in high-Z state during inter-IMPR II collisions or when the network is idle. IDAT remains high when there is a transmit collision in the IMPR II. Inter-IMPR II IJAM: IJAM is driven low when a valid packet is being sent. IJAM is driven high when IDAT carries a collision message (i.e., always high or always low). IDAT = 0 indicates a multiport collision and IDAT = 1 indicates a single port collision condition. During inter-IMPR II collisions or when the network is idle, IJAM should be in high-Z state. MANAGEMENT BUS PINS IMPR II Reset: The IMPR II will be forced into its initial state when RST is driven low. Management Bus Clock: The management data are clocked by MCLK serially. The rising edge of MCLK will latch the data into or out of the IMPR II. ICOL 40 I IDCLK 44 I O IDAT 45 I O Z IJAM 42 I O Z RST 38 I MCLK 28 I -5- Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF Continued MANAGEMENT BUS PINS NAME MSI NO. 27 I/O I DESCRIPTION Management Data in: The management command is serially clocked into IMPR II by MCLK. Management Data Out: The network status or the internal management status of the IMPR II is serially read out from MSO whenever the IMPR II receives a status read command. IMPR II Test Mode: This pin should be tied high during test mode and tied low during normal operations. Network Port Carrier Sense: The carrier sense signals for the IMPR II's internal logic from the AUI port and eight TP ports are serially sampled and output through PCRS. The output bits are stream synchronized to X1 clock. Network Port Carrier Sense Strobe: The serial bit stream on PCRS can be latched by an external latch using the STR signal. The STR goes high for two X1 clock cycles after the nine carrier sense bits are output through PCRS. System Clock Input: An external 20 MHz system clock source is connected to this pin to provide the operating clock. For crystal applications, a 20 MHz crystal may be connected across pins X1 and X2. Crystal Clock Feedback: Pin X2 should be left floating when an external clock source is used. MSO 29 O TEST 37 I PCRS 32 O STR 31 O X1 34 I X2 35 O PORT STATUS DIRECT REPORT INTERFACE PINS M1 M0 25 26 I Port Status Direct Report Select Pins: These two pins control the output status of the port status pins. Four output states can be selected by M1, M0: TP AUI M1 M0 XCOLRPT 47 O Link/Activity Partition Polarity error COL/Activity Partition Loopback error 0 0 0 1 1 0 Utilization Utilization 1 1 Collision Status Direct Report Output: Whenever a collision event occurs, this pin is active high. This pin drives a TTL data buffer, which directly drives an LED. -6- Preliminary W89C982AF Continued PORT STATUS DIRECT REPORT INTERFACE PINS NAME AUI RPT TP0 RPT TP7 RPT NO. 48 I/O O DESCRIPTION AUI Port Status Direct Report Output: This pin outputs the AUI port status selected by M0/M1. This pin drives a TTL data buffer, which directly drives an LED. TP Port Status Direct Report Output: These pins output the TP port status selected by M0/M1. These pins drive a TTL data buffer, which directly drives an LED. POWER GROUND PINS VDD VSS AVDD 10, 19, 52, 64, 73 7, 22, 53, 61, 76 87 I TP Receive Power Supply: +5V DC power supply. This pin should be decoupled with a 22 µF capacitor and kept separate from other power and ground planes. AVSS PLL VDD PLL VSS DVDD DVSS 94 1 I I TP Receive Ground: Grounding pins. PLL Power Supply: +5V DC power supply. This pin should be decoupled with a 22 µF capacitor and kept separate from other power and ground planes. 2 33, 41 30, 36, 43 I I I PLL Ground: Grounding pins. Digital Power Supply: +5V DC power supply. Digital Ground: Grounding pins. I I Power Supply for TP Transmit/Port Status Pins: +5V DC power supply. Ground for TP Transmit/Port Status Pins. 49−51, 54−58 O -7- Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF BLOCK DIAGRAM Port Partition/ Reconnection Logic Rx MUX PLL Decoder MUX Twisted Pair Line Transceiver 1 Inter-IMPR II Interface . . . . . . Timer and Counters Main state Machine and Glue logic FIFO Control Logic FIFO Jabber lockup and Fragment extension Logic Preamble/ JAM Generator Twisted Pair Line Transceiver 8 Encoder and Transmitter Logic Tx MUX AUI Interface Management Logic Management Interface Port status direct report FUNCTIONAL DESCRIPTION The Integrated Multiple Port Repeater II implements the functions stipulated in the IEEE repeater specifications, the functions specified by 10BASE-T standards, and functions for network management. It provides an Inter-IMPR II interface to allow implementation of a repeater set with more network ports. The block functions of the IMPR II are described below. AUI Interface and Twisted Pair Line Transceiver The AUI provides an interface for an external Medium Attached Unit (MAU) connected to the IMPR II. The IMPR II can be used to connect a 10BASE2 or 10BASE5 Ethernet to a 10BASE-T Ethernet via a coaxial transceiver. The Twisted Pair Line Transceiver provides the interface used to connect IEEE 802.3 LAN stations (Data Terminal Equipment, or DTEs) into Ethernet networks constructed from twisted pair media. The Twisted Pair Line Transceiver also contains a link test function and autopolarity reversal function for wiring detection. Link Test Function The link test function of the TP port is used to check whether the TP port is linked to an active TP port. The TP port will enter link fail state if it does not receive any packets or link test pulses for more than 60 mS, until it receives either six consecutive link pulses or a packet. When the TP port is in link -8- Preliminary W89C982AF fail state, the IMPR II will not transmit any signal (packets or link pulses) on the TP port and the first input packet will not be retransmitted. The IMPR II will transmit link test pulses to any TP port after the transmitter of the TP port has been inactive for more than 16 mS after the TP port enters link good state. The link test function of the TP port is user-programmable using the management functions of the IMPR II. The TP port is forced into link good status if the link test function is disabled. The link test function is enabled by default each time the IMPR II is reset. Automatic Polarity Reversal Function The automatic polarity reversal function checks the polarity of the input data packets or link pulses. The polarity of the TP port will be set to negative when the polarity of the first input packet or the first three consecutive link pulses following reset or following entry of the TP port into link fail state are detected to be negative. Once the polarity of the TP port is set to negative, all consequent input packets will be retransmitted with data that are inverted with respect to the input packet after the TP port enters link good state. If the polarity of the TP port is not set to negative, all input packets will be retransmitted without any modification of the data polarity. Once the polarity of the TP port is determined, the polarity of this port will not be updated until the IMPR II is either reset or re-enters link fail state, regardless of whether the automatic polarity reversal function is disabled or enabled. The automatic polarity reversal function is user-programmable using the management functions of the IMPR II and is enabled by default each time the IMPR II is reset. The default status of polarity is "correct" when the IMPR II is in reset state. Port Partition/Reconnection Logic The port partition/reconnection logic implements the segment partitioning algorithm and the segment reconnection algorithm. These algorithms are defined by IEEE specifications and are used to protect the network from malfunctioning segments. There are nine partition/reconnection machines in an IMPR II. Each port partition reconnection machine controls an individual network port. A network port will be partitioned by the IMPR II when either of the following conditions is detected: (1) A collision condition exists continuously for a period of up to 1024 bit times. (2) Thirty-two consecutive collisions occur. A collision condition is defined as more than two network ports attempting to transmit simultaneously or as a receive collision from the AUI. The IMPR II can reconnect a partitioned network port using algorithms selected by programming the management logic. The following are the two reconnection algorithms: (1) Standard reconnection algorithm: A partitioned network port will be reconnected if a data packet longer than 512 bit times is retransmitted to or received from that port without collision. (2) Alternative reconnection algorithm: A partitioned network port will be reconnected if a data packet longer than 512 bit times is retransmitted to that port without collision. The reconnection algorithms for all the TP ports and the AUI port are programmed individually; however, all the TP ports use the same algorithm. The standard algorithm is selected by default each time the IMPR II is reset. Port Status Direct Report Function -9- Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF The IMPR II provides one pin (XCOLRPT) for collision status report, two pins (M0/M1) for port status report mode selection, and nine pins for port status report (AUIRPT, TP0-7RPT). XCOLRPT is active when a collision occurs. Each of the nine port status report pins can directly report four aspects of the port status. Which aspect of the network status is reported by these pins is determined by the two mode selection pins, M1 and M0, as shown in the table below. TP LINK/ACTIVITY AUI COL/ACTIVITY M1 M0 0 0 PARTITION 0 1 TP POLARITY AUI LOOPBACK ERROR 1 0 UTILIZATION UTILIZATION 1 1 When M0 and M1 are set to "0," the pins report TP link/activity and AUI COL/activity. In this mode, a low output on AUIRPT and TP0-7RPT means all the TP ports are in the link fail state, a high means all the TP ports are in link good state, and the AUI is in collision state, and a 10 Hz signal means incoming packets are being received by the AUI/TP ports. (Note that the 10 Hz signal is still reported if the ports are partitioned or disabled.) If M0 is set to "1" and M1 to "0," the port partition status will be reported. In this mode, a "0" output means that all the ports are connected correctly, and a "1" means that the AUI/TP ports are in a partition state. When M0 is set to "0" and M1 to "1," AUI loopback errors and TP polarity status will be reported. In this mode, a "0" output means that the AUI loopback and TP polarity are correct, and a "1" means that an AUI loopback error has been detected and the TP port polarity is reversed. If M0 and M1 are both set to "1," the network utilization will be reported. In this mode, each LED stands for 10% of utilization. The percentage of network utilization is shown the following table. % OF UTILIZATION AUI LED TP0 LED TP1 LED TP2 LED TP3 LED TP4 LED TP5 LED TP6 LED TP7 LED 10% 30% 50% 90% v v v v v v v v v v v v v v v v v v Using pins M1 and M0 and external transistors, the IMPR II can drive LEDs to indicate the status of the AUI/TP ports sequentially; the application circuit for the LEDs is shown below. If a simple decoder is connected to pins M1 and M0 and a switch circuit is connected to TP0RPT to TP7RPT, the TP port link/activity, partition, polarity, and network utilization can be displayed simultaneously. - 10 - Preliminary W89C982AF R R = 330 Collision LED W89C982AF XCOLRPT AUIRPT TP0RPT M1 M0 . . . . . TP7RPT . . . . R R = 330 TP7 status LED * Set M1, M0 to select port status output. Initial State After Reset When RST is driven low, the IMPR II is reset. The minimum time the reset signal must be held low to trigger a reset is 100 µS. During reset, the IMPR II places all outputs in the inactive state (except for the auto polarity reversal function). Active low outputs stay high, active high outputs stay low, link test is enabled, and the TP link is in a fail state. The AUI/TP auto partition/reconnection uses the standard algorithm, AUI/TP transmitters are idle, AUI/TP receivers are enabled, IDAT and IJAM are in highimpedance state, STR is low, and the auto polarity reversal function is enabled. Management Logic and Management Interface The major functions of the management logic are enabling/disabling networks, partitioning/reconnecting network ports, enabling/disabling the link test and autopolarity reversal functions of the twisted pair line transceiver, and accessing the link status and polarity status of the twisted pair line transceiver. The management interface is a signal bus that contains input/output signals to/from the management logic and the internal carrier sense signals for the nine network ports of the IMPR II. The management logic can accept and execute management commands when the IMPR II is in normal mode, i.e., the TEST pin of the IMPR II is tied low. All management commands are byteoriented and are clocked into the IMPR II serially by an external clock. Some of the commands require an output from the IMPR II in response and some do not. At least 20 clocks are required to send a command that requires an output response from the IMPR II; 14 clocks are needed to send a command that requires no response. The serial command data stream and any associated output response data stream are structured in a manner compatible with the RS232 serial data format, i.e., one start bit followed by eight data bits, with the LSB sent first and the MSB last. - 11 - Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF The following table summarizes the management commands. The LSBs of both the MSI data and the MSO data are shown on the right and the MSBs are shown on the left. Each command is described in more detail below. MSI INPUT DATA 11010000 11100000 10000000 10001111 11110000 10001111 10001011 10001101 10001001 00111111 00101111 00110bbb 00100bbb 01010bbb 01000bbb 01110bbb 01100bbb 00011111 00010000 00001CSA MSO READ DATA P7 . . . P0 P7 . . . P0 P7 . . . P0 P7 . . . P0 M0000000 PBSL0000 PBSL0000 PBSL0000 PBSL0000 None None None None None None None None None None None FUNCTIONS Read link test status of TP ports Read polarity status of TP ports Read partition status of TP ports Read bit rate error status of TP ports Read MJLP status Read AUI port status (B, S, L cleared) Read AUI port status (S, L cleared) Read AUI port status (B cleared) Read AUI port status (None cleared) Enable AUI port Disable AUI port Enable TP ports Disable TP ports Enable TP port link test function Disable TP port link test function Enable TP ports auto polarity reversal function Disable TP ports auto polarity reversal function Set AUI port alternate reconnection algorithm Set TP port alternate reconnection algorithm Set IMPR II programmable option Read Link Test Status of TP Ports The link test status of all eight TP ports can be read using this command. Bits 0 through 7 correspond to the link test status of TP ports 0 through 7. A "1" on the MSO bit indicates "Link Good" status and a "0" indicates "Link Fail" status. Read Polarity Status of TP Ports The polarity status of all eight TP ports can be read using this command. Bits 0 through 7 correspond to the polarity status of TP ports 0 through 7. A "1" on the MSO bit indicates reversed polarity and a "0" indicates positive polarity. Read Partition Status of TP Ports The partition status of all eight TP ports can be read using this command. Bits 0 through 7 correspond to the polarity status of TP ports 0 through 7. A "1" on the MSO bit indicates a connected status and a "0" indicates a partitioned status. - 12 - Preliminary W89C982AF Read Bit Rate Error Status of TP Ports The bit rate error status of the TP ports can be read using this command. Bits 0 through 7 correspond to the polarity status of TP ports 0 through 7. A "1" on the MSO bit indicates that a bit rate error has occurred and a "0" indicates no bit rate error has occurred. Read MJLP Status The MAU jabber lock-up protection status can be accessed using this command. A "1" on the MSB indicates the transmit function of the IMPR II has been inhibited. The status can also be cleared using this command. Read AUI Port Status The AUI port status, including partition, bit rate error, SQE test, and loopback error, can be accessed using different variations of this command. Four different specific commands can be used, as shown in the following table. MSI DATA 10001111 10001011 10001101 10001001 MSO DATA PBSL0000 PBSL0000 PBSL0000 PBSL0000 CLEAR BITS B, S, L read cleared. P not cleared. S, L read cleared. P, B not cleared. B read cleared. P, S, L not cleared. P, B, S, L not cleared. Enable AUI Port When disabled, the AUI port can be re-enabled using this command. The AUI port will then carry out normal transmitting and receiving operations. To reconnect a partitioned AUI port, the port must first be disabled and then re-enabled using this command. Disable AUI Port This command is used to disable the AUI port. When the AUI port is disabled, all inputs (the carrier sense and the SQE) to the AUI port will be ignored by the IMPR II and the IMPR II will not transmit any signal on the AUI port. In addition, the partition machine for the AUI port will be forced into idle status. Enable TP Ports This command is used to enable a disabled TP port, allowing it to perform normal transmitting and receiving operations. To reconnect a partitioned TP port or force a TP port into link fail state, the port must first be disabled and then re-enabled using this command. Disable TP Ports Each TP port can be disabled individually. Bits 0, 1, and 2 are used to indicate the TP port that is to be disabled, as follows: - 13 - Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 TP PORT DISABLED TP0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 When a TP port is disabled, all inputs (the carrier sense) to that port will be ignored by the IMPR II and the IMPR II will not transmit any signal on the port. The partition machine for the port will be forced into the idle state and the link test will indicate that the port is in the "Link Fail" state. Enable TP Port Link Test Function This command is used to re-enable a link-test disabled TP port. Using this command on a TP port that is already enabled will have no effect on the port. Disable TP Port Link Test Function The TP port link test function can be enabled or disabled port-by-port. Bits 0, 1, and 2 are used to select which TP port is to be disabled in the manner described under the "Disable TP ports" command above. Once the link test function is disabled, the TP port will not enter the link fail state. Enable TP Port Auto Polarity Reversal Function The auto polarity reversal function of the TP ports can be enabled or disabled port-by-port. Bits 0, 1, and 2 are used to indicate which TP port is to be enabled, in the manner described under the "Disable TP ports" command above. When the auto polarity reversal function is enabled, the TP port will check the polarity of input packets once it enters the link fail state. This function is enabled by default each time the IMPR II is reset. Disable TP Port Auto Polarity Reversal Function This command is used to disable the auto polarity reversal function of a TP port so that the port will no longer check the polarity of input packets. If an input packet with reversed data is received, the IMPR II will not correct the polarity and retransmit the packet to all the network ports. In this case, failure to reverse the polarity may cause a network error. Set AUI Port Alternative Reconnection Algorithm The partition/reconnection scheme can be programmed for the alternative (transmit only) reconnection algorithm using this command. To return the partition/reconnection logic of the AUI port back to the standard reconnection (transmit or receive) algorithm, the IMPR II must be reset. Set TP Port Alternative Reconnection Algorithm The partition/reconnection scheme can be programmed for the alternative (transmit only) reconnection algorithm using this command. To return the partition/reconnection logic of a TP port back to the standard reconnection (transmit or receive) algorithm, the IMPR II must be reset. - 14 - Preliminary W89C982AF The other main function of the management logic is the port activity monitoring function. The internal carrier sense signal of all network ports is sampled out serially. The accuracy of the carrier sense signals is 10 bit times. The first bit samples the internal carrier sense signal of the AUI port, the second bit samples TP0, the third bit samples TP1, and so forth. The tenth bit time is idle, and a strobe signal will be active during the tenth bit time. With the help of the strobe signal, the serial sampled carrier sense signal can be latched to a serial-to-parallel shifter. IMPR II Programmable Options Three IMPR II programmable options can set by this command via the appropriate bit in MSI data. The three programmable options are CI reporting, AUI SQE test mask, and alternative port activity monitor function, which correspond to bits C, S, and A, respectively. CI Reporting Setting bit C = 1 will alter the function of the STR pin. STR will become an input pin for repeater management devices and PCRS will insert the CI bit immediately before the AUI bit. AUI SQE Test Mask Setting S = 1 will disable the AUI SQE test when the SQE signal is within the SQE test window and no jam pattern will be asserted after transmitted packets. The SQE test window is from 6 bit times to 34 bit times. When the SQE signal is larger than the SQE test window, a collision condition has occurred. Alternative Port Activity Monitor Setting A = 1 will enable the alternative PAM function, so that repeater management devices can monitor the status of each port using the unmodified PCRS signal. The IMPR II Kernel Logic The kernel logic of the IMPR II includes a main state machine and glue logic, timers and counters, jabber lockup and fragment extension logic, a PLL decoder, encoder and transmitter, a 64-bit FIFO with FIFO control logic, and a preamble/jam generator. These blocks perform most of the operations needed to fulfill the requirements of the IEEE repeater specification. When a packet is received by a connected port, it is sent via the receive multiplexer to the PLL decoder. Data and collision status are sent to the main state machine via the port partition/reconnection logic. This enables the main state machine to determine the source of data to be repeated and the type of data to be transmitted. The transmit data may be either the received packet's data field or a preamble/jam pattern consisting of a 1010... bit pattern. Associated with the main state machine are a series of timers and counters which ensure that various IEEE specification times (referred to as the TW1 to TW6 times) are fulfilled. The PLL decoder decodes the received data from Manchester code format into NRZ format and recovers the jitter accumulated over the receiving segment. The preamble/jam generator and the FIFO compensate for the preamble bit loss caused by receptions by the twisted pair line transceiver. The FIFO is used to store the bits of the data field temporarily while the preamble/jam generator is sending the preamble of the transmitting packet. A 1010... jam pattern is generated under network collision conditions. The jabber lockup and fragment extension logic monitors the retransmitted packet. A jam pattern will be appended to short packets (less than 96 bits in length) to extend them to a full 96 bits. The jabber - 15 - Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF lockup and fragment extension logic will inhibit the encoder/transmitter logic when the retransmitted packet is more than 65536 bits in length. Packet repetition and network collision handling are performed by the main state machine according to IEEE specifications. Soon after the network port receiving data packet has been identified, the main state machine enables the preamble/jam generator to generate a preamble pattern onto the encoder/transmitter. While the preamble is being transmitted, the received data are still being monitored. The main state machine will enable the FIFO control logic to read the valid data into the FIFO when the start of frame delimiter "SFD" is detected. A 1011 bit pattern is filled into the FIFO before the SFD is detected. Removal of the FIFO data begins after a 60-bit preamble pattern has been sent. Inter-IMPR II Interface The inter-IMPR II interface are designed for large hub applications. The inter-IMPR II interface allows a minimum of four IMPR IIs to be integrated together to implement a hub with 32 twisted pair line ports and four AUI ports. An external integrator is needed to handle the IMPR IIs. The data transfers on the inter-IMPR II interface are in NRZ format and certain signals are used to indicate the network status. Signals included on the inter-IMPR II interface allow the IMPR IIs to cooperate with each other in an appropriate manner. Those signals include IDAT, IDCLK, IJAM, ICRS , IBEN , and ICOL . The ICRS , IBEN , ICOL , IJAM, are the control signals. The IDAT and IDCLK are used to transmit or receive data when the IMPR II asserts ICRS and the external integrator asserted IBEN and deasserted ICOL to each IMPR II. The IDAT and IDCLK transmit data and a 10 MHz clock to the IMPR II integrator. When the IMPR II has not asserted ICRS and the integrator has asserted IBEN and deasserted ICOL to each IMPR II , the IMPR II receives the data and a 10 MHz clock from IDAT and IDCLK. When IJAM is asserted, it indicates that a single port collision (IDAT = 1) or a multiport collision (IDAT = 0) is occurring. IMPR II Integrator ICRSBa IDATa, IBENBa, IDCLKa, ICOLBa IJAMa ICRSBb IDATb, IBENBb, ICRSBc IDCLKb, ICOLBb IJAMb IDATc, IBENBc, IDCLKc, ICOLBc IJAMc 982Aa 982Ab 982Ac X1a X1b X1c The figure above depicts an inter-IMPR II application circuit. The circuit requires an external inter IMPR II integrator. The external integrator integrated the ICRS signal from each IMPR II and generates signals, IBEN and ICOL , to the IMPR II. Each IMPR II checks IBEN , ICOL to handle the IDAT, IDCLK, IJAM signal direction. Note that the inter-IMPR II uses different clocks source (X1a, X1b, X1c, etc.) to construct a large scale repeater application. - 16 - Preliminary W89C982AF ABSOLUTE MAXIMUM RATINGS PARAMETER Operating Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering 10 seconds maximum) SYM. TA TS VDD VIN VOUT Tl MINIMUM 0 -55 -0.5 VSS -0.5 VSS -0.5 -55 MAXIMUM 70 150 7.0 VDD +0.5 VDD +0.5 250 UNIT °C °C V V V °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Power Supply (VDD = 4.75 to 5.25V, VSS = 0V, TA = 0° C to 70° C) PARAMETER Power Supply Current (idle) Power Supply Current (transmitting with no TP load) Power Supply Current (transmitting with TP load) SYMBOL IDDI IDDT IDDL TYPICA L - MAXIMU M 100 300 Note UNI T mA mA mA Note: For a TP typical load, each TP port will require an additional IDD current (maximum 32 mA). Less than 20% of the power will be dissipated by the IMPR II, the remaining power is dissipated by the external TP load. DC CHARACTERISTICS (VDD = 4.75V to 5.25V, VSS = 0V, TA = 0° C to 70° C) Digital PARAMETER Low Input Voltage High Input Voltage High Output Voltage (VDD = 4.5V) High Output Voltage (VDD = 4.5V) Input Leakage Current (Note 1) Input Current (Note 2) Output Leakage Current (VDD = 5.5V) Notes: 1. All of the input pins except those stated in Note 2. 2. TEST, IBENB, ICOLB, MSI, X1, M0, M1, these pins had been pull low or pull high. SYMBOL VIL VIH VOL VOH IIL1 IIL2 IOL MINIMUM VSS -0.5 3.85 2.4 MAXIMUM 0.8 VDD +0.5 0.4 10 500 10 UNIT V V V V µA µA µA - 17 - Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF AUI PARAMETER Input Current at CI+/-, DI+/- pairs Differential Output Voltage (DO+/-) Differential Output Voltage Imbalance (DO+/-) Undershoot Voltage (DO+/-) Differential Squelch Threshold (CI+/-, DI+/-) Differential Input Common Mode Voltage (DI+/-, CI+/-) SYM. IIA VDD VOB VU VDS VCM -175 1 +/-550 MIN. MAX. 2 +/-1200 40 100 -300 4.0 UNIT mA mV mV mV mV V Twisted Pair PARAMETER Power Supply Voltage Input Voltage RD+/- Differential Input Resistance RD+/- Differential Input Voltage (VDD = 5V) RD+/- Squelched Threshold RD+/- low Squelched Threshold RD+/- Input Switching Threshold DT+, DT-, DD+, DD- Imbalance Voltage DT+, DT-, DD+, DD- High Output Voltage DT+, DT-, DD+, DD- Low Output Voltage (I = 32 mA) DT+, DT-, DD+, DD- Output Current DT+, DT-, DD+, DD- Output Resistance Pad Capacitance SYM. VDD VIN RTI VTIV VTPS VTPU VRDT VTDU VTOH VTOL ITO RTO CLD VDD TP -0.44 MIN. 4.5 -0.3 ±0.3 ±300 ±150 ±5 TYP. 5.0 MAX. 5.5 VDD +0.3 10 ±3.1 UNI T V KΩ V mV mV mV mV V V mA ±400 ±220 ±10 ±585 ±300 ±20 ±40 VDD TP VDD TP +0.44 VSS TP 32 5 7 8 10 Ω pF - 18 - Preliminary W89C982AF AC CHARACTERISTICS (VDD = 4.75V to 5.25V, VSS = 0V, TA = 0° C to 70° C) System Clock Timing NO. 1 2 3 4 5 DESCRIPTION X1 clock rising time X1 clock falling time X1 clock period X1 clock high X1 clock low FIG. 1 1 1 1 1 49.995 22.5 22.5 MIN. TYP. MAX. 10 10 50.005 27.5 27.5 UNIT nS nS nS nS nS System Clock Timing Diagram 3 4 X1 1 2 5 Figure 1 Reset Timing NO. 1 2 3 DESCRIPTION Reset pulse width RST Low hold time with respect to X1 clock RST High setup time with X1 clock rising time FIG. 2 2 2 MIN. 100 5 20 TYP. MAX. UNIT µS nS nS Reset Timing Diagram X1 3 RST 2 1 Figure 2 - 19 - Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF Management Bus Clock Timing NO. 1 2 3 4 5 6 7 8 DESCRIPTION MCLK Clock Rising Time MCLK Clock Falling Time MCLK Clock Period MCLK Clock High MCLK Clock Low MSI Input Data Setup Time with Respect to MCLK Rising Edge MSI Input Data Hold Time with Respect to MCLK Rising Edge MSO Output Data Delay with Respect to MCLK Rising Edge FIG. MIN. MAX. UNIT 3 3 3 3 3 3 3 3 100 30 30 10 10 40 10 10 nS nS nS nS nS nS nS nS Management Bus Clock Timing Diagram 3 1 MCLK 4 5 6 MSI 7 2 8 MSO Figure 3 Management Bus Carrier Sense Timing NO. 1 2 3 DESCRIPTION X1 Rising Edge to STR High X1 Rising Edge to STR Low X1 Rising Edge to Valid PCRS FIG. 4 4 4 MIN. TYP. MAX. 40 40 40 UNIT nS nS nS Management Bus Carrier Sense Timing Diagram X1 PCRS 3 AUI TPO STR 1 2 Figure 4 - 20 - Preliminary W89C982AF Inter-IMPR II Interface Input Timing NO. 1 2 DESCRIPTION Receive-in IDAT/IJAM setup time to receive-in IDCLK rising Receive-in IDAT/IJAM hold time from receive-in IDCLK rising FIG. 5 5 MIN. 20 20 TYP. MAX. UNIT nS nS Inter-IMPR II Interface Input Timing Diagram High_Z IDCLK High_Z ICRSB IBENB ICOLB 1 IDAT IJAM 2 Figure 5 - 21 - Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF Inter-IMPR II Interface Output Timing NO. 1 2 3 4 DESCRIPTION ICRS asserted to IBEN asserted ICRS deasserted to IBEN deasserted FIG. 6 6 6 6 MIN. TYP. MAX. 35 35 UNIT nS nS nS nS Transmit-out IDAT/IJAM setup time to transmit-out IDCLK rising Transmit-out IDAT/IJAM hold time from transmit-out IDCLK rising 30 30 Inter-IMPR II Interface Output Timing Diagram High_Z High_Z IDCLK ICRS 1 2 IBEN ICOL IDAT IJAM 3 4 Figure 6 - 22 - Preliminary W89C982AF Inter-IMPR II Interface Collision Timing NO. 1 2 DESCRIPTION ICRS asserted to ICOL assertion ICRS deasserted to ICOL dessertion FIG. 7 7 MIN. TYP. MAX. 35 35 UNIT nS nS Inter-IMPR II Interface Collision Timing Diagram ICRS 1 2 ICOL IBEN Figure 7 Inter-IMPR II Interface to AUI/TP Port Timing NO. 1 2 DESCRIPTION Inter-IMPR II Interface to AUI Propagation Delay Inter-IMPR II Interface to TP Propagation Delay FIG. 8 8 MIN. TYP. 5 5 MAX UNIT Bits Bits Inter-IMPR II Interface to AUI/TP port Timing Diagram IDAT 1 Valid Data DI+/DT+ 2 DTDDDD+ Figure 8 - 23 - Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF Output Driver Timing NO. 1 DESCRIPTION DT+ to DD+ and DT- to DD- delay FIG. 9 MIN. 47 TYP. MAX. 53 UNIT nS Output Driver Timing Diagram Twister Pair Drivers DT+ DT1 DD1 DD+ Figure 9 Repetition Timing (part 1) NO. 1 2 3 4 DESCRIPTION Minimum AUI Start of Idle (SOI) Pulse Width Start of Idle Generated on Twisted Pair AUI to TP Propagation Delay AUI to Inter-IMPR II interface Propagation Delay FIG. 10 10 10 10 MIN. 200 250 TYP. 300 6 5 MAX. 350 UNIT nS nS Bits Bits Repetition Timing Diagram (part 1) 1 DI+/2 DT+ 3 DTDDDD+ 4 IDAT Valid Data Figure 10 - 24 - Preliminary W89C982AF Repetition Timing (part 2) NO. 1 2 3 4 DESCRIPTION Minimum Twisted Pair (SOI) Pulse Width TP to AUI Propagation Delay TP to TP Propagation Delay TP to Inter-IMPR II Interface Propagation Delay FIG. 11 11 11 11 MIN. 200 7 7 6 TYP. MAX UNIT nS Bits Bits Bits Repetition Timing Diagram (part 2) 1 RD+/2 DO+ DO3 DT+ DTDDDD+ 4 IDAT Valid Data Figure 11 - 25 - Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF Link Test Timing NO. 1 2 3 DESCRIPTION DT+ link pulse width Duration between transmitted link pulses Duration between received link pulses FIG. 12 12 12 3.8 MIN. TYP. 100 16 64 64 MAX. UNIT nS mS mS Link Test Timing Diagram 1 DT+ DTDDDD+ 2 TX+/Transmitted Link Pulse 3 RX+/Received Link Pulse Figure 12 AUI and DO+/- Switch Test Load DO+ 270 ohm 78 ohm 27 uH DO270 ohm - 26 - Preliminary W89C982AF Digital Output Switching Test Load 50 pF Pre-equalization Network 56 ohm DTX+ 390 ohm DDX+ 56 ohm DTX390 ohm DDXRDX+ 100 ohm RDXRxTxRx+ 1.21 Kohm Tx+ - 27 - Publication Release Date: November 1996 Revision A1 Preliminary W89C982AF PACKAGE DIMENSIONS 100-pin QFP HD D 100 81 1 80 Symbol Dimension in inches Dimension in mm Min 0.004 0.107 0.010 0.004 0.546 0.782 0.020 0.728 0.964 0.039 0.087 Nom Max 0.130 Min 0.10 Nom Max 3.30 E HE 30 51 A A1 A2 b c D E e HD HE L L1 y θ Notes: 0.112 0.012 0.006 0.551 0.787 0.026 0.740 0.976 0.047 0.095 0.117 0.016 0.010 0.556 0.792 0.032 0.752 0.988 0.055 0.103 0.004 2.718 0.254 0.101 13.87 19.87 0.498 18.49 24.49 0.991 2.21 2.845 0.305 0.152 14.00 20.00 0.65 18.80 24.80 1.194 2.413 2.972 0.407 0.254 14.13 20.13 0.802 19.10 25.10 1.397 2.616 0.102 0 12 0 12 31 e b 50 c A2 A θ L L1 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. Seating Plane See Detail F A1 y Detail F Headquarters Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Rm. 803, World Trade Square, Tower II, Winbond Memory Lab. No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 N. First Street, San Jose, FAX: 852-27552064 FAX: 886-3-5792646 CA 95134, U.S.A. http://www.winbond.com.tw/ TEL: 1-408-9436666 Voice & Fax-on-demand: 886-2-7197006 FAX: 1-408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 28 -