W90N740CD

W90N740CD/W90N740CDG DATA SHEET WINBOND 32-BIT ARM7TDMI-BASED MICRO-CONTROLLER The information described in this document is the exclusive intellectual property of Winbond Electronics Corporation and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes of W90N740-based system design. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Winbond Electronics Corp. -I- Publication Release Date: Aug. 18, 2005 Revision A6 W90N740CD/W90N740CDG Table of content1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES ................................................................................................................................. 1 BLOCK DIAGRAM ...................................................................................................................... 5 PIN CONFIGURATION ............................................................................................................... 6 PIN ASSIGNMENT ..................................................................................................................... 7 PIN DESCRIPTION................................................................................................................... 10 FUNCTIONAL DESCRIPTION ................................................................................................. 14 7.1 7.2 ARM7TDMI CPU Core.................................................................................................. 14 System Manager........................................................................................................... 15 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 Overview.........................................................................................................................15 System Memory Map......................................................................................................15 Address Bus Generation ................................................................................................17 Data Bus Connection with External Memory...................................................................18 Bus Arbitration ................................................................................................................28 Power-On Setting ...........................................................................................................29 System Manager Control Registers Map ........................................................................30 EBI Overview..................................................................................................................35 SDRAM Controller ..........................................................................................................36 External Bus Mastership.................................................................................................41 EBI Control Registers Map .............................................................................................41 On-Chip RAM .................................................................................................................56 Non-Cacheable Area ......................................................................................................56 Instruction Cache............................................................................................................56 Data Cache.....................................................................................................................59 Write Buffer ....................................................................................................................61 EMC Descriptors ............................................................................................................64 EMC Register Mapping ..................................................................................................70 NAT Process Flow........................................................................................................102 NATA Registers Map....................................................................................................103 GDMA Function Description .........................................................................................113 GDMA Registers Map...................................................................................................114 7.3 External Bus Interface (EBI) ......................................................................................... 35 7.3.1 7.3.2 7.3.3 7.3.4 7.4 Cache Controller........................................................................................................... 56 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.5 Ethernet MAC Controller (EMC) ................................................................................... 64 7.5.1 7.5.2 7.6 Network Address Translation Accelerator (NATA) ..................................................... 101 7.6.1 7.6.2 7.7 GDMA Controller ........................................................................................................ 113 7.7.1 7.7.2 - II - W90N740CD/W90N740CDG 7.8 7.9 7.10 USB Host Controller ................................................................................................... 121 7.8.1 7.9.1 7.10.1 7.10.2 7.10.3 USB Host Controller Registers Map .............................................................................122 UART Control Registers Map .......................................................................................140 General Timer Controller ............................................................................................150 Watch Dog Timer........................................................................................................150 Timer Control Registers Map......................................................................................151 Interrupt Sources ........................................................................................................157 AIC Registers Map .....................................................................................................158 GPIO Controller Registers Map ..................................................................................168 UART Controller ......................................................................................................... 139 TIMER Controller ........................................................................................................ 150 7.11 Advanced Interrupt Controller (AIC) ........................................................................... 156 7.11.1 7.11.2 7.12 8. General-Purpose Input/Output Controller (GPIO) ...................................................... 167 7.12.1 ELECTRICAL CHARACTERISTICS....................................................................................... 174 8.1 8.2 8.3 Absolute Maximum Ratings ........................................................................................ 174 DC Characteristics...................................................................................................... 175 8.2.1 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 USB Transceiver DC Characteristics............................................................................175 EBI/SDRAM Interface AC Characteristics ....................................................................176 EBI/External Master Interface AC Characteristics ........................................................176 EBI/(ROM/SRAM/External I/O) AC Characteristics ......................................................177 USB Transceiver AC Characteristics............................................................................178 EMC MII AC Characteristics .........................................................................................179 AC Characteristics ...................................................................................................... 176 9. 10. 11. 12. PACKAGE DIMENSIONS ....................................................................................................... 181 W90N740 REGISTERS MAPPING TABLE ............................................................................ 182 ORDERING INFORMATION .................................................................................................. 194 REVISION HISTORY .............................................................................................................. 194 - III - Publication Release Date: Aug. 18, 2005 Revision A6 W90N740CD/W90N740CDG 1. GENERAL DESCRIPTION The W90N740 micro-controller is 16/32 bit, ARM7TDMI based RISC micro-controller for network as well as embedded applications. An integrated dual Ethernet MAC, the W90N740, is designed for use in broadband routers, wireless access points, residential gateways and LAN camera. The W90N740N is built around The ARM7TDMI CPU core designed by Advanced RISC Machines, Ltd. And achieves 80MHz under worse conditions. Its small size, fully static design is particularly suitable for cost-sensitive and power-sensitive applications. It designs as Harvard architecture by offering an 8Kbyte I-cache/SRAM and an 2K-byte D-cache/SRAM with flexible configuration and two way set associative structure to balance data movement between CPU and external memory. Four stages write buffer also improves latency for write operations. The external bus interface (EBI) controller provides single bus architecture, 8/16/32 bit data width to access external SDRAM, ROM/SRAM, flash memory and I/O devices. It achieves same frequency as CPU core to minimize latency if internal cache misses. Memory controller supports different kinds of SDRAM types and configurations to ease system design. The System Manager includes an internal 32bit system bus arbiter and a PLL clock controller. Generic I/O bus is easily served as PCMCIA-like interface for 802.11b wireless LAN connection. Two 10/100Mb MACs of Ethernet controller is built in to reduce total system cost and increase performance between WAN and LAN port. Either MII or RMII of MAC is selected for external 10/100 PHY chip to design for varieties of applications. A powerful NAT accelerator (Patent Pending) between LAN and WAN reduces the software loading of CPU and speeds up performance between LAN and WAN. W90N740 integrates root hub of USB 1.1 host controller with one port transceiver and uses additional port with external transceiver if necessary, which can add valuable functions like flash disk, printer server, Bluetooth device via USB port. The important peripheral functions include one full wired high speed UART channel, 2-Channel GDMA, one watch-dog timer, two 24-bit timers with 8-bit prescale, 20 programmable I/O ports, and an advanced interrupt controller. 2. FEATURES Architecture • • • • Highly-integrated system for embedded Ethernet applications Powerful ARM7TDMI core and fully 16/32-bit RISC architecture Big /Little-Endian mode supported Cost-effective JTAG-based debug solution System Manager • • • • • System memory map & on-chip peripherals memory map The data bus width of external memory address & data bus connection with external memory Bus arbitration supports the Fixed Priority Mode & Rotate Priority Mode Power-On setting On-Chip PLL module control & Clock select control -1- Publication Release Date: Aug. 18, 2005 Revision A6 W90N740CD/W90N740CDG External Bus Interface (EBI) • • • • • External I/O Control with 8/16/32 bit external data bus Cost-effective memory-to-peripheral DMA interface SDRAM Controller supports up to 2 external SDRAM & the maximum size of each device is 32MB ROM/FLASH & External I/O interface Support for PCMCIA 16-bit PC Card devices On-Chip Instruction and Data Cache • • • • Two-way, Set-associative, 8K-byte I-cache and 2K-byte D-cache Support for LRU (Least Recently Used) Protocol Cache can be configured as an internal SRAM Support Cache Lock function Ethernet MAC Controller (EMC) • • • • • • • • • IEEE 802.3 protocol engine with programmable MII or RMII interface for 10/100 Mbits/s DMA engine with burst mode 256 bytes transmit & 256 bytes receive FIFO for MAC protocol engine and DMA access Built-in 16 entry CAM Address Register Support long frame (more than 1518 bytes) and short frame (less than 64 bytes) Re-transmit (during collision) the frame without DMA access Half or full duplex function option Support Station Management for external PHY On-Chip Pad generation NAT Accelerator (Patent Pending) • • • Hardware acceleration on IP address / port number look up and replacement for network address translation, including MAC address translation Provide 64 entries of translation table Support TCP / UDP packets GDMA Controller • • • • 2 Channel GDMA for memory-to-memory data transfers without CPU intervention Increase or decrease source / destination address in 8-bit, 16-bit, or 32-bit data transfers Supports 4-data burst mode to boost performance Support external GDMA request -2- W90N740CD/W90N740CDG USB Host Controller • • • • USB 1.1 compatible Open Host Controller Interface (OHCI) 1.1 compatible. Supports both low-speed (1.5 Mbps) and full-speed (12Mbps) USB devices. Built-in DMA for real-time data transfer UART • • • • • • • One UART (serial I/O) blocks with interrupt-based operation Full set of MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD) Fully programmable serial-interface characteristics: Break generation and detection False start bit detection Parity, overrun, and framing error detection Full prioritized interrupt system controls Timers • • • Two programmable 24-bit timers with 8-bit pre-scalar One programmable 24-bit Watch-Dog timer One-short mode, period mode or toggle mode operation Programmable I/Os • • 21 programmable I/O ports I/O ports Configurable for Multiple functions Advanced Interrupt Controller (AIC) • • • • • • 18 interrupt sources, including 4 external interrupt sources Programmable normal or fast interrupt mode (IRQ, FIQ) Programmable as either edge-triggered or level-sensitive for 4 external interrupt sources Programmable as either low-active or high-active for 4 external interrupt sources Priority methodology is encoded to allow for interrupt daisy-chaining Automatically mask out the lower priority interrupt during interrupt nesting GPIO Controller • Programmable as an input or output pin -3- Publication Release Date: Aug. 18, 2005 Revision A6 W90N740CD/W90N740CDG On-Chip PLL • • • One PLL for both CPU and USB host controller The external clock can be multiplied by on-chip PLL to provide high frequency system clock Programmable clock frequency, and the input frequency range is 3-30MHz; 15MHz is preferred. Operation Voltage Range • • 2.7 – 3.6 V for IO Buffer 1.62 – 1.98 V for Core Logic Operation Temperature Range • 0 – 70 Degree C Operating Frequency • 80 MHz (default) Package Type • 176-pin LQFP -4- W90N740CD/W90N740CDG 3. BLOCK DIAGRAM W90N740 TDMI Bus JTAG ICE ARM7TDMI Wrapper 8K-Byte I Cache 2K-Byte D Cache Cache Controller PLL Clock Controller AHB Arbiter UART COM Port AHB Decoder SDRAM EBI Bus External Bus Controller ROM Flash RAM PCMCIA IO Dev APB Bridge Interrupt Controller External Interrupts AHB Bus APB Bus TIMER x2 GDMA Controller WDT GPIO USB Device USB Host Controller Ethenet MAC Controller 0 NAT Accelerator Ethenet MAC Controller 1 PHY PHY Fig 3.1 W90N740 Functional Block Diagram -5- Publication Release Date: Aug. 18, 2005 Revision A6 W90N740CD/W90N740CDG 4. PIN CONFIGURATION GP17/nIRQ0 GP18/nIRQ1 GP19/nIRQ2 GP20/nIRQ3 GP5/nRTS GP6/nCTS GP10/TxD GP11/RxD VDD33 MDC0 MDIO0 TX0_EN VSS33 TX0D0 TX0D1 TX0D2 TX0D3 TX0_CLK COL0 CRS0 RX0_CLK RX0D0 VDD18 VSS18 RX0D1 RX0D2 RX0D3 RX0_DV RX0_ERR VDD33 XTAL EXTAL VSS33 RX1_ERR RX1_CLK RX1_DV RX1D0 RX1D1 RX1D2 RX1D3 AVDD18 AVSS18 DVDD18 DVSS18 175 170 165 160 155 150 145 140 135 130 5 TX1D0 TX1D1 TX1D2 TX1D3 TX1EN COL1 CRS1 MDIO1 VSS33 MDC1 TX1CLK VDD33 GP0 GP1 GP2 GP3 GP12/nWDOG GP13/TIMER0 GP14/TIMER1 TMS TDI VDD18 VSS18 TDO TCK nTRST nRESET GP15/nXDACK GP16/nXDREQ EMACK EMREQ nWAIT VDD33 nOE VSS33 nECS0 nECS1 nECS2 nECS3 nBTCS nSCS0 nSCS1 SDQM0 SDQM1 125 10 120 15 20 W90N740 176-Pin LQFP 115 110 25 105 30 100 35 95 40 90 50 55 60 65 70 75 80 85 USBVDD DP DN USBVSS GP9/nDSR GP8/nDTR GP7/nCD GP4/nRI D31 D30 D29 D28 D27 D26 VSS33 D25 VDD33 D24 D23 VDD18 VSS18 D22 D21 D20 D19 D18 D17 D16 D15 D14 VSS33 D13 VDD33 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 VSS33 D0 VDD33 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 VSS33 A13 VDD33 A12 VDD18 VSS18 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSS33 MCLK VDD33 nSCAS nSRAS nSWE MCKE NC NC SDQM3 SDQM2 Fig 4.1 176-Pin LQFP Pin Diagram -6- W90N740CD/W90N740CDG 5. PIN ASSIGNMENT Table 4 W90N740 Pins Assignment PIN NAME Clock & Reset EXTAL XTAL MCLK nRESET TAP Interface TCK TMS TDI TDO nTRST External Bus Interface A [24:22] A [21:0] D [31:16] D [15:0] nWBE [3:0]/ SDQM [3:0] nSCS[1:0] NSRAS NSCAS NSWE MCKE NC NC EMREQ EMACK nWAIT NBTCS nECS[3:0] NOE ( 78 pins ) 84-82 81-74, 72, 70,67-56 124-119, 117, 115-114, 111-105 104-103, 101, 99-88, 86 46-43 42, 41 51 52 50 49 48 47 31 30 32 40 39-36 34 ( 5 pins ) 25 20 21 24 26 164 163 54 27 176-PIN LQFP ( 4 pins ) -7- Publication Release Date: Aug. 18, 2005 Revision A6 W90N740CD/W90N740CDG Table 4 W90N740 Pins Assignment, continued PIN NAME Ethernet Interface (0) MDC0 MDIO0 COL0 / CRS0 / R1B_CRSDV TX0_CLK TX0D [3:0] / R1B_TXD [1:0], R0_TXD [1:0] TX0_EN / R0_TXEN RX0_CLK / R0_REFCLK RX0D [3:0] / R1B_RXD [1:0], R0_RXD [1:0] RX0_DV / R0_CRSDV RX0_ERR Ethernet Interface (1) MDC1 MDIO1 COL1 CRS1 TX1_CLK TX1D [3:0] / R1A_TX [1:0] TX1_EN /R1A_TXEN RX1_CLK / R1A_REFCLK RX1D [3:0] / R1A_RXD [1:0] RX1_DV / R1A_CRSDV RX1_ERR / R1A_RXERR 10 8 6 7 11 4-1 5 167 142 143 151 152 150 176-PIN LQFP ( 17 pins ) 149-146 144 153 159-157, 154 160 161 ( 17 pins ) 172-169 168 166 -8- W90N740CD/W90N740CDG Table 4 W90N740 Pins Assignment, continued NAME USB Interface DP DN Miscellaneous GP [20:17] / nIRQ [3:0] GP16 / nXDREQ GP15 /nXDACK GP14 / TIMER1/ SPEED GP13 / TIMER0/ STDBY GP12 /nWDOG GP11 /RxD GP10 /TxD GP9/nDSR/nTOE GP8 /nDTR/FSE0 GP7 /nCD / VO GP6 /nCTS/ VM GP5 /nRTS/ VP GP4 /nRI / RCV GP [3:0] Power/Ground VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS DVDD18 DVSS18 AVDD18 AVSS18 136-133 29 28 19 18 17 140 139 128 127 126 138 137 125 16-13 131 130 176-PIN LQFP ( 2 pins ) ( 21 pins ) (32 pins) 22, 69, 113, 155 23, 68, 112, 156 12, 33, 53, 71, 85, 100, 116, 141, 162 9, 35, 55, 73, 87, 102, 118, 145, 165 132 129 175 176 173 174 -9- Publication Release Date: Aug. 18, 2005 Revision A6 W90N740CD/W90N740CDG 6. PIN DESCRIPTION Table 6.1 W90N740 Pins Description PIN NAME IO TYPE PAD TYPE DESCRIPTION System Clock & Reset EXTAL XTAL MCLK nRESET TAP Interface TCK TMS TDI TDO nTRST ID IU IU O IU internal pulldown internal pull-up internal pull-up internal pull-up JTAG Test Clock, JTAG Test Mode Select, JTAG Test Data in, JTAG Test Data out JTAG Reset, active-low, I O O I External Clock / Crystal Input Crystal Output System Master Clock Out, SDRAM clock System Reset, active-low External Bus Interface A [24:22] A [21:0] D [31:16] D [15:0] nWBE [3:0]/ SDQM [3:0] nSCS [1:0] nSRAS nSCAS nSWE MCKE O IO IO IO Address Bus (MSB) of external memory and IO devices Address Bus of external memory and IO devices Data Bus (MSB) of external memory and IO device, Data Bus (LSB) of external memory and IO device Write Byte Enable for specific device(nECS[3:0]), IO Data input/output Mask signal for SDRAM (nSCS[1:0]), active-low These pins are always Output in normal mode, and Input type in internal SRAM test mode. SDRAM chip select for two external banks, active-low. Row Address Strobe for SDRAM, active-low Column Address Strobe for SDRAM, active-low SDRAM Write Enable, active-low SDRAM Clock Enable, active-high External Master Bus Request EMREQ ID internal pull-down This is used to request external bus. When EMACK active, indicates the bus grants the bus, chip drives all the output pins of the external bus to high impedance. External Bus Acknowledge External Wait, active-low ROM/Flash Chip Select, active-low External I/O Chip Select, active-low. ROM/Flash, External Memory Output Enable, active-low O O O O O - EMACK nWAIT nBTCS nECS [3:0] nOE O IU O IO O internal pull-up - - 10 - W90N740CD/W90N740CDG Pins Description, continued PIN NAME IO TYPE PAD TYPE DESCRIPTION MII Management Data Clock for Ethernet 0. It is the reference clock of MDIO0. Each MDIO0 data will be latched at the rising edge of MDC0 clock. MII Management Data I/O for Ethernet 0. It is used to transfer MII control and status information between PHY and MAC. Collision Detect for Ethernet 0 in MII mode. This shall be asserted by PHY upon detecting a collision happened over the medium. It will be asserted and lasted until collision condition vanishes. Carrier Sense for Ethernet 0 in MII mode. In RMII mode, external pull-up is necessary. Transmit Data Clock for Ethernet 0 in MII mode. TX0_CLK is driven by PHY and provides the timing reference for TX0_EN and TX0D. The clock will be 25MHz or 2.5 MHz. Transmit Data bus (4-bit) for Ethernet 0 in MII mode. The nibble transmit data bus is synchronized with TX0_CLK. It should be latched by PHY at the rising edge of TX0_CLK. In RMII mode, TX0D [1:0] are used as R0_TXD [1:0], 2-bit Transmit Data bus for Ethernet 0; Transmit Enable for Ethernet 0 in MII. It indicates the transmit activity to external PHY. It will be synchronized with TX0_CLK. In RMII mode, R0_TXEN shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all dibits to be transmitted are presented. Of course, it is synchronized with R0_REFCLK. Receive Data Clock for Ethernet 0 in MII mode When it is used as a received clock pin, it is from PHY. The clock will be either 25 MHz or 2.5 MHz. The minimum duty cycle at its high or low state should be 35% of the nominal period for all conditions. In RMII mode, this pin is used as R0_REFCLK, Reference Clock; The clock shall be 50MHz +/- 50 ppm with minimum 35% duty cycle at high or low state. Receive Data bus (4-bit) for Ethernet 0 in MII mode. They are driven by external PHY, and should be synchronized with RX0_CLK and valid only when RX0_DV is valid. In RMII mode, RX0D [1:0] are used as R0_RXD [1:0], 2-bit Receive Data bus for Ethernet 0; Receive Data Valid for Ethernet 0 in MII mode. It will be asserted when received data is coming and present, and de-asserted at the end of the frame. In RMII mode, this pin is used as the R0_CRSDV, Carrier Sense / Receive Data Valid for Ethernet 0. The R0_CRSDV shall be asserted by PHY when the receive medium is non-idle. Loss of carrier shall result in the de-assertion of R0_CRSDV synchronous to the cycle of R0_REFCLK, and only on nibble boundaries. Receive Data Error for Ethernet 0 in MII mode. It indicates a data error detected by PHY. The assertion should be lasted for longer than a period of RX0_CLK. When RX0_ERR is asserted, the MAC will report a CRC error. Ethernet Interface (0) MDC0 MDIO0 COL0 CRS0 TX0_CLK O IO I I I - TX0D [3:0]/ --, R0_TXD [1:0] O - TX0_EN / R0_TXEN O - RX0_CLK / R0_REFCLK I - RX0D [3:0] / --, R0_RXD [1:0] I - RX0_DV / R0_CRSDV I - RX0_ERR I - - 11 - Publication Release Date: Aug. 18, 2005 Revision A6 W90N740CD/W90N740CDG Pins Description, continued PIN NAME IO TYPE PAD TYPE DESCRIPTION MII Management Data Clock for Ethernet 1. It is the reference clock of MDIO1. Each MDIO1 data will be latched at the rising edge of MDC1 clock. MII Management Data I/O for Ethernet 1. It is used to transfer MII control and status information between PHY and MAC. Collision Detect for Ethernet 1 in MII mode. This shall be asserted by PHY upon detecting a collision happened over the medium. It will be asserted and lasted until collision condition vanishes. External pull-up is necessary in RMII mode. Carrier Sense for Ethernet 1 in MII mode. External pull-up is necessary in RMII mode. Transmit Data Clock for Ethernet 1 in MII mode, TX1_CLK is driven by PHY and provides the timing reference for TX1_EN and TX1D. The clock will be 25MHz or 2.5 MHz. External pullup will be necessary in RMII mode. Transmit Data bus (4-bit) for Ethernet 1 in MII mode. The nibble transmit data bus is synchronized with TX1_CLK. It should be latched by PHY at the rising edge of TX1_CLK. In RMII mode, TX1D [1:0] are used as R1A_TXD [1:0], 2-bit Transmit Data bus for Ethernet 1 Transmit Enable for Ethernet 1 in MII and RMII mode. It indicates the transmit activity to external PHY. It will be synchronized with TX1_CLK in MII mode. Receive Data Clock for Ethernet 1 in MII mode. When it is used as a received clock pin, it is from PHY. The clock will be either 25 MHz or 2.5 MHz. The minimum duty cycle at its high or low state should be 35% of the nominal period for all conditions. In RMII mode, this pin is used as R1A_REFCLK, Reference Clock and only available for 176-pin package. The clock shall be 50MHz +/-50 ppm with minimum 35% duty cycle at high or low state. Receive Data bus (4-bit) for Ethernet 1 in MII mode. They are driven by external PHY, and should be synchronized with RX1_CLK and valid only when RX1_DV is valid. In RMII mode, RX1D [1:0] are used as R1A_RXD [1:0], 2-bit Receive Data bus for Ethernet 1. Receive Data Valid for Ethernet 1 in MII mode. It will be asserted when received data is coming and present, and de-asserted at the end of the frame. In RMII mode, this pin is used as the R1A_CRSDV, Carrier Sense / Receive Data Valid for Ethernet 1 and only available for 176-pin package. The R1A_CRSDV shall be asserted by PHY when the receive medium is non-idle. Loss of carrier shall result in the de-assertion of R1A_CRSDV synchronous to the cycle of R1A_REFCLK, and only on nibble boundaries. Receive Data Error for Ethernet 1 in MII and RMII mode. It indicates a data error detected by PHY. The assertion should be lasted for longer than a period of RX0_CLK. When RX0_ERR is asserted, the MAC will report a CRC error. Ethernet Interface (1) MDC1 MDIO1 O IO - COL1 I - CRS1 I - TX1_CLK I - TX1D [3:0] / --,R1A_TXD [1:0] TX1_EN/ R1A_TXEN/R1B_ TXEN O - O - RX1_CLK / R1A_REFCLK I - RX1D [3:0] / --, R1A_RXD[1:0] I - RX1_DV/ R1A_CRSDV I - RX1_ERR / R1A_RXERR I - - 12 - W90N740CD/W90N740CDG Pins Description, continued NAME USB Interface DP DN Miscellaneous GP[20:17] / nIRQ[3:0] GP16 / nXDREQ GP15 /nXDACK GP14 / TIMER1/SPEED GP13 / TIMER0/STDBY GP12 /nWDOG GP11 /RxD GP10 /TxD GP9/nDSR/nTOE GP8 /nDTR/FSE0 GP7 /nCD /VO GP6 /nCTS/ VM GP5 /nRTS/ VP GP4 /nRI /RCV GP[3:0] Power/Ground VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS DVDD18 DVSS18 AVDD18 AVSS18 IO TYPE PAD TYPE DESCRIPTION IO IO - Differential Positive USB IO signal Differential Negative (Minus) USB IO signal IO IO IO IO IO IO IO IO IO - External Interrupt Request or General Purpose I/O External DMA Request or General Purpose I/O External DMA Acknowledge or General Purpose I/O Timer 1 or General Purpose I/O. This pin is also used as SPEED, Speed mode control for external USB transceiver Timer 0 or General Purpose I/O. This pin is also used as STDBY, StandBy control for external USB transceiver Watchdog Timer Timeout Flag (active-low) or General Purpose I/O UART Receive Data or General Purpose I/O UART Transmit Data or General Purpose I/O UART Receive Clock or General Purpose I/O. This pin is also used as nTOE, Output Enable control (active-low) for external USB transceiver. UART Transmit Clock or General Purpose I/O. This pin is also used as SE0, Differential Data Transceiver Output for external USB transceiver. T UART Carrier Detector or General Purpose I/O. This pin is also used as VO, Data Output for external USB transceiver. UART Clear to Send or General Purpose I/O. This pin is also used as VM, Data Negative (Minus) Input for external USB receiver. UART Ready to Send or General Purpose I/O. This pin is also used as VP, Data Positive Input for external USB receiver. UART Ring Indicator or General Purpose I/O. This pin is also used as RCV, Difference Receiver Input. General Purpose I/O. Core Logic power (1.8V) Core Logic ground (0V) IO Buffer power (3.3V) IO Buffer ground (0V) USB power (3.3V) USB ground (0V) PLL Digital power (1.8V) PLL Digital ground (0V) PLL Analog power (1.8V) PLL Analog ground (0V) IO IO IO IO IO IO P G P G P G P G P G - - 13 - Publication Release Date: Aug. 18, 2005 Revision A6 W90N740CD/W90N740CDG 7. FUNCTIONAL DESCRIPTION 7.1 ARM7TDMI CPU Core The ARM7TDMI CPU core is a member of the ARM family of general-purpose 32-bit microprocessors, which offer high performance for very low power consumption. The architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set Computer (CISC) systems. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. The high instruction throughput and impressive real-time interrupt response are the major benefits. The ARM7TDMI core can execute two instruction sets: (1) The standard 32-bit ARM instruction set (2) The 16-bit THUMB instruction set The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM core while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. THUMB instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with the same effect on the processor model. In the other words, the THUMB architecture give 16-bit systems a way to access the 32-bit performance of the ARM Core without requiring the full overhead of 32-bit processing. ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 set are visible; the other registers are used to speed up exception processing. All the register specifies in ARM instructions can address any of the 16 registers. The CPU also supports 5 types of exception, such as two levels of interrupt, memory aborts, attempted execution of an undefined instruction and software interrupts. A[31:0] Address Register Incrementer Bus Scan Control Address Incrementer Register Bank (31 x 32-bit registers) (6 status registers) B Bus PC Bus Instruction Decoder Control Logic 32 x8 Multiplier ALU Bus A Bus Barrel Shifter Instruction Pipeline Read Data Register Thumb Instruction Decoder Writer Data Register 32-bit ALU D[31:0] Fig 7.1 ARM7TDMI CPU Core Block Diagram - 14 - W90N740CD/W90N740CDG 7.2 7.2.1 • • • • • System Manager Overview System memory map & on-chip peripherals memory map The data bus width of external memory address & data bus connection with external memory Bus arbitration supports the Fixed Priority Mode & Rotate Priority Mode Power-On setting On-Chip PLL module control & Clock select control The functions of the System Manager: 7.2.2 System Memory Map W90N740 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0.0000 – 0xFFFF.FFFF) and the On-Chip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable space: 0x0~0x7FDF.FFFF if Cache ON; non-cacheable space: 0x8000.0000 ~ 0xFFDF.FFFF). The size and location of each bank is determined by the register settings for “current bank base address pointer” and “current bank size”. (*Note: The address boundaries of consecutive banks must not overlap, when setting the bank control registers.) The start address of each memory bank is not fixed, except On-Chip Peripherals and On-Chip RAM. You can use bank control registers to assign a specific bank start address by setting the bank’s base pointer (13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer