W90N745CDG

W90N745CD/W90N745CDG 32-BIT ARM7TDMI-BASED MCU W90N745 16/32-bit ARM microcontroller Product Data Sheet W90N745CD/W90N745CDG Revision History REVISION DATE COMMENTS A A1 A2 2006/06/23 2006/08/30 2006/09/22 Draft Add Electrical specification Delete Chapter 6: BLOCK DIAGRAM -I- Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG Table of Contents1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES ................................................................................................................................. 2 PIN DIAGRAM ............................................................................................................................ 7 PIN ASSIGNMENT ..................................................................................................................... 8 PIN DESCRIPTION................................................................................................................... 13 FUNCTIONAL DESCRIPTION ................................................................................................. 24 6.1 6.2 ARM7TDMI CPU CORE ............................................................................................... 24 System Manager........................................................................................................... 25 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 Overview ........................................................................................................................ 25 System Memory Map...................................................................................................... 25 Address Bus Generation ................................................................................................ 28 Data Bus Connection with External Memory .................................................................. 28 Bus Arbitration................................................................................................................ 37 Power Management ....................................................................................................... 38 Power-On Setting ........................................................................................................... 41 System Manager Control Registers Map ........................................................................ 41 EBI Overview.................................................................................................................. 56 SDRAM Controller .......................................................................................................... 56 EBI Control Registers Map ............................................................................................. 60 On-Chip RAM ................................................................................................................. 79 Non-Cacheable Area ...................................................................................................... 79 Instruction Cache............................................................................................................ 80 Data Cache .................................................................................................................... 82 Write Buffer .................................................................................................................... 84 Cache Control Registers Map......................................................................................... 84 EMC Functional Description ........................................................................................... 93 EMC Register Mapping ................................................................................................ 103 GDMA Functional Description ...................................................................................... 158 GDMA Register Map .................................................................................................... 159 USB Host Functional Description ................................................................................. 168 USB Host Controller Registers Map ............................................................................. 169 USB Endpoints ............................................................................................................. 192 6.3 External Bus Interface .................................................................................................. 56 6.3.1 6.3.2 6.3.3 6.4 Cache Controller........................................................................................................... 79 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.5 Ethernet MAC Controller............................................................................................... 92 6.5.1 6.5.2 6.6 GDMA Controller ........................................................................................................ 158 6.6.1 6.6.2 6.7 USB Host Controller ................................................................................................... 168 6.7.1 6.7.2 6.8 USB Device Controller................................................................................................ 192 6.8.1 - II - W90N745CD/W90N745CDG 6.8.2 6.8.3 Standard Device Request............................................................................................. 192 USB Device Register Description ................................................................................. 192 I²S Interface.................................................................................................................. 231 AC97 Interface ............................................................................................................. 232 Audio Controller Register Map...................................................................................... 235 UART0........................................................................................................................ 256 UART1........................................................................................................................ 256 UART2........................................................................................................................ 258 UART3........................................................................................................................ 260 General UART Controller ........................................................................................... 261 High speed UART Controller ...................................................................................... 274 General Timer Controller ............................................................................................ 288 Watchdog Timer ......................................................................................................... 288 Timer Control Registers Map...................................................................................... 288 Interrupt Sources ........................................................................................................ 298 AIC Registers Map ..................................................................................................... 301 GPIO Register Description ......................................................................................... 316 GPIO Register Description ......................................................................................... 317 I2C Protocol ................................................................................................................ 339 I2C Serial Interface Control Registers Map ................................................................. 342 USI Timing Diagram ................................................................................................... 350 USI Registers Map ..................................................................................................... 351 PWM Double Buffering and Reload Automatically...................................................... 359 Modulate Duty Ratio ................................................................................................... 359 Dead Zone Generator................................................................................................. 360 PWM Timer Start Procedure ...................................................................................... 360 PWM Timer Stop Procedure....................................................................................... 360 PWM Register Map .................................................................................................... 361 Keypad Interface Register Map .................................................................................. 372 Register Description ................................................................................................... 373 6.9 Audio Controller .......................................................................................................... 231 6.9.1 6.9.2 6.9.3 6.10 Universal Asynchronous Receiver/Transmitter Controller ......................................... 254 6.10.1 6.10.2 6.10.3 6.10.4 6.10.5 6.10.6 6.11 Timer/Watchdog Controller......................................................................................... 288 6.11.1 6.11.2 6.11.3 6.12 Advanced Interrupt Controller..................................................................................... 297 6.12.1 6.12.2 6.13 General-Purpose Input/Output ................................................................................... 314 6.13.1 6.13.2 6.14 I C Interface ................................................................................................................ 338 6.14.1 6.14.2 2 6.15 Universal Serial Interface............................................................................................ 349 6.15.1 6.15.2 6.16 PWM ........................................................................................................................... 358 6.16.1 6.16.2 6.16.3 6.16.4 6.16.5 6.16.6 6.17 Keypad Interface......................................................................................................... 371 6.17.1 6.17.2 - III - Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG 6.18 PS2 Host Interface Controller ..................................................................................... 380 6.18.1 6.18.2 PS2 Host Controller Interface Register Map............................................................... 381 Register Description ................................................................................................... 382 7. ELECTRICAL SPECIFICATIONS........................................................................................... 386 7.1 7.2 Absolute Maximum Ratings ........................................................................................ 386 DC Specifications ....................................................................................................... 386 7.2.1 7.2.2 Digital DC Characteristics............................................................................................. 386 USB Transceiver DC Characteristics............................................................................ 388 EBI/SDRAM Interface AC Characteristics .................................................................... 389 EBI/(ROM/SRAM/External I/O) AC Characteristics ...................................................... 390 USB Transceiver AC Characteristics............................................................................ 391 EMC RMII AC Characteristics ...................................................................................... 391 AC97/I2S Interface AC Characteristics......................................................................... 393 I2C Interface AC Characteristics ................................................................................... 395 USI Interface AC Characteristics .................................................................................. 396 PS2 Interface AC Characteristics ................................................................................. 397 7.3 AC Specifications........................................................................................................ 389 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 8. 9. 10. ORDERING INFORMATION .................................................................................................. 399 PACKAGE SPECIFICATIONS................................................................................................ 400 APPENDIX A: W90N745 REGISTERS MAPPING TABLE .................................................... 401 - IV - W90N745CD/W90N745CDG 1. GENERAL DESCRIPTION The W90N745 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte Dcache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost sensitive and power sensitive applications. One 100/10 Mbit MAC of Ethernet controller is built-in to reduce total system cost. The W90N745 also provides one USB 1.1 host controller, one USB 1.1 device controller, one AC97/I²S controller, one 2-channel GDMA, four independent UARTs, one watchdog timer, two 24-bit timers with 8-bit pre-scale, up to 31 programmable I/O ports, PS2 keyboard controller and an advanced interrupt controller. The external bus interface (EBI) controller provides for SDRAM, ROM/SRAM, flash memory and I/O devices. The system manager includes an internal 32-bit system bus arbiter and a PLL clock controller. With a wide range of serial communication and Ethernet interfaces, the W90N745 is suitable for communication gateways as well as many other general purpose applications. -1- Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG 2. FEATURES Architecture • • • • Fully 16/32-bit RISC architecture Little/Big-Endian mode supported Efficient and powerful ARM7TDMI core Cost-effective JTAG-based debug solution External Bus Interface • • • • • 8/16-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os Support for SDRAM Programmable access cycle (0-7 wait cycle) Four-word depth write buffer for SDRAM write data Cost-effective memory-to-peripheral DMA interface Instruction and Data Cache • • • • Two-way, set-associative, 4K-byte I-cache and 4K-byte D-cache Support for LRU (Least Recently Used) protocol Cache can be configured as internal SRAM Support cache lock function Ethernet MAC Controller • • • • • • • • • • • • DMA engine with burst mode MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx) Data alignment logic Endian translation 100/10 Mbit per second operation Full compliance with IEEE standard 802.3 RMII interface only Station Management Signaling On-chip CAM (up to 16 destination addresses) Full-duplex mode with PAUSE feature Long/short packet modes PAD generation -2- W90N745CD/W90N745CDG DMA Controller • • • • 2-channel general DMA for memory-to-memory data transfers without CPU intervention Initialed by a software or external DMA request Increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers 4-data burst mode UART • • • • • • • • • Four UART (serial I/O) blocks with interrupt-based operation Support for 5-bit, 6-bit, 7-bit or 8-bit serial data transmit and receive Programmable baud rates 1, ½ or 2 stop bits Odd or even parity Break generation and detection Parity, overrun and framing error detection X16 clock mode UART1 supports Bluetooth, and UART2 supports IrDA1.0 SIR Timers • • • Two programmable 24-bit timers with 8-bit pre-scaler One programmable 20 bit with selectable additional 8-bit prescaler watchdog timer One-shot mode, periodical mode or toggle mode operation Programmable I/Os • • • 31 programmable I/O ports Pins individually configurable to input, output or I/O mode for dedicated signals I/O ports are configurable for multiple functions Advanced Interrupt Controller • • • • • • 24 interrupt sources, including 4 external interrupt sources Programmable normal or fast interrupt mode (IRQ, FIQ) Programmable as either edge-triggered or level-sensitive for 4 external interrupt sources Programmable as either low-active or high-active for 4 external interrupt sources Priority methodology is encoded to allow for interrupt daisy-chaining Automatically mask out the lower priority interrupt during interrupt nesting -3- Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG USB Host Controller • • • • • USB 1.1 compliant Compatible with Open HCI 1.0 specification Supports low-speed and full speed devices Build-in DMA for real time data transfer Two on-chip USB transceivers with one optionally shared with USB device controller USB Device Controller • • USB 1.1 compliant Support four USB endpoints including one control endpoint and 3 configurable endpoints for rich USB functions Two PLLs • • • • • The external clock can be multiplied by on-chip PLL to provide high frequency system clock The input frequency range is 3-30MHz; 15MHz is preferred. One PLL for both CPU and USB host/device controller One PLL for audio I²S 12.288/16.934MHz clock source Programmable clock frequency 4-Channel PWM • • • • • Four 16-bit timers with PWM Two 8-bit pre-scalers & Two 4-bit dividers Programmable duty control of output waveform (PWM) Auto reload mode or one-shot pulse mode Dead-zone generator 2 I C Master • • • • • • • • • • 2-channel I2C Compatible with Philips I2C standard, support master mode only Support multi master operation Clock stretching and wait state generation Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer Software programmable acknowledge bit Arbitration lost interrupt, with automatic transfer cancellation Start/Stop/Repeated Start/Acknowledge generation Start/Stop/Repeated Start detection Bus busy detection -4- W90N745CD/W90N745CDG • • Supports 7 bit addressing mode Software mode I2C Universal Serial Interface (USI) • • • • • • • • • 1-channel USI Support USI (Microwire/SPI) master mode Full duplex synchronous serial data transfer Variable length of transfer word up to 32 bits Provide burst mode operation, transmit/receive can be executed up to four times in one transfer MSB or LSB first data transfer Rx and Tx on both rising or falling edge of serial clock independently Two slave/device select lines Fully static synchronous design with one clock domain 2-Channel AC97/I²S Audio Codec Host Interface • • • • AHB master port and an AHB slave port are offered in audio controller. Always 8-beat incrementing burst Always bus lock when 8-beat incrementing burst When reach middle and end address of destination address, a DMA_IRQ is requested to CPU automatically KeyPad Scan Interface • • • • Scan up to 16 rows by 8 columns with an external 4 to 16 decoder and 4x8 array without auxiliary component Programmable debounce time One or two keys scan with interrupt and three keys reset function. Wakeup CPU from IDEL/Power Down mode PS2 Host Interface • • • APB slave consisted of PS2 protocol. Connect IBM keyboard or bar-code reader through PS2 interface. Provide hardware scan code to ASCII translation -5- Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG Power management • • • • Programmable clock enables for individual peripheral IDLE mode to halt ARM core and keep peripheral working Power-Down mode to stop all clocks included external crystal oscillator. Exit IDLE by all interrupts Exit Power-Down by keypad,USB device and external interrupts Operation Voltage Range • • 3.0 ~ 3.6 V for IO buffer 1.62 ~ 1.98 V for core logic Operation Temperature Range • TBD Operating Frequency • Up to 80 MHz Package Type • 128-pin LQFP -6- W90N745CD/W90N745CDG 3. PIN DIAGRAM Figure 3.1 Pin Diagram -7- Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG 4. PIN ASSIGNMENT Table 4.1 W90N745 Pins Assignment PIN NAME 128-PIN LQFP Clock & Reset EXTAL (15M) XTAL (15M) nRESET JTAG Interface TMS TDI TDO TCK nTRST External Bus Interface A [20:0] D [15:0] nWBE [1;0] / SDQM [1:0] nSCS [1:0] nSRAS nSCAS MCKE nSWE MCLK nWAIT / GPIO [30] / nIRQ [3] nBTCS nECS [3:0] nOE ( 3 pins ) 40 41 25 ( 5 pins ) 33 34 35 36 37 ( 53 pins ) 89-86,84-82,80-77,75-71,69-65 110-111,113-116,118-122,124-128 108,107 100,99 101 102 98 106 104 96 97 90,92-94 95 -8- W90N745CD/W90N745CDG Table 4.1 W90N745 Pins Assignment, continued PIN NAME 128-PIN LQFP Ethernet Interface PHY_MDC / GPIO [29] / KPROW [1] PHY_MDIO / GPIO [28] / KPROW [0] PHY_TXD [1:0] / GPIO [27:26] / KPCOL [7:6] PHY_TXEN / GPIO [25] / KPCOL [5] PHY_REFCLK / GPIO [24] / KPCOL [4] PHY_RXD [1:0] / GPIO [23:22] / KPCOL [3:2] PHY_CRSDV / GPIO [21] / KPCOL [1] PHY_RXERR / GPIO [20] / KPCOL [0] AC97/I²S/PWM/UART3 AC97_nRESET / I²S_MCLK / GPIO [0] / nIRQ [2] / USB_PWREN ( 10 pins ) 64 63 62,60 59 58 57,55 54 53 ( 5 pins ) 44 -9- Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG Table 4.1 W90N745 Pins Assignment, continued PIN NAME 128-PIN LQFP AC97/I²S/PWM/UART3 AC97_DATAI / I²S_DATAI / PWM [0] / DTR3 / GPIO [1] AC97_DATAO / I²S_DATAO / PWM [1] / DSR3 / GPIO [2] AC97_SYNC / I²S_LRCLK / PWM [2] / TXD3 / GPIO [3] AC97_BITCLK / I²S_BITCLK / PWM [3] / RXD3 GPIO [4] USB Interface DP0 DN 0 DP1 DN1 Miscellaneous nIRQ [1] / GPIO [17] / USB_OVRCUR nIRQ [0] / GPIO [16] nWDOG / GPIO [15] / USB_PWREN TEST ( 5 pins ) 45 46 47 48 ( 4 pins ) 7 6 2 3 ( 7 pins ) 32 31 38 26 - 10 - W90N745CD/W90N745CDG Table 4.1 W90N745 Pins Assignment, continued PIN NAME 128-PIN LQFP I C/USI(SPI/MW) SCL0 / SFRM / TIMER0 / GPIO [11] SDA0 / SSPTXD / TIMER1 / GPIO [12] SCL1 / SCLK / GPIO [13] / KPROW [3] SDA1 / SSPRXD / GPIO [14] / KPROW [2] UART0/UART1/UART2/PS2 TXD0 / GPIO [5] RXD0 / GPIO [6] TXD1 / GPIO [7] RXD1 / GPIO [8] CTS1 / TXD2(IrDA) / PS2_CLK / GPIO [9] RTS1 / RXD2(IrDA) / PS2_DATA / GPIO [10] 2 ( 4 pins ) 17 18 19 20 ( 6 pins ) 10 11 12 13 14 15 - 11 - Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG Table 4.1 W90N745 Pins Assignment, continued PIN NAME 128-PIN LQFP XDMA nXDREQ / GPIO [19] / nXDACK / GPIO [18] / Power/Ground VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS PLLVDD18 PLLVSS18 ( 2 pins ) 51 52 ( 36 pins ) 21,43,49,85,112 22,50,81,109 9,23,42,61,76,103,117 16,24,39,56,70,91,105,123 1,8 4,5 27,30 28,29 - 12 - W90N745CD/W90N745CDG 5. PIN DESCRIPTION Table 5.1 W90N745 Pins Description PIN NAME Clock & Reset IO TYPE I O IS IUS IUS O IDS IUS O IOS IOS IOS O O O O O O DESCRIPTION 15MHz External Clock / Crystal Input 15MHz Crystal Output System Reset, active-low JTAG Test Mode Select, internal pull-up with 70K ohm JTAG Test Data in, internal pull-up with 70K ohm JTAG Test Data out JTAG Test Clock, internal pull-down with 58K ohm JTAG Reset, active-low, internal pull-up with 70K ohm Address Bus (MSB) of external memory and IO devices. Address Bus of external memory and IO devices. Data Bus (LSB) of external memory and IO device. Write Byte Enable for specific device (nECS [1:0]). Data Bus Mask signal for SDRAM (nSCS [1:0]), active-low. SDRAM chip select for two external banks, active-low. Row Address Strobe for SDRAM, active-low. Column Address Strobe for SDRAM, active-low. SDRAM Clock Enable, active-high SDRAM Write Enable, active-low System Master Clock Out, SDRAM clock, output with slew-rate control External Wait, active-low. This pin indicates that the external devices need more active cycle during access operation. General Programmable In/Out Port GPIO[30]. If memory and IO devices in EBI do not need wait request, it can be configured as GPIO[30] or nIRQ3. ROM/Flash Chip Select, active-low. External I/O Chip Select, active-low. ROM/Flash, External Memory Output Enable, active-low. EXTAL (15M) XTAL (15M) nRESET JTAG Interface TMS TDI TDO TCK nTRST External Bus Interface A [20:18] A [17:0] D [15:0] nWBE [1:0] / SDQM [1:0] nSCS [1:0] nSRAS nSCAS MCKE nSWE MCLK nWAIT / GPIO[30] / nIRQ3 nBTCS nECS [3:0] nOE IUS O IO O - 13 - Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG Table 5.1 W90N745 Pins Description, continued PIN NAME Ethernet Interface PHY_MDC / GPIO [29] / KPROW [1] PHY_MDIO / GPIO [28] / KPROW [0] PHY_TXD [1:0] / GPIO [27:26] / KPCOL [7:6] PHY_TXEN / IO TYPE DESCRIPTION RMII Management Data Clock for Ethernet. It is the reference clock of MDIO. Each MDIO data will be latched at the rising edge of MDC clock. General Programmable In/Out Port [29] Keypad ROW[1] scan output. RMII Management Data I/O for Ethernet. It is used to transfer RMII control and status information between PHY and MAC. General Programmable In/Out Port [28] Keypad ROW[0] scan output. 2-bit Transmit Data bus for Ethernet. General programmable In/Out Port [27:26] Keypad column input [7:6], active low PHY_TXEN shall be asserted synchronously with the first 2-bit of the preamble and shall remain asserted while all di-bits to be transmitted are presented. Of course, it is synchronized with PHY_REFCLK. General Programmable In/Out Port [25] Keypad column input [5], active low Reference Clock. The clock shall be 50MHz +/- 50 ppm with minimum 35% duty cycle at high or low state. General Programmable In/Out port [24] Keypad column input [4], active low 2-bit Receive Data bus for Ethernet. General Programmable In/Out Port [23:22] Keypad column input [3:2], active low Carrier Sense / Receive Data Valid for Ethernet. The PHY_CRSDV shall be asserted by PHY when the receive medium is non-idle. Loss of carrier shall result in the de-assertion of PHY_CRSDV synchronous to the cycle of PHY_REFCLK, and only on 2-bit receive data boundaries. General Programmable In/Out port [21] Keypad column input [1], active low Receive Data Error for Ethernet. It indicates a data error detected by PHY.The assertion should be lasted for longer than a period of PHY_REFCLK. When PHY_RXERR is asserted, the MAC will report a CRC error. General programmable In/Out port [20] Keypad column input [0], active low IOU IO IOU IOU GPIO [25] / KPCOL [5] PHY_REFCLK / GPIO [24] / KPCOL [4] PHY_RXD [1:0] / GPIO [23:22] / KPCOL [3:2] PHY_CRSDV / IOS IOS IOS GPIO [21] / KPCOL [1] PHY_RXERR / IOS GPIO [20] / KPCOL [0] - 14 - W90N745CD/W90N745CDG Table 5.1 W90N745 Pins Description, continued PIN NAME IO TYPE DESCRIPTION AC97 CODEC Host Interface RESET Output. I²S CODEC Host Interface System Clock Output. General Purpose In/Out port [0] External interrupt request. USB host power enable output AC97 CODEC Host Interface Data Input. I²S CODEC Host Interface Data Input. PWM Channel 0 output. Data Terminal Ready for UART3. General Purpose In /Out port [1] AC97 CODEC Host Interface Data Output. I²S CODEC Host Interface Data Output. PWM Channel 1 output. Data Set Ready for UART3. General Purpose In/Out port [2] AC97 CODEC Host Interface Synchronous Pulse Output. I²S CODEC Host Interface Left/Right Channel Select Clock. PWM Channel 2 output. Transmit Data for UART3. General Purpose In/Out port [3] AC97 CODEC Host Interface Bit Clock Input. I²S CODEC Host Interface Bit Clock. PWM Channel 3 output. Receive Data for UART3. General Purpose In/Out port [4]. Differential Positive USB IO signal Differential Negative USB IO signal Differential Positive USB IO signal Differential Negative USB IO signal External Interrupt Request AC97/I²S/PWM/UART3 AC97_nRESET / I²S_MCLK / IOU GPIO [0] / nIRQ [2] / USB_PWREN AC97_DATAI / I²S_DATAI / IOU PWM [0] / DTR3 / GPIO [1] AC97_DATAO / I²S_DATAO / PWM [1] / DSR3 / GPIO [2] AC97_SYNC / I²S_LRCLK / PWM [2] / TXD3 / GPIO [3] AC97_BITCLK / I²S_BITCLK / PWM [3] / RXD3 / GPIO [4] USB Interface DP0 DN0 DP1 DN1 Miscellaneous nIRQ [1:0] / GPIO [17:16] / USB_OVRCUR nWDOG / GPIO [15] / USB_PWREN TEST IOU IDS IOU IOU IOS IO IO IO IO IOU General Purpose I/O nIRQ1 is used as USB host over-current detection input Watchdog Timer Timeout Flag and Keypad 3-keys reset output, active low General Purpose In/output USB host power switch enable output This test pin must be short to ground or left unconnected - 15 - Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG Table 5.1 W90N745 Pins Description, continued PIN NAME I C/USI 2 IO TYPE 2 DESCRIPTION I C Serial Clock Line 0. USI Serial Frame. Timer0 time out output. General Purpose In/Out port [11]. I C Serial Data Line 0 USI Serial Transmit Data Timer1 time out output General Purpose In/Out port [12] I C Serial Clock Line 1 USI Serial Clock General Purpose In/Out port [13] Keypad row scan output [3] I C Serial Data Line 1 USI Serial Receive Data General Purpose In/Out port [14] Keypad scan output [2] UART0 Transmit Data. General Purpose In/Out [5] UART0 Receive Data. General Purpose In/Out [6] UART1 Transmit Data. General Purpose In/Out [7] UART1 Receive Data. General Purpose In/Out [8] UART1 Clear To Send for Bluetooth application UART2 Transmit Data supporting SIR IrDA. PS2 Interface Clock Input/Output General Purpose In/Out [9] UART1 Request To Send for Bluetooth application UART2 Receive Data supporting SIR IrDA. PS2 Interface Bi-Directional Data Line. General Purpose In/Out [10] External DMA Request. General Purpose In/Out [19] External DMA Acknowledgement. General Purpose In/Out [18] 2 2 2 SCL0 / SFRM / TIMER0 / GPIO [11] SDA0 / SSPTXD / TIMER1 / GPIO [12] SCL1 / SCLK / GPIO [13] / KPROW [3] SDA1 / SSPRXD / GPIO [14] / KPROW [2] IOU IOU IOU IDU UART0/UART1/UART2 TXD0 / IOU GPIO [5] RXD0 / IOU GPIO [6] TXD1 / IOU GPIO [7] RXD1 / IOU GPIO [8] CTS1/ TXD2(IrDA) / IOU PS2_CLK / GPIO [9] RTS1/ RXD2(IrDA) / IOU PS2_DATA / GPIO [10] XDMA nXDREQ / IO GPIO [19] / nXDACK / IO GPIO [18] / - 16 - W90N745CD/W90N745CDG Table 5.1 W90N745 Pins Description, continued PIN NAME IO TYPE DESCRIPTION Power/Ground VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS DVDD18 DVSS18 AVDD18 AVSS18 P G P G P G P G P G Core Logic power (1.8V) Core Logic ground (0V) IO Buffer power (3.3V) IO Buffer ground (0V) USB power (3.3V) USB ground (0V) PLL Digital power (1.8V) PLL Digital ground (0V) PLL Analog power (1.8V) PLL Analog ground (0V) - 17 - Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG Table 5.2 W90N745 128-pin LQFP Multi-function List PIN NO. DEFAULT FUNCTION0 USBVDD DP1 DN1 USBVSS USBVSS DN0 DP0 USBVDD VDD33 FUNCTION1 - FUNCTION2 - FUNCTION3 - USB1.1 Host/Device Interface 1 2 3 4 5 6 7 8 9 USBVDD DP1 DN1 USBVSS USBVSS DN0 DP0 USBVDD VDD33 UART[2:0]/PS2 Interface 10 11 12 13 14 15 16 GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] VSS33 GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] VSS33 I C/USI Interface 17 18 19 20 21 22 23 24 GPIO[11] GPIO[12] GPIO[13] GPIO[14] VDD18 VSS18 VDD33 VSS33 GPIO[11] GPIO[12] GPIO[13] GPIO[14] VDD18 VSS18 VDD33 VSS33 I C_SCL0 I C_SDA0 I C_SCL1 I C_SDA1 2 2 2 2 2 UART_TXD0 UART_RXD0 UART_TXD1 UART_RXD1 UART_TXD2 UART_RXD2 - UART_CTS1 UART_RTS1 - PS2_CLK PS2_DATA - SSP_FRAM SSP_TXD SSP_SCLK SSP_RXD - TIMER0 TIMER1 KPI_ROW[3] KPI_ROW[2] - System Reset & TEST 25 26 nRESET TEST nRESET TEST - - 18 - W90N745CD/W90N745CDG Table 5.2 W90N745 128-pin LQFP Multi-function List, continued PLL Power/Ground 27 28 29 30 PLL_VDD18 PLL_VSS18 PLL_VSS18 PLL_VDD18 PLL_VDD18 PLL_VSS18 PLL_VSS18 PLL_VDD18 - External IRQ[1:0]/USB Over Current 31 32 GPIO[16] GPIO[17] GPIO[16] GPIO[17] nIRQ [0] nIRQ [1] JTAG Interface 33 34 35 36 37 TMS TDI TDO TCK nTRST TMS TDI TDO TCK nTRST USB_OVRCUR - WatchDog/USB Power Enable 38 39 GPIO[15] VSS33 GPIO[15] VSS33 System Clock 40 41 42 43 EXTAL(15M) XTAL(15M) VDD33 VDD18 EXTAL(15M) XTAL(15M) VDD33 VDD18 nWDOG USB_PWREN - - 19 - Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG Table 5.2 W90N745 128-pin LQFP Multi-function List, continued PIN NO. DEFAULT FUNCTION0 FUNCTION1 AC97_nRESET FUNCTION2 FUNCTION3 AC97/I²S/PWM/UART3 Interface 44 GPIO[0] GPIO[0] or I²SMCLK AC97_DATAI 45 GPIO[1] GPIO[1] or I²SDATAI AC97_DATAO 46 GPIO[2] GPIO[2] or I²SDATAO AC97_SYNC 47 GPIO[3] GPIO[3] or I²SLRCLK AC97_BITCLK 48 GPIO[4] GPIO[4] VDD18 VSS18 XDMAREQ 51 52 GPIO[19] GPIO[18] GPIO[19] GPIO[18] nXDREQ nXDACK or I²SBITCLK 49 50 VDD18 VSS18 PWM3 UART_RXD3 PWM2 UART_TXD3 PWM1 UART_DSR3 PWM0 UART_DTR3 nIRQ [2] USB_PWREN Ethernet RMII/KeyPad Interface 53 54 55 56 57 58 59 60 61 62 63 64 GPIO[20] GPIO[21] GPIO[22] VSS33 GPIO[23] GPIO[24] GPIO[25] GPIO[26] VDD33 GPIO[27] GPIO[28] GPIO[29] GPIO[20] GPIO[21] GPIO[22] VSS33 GPIO[23] GPIO[24] GPIO[25] GPIO[26] VDD33 GPIO[27] GPIO[28] GPIO[29] PHY_RXERR PHY_CRSDV PHY_RXD[0] PHY_RXD[1] PHY_REFCLK PHY_TXEN PHY_TXD[0] PHY_TXD[1] PHY_MDIO PHY_MDC KPI_COL[0] KPI_COL[1] KPI_COL[2] KPI_COL[3] KPI_COL[4] KPI_COL[5] KPI_COL[6] KPI_COL[7] KPI_ROW[0] KPI_ROW[1] - - 20 - W90N745CD/W90N745CDG Table 5.2 W90N745 128-pin LQFP Multi-function List, continued PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 A[0] A[1] A[2] A[3] A[4] VSS33 A[5] A[6] A[7] A[8] A[9] VDD33 A[10] A[11] A[12] A[13] VSS18 A[14] A[15] A[16] VDD18 A[17] A[18] A[19] A[20] nECS[3] VSS33 A[0] A[1] A[2] A[3] A[4] VSS33 A[5] A[6] A[7] A[8] A[9] VDD33 A[10] A[11] A[12] A[13] VSS18 A[14] A[15] A[16] VDD18 A[17] A[18] A[19] A[20] nECS[3] VSS33 - - 21 - Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG Table 5.2 W90N745 128-pin LQFP Multi-function List, continued PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 nECS[2] nECS[1] nECS[0] nOE nWAIT nBTCS MCKE nSCS[0] nSCS[1] nSRAS nSCAS VDD33 MCLK VSS33 nSWE nWBE/SDQM[0] nWBE/SDQM[1] VSS18 D[15] D[14] VDD18 D[13] D[12] D[11] D[10] VDD33 D[9] D[8] D[7] nECS[2] nECS[1] nECS[0] nOE GPIO[30] nBTCS MCKE nSCS[0] nSCS[1] nSRAS nSCAS VDD33 MCLK VSS33 nSWE nWBE or SDQM[0] nWBE or SDQM[1] VSS18 D[15] D[14] VDD18 D[13] D[12] D[11] D[10] VDD33 D[9] D[8] D[7] nWAIT nIRQ [3] - - 22 - W90N745CD/W90N745CDG Table 5.2 W90N745 128-pin LQFP Multi-function List, continued PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 121 122 123 124 125 126 127 128 D[6] D[5] VSS33 D[4] D[3] D[2] D[1] D[0] D[6] D[5] VSS33 D[4] D[3] D[2] D[1] D[0] - - 23 - Publication Release Date: September 22, 2006 Revision A2 W90N745CD/W90N745CDG 6. FUNCTIONAL DESCRIPTION 6.1 ARM7TDMI CPU CORE The ARM7TDMI CPU core is a member of the Advanced RISC Machines (ARM) family of generalpurpose 32-bit microprocessors, which offer high performance for very low power consumption. The architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set Computers. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. The high instruction throughput and impressive real-time interrupt response are the major benefits. The ARM7TDMI CPU core has two instruction sets: (1) The standard 32-bit ARM set (2) A 16-bit THUMB set The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM core while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. THUMB instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with the same effect on the processor model. ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 sets are visible; the other registers are used to speed up exception processing. All the register specified in ARM instructions can address any of the 16 registers. The CPU also supports 5 types of exception, such as two levels of interrupt, memory aborts, attempted execution of an undefined instruction and software interrupts. A[31:0] Address Register Incrementer Bus Scan Control Address Incrementer Register Bank (31 x 32-bit registers) (6 status registers) B Bus PC Bus Instruction Decoder Control Logic 32 x8 Multiplier ALU Bus A Bus Barrel Shifter Instruction Pipeline Read Data Register Thumb Instruction Decoder Writer Data Register 32-bit ALU D[31:0] Figure 6.1.1 ARM7TDMI CPU Core Block Diagram - 24 - W90N745CD/W90N745CDG 6.2 6.2.1 System Manager Overview System memory map Data bus connection with external memory Product identifier register Bus arbitration PLL module Clock select and power saving control register Power-On setting The W90N745 system manager has the following functions. 6.2.2 System Memory Map W90N745 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0_0000 – 0xFFFF_FFFF) and the OnChip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable space:0x0000_0000~0x7FDF_FFFF if Cache ON; non-cacheable space: 0x8000_0000~0xFFDF_FFFF). The size and location of each bank is determined by the register settings for “current bank base address pointer” and “current bank size”. Please note that when setting the bank control registers, the address boundaries of consecutive banks must not overlap. Except On-Chip Peripherals and On-Chip RAM, the start address of each memory bank is not fixed. You can use bank control registers to assign a specific bank start address by setting the bank’s base pointer (13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer