W90P710CDG

W90P710CD/W90P710CDG 32-BIT ARM7TDMI-BASED MCU W90P710CD/W90P710CDG 16/32-bit ARM microcontroller Product Data Sheet -1- Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Revision History REVISION DATE COMMENTS A A.1 A.2 2005/12/02 2005/12/21 2006/01/17 Draft Modify the register definition Modify SD description Update LCD C version design spec. Update Smartcard C version design spec. Add RTC 32.768K clock measurment apllication note. Add RTC application note. Change EBI SDRAM control register SDCONFx[13] AUTOPR definition. A.3 2006/07/07 B 2006/07/26 Modify LCD register map section 7.2.2 Change 2 to 1 slave/device select lines Change SDIO to SD Add Electrical specification SDO change to SD page 11 SDIO change to SD page 33 “W99P710” change to “W90P710” page 245 Delete “it is same as the UART of W99740” page 333 Delete “it is same as the UART of W99702” page 332 Delete “note” page 337,338 ADD USB WakeUp control bit Update table 5.2 B1 2006/08/08 B2 2006/09/19 Delete section 6 -2- W90P710CD/W90P710CDG Table of Contents1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ......................................................................................................... 6 FEATURES ................................................................................................................................. 6 PIN DIAGRAM .......................................................................................................................... 13 PIN ASSIGNMENT ................................................................................................................... 14 PIN DESCRIPTION................................................................................................................... 20 FUNCTIONAL DESCRIPTION ................................................................................................. 33 6.1 6.2 ARM7TDMI CPU CORE ............................................................................................... 33 System Manager........................................................................................................... 34 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 Overview ......................................................................................................................34 System Memory Map....................................................................................................34 Address Bus Generation ..............................................................................................37 Data Bus Connection with External Memory ................................................................37 Bus Arbitration..............................................................................................................46 Power management .....................................................................................................47 Power-On Setting .........................................................................................................49 System Manager Control Registers Map ......................................................................50 EBI Overview................................................................................................................64 SDRAM Controller ........................................................................................................64 EBI Control Registers Map ...........................................................................................68 On-Chip RAM ...............................................................................................................86 Non-Cacheable Area ....................................................................................................86 Instruction Cache..........................................................................................................87 Data Cache ..................................................................................................................89 Write Buffer ..................................................................................................................91 Cache Control Registers Map.......................................................................................91 EMC Functional Description .........................................................................................98 EMC Register Mapping ..............................................................................................108 GDMA Functional Description ....................................................................................161 GDMA Register Map ..................................................................................................162 USB Host Functional Description ...............................................................................171 USB Host Controller Registers Map ...........................................................................172 HCCA .........................................................................................................................194 Endpoint Descriptor ....................................................................................................194 Transfer Descriptor.....................................................................................................194 6.3 External Bus Interface .................................................................................................. 64 6.3.1 6.3.2 6.3.3 6.4 Cache Controller........................................................................................................... 86 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.5 Ethernet MAC Controller............................................................................................... 97 6.5.1 6.5.2 6.6 GDMA Controller ........................................................................................................ 161 6.6.1 6.6.2 6.7 USB Host Controller ................................................................................................... 171 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.8 USB Device Controller................................................................................................ 194 Publication Release Date: September 19, 2006 Revision B2 -3- W90P710CD/W90P710CDG 6.8.1 6.8.2 6.8.3 USB Endpoints ...........................................................................................................195 Standard device request.............................................................................................195 USB Device Register Description ...............................................................................195 Functional Description ................................................................................................234 Register Mapping .......................................................................................................236 SD Register Description .............................................................................................237 Main Features ............................................................................................................253 LCD Register MAP .....................................................................................................254 LCD Special Register Description ..............................................................................256 IIS Interface ................................................................................................................307 AC97 Interface ...........................................................................................................308 Audio Controller Register Map....................................................................................311 UART0........................................................................................................................332 UART1........................................................................................................................332 UART2........................................................................................................................334 UART3........................................................................................................................336 General UART Controller ...........................................................................................337 High speed UART Controller ......................................................................................350 General Timer Controller ............................................................................................364 Watchdog Timer .........................................................................................................364 Timer Control Registers Map......................................................................................364 Interrupt Sources ........................................................................................................373 AIC Registers Map .....................................................................................................376 GPIO Control Registers Map......................................................................................392 GPIO Register Description .........................................................................................393 RTC Register Map......................................................................................................426 RTC Application Note .................................................................................................439 Register Mapping .......................................................................................................440 Register Description ...................................................................................................442 Functional description.................................................................................................468 I2C Protocol ................................................................................................................472 I2C Serial Interface Control Registers Map ................................................................475 6.9 SD Host Controller...................................................................................................... 234 6.9.1 6.9.2 6.9.3 6.10 LCD Controller ............................................................................................................ 253 6.10.1 6.10.2 6.10.3 6.11 Audio Controller .......................................................................................................... 307 6.11.1 6.11.2 6.11.3 6.12 Universal Asynchronous Receiver/Transmitter Controller ......................................... 330 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 6.12.6 6.13 Timer/Watchdog Controller......................................................................................... 364 6.13.1 6.13.2 6.13.3 6.14 Advanced Interrupt Controller..................................................................................... 372 6.14.1 6.14.2 6.15 General-Purpose Input/Output ................................................................................... 389 6.15.1 6.15.2 6.16 Real Time Clock ......................................................................................................... 424 6.16.1 6.16.2 6.17 Smart Card Host Interface .......................................................................................... 440 6.17.1 6.17.2 6.17.3 6.18 I2C Interface ............................................................................................................... 471 6.18.1 6.18.2 -4- W90P710CD/W90P710CDG 6.19 Universal Serial Interface............................................................................................ 483 6.19.1 6.19.2 USI Timing Diagram ...................................................................................................483 USI Registers Map .....................................................................................................484 PWM double buffering and reload automatically ........................................................491 Modulate Duty Ratio ...................................................................................................492 Dead Zone Generator.................................................................................................492 PWM Timer Start procedure.......................................................................................493 PWM Timer Stop procedure .......................................................................................493 PWM Register Map ....................................................................................................494 KeyPad Interface Register Map..................................................................................503 Register Description ...................................................................................................504 PS2 Host Controller Interface Register Map...............................................................512 Register Description ...................................................................................................512 6.20 PWM ........................................................................................................................... 491 6.20.1 6.20.2 6.20.3 6.20.4 6.20.5 6.20.6 6.21 Keypad Interface......................................................................................................... 502 6.21.1 6.21.2 6.22 PS2 Host Interface Controller ..................................................................................... 511 6.22.1 6.22.2 7. ELECTRICAL SPECIFICATIONS........................................................................................... 516 7.1 7.2 Absolute Maximum Ratings ........................................................................................ 516 DC Specifications ....................................................................................................... 516 7.2.1 7.2.2 Digital DC Characteristics...........................................................................................516 USB Transceiver DC Characteristics..........................................................................518 EBI/SDRAM Interface AC Characteristics ..................................................................518 EBI/(ROM/SRAM/External I/O) AC Characteristics ....................................................519 USB Transceiver AC Characteristics..........................................................................520 EMC RMII AC Characteristics ....................................................................................521 LCD Interface AC Characteristics...............................................................................523 SD Interface AC Characteristics .................................................................................524 AC97/I2S Interface AC Characteristics.......................................................................525 Smart Card Interface AC Characteristics....................................................................527 I2C Interface AC Characteristics ................................................................................528 USI Interface AC Characteristics ................................................................................529 PS2 Interface AC Characteristics ...............................................................................531 7.3 AC Specifications........................................................................................................ 518 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 8. 9. 10. ORDERING INFORMATION .................................................................................................. 532 PACKAGE SPECIFICATIONS................................................................................................ 533 APPENDIX A: W90P710 REGISTERS MAPPING TABLE..................................................... 534 -5- Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 1. GENERAL DESCRIPTION The W90P710 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte Dcache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost sensitive and power sensitive applications. One 10/100 Mb MAC of Ethernet controller is built-in to reduce total system cost. A LCD controller is also built-in to support TFT and low cost STN LCD modules. With one USB 1.1 host controller, one USB 1.1 device controller, two smart card host controller, four independent UARTs, one Watchdog timer, up to 71 programmable I/O ports, PS/2 keyboard controller and an advanced interrupt controller, the W90P710 is particularly suitable for point-of-sale (POS), access control and data collector. The W90P710 also provides one AC97/I²S controller, one SD host controller, one 2-Channel GDMA, two 24-bit timers with 8-bit pre-scale, The external bus interface (EBI) controller provides for SDRAM, ROM/SRAM, flash memory and I/O devices. The System Manager includes an internal 32-bit system bus arbiter and a PLL clock controller. With a wide range of serial communication and Ethernet interfaces, the W90P710 is also suitable for communication gateways as well as many other general purpose applications. 2. FEATURES Architecture Fully 16/32-bit RISC architecture Little/Big-Endian mode supported Efficient and powerful ARM7TDMI core Cost-effective JTAG-based debug solution External Bus Interface 8/16/32-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os Support for SDRAM Programmable access cycle (0-7 wait cycle) Four-word depth write buffer for SDRAM write data Cost-effective memory-to-peripheral DMA interface Instruction and Data Cache Two-way, Set-associative, 4K-byte I-cache and 4K-byte D-cache Support for LRU (Least Recently Used) Protocol Cache can be configured as internal SRAM Support Cache Lock function -6- W90P710CD/W90P710CDG Ethernet MAC Controller DMA engine with burst mode MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx) Data alignment logic Endian translation 100/10-Mbit per second operation Full compliance with IEEE standard 802.3 RMII interface only Station Management Signaling On-Chip CAM (up to 16 destination addresses) Full-duplex mode with PAUSE feature Long/short packet modes PAD generation LCD Controller (LCDC) (1) STN LCD Display Supports 4-bit single scan Monochrome STN LCD panel, 8-bit single scan Monochrome STN LCD panel, 8-bit single scan Color STN LCD panel Up to 16 gray levels display for Monochrome STN LCD panel Up to 4096(12bpp) colors display for Color STN LCD panel Virtual coloring method: Frame Rate Control (16-level) Anti-flickering method: Time-based Dithering (2) TFT LCD Display Supports Sync-type TFT LCD panel and Sync-type High-color TFT LCD panel Supports direct or palettized color display (3) TV Encoder Supports 8-bit YCbCr data output format to connect with external TV Encoder (4) LCD Preprocessing Supports RGB Raw-data or packetd YUV422 format Programmable parameters for different image size Build in two FIFOs, FIFO 1 is for Video image and FIFO 2 is for OSD image. Each FIFO is 16 words deep -7- Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG (5) LCD Post processing Support for one OSD (On-Screen-Display) overlay Support various OSD function Programmable parameters for different display panel (6) Others Color-look up table size 256x32 bit for TFT used when displaying 1bpp, 2bpp, 4bpp, 8bpp image Dedicated DMA for block transfer mode DMA Controller 2-channel General DMA for memory-to-memory data transfers without CPU intervention Initialed by a software or external DMA request Increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers 4-data burst mode UART Four UART (serial I/O) blocks with interrupt-based operation Support for 5-bit, 6-bit, 7-bit or 8-bit serial data transmit and receive Programmable baud rates 1, ½ or 2 stop bits Odd or even parity Break generation and detection Parity, overrun and framing error detection X16 clock mode UART1 supports Bluetooth, and UART2 supports IrDA1.0 SIR Timers Two programmable 24-bit timers with 8-bit pre-scaler One programmable 20 bit with selectable additional 8-bit prescaler Watchdog timer One-shot mode, periodical mode or toggle mode operation Programmable I/Os 71 programmable I/O ports Pins individually configurable to input, output or I/O mode for dedicated signals I/O ports are configurable for Multiple functions -8- W90P710CD/W90P710CDG Advanced Interrupt Controller 31 interrupt sources, including 6 external interrupt sources Programmable normal or fast interrupt mode (IRQ, FIQ) Programmable as either edge-triggered or level-sensitive for 6 external interrupt sources Programmable as either low-active or high-active for 6 external interrupt sources Priority methodology is encoded to allow for interrupt daisy-chaining Automatically mask out the lower priority interrupt during interrupt nesting USB Host Controller USB 1.1 compliant Compatible with Open HCI 1.0 specification Supports low-speed and full speed devices Build-in DMA for real time data transfer Two on-chip USB transceivers with one optionally shared with USB Device Controller USB Device Controller USB 1.1 compliant Support four USB endpoints including one control endpoint and 3 configurable endpoints for rich USB functions Two PLLs The external clock can be multiplied by on-chip PLL to provide high frequency system clock The input frequency range is 3-30MHz; 15MHz is preferred. One PLL for both CPU and USB host/device controller One PLL for LCD pixel clock and audio IIS 12.288/16.934MHz clock source Programmable clock frequency Real Time Clock (RTC) 32.768KHz operation Time counter (second, minute, hour) and calendar counter (day, month, year) Alarm register (second, minute, hour, day, month, year) 12 or 24-hour mode selectable Recognize leap year automatically Day of the week counter Frequency compensate register (FCR) Beside FCR, all clock and alarm data expressed in BCD code Support tick time interrupt Publication Release Date: September 19, 2006 Revision B2 -9- W90P710CD/W90P710CDG 4-Channel PWM Four 16-bit timers with PWM Two 8-bit pre-scalers & Two 4-bit dividers Programmable duty control of output waveform Auto reload mode or one-shot pulse mode Dead-zone generator I2C Master Two Channel I2C Compatible with Philips I2C standard, support master mode only Support multi master operation Clock stretching and wait state generation Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer Software programmable acknowledge bit Arbitration lost interrupt, with automatic transfer cancellation Start/Stop/Repeated Start/Acknowledge generation Start/Stop/Repeated Start detection Bus busy detection Supports 7 bit addressing mode Software mode I2C Universal Serial Interface (USI) 1-Channel USI Support USI (Microwire/SPI) master mode Full duplex synchronous serial data transfer Variable length of transfer word up to 32 bits Provide burst mode operation, transmit/receive can be executed up to four times in one transfer MSB or LSB first data transfer Rx and Tx on both rising or falling edge of serial clock independently Two slave/device select lines Fully static synchronous design with one clock domain 2-Channel AC97/I2S Audio Codec Host Interface AHB master port and an AHB slave port are offered in audio controller. Always 8-beat incrementing burst Always bus lock when 8-beat incrementing burst - 10 - W90P710CD/W90P710CDG When reach middle and end address of destination address, a DMA_IRQ is requested to CPU automatically Smart Card Host Interface (SCHI) ISO-7816 compliant PC/SC T=0, T=1 compliant 16-byte transmitter FIFO and 16-byte receiver FIFO FIFO threshold interrupt to optimize system performance Programmable transmission clock frequency Versatile baud rate configuration UART-like register file structure General-purpose C4, C8 channels SD Host Interface Directly connect to Secure Digital (SD, MMC) flash memory card. Supports DMA function to accelerate the data transfer between the internal buffer, external SDRAM, and flash memory card. Two 512 bytes internal buffers are embedded inside the controller. No SPI mode. KeyPad Scan Interface Scan up to 16 rows by 8 columns with an external 4 to 16 decoder and 4 rows by 8 columns array without auxiliary component Programmable debounce time One or two keys scan with interrupt and three keys reset function. Wakeup CPU from IDEL/Power Down mode PS2 Host Interface APB slave consisted of PS2 protocol. Connect IBM keyboard or bar-code reader through PS2 interface. Provide hardware scan code to ASCII translation Power management Programmable clock enables for individual peripheral IDLE mode to halt ARM Core and keep peripheral working Power-Down mode to stop all clocks included external crystal oscillator. Exit IDLE by all interrupts Exit Power-Down by keypad,USB device and external interrupts - 11 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Operation Voltage Range 3.0 ~ 3.6 V for IO Buffer 1.62 ~ 1.98 V for Core Logic Operation Temperature Range TBD Operating Frequency Up to 80 MHz Package Type 176-pin LQFP - 12 - W90P710CD/W90P710CDG 10 15 20 25 30 35 3. PIN DIAGRAM USB1VDD DP1 DN1 USB1VSS USB0VSS DN0 DP0 USB0VDD VDD33 TXD0/GPIO[5] RXD0/GPIO[6] TXD1/GPIO[7] RXD1/GPIO[8] CTS1/TXD2(IrDA)/PS2_CLK/GPIO[9] RTS1/RXD2(IrDA)/PS2_DATA/GPIO[10] VSS33 SCL0/SFRM/TIMER0/GPIO[11] SDA0/SSPTXD/TIMER1/GPIO[12] SCL1/SCLK/KPI_ROW[3]/GPIO[13] SDA1/SSPRXD/KPI_ROW[2]/GPIO[14] VDD18 VSS18 KPI_ROW[0]/VCLK/GPIO[30] KPI_ROW[1]/VDEN/GPIO[31] KPI_ROW[2]/VSYNC/GPIO[32] KPI_ROW[3]/HSYNC/GPIO[33] KPI_COL[7]/VD[7]/GPIO[41] KPI_COL[6]/VD[6]/GPIO[40] KPI_COL[5]/VD[5]/GPIO[39] KPI_COL[4]/VD[4]/GPIO[38] KPI_COL[3]/VD[3]/GPIO[37] KPI_COL[2]/VD[2]/GPIO[36] KPI_COL[1]/VD[1]/GPIO[35] KPI_COL[0]/VD[0]/GPIO[34] VDD33 VSS33 nRESET TEST PLL0VDD18 PLL0VSS18 PLL1VSS18 PLL1VDD18 nIRQ[0]/GPIO[16] nIRQ[1]/GPIO[17] 40 nBTCS MCKE nSCS[0] nSCS[1] nSRAS nSCAS VDD33 MCLK VSS33 nWE nWBE[0]/SDQM[0] nWBE[1]/SDQM[1] nWBE[2]/SDQM[2]/GPIO[69] nWBE[3]/SDQM[3]/GPIO[68] nIRQ[2]/GPIO[18] nIRQ[3]/GPIO[19] D[23]/VD[15]/GPIO[59] D[22]/VD[14]/GPIO[58] D[21]/VD[13]/GPIO[57] D[20]/VD[12]/GPIO[56] D[19]/VD[11]/GPIO[55] D[18]/VD[10]/GPIO[54] D[17]/VD[9]/GPIO[53] D[16]/VD[8]/GPIO[52] VSS18 D[15]/TBUS[15] D[14]/TBUS[14] VDD18 D[13]/TBUS[13] D[12]/TBUS[12] D[11]/TBUS[11] D[10]/TBUS[10] VDD33 D[9]/TBUS[9] D[8]/TBUS[8] D[7]/TBUS[7] D[6]/TBUS[6] D[5]/TBUS[5] VSS33 D[4]/TBUS[4] D[3]/TBUS[3] D[2]/TBUS[2] D[1]/TBUS[1] D[0]/TBUS[0] 135 100 140 145 85 80 W90P710 75 70 65 160 60 165 55 170 50 175 5 - 13 - 155 Fig 3.1 Pin Diagram 150 PHY_MDC/GPIO[51]/KP_ROW[1]/VD[17] PHY_MDIO/GPIO[50]/KPI_ROW[0]/VD[16] PHY_TXD[1]/GPIO[49]/KPI_COL[7]/VD[15] VDD33 PHY_TXD[0]/GPIO[48]/KPI_COL[6]/VD[14] PHY_TXEN/GPIO[47]/KPI_COL[5]/VD[13] PHY_REFCLK/GPIO[46]/KPI_COL[4]/VD[12] PHY_RXD[1]/GPIO[45]/KPI_COL[3]/VD[11] VSS33 PHY_RXD[0]/GPIO[44]/KPI_COL[2]/VD[10] PHY_CRSDV/GPIO[43]/KPI_COL[1]/VD[9] PHY_RXERR/GPIO[42]/KPI_COL[0]/VD[8] SC1_PWR/nXDACK/VD[8]/GPIO[20] SC1_PRES/nXDREQ/VD[9]GPIO[21] SC1_RST/SD_CD/VD[10]/GPIO[22] VSS33 SC1_CLK/SD_PWR/VD[11]/GPIO[23] SC1_DAT/SD_DAT3/VD[12]/GPIO[24] SC0_PWR/SD_DAT2/VD[13]/GPIO[25] VDD33 SC0_PRES/SD_DAT1/VD[14]/GPIO[26] SC0_RST/SD_DAT0/VD[15]/GPIO[27] SC0_CLK/SD_CLK/VD[16]/GPIO[28] SC0_DAT/SD_CMD/VD[17]/[GPIO[29] VSS18 VDD18 AC97_BITCLK/I2S_BITCLK/PWM[3]/RXD3/GPIO[4] AC97_SYNC/I2S_LRCLK/PWM[2]/TXD3/GPIO[3] AC97_DATAO/I2S_DATAO/PWM[1]/DSR3/GPIO[2] AC97_DATAI/I2S_DATAI/PWM[0]/DTR3/GPIO[1] AC97_nRESET/I2S_MCLK/GPIO[0] EXTAL32 (32.768K) XTAL32 (32.768K) RTCVDD18 VDD33 XTAL(15M) EXTAL(15M) VSS33 nWDOG/GPIO[15] nTRST TCK TDO TDI TMS 176 -pin LQFP Publication Release Date: September 19, 2006 Revision B2 105 110 95 90 125 130 120 115 nWAIT/TREQB nOE nECS[0] nECS[1] nECS[2] VDD33 VSS33 nECS[3] D[24]/VD[16]/GPIO[60] D[25]/VD[17]/GPIO[61] D[26]/VD[18]/GPIO[62] D[27]/VD[19]/GPIO[63] VDD33 D[28]/VD[20]/GPIO[64] D[29]/VD[21]/GPIO[65] D[30]/VD[22]/GPIO[66] D[31]/VD[23]/GPIO[67] A[21] VSS33 A[20] A[19] A[18] A[17]/TREQA VDD18 A[16]/TACK A[15]/TBUS[31] A[14]/TBUS[30] VSS18 A[13]/TBUS[29] A[12]/TBUS[28] A[11]/TBUS[27] A[10]/TBUS[26] VDD33 A[9]/TBUS[25] A[8]/TBUS[24] A[7]/TBUS[23] A[6]/TBUS[22] A[5]/TBUS[21] VSS33 A[4]/TBUS[20] A[3]/TBUS[19] A[2]/TBUS[18] A[1]/TBUS[17] A[0]/TBUS[16] W90P710CD/W90P710CDG 4. PIN ASSIGNMENT Table 4.1 W90P710 Pins Assignment PIN NAME 176-PIN LQFP Clock & Reset EXTAL (15M) XTAL (15M) EXTAL32 (32.768K) XTAL32 (32.768K) nRESET JTAG Interface TMS TDI TDO TCK nTRST External Bus Interface A [21] A [20:0] D [31:16] / VD [23:8] / GPIO [67:52] D [15:0] nWBE [3:2] / SDQM [3:2] / GPIO[69:68] nWBE [1;0] / SDQM [1:0] nSCS [1:0] nSRAS nSCAS MCKE nSWE MCLK nWAIT/ GPIO[70] / nIRQ5 nBTCS nECS [3] nECS [2:0] nOE ( 5 pins ) 52 53 57 56 37 ( 5 pins ) 45 46 47 48 49 ( 72 pins ) 115 113-110,108-106, 104-101,99-95, 93-89 116-119,121-124, 149-156 158,159,161-164, 166-170,172-176 146,145 144,143 136,135 137 138 134 142 140 132 133 125 128-130 131 - 14 - W90P710CD/W90P710CDG Table 4.1 W90P710 Pins Assignment (Continued) PIN NAME 176-PIN LQFP Ethernet Interface PHY_MDC / GPIO [51] / KPROW[1] / VD[17] PHY_MDIO / GPIO [50] / KPROW[0] / LD[16] PHY_TXD [1:0] / GPIO[49:48] / KPCOL[7:6] / VD[15:14] PHY_TXEN / GPIO [47] / KPCOL[5] / VD[13] PHY_REFCLK / GPIO [46] / KPCOL[4] / VD[12] PHY_RXD [1:0] / GPIO [45:44] / KPCOL[3:2] / VD[11:10] PHY_CRSDV / GPIO [43] / KPCOL[1] / VD[9] PHY_RXERR / GPIO [42] / KPCOL[0] / VD[8] AC97/I2S/PWM/UART3 AC97_nRESET / I2S_MCLK / GPIO [0] / USB_PWREN ( 10 pins ) 88 87 86,84 83 82 81,79 78 77 ( 5 pins ) 58 - 15 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Table 4.1 W90P710 Pins Assignment (Continued) PIN NAME 176-PIN LQFP AC97/I2S/PWM/UART3 AC97_DATAI / I2S_DATAI / PWM [0] / DTR3 / GPIO [1] AC97_DATAO / I2S_DATAO / PWM [1] / DSR3 / GPIO [2] AC97_SYNC / I2S_LRCLK / PWM [2] / TXD3 / GPIO [3] AC97_BITCLK / I2S_BITCLK / PWM [3] / RXD3 GPIO [4] USB Interface DP0 DN 0 DP1 DN1 Miscellaneous nIRQ [3:2] / GPIO [19:18] nIRQ [1] / GPIO [17] / USB_OVRCUR nIRQ [0] / GPIO [16] nWDOG / GPIO [15] / USB_PWREN RTCVDD18 ( 5 pins ) 59 60 61 62 ( 4 pins ) 7 6 2 3 ( 7 pins ) 148,147 44 43 50 55 - 16 - W90P710CD/W90P710CDG Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQFP I2C/USI(Microwire/SPI) SCL0 / SFRM / Timer0 / GPIO [11] SDA0 / SSPTXD / Timer1 / GPIO [12] SCL1 / SCLK / GPIO [13] / KPROW[3] SDA1 / SSPRXD / GPIO [14] / KPROW[2] UART0/UART1/UART2/PS2 TXD0 / GPIO [5] RXD0 / GPIO [6] TXD1 / GPIO [7] RXD1 / GPIO [8] CTS1 / TXD2(IrDA) / PS2_CLK / GPIO [9] RTS1 / RXD2(IrDA) / PS2_DATA / GPIO [10] ( 4 pins ) 17 18 19 20 ( 6 pins ) 10 11 12 13 14 15 - 17 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQFP SCHI/SD/XDMA SC0_DAT / SD_CMD / GPIO [29] / VD[17] SC0_CLK / SD_CLK / GPIO [28] / VD[16] SC0_RST / SD_DAT0 / GPIO [27] / VD[15] SC0_PRES / SD_DAT1 / GPIO [26] / VD[14] SC0_PWR / SD_DAT2 / GPIO [25] / VD[13] SC1_DAT / SD_DAT3 / GPIO [24] / VD[12] SC1_CLK / GPIO [23] / VD[11] SC1_RST / SD_CD / GPIO [22] / VD[10] SC1_PRES / nXDREQ / GPIO [21] / VD[9] SC1_PWR / nXDACK / GPIO [20] / VD[8] ( 10 pins ) 65 66 67 68 70 71 72 74 75 76 - 18 - W90P710CD/W90P710CDG Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQFP LCDC VD[7:0] / GPIO [41:34]/ KPCOL[7:0] HSYNC / GPIO [33]/ KPROW[3] VSYNC / GPIO [32]/ KPROW[2] VDEN / GPIO [31]/ KPROW[1] VCLK / GPIO [30]/ KPROW[0] Power/Ground VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS PLLVDD18 PLLVSS18 ( 12 pins ) 27-34 26 25 24 23 ( 36 pins ) 21,63,109,160 22,38,64,105,157 9,35,54,69,85,100, 120,127,139,165 16,36,51,73,80,94, 114,126,141,171 1,8 4,5 39,42 40,41 - 19 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 5. PIN DESCRIPTION Table 5.1 W90P710 Pins Description PIN NAME Clock & Reset IO TYPE I O I O IS IDS IUS IUS O IUS O IOS IOU IOU IOU O O O O O O DESCRIPTION 15MHz External Clock / Crystal Input 15MHz Crystal Output 32768Hz External Clock / Crystal Input(for RTC) 32768Hz Crystal Output(for RTC) System Reset, active-low JTAG Test Clock, internal pull-down with 58K ohm JTAG Test Mode Select, internal pull-up with 70K ohm JTAG Test Data in, internal pull-up with 70K ohm JTAG Test Data out JTAG Reset, active-low, internal pull-up with 70K ohm Address Bus (MSB) of external memory and IO devices. Address Bus of external memory and IO devices. Data Bus (MSB) of external memory and IO device, internal pull-up with 70K ohm. General Programmable In/Out Port GPIO[67:52]. Data Bus (LSB) of external memory and IO device. Write Byte Enable for specific device (nECS [3:0]). Data Bus Mask signal for SDRAM (nSCS [1:0]), active-low. General Programmable In/Out Port [69:68] SDRAM chip select for two external banks, active-low. Row Address Strobe for SDRAM, active-low. Column Address Strobe for SDRAM, active-low. SDRAM Write Enable, active-low SDRAM Clock Enable, active-high System Master Clock Out, SDRAM clock, output with slew-rate control External Wait, active-low. This pin indicates that the external devices need more active cycle during access operation. General Programmable In/Out Port GPIO[70]. If memory and IO devices in EBI do not need wait request, it can be configured as GPIO[7] or nIRQ5 ROM/Flash Chip Select, active-low. External I/O Chip Select, active-low. ROM/Flash, External Memory Output Enable, active-low. EXTAL (15M) XTAL (15M) EXTAL32(32.768 K) XTAL32(32.768K) nRESET JTAG Interface TCK TMS TDI TDO nTRST External Bus Interface A [21:18] A [17:0] D [31:16] / VD[23:8] / GPIO [67:52] D [15:0] / nWBE [3:0] / SDQM [3:0] / GPIO[69:68] nSCS [1:0] nSRAS nSCAS nSWE MCKE MCLK nWAIT / GPIO[70] / nIRQ5 nBTCS nECS [3:0] nOE IOU O O O - 20 - W90P710CD/W90P710CDG Table 5.1 W90P710 Pins Description (Continued) Pin Name Ethernet Interface PHY_MDC / GPIO [51] / KPROW[1] / VD[17] PHY_MDIO / GPIO [50] / KPROW[0] / VD[16] PHY_TXD [1:0] / GPIO [49:48] / KPCOL[7:6] / VD[15] PHY_TXEN / GPIO [47] / KPCOL[5] / VD[14:13] PHY_REFCLK / GPIO [46] / KPCOL[4] / VD[12] PHY_RXD [1:0] / GPIO [45:44] / KPCOL[3:2] / VD[11:10] PHY_CRSDV / GPIO [43] / KPCOL[1] / VD[9] IO Type Description RMII Management Data Clock for Ethernet. It is the reference clock of MDIO. Each MDIO data will be latched at the rising edge of MDC clock. General Programmable In/Out Port [51] Keypad ROW[1] scan output. LCD Pixel Data Output[17]. RMII Management Data I/O for Ethernet. It is used to transfer RMII control and status information between PHY and MAC. General Programmable In/Out Port [51] Keypad ROW[0] scan output. LCD Pixel Data Output[16]. 2-bit Transmit Data bus for Ethernet. General programmable In/Out Port [49:48] Keypad Column input [7:6], active low LCD Pixel Data Output[15]. PHY_TXEN shall be asserted synchronously with the first 2-bit of the preamble and shall remain asserted while all di-bits to be transmitted are presented. Of course, it is synchronized with PHY_REFCLK. General Programmable In/Out Port [47] Keypad column input [5], active low LCD Pixel Data Output[14:13]. Reference Clock. The clock shall be 50MHz +/- 50 ppm with minimum 35% duty cycle at high or low state. General Programmable In/Out port [46] Keypad column input [4], active low LCD Pixel Data Output[12]. 2-bit Receive Data bus for Ethernet. General Programmable In/Out Port [45:44] Keypad column input [3:2], active low LCD Pixel Data Output[11:10]. Carrier Sense / Receive Data Valid for Ethernet. The PHY_CRSDV shall be asserted by PHY when the receive medium is non-idle. Loss of carrier shall result in the de-assertion of PHY_CRSDV synchronous to the cycle of PHY_REFCLK, and only on 2-bit receive data boundaries. General Programmable In/Out port [43] Keypad column input [1], active low LCD Pixel Data Output[9]. Receive Data Error for Ethernet. It indicates a data error detected by PHY.The assertion should be lasted for longer than a period of PHY_REFCLK. When PHY_RXERR is asserted, the MAC will report a CRC error. General programmable In/Out port [42] Keypad column input [0], active low LCD Pixel Data Output[8]. IOU IO IOU IOU IOS IOS IOS PHY_RXERR / GPIO [42] / KPCOL[0] / VD[8] IOS - 21 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type Description AC97 CODEC Host Interface RESET Output. I2S CODEC Host Interface System Clock Output. General Purpose In/Out port [0] External interrupt request. USB host power enable output AC97 CODEC Host Interface Data Input. I2S CODEC Host Interface Data Input. PWM Channel 0 Output. Data Terminal Ready for UART4. General Purpose In /Out port [1] AC97 CODEC Host Interface Data Output. I2S CODEC Host Interface Data Output. PWM Channel 1 Output. Data Set Ready for UART4. General Purpose In/Out port [2] AC97 CODEC Host Interface Synchronous Pulse Output. I2S CODEC Host Interface Left/Right Channel Select Clock. PWM Channel 2 Output. Transmit Data for UART4. General Purpose In/Out port [3] AC97 CODEC Host Interface Bit Clock Input. I2S CODEC Host Interface Bit Clock. PWM Channel 3 Output. Receive Data for UART4. General Purpose In/Out port [4]. Differential Positive USB IO signal Differential Negative USB IO signal Differential Positive USB IO signal Differential Negative USB IO signal External Interrupt Request General Purpose I/O. External Interrupt Request General Purpose I/O nIRQ1 is used as USB host over-current detection input Watchdog Timer Timeout Flag and Keypad 3-keys reset output, active low General Purpose In/output USB host power switch enable output RTC independent battery power (1.8V) AC97/I2S/PWM/UART3 AC97_nRESET / I2S_MCLK / GPIO [0] / IOU nIRQ4 / USB_PWREN AC97_DATAI / I2S_DATAI / PWM [0] / IOU DTR4 / GPIO [1] AC97_DATAO / I2S_DATAO / PWM [1] / DSR4 / GPIO [2] AC97_SYNC / I2S_LRCLK / PWM [2] / TXD4 / GPIO [3] AC97_BITCLK / I2S_BITCLK / PWM [3] / RXD4 / GPIO [4] USB Interface DP0 DN0 DP1 DN1 Miscellaneous nIRQ [3:2] / GPIO [19:18] nIRQ [1:0] / GPIO [17:16] USB_OVRCUR nWDOG / GPIO [15] / USB_PWREN RTCVDD IOU P IOU IOU IOU IOS IO IO IO IO IOU - 22 - W90P710CD/W90P710CDG Table 5.1 W90P710 Pins Description (Continued) Pin Name I2C/USI(Microwire/SPI) IO Type Description SCL0 / SFRM / IOU Timer0 / GPIO [11] SDA0 / SSPTXD / IOU Timer1 / GPIO [12] SCL1 / SCLK / IOU GPIO [13] KPROW[3] SDA1 / SSPRXD / IDU GPIO [14] / KPROW[2] UART0/UART1/UART2 TXD0 / IOU GPIO [5] RXD0 / IOU GPIO [6] TXD1 / IOU GPIO [7] RXD1 / IOU GPIO [8] CTS1/ TXD2(IrDA) / IOU PS2_CLK / GPIO [9] RTS1/ RXD2(IrDA) / IOU PS2_DATA / GPIO [10] SCHI/SD/XDMA SC0_DAT/ SD_CMD / IOU GPIO [29] / VD[17] SC0_CLK / SD_CLK / IO GPIO [28] / VD[16] I2C Serial Clock Line 0. USI Serial Frame. Timer0 time out output. General Purpose In/Out port [11]. I2C Serial Data Line 0 USI Serial Transmit Data Timer1 time out output General Purpose In/Out port [12] I2C Serial Clock Line 1 USI Serial Clock General Purpose In/Out port [13] Keypad row scan output [3] I2C Serial Data Line 1 USI Serial Receive Data General Purpose In/Out port [14] Keypad scan output [2] UART0 Transmit Data. General Purpose In/Out [5] UART0 Receive Data. General Purpose In/Out [6] UART1 Transmit Data. General Purpose In/Out [7] UART1 Receive Data. General Purpose In/Out [8] UART1 Clear To Send for Bluetooth application UART2 Transmit Data supporting SIR IrDA. PS2 Interface Clock Input/Output General Purpose In/Out [9] UART1 Request To Send for Bluetooth application UART2 Receive Data supporting SIR IrDA. PS2 Interface Bi-Directional Data Line. General Purpose In/Out [10] Smart Card I/O Contact to Card 0. SD Mode – Command/Response; General Purpose In/Out [29] LCD Pixel Data Output[17]. Smart Card Clock Output to Card 0. SD Mode – Clock; General Purpose In/Out [28] LCD Pixel Data Output[16]. - 23 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Table 5.1 W90P710 Pins Description (Continued) Pin Name SCHI/SD/XDMA SC0_RST / SD_DAT0 / GPIO [27] / VD[15] SC0_PRES / SD_DAT1 / GPIO [26] VD[14] SC0_nPWR / SD_DAT2 / GPIO [25] / VD[13] SC1_DAT / SD_DAT3 / GPIO [24] / VD[12] SC1_CLK / GPIO [23] / VD[11] SC1_RST / SD_CD / GPIO [22] / VD[10] SC1_PRES / nXDREQ / GPIO [21] / VD[9] SC1_nPWR / nXDACK / GPIO [20] / VD[8] LCD Interface IO Type Description Smart Card Reset Output to Card 0. SD Mode – Data Line Bit 0; General Purpose In/Out [27] LCD Pixel Data Output[15]. Smart Card 0 Presence Contact Input. SD Mode – Data Line Bit 1. General Purpose In/Out [26] LCD Pixel Data Output[14].] Smart Card 0 Power FET Control Signal Output. SD Mode – Data Line Bit 2. General Purpose In/Out [25] LCD Pixel Data Output[13]. Smart Card I/O Contact to Card 1. SD Mode – Data Line Bit 3; General Purpose In/Out [24] LCD Pixel Data Output[12]. Smart Card Clock Output to Card 1. General Purpose In/Out [23] LCD Pixel Data Output[11]. Smart Card Reset Output to Card 1. SD Mode – Card Detect. General Purpose In/Out [22] LCD Pixel Data Output[10]. Smart Card 1 Presence Contact Input. External DMA Request. General Purpose In/Out [21] LCD Pixel Data Output[9]. Smart Card 1 Power FET Control Signal Output. External DMA Acknowledgement. General Purpose In/Out [20] LCD Pixel Data Output[8]. LCD Pixel Data Output [7:0]. General Purpose In/Out [41:34] Keypad Column input [7:0], active low Horizontal Sync General Purpose In/Out [33] Keypad ROW[3] scan output. Vertical Sync General Purpose In/Out [32] Keypad ROW[2] scan output. Data Enable or Display Control Signal. General Purpose In/Out [31] Keypad ROW[1] scan output. IO IO IO IO IO IO IO IO VD [7:0] / GPIO [41:34]/ KPCOL[7:0] HSYNC / GPIO [33]/ KPROW[3] VSYNC / GPIO [32]/ KPROW[2] VDEN / GPIO [31]/ KPROW[1] IOU IOU IOU IOU - 24 - W90P710CD/W90P710CDG Table 5.1 W90P710 Pins Description (Continued) Pin Name Power/Ground IO Type P G P G P G P G P G Description VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS DVDD18 DVSS18 AVDD18 AVSS18 Core Logic power (1.8V) Core Logic ground (0V) IO Buffer power (3.3V) IO Buffer ground (0V) USB power (3.3V) USB ground (0V) PLL Digital power (1.8V) PLL Digital ground (0V) PLL Analog power (1.8V) PLL Analog ground (0V) - 25 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List PIN NO. 1 2 3 4 5 6 7 8 9 DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 USB1.1 Host/Device Interface USB1VDD DP1 DN1 USB1VSS USB0VSS DN0 DP0 USB0VDD VDD33 USB1VDD DP1 DN1 USB1VSS USB0VSS DN0 DP0 USB0VDD VDD33 - UART[2:0]/PS2 Interface 10 11 12 13 14 15 16 GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] VSS33 GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] VSS33 UART_TXD0 UART_RXD0 UART_TXD1 UART_RXD1 UART_TXD2 UART_RXD2 I2C/USI Interface 17 18 19 20 21 22 GPIO[11] GPIO[12] GPIO[13] GPIO[14] VDD18 VSS18 GPIO[11] GPIO[12] GPIO[13] GPIO[14] VDD18 VSS18 I2C_SCL0 I2C_SDA0 I2C_SCL1 I2C_SDA1 SSP_FRAM SSP_TXD SSP_RXD SSP_SCLK TIMER0 TIMER1 KPROW[2] KPROW[3] UART_CTS1 UART_RTS1 PS2_CLK PS2_DATA - LCD /KeyPad Interface 23 24 25 26 27 GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[41] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[41] LCD_VCLK LCD_VDEN LCD_VSYNC LCD_HSYNC LCD_VD[7] KPROW[0] KPROW[1] KPROW[2] KPROW[3] KPCOL[7] - - 26 - W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 LCD /KeyPad Interface 28 29 30 31 32 33 34 35 36 GPIO[40] GPIO[39] GPIO[38] GPIO[37] GPIO[36] GPIO[35] GPIO[34] VDD33 VSS33 GPIO[40] GPIO[39] GPIO[38] GPIO[37] GPIO[36] GPIO[35] GPIO[34] VDD33 VSS33 System Reset 37 38 nRESET VSS33 nRESET VSS33 LCD_VD[6] LCD_VD[5] LCD_VD[4] LCD_VD[3] LCD_VD[2] LCD_VD[1] LCD_VD[0] KPCOL[6] KPCOL[5] KPCOL[4] KPCOL[3] KPCOL[2] KPCOL[1] KPCOL[0] - PLL Power/Ground 39 40 41 42 PLL0_VDD18 PLL0_VSS18 PLL1_VSS18 PLL1_VDD18 PLL0_VDD18 PLL0_VSS18 PLL1_VSS18 PLL1_VDD18 - External IRQ[1:0]/USB Over Current 43 44 GPIO[16] GPIO[17] GPIO[16] GPIO[17] nIRQ[0] nIRQ[1] JTAG Interface 45 46 47 48 49 TMS TDI TDO TCK nTRST TMS TDI TDO TCK nTRST USB_OVRCUR - WatchDog/USB Power Enable 50 51 GPIO[15] VSS33 GPIO[15] VSS33 nWDOG USB_PWREN - - 27 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 System/RTC Clock 52 53 54 55 56 57 EXTAL(15M) XTAL(15M) VDD33 RTCVDD18 XTAL32 (32K) EXTAL32 (32K) EXTAL(15M) XTAL(15M) VDD33 RTCVDD18 XTAL32 (32K) EXTAL32 (32K) - AC97/I2S/PWM/UART3 Interface 58 59 60 61 62 63 64 GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] VDD18 VSS18 GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] VDD18 VSS18 AC97_nRESET AC97_DATAI AC97_DATAO AC97_SYNC AC97_BITCLK IRQ4 PWM0 PWM1 PWM2 PWM3 USB_PWREN UART_DTR3 UART_DSR3 UART_TXD3 UART_RXD3 - SmartCard/SD/USB Power/XDMAREQ/LCD Interace 65 66 67 68 69 70 71 72 73 74 75 76 GPIO[29] GPIO[28] GPIO[27] GPIO[26] VDD33 GPIO[25] GPIO[24] GPIO[23] VSS33 GPIO[22] GPIO[21] GPIO[20] GPIO[29] GPIO[28] GPIO[27] GPIO[26] VDD33 GPIO[25] GPIO[24] GPIO[23] VSS33 GPIO[22] GPIO[21] GPIO[20] SD_CD nXQREQ nXDACK SC1_RST SC1_PRES SC1_PWR LCD_VD[10] LCD_VD[9] LCD_VD[8] SD_DAT[2] SD_DAT[3] USBPWREN SC0_PWR SC1_IO SC1_CLK LCD_VD[13] LCD_VD[12] LCD_VD[11] SD_CMD SD_CLK SD_DAT[0] SD_DAT[1] SC0_IO SC0_CLK SC0_RST SC0_PRES LCD_VD[17] LCD_VD[16] LCD_VD[15] LCD_VD[14] - 28 - W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Ethernet RMII/KeyPad Interface 77 78 79 80 81 82 83 84 85 86 87 88 GPIO[42] GPIO[43] GPIO[44] VSS33 GPIO[45] GPIO[46] GPIO[47] GPIO[48] VDD33 GPIO[49] GPIO[50] GPIO[51] GPIO[42] GPIO[43] GPIO[44] VSS33 GPIO[45] GPIO[46] GPIO[47] GPIO[48] VDD33 GPIO[49] GPIO[50] GPIO[51] PHY_RXERR PHY_CRSDV PHY_RXD[0] PHY_RXD[1] PHY_REFCLK PHY_TXEN PHY_TXD[0] PHY_TXD[1] PHY_MDIO PHY_MDC KPCOL[0] KPCOL[1] KPCOL[2] KPCOL[3] KPCOL[4] KPCOL[5] KPCOL[6] KPCOL[7] KPROW[0] KPROW[1] LCD_VD[15] LCD_VD[16] LCD_VD[17] LCD_VD[8] LCD_VD[9] LCD_VD[10] LCD_VD[11] LCD_VD[12] LCD_VD[13] LCD_VD[14] Memory Address/Data/Control 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 A[0] A[1] A[2] A[3] A[4] VSS33 A[5] A[6] A[7] A[8] A[9] VDD33 A[10] A[11] A[12] A[13] A[0] A[1] A[2] A[3] A[4] VSS33 A[5] A[6] A[7] A[8] A[9] VDD33 A[10] A[11] A[12] A[13] - - 29 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 VSS18 A[14] A[15] A[16] VDD18 A[17] A[18] A[19] A[20] VSS33 A[21] D[31] D[30] D[29] D[28] VDD33 D[27] D[26] D[25] D[24] nECS[3] VSS33 VDD33 nECS[2] nECS[1] nECS[0] nOE nWAIT nBTCS MCKE VSS18 A[14] A[15] A[16] VDD18 A[17] A[18] A[19] A[20] VSS33 A[21] GPIO[67] GPIO[66] GPIO[65] GPIO[64] VDD33 GPIO[63] GPIO[62] GPIO[61] GPIO[60] nECS[3] VSS33 VDD33 nECS[2] nECS[1] nECS[0] nOE GPIO[71] nBTCS MCKE D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] nWAIT LCD_VD[23] LCD_VD[22] LCD_VD[21] LCD_VD[20] LCD_VD[19] LCD_VD[18] LCD_VD[17] LCD_VD[16] IRQ5 - - 30 - W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 152 153 154 155 156 157 158 159 160 161 162 nSCS[0] nSCS[1] nSRAS nSCAS VDD33 MCLK VSS33 nWE nWBE_SDQM[0] nWBE_SDQM[1] nWBE_SDQM[2] nWBE_SDQM[3] GPIO[18] GPIO[19] GPIO[59] D[22] D[21] D[20] D[20] D[19] D[18] D[17] D[16] VSS18 D[15] D[14] VDD18 D[13] D[12] nSCS[0] nSCS[1] nSRAS nSCAS VDD33 MCLK VSS33 nWE nWBE_SDQM[0] nWBE_SDQM[1] GPIO[69] GPIO[68] GPIO[18] GPIO[19] GPIO[59] GPIO[58] GPIO[57] GPIO[56] GPIO[56] GPIO[55] GPIO[54] GPIO[53] GPIO[52] VSS18 D[15] D[14] VDD18 D[13] D[12] nWBE_SDQM[2] nWBE_SDQM[3] nIRQ[2] nIRQ[3] D[23] D[22] D[21] D[20] D[20] D[19] D[18] D[17] D[16] LCD_VD[15] LCD_VD[14] LCD_VD[13] LCD_VD[12] LCD_VD[12] LCD_VD[11] LCD_VD[10] LCD_VD[9] LCD_VD[8] - - 31 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 163 164 165 166 167 168 169 170 171 172 173 174 175 176 D[11] D[10] VDD33 D[9] D[8] D[7] D[6] D[5] VSS33 D[4] D[3] D[2] D[1] D[0] D[11] D[10] VDD33 D[9] D[8] D[7] D[6] D[5] VSS33 D[4] D[3] D[2] D[1] D[0] - - 32 - W90P710CD/W90P710CDG 6. 6.1 FUNCTIONAL DESCRIPTION ARM7TDMI CPU CORE The ARM7TDMI CPU core is a member of the Advanced RISC Machines (ARM) family of generalpurpose 32-bit microprocessors, which offer high performance for very low power consumption. The architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set Computers. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. The high instruction throughput and impressive real-time interrupt response are the major benefits. The ARM7TDMI CPU core has two instruction sets: (1) The standard 32-bit ARM set (2) A 16-bit THUMB set The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM core while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. THUMB instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with the same effect on the processor model. ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 sets are visible; the other registers are used to speed up exception processing. All the register specified in ARM instructions can address any of the 16 registers. The CPU also supports 5 types of exception, such as two levels of interrupt, memory aborts, attempted execution of an undefined instruction and software interrupts. A[31:0] Address Register Incrementer Bus Scan Control Address Incrementer Register Bank (31 x 32-bit registers) (6 status registers) B Bus PC Bus Instruction Decoder Control Logic 32 x8 Multiplier ALU Bus A Bus Barrel Shifter Instruction Pipeline Read Data Register Thumb Instruction Decoder Writer Data Register 32-bit ALU D[31:0] Fig 6.1 ARM7TDMI CPU Core Block Diagram - 33 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 6.2 6.2.1 System Manager Overview The W90P710 System Manager has the following functions. System memory map Data bus connection with external memory Product identifier register Bus arbitration PLL module Clock select and power saving control register Power-On setting 6.2.2 System Memory Map W90P710 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0_0000 – 0xFFFF_FFFF) and the OnChip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable space: 0x0000_0000 ~ 0x7FDF_FFFF if Cache ON; non-cacheable space: 0x8000_0000 ~ 0xFFDF_FFFF). The size and location of each bank is determined by the register settings for “current bank base address pointer” and “current bank size”. Please note that when setting the bank control registers, the address boundaries of consecutive banks must not overlap. Except On-Chip Peripherals and On-Chip RAM, the start address of each memory bank is not fixed. You can use bank control registers to assign a specific bank start address by setting the bank’s base pointer (13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer FCR [11:8] = 0xc Fraction part: 0.65 X 60 = 39(0x27) => FCR[5:0]=0x27 Frequency counter measurement: 32765.27Hz Integer part: 32765=> FCR [11:8] = 0x4 Fraction part: 0.27 X 60 = 16.2(0x10) => FCR [5:0] = 0x10 RTC Time Loading Register (RTC_TLR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_TLR 0xFFF8_400C R/W RTC Time Loading Register 0X0000_0000 31 23 Reserved 15 Reserved 7 Reserved 30 22 29 21 Hi_hr 28 Reserved 20 27 19 26 18 Lo_hr 25 17 24 16 14 13 Hi_min 12 11 10 Lo_min 9 8 6 5 Hi_sec 4 3 2 Lo_sec 1 0 Note: TLR is a BCD digit counter and RTC will not check loaded data. BITS DESCRIPTIONS [21:20] [19:16] [14:12] [11:8] [6:4] [3:0] Hi_hr Lo_hr Hi_min Lo_min Hi_sec Lo_sec 10 hour time digit 1 hour time digit 10 min time digit 1 min time digit 10 sec time digit 1 sec time digit - 429 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG RTC Calendar Loading Register (RTC_CLR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_CLR 0xFFF8_4010 R/W RTC Calendar Loading Register 0X0005_0101 31 23 15 7 Reserved 30 22 Hi_year 14 Reserved 6 29 21 13 5 Hi_day 28 Reserved 20 12 Hi_mon 4 27 19 11 3 26 18 Lo_year 10 Lo_mon 2 Lo_day 25 17 9 1 24 16 8 0 Note: CLR is a BCD digit counter and RTC will not check loaded data. BITS DESCRIPTIONS [23:20] [19:16] [12] [11:8] [5:4] [3:0] Hi_year Lo_year Hi_mon Lo_mon Hi_day Lo_day 10-year calendar digit 1-year calendar digit 10-month calendar digit 1-month calendar digit 10-day calendar digit 1-day calendar digit RTC Time Scale Selection Register (RTC_TSSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_TSSR 0xFFF8_40014 R/W Time Scale Selection Register 0X0000_0001 - 430 - W90P710CD/W90P710CDG 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 Reserved 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 24Hr/12Hr BITS DESCRIPTIONS [31:1] Reserved 24Hr/12Hr : 24hour / 12 hour mode selection It indicate that TLR and TAR are in 24-hour mode or 12-hour mode 1 = select 24-hour time scale 0 = select 12-hour time scale with am and pm indication 24-hour time scale 12-hour time scale 24-hour time scale 12-hour time scale 00 01 [0] 24Hr/12Hr 02 03 04 05 06 07 08 09 10 11 12(AM12) 01(AM01) 02(AM02) 03(AM03) 04(AM04) 05(AM05) 06(AM06) 07(AM07) 08(AM08) 09(AM09) 10(AM10) 11(AM11) 12 13 14 15 16 17 18 19 20 21 22 23 32(PM12) 21(PM01) 22(PM02) 23(PM03) 24(PM04) 25(PM05) 26(PM06) 27(PM07) 28(PM08) 29(PM09) 30(PM10) 31(PM11) - 431 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG RTC Day of the Week Register (RTC_DWR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_DWR 0xFFF8_4018 R/W Day of the Week Register 0X0000_0006 31 23 15 7 30 22 14 6 29 21 13 5 Reserved 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 25 17 9 1 DWR[2:0] 24 16 8 0 BITS DESCRIPTIONS [31:3] Reserved DWR[2:0] : Day of the Week Register 0 1 Sunday Monday Tuesday Wednesday Thursday Friday Saturday [2:0] DWR 2 3 4 5 6 RTC Time Alarm Register (RTC_TAR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_TAR 0xFFF8_401C R/W RTC Time Alarm Register 0X0000_0000 - 432 - W90P710CD/W90P710CDG 31 23 Reserved 15 Reserved 7 Reserved 30 22 14 6 29 21 13 Hi_min_alarm 5 Hi_sec_alarm 28 Reserved 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 Hi_hr_alarm Hi_hr_alarm Lo_min_alarm Lo_sec_alarm TAR is a BCD digit register and RTC will not check loaded data. BITS DESCRIPTIONS [31:22] [21:20] [19:16] [15] [14:12] [11:8] [7] [6:4] [3:0] Reserved Hi_hr_alarm Lo_hr_alarm Reserved Hi_min_alarm Lo_min_alarm Reserved Hi_sec_alarm Lo_sec_alarm 10 hour time digit 1 hour time digit 10 min time digit 1 min time digit 10 sec time digit 1 sec time digit RTC Calendar Alarm Register (RTC_CAR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_CAR 0xFFF8_4020 R/W RTC Calendar Alarm Register 0X0000_0000 - 433 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 31 23 15 30 22 14 Reserved 29 21 13 28 Reserved 20 12 Hi_mon_ alarm 27 19 11 26 18 10 25 17 9 24 16 8 Hi_year_alarm Lo_year_alarm Lo_mon_alarm 3 2 1 0 7 Reserved 6 5 4 Hi_day_alarm Lo_day_alarm CAR is a BCD digit register and RTC will not check loaded data. BITS DESCRIPTIONS [31:24] [23:20] [19:16] [15:13] [12] [11:8] [5:4] [3:0] Reserved Hi_year Lo_year Reserved Hi_mon Lo_mon Hi_day Lo_day 10-year calendar digit 1-year calendar digit 10-month calendar digit 1-month calendar digit 10-day calendar digit 1-day calendar digit RTC Leap year Indication Register (RTC_LIR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_LIR 0xFFF8_4024 R RTC Leap year Indication Register 0X0000_0000 - 434 - W90P710CD/W90P710CDG 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 Reserved 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 LIR[0] BITS DESCRIPTIONS [31:1] Reserved LIR [0]: Real only. Leap year Indication REGISTER [0] LIR 1 = It indicate that this year is leap year 0 = It indicate that this year is not a leap year RTC Interrupt Enable Register (RTC_RIER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_RIER 0xFFF8_4028 R/W RTC Interrupt Enable Register 0X0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 Reserved 27 19 11 3 26 18 10 2 25 17 9 1 Tick_int_en 24 16 8 0 Alarm_int_en - 435 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:2] [1] Reserved Tick_int_en 1 = RTC Time Tick Interrupt and counter enable 0 = RTC Time Tick Interrupt and counter disable 1 = RTC Alarm Interrupt enable 0 = RTC Alarm Interrupt disable [0] Alarm_int_en RTC Interrupt Indication Register (RTC_RIIR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_RIIR 0xFFF8_402C R/C RTC Interrupt Indication Register 0X0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 Reserved 27 19 11 3 26 18 10 2 25 17 9 1 Tick_int_st 24 16 8 0 Alarm_int_st BITS DESCRIPTIONS [31:2] Reserved RTC Time Tick Interrupt Indication REGISTER 1 = It indicates that time tick interrupt has been activated. [1] Tick_int_st 0 = It indicates that time tick interrupt has never occurred. Software Can also clear this bit after RTC interrupt has occur. - 436 - W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS RTC Alarm Interrupt Indication REGISTER 1 = It indicates that time counter and calendar counter have counted [0] Alarm_int_st to a specified time recorded in TAR and CAR. RTC alarm interrupt has been activated. 0 = It indicates that alarm interrupt has never occurred. Software can Also clear this bit after RTC interrupt has occurred. Note : User can clear these two bits by writing 0x0 to RIIR RTC Tick Time Register (RTC_TTR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_TTR 0xFFF8_4030 R/W RTC Tick Time Register 0X0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 Reserved 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 26 18 10 2 25 17 9 1 TTI 24 16 8 0 - 437 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:3] Reserved RTC Tick Time Interrupt request Interval The TTR [2:0] is used to select tick time interrupt request interval. The period of tick time interrupt is as follow: TTR[2:0] 0 Tick Time interrupt interval 1 sec 1/2 sec 1/4 sec 1/8 sec 1/16 sec 1/32 sec 1/64 sec 1/128 sec [2:0] TTI 1 2 3 4 5 6 7 - 438 - W90P710CD/W90P710CDG 6.16.2 RTC Application Note Detect RTC frequency Step1. Configure GPIO register GPIOCFG5[21:20] as “2’b11” Step2. Making use of frequency counter (for example: Agilent 53131A) to detect W90P710 IO Pin “GPIO15/nWDOG/USBPWREN”. Note: Because the parasitic capacitance would slow crystal oscillation, do not connect the probe with 32K crystal directly. RTC application circuit 1. The recommended RTC appliction circuit is ad following: RTCVDD1.8V C1 EXTAL32 C2 XTAL32 2. 3. 4. 5. C1 and C2 can not be connected to ground for improving noise issue. Do not connect any register in the circuit. Redundant register may stop crystal oscillation. To avoid parastic capacitance and resistance, user had better to place all components as close as possible. The C1 and C2 vaule would be changed by different crystal because different crystal requires different oscillation condition. In general, capacitance value of C1/C2 is between 10pF and 30pF. - 439 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 6.17 Smart Card Host Interface The Smart Card resides in APB bus. The whole chip of W90P710 operates at voltage level of 3.3 V except Smart Card Interface port's I/O pins that are at 5 V to be compatible with mainstream Smart Card implementations. Advanced power management feature further optimizes power consumption whether in operation or in power down mode. ISO-7816 compliant PC/SC T=0, T=1 compliant 16-byte transmitter FIFO and 16-byte receiver FIFO FIFO threshold interrupt to optimize system performance Programmable transmission clock frequency Versatile baud rate configuration UART-like register file structure Versatile 8-bit, 16-bit, 24-bit time-out counter for Answer-To-Reset (ATR) and waiting times processing. Parity error counter in reception mode and in transmission mode with automatic re-transmission. Automatic activation and deactivation sequence through an independence sequencer 6.17.1 Register Mapping R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written. Table 6.12.2.1 Smart Card Host Interface 0 Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE Smartcard Host Interface 0 SCHI_RBR0 SCHI_TBR0 SCHI_IER0 SCHI_ISR0 SCHI_SCFR0 SCHI_SCCR0 SCHI_CBR0 SCHI_SCSR0 SCHI_GTR0 SCHI_ECR0 SCHI_TMR0 SCHI_TOC0 0xFFF8_5000 (BDLAB=0) R Receiver Buffer Register Undefined Undefined 0x0000_0080 0X0000_00C1 0x0000_0000 0x0000_0018 0x0000_000C 0x0000_0060 0x0000_0001 0x0000_0052 0x0000_0000 0x0000_0000 0x0000_0000 0xFFF8_5000 (BDLAB=0) W Transmitter Buffer Register 0xFFF8_5004 (BDLAB=0) R/W Interrupt Enable Register 0xFFF8_5008 (BDLAB=0) 0xFFF8_500C 0xFFF8_5010 0xFFF8_5014 0xFFF8_5018 0xFFF8_501C 0xFFF8_5020 0xFFF8_5028 R Interrupt Status Register 0xFFF8_5008 (BDLAB=0) W Smart card FIFO Control Register R/W Smart card Control Register R/W Clock Base Register R Smart Card Status Register R/W Guard Rime Register R/W Extended Control Register R/W Test Mode Register R/W Time out Configuration Register R/W Time out Initial Register 0 SCHI_TOIR0_0 0xFFF8_502C - 440 - W90P710CD/W90P710CDG Table 6.12.2.1 Smart Card Host Interface 0 Register Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOIR1_0 0xFFF8_5030 SCHI_TOIR2_0 0xFFF8_5034 SCHI_TOD0_0 0xFFF8_5038 SCHI_TOD1_0 0xFFF8_503C SCHI_TOD2_0 0xFFF8_5040 SCHI_BTOR_0 0xFFF8_5044 SCHI_BLL_0 SCHI_BLH_0 SCHI_ID_0 SCHI_RBR1 SCHI_TBR1 SCHI_IER1 SCHI_ISR1 SCHI_SCFR1 SCHI_SCCR1 SCHI_CBR1 SCHI_SCSR1 SCHI_GTR1 SCHI_ECR1 SCHI_TMR1 SCHI_TOC1 R/W Time out Initial Register 1 R/W Time out Initial Register 2 R R R Time out Data Register 0 Time out Data Register 1 Time out Data Register 2 0x0000_0000 0x0000_0000 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_0000 R/W Buffer Time out Data Register 0xFFF8_5000 (BDLAB=1) R/W 0xFFF8_5004 (BDLAB=1) R/W 0xFFF8_5008 (BDLAB=1) 0xFFF8_5800 (BDLAB=0) R R Baud Rate Divisor Latch Lower Byte 0x0000_001F Register Baud Rate Divisor Latch Higher 0x0000_0000 Byte Register Smart Card ID Number Register Receiver Buffer Register 0x0000_0070 Undefined Undefined 0x0000_0080 0X0000_00C1 0x0000_0000 0x0000_0018 0x0000_000C 0x0000_0060 0x0000_0001 0x0000_0052 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_0000 Smartcard Host Interface 1 0xFFF8_5800 (BDLAB=0) W Transmitter Buffer Register 0xFFF8_5804 (BDLAB=0) R/W Interrupt Enable Register 0xFFF8_5808 (BDLAB=0) 0xFFF8_580C 0xFFF8_5810 0xFFF8_5814 0xFFF8_5818 0xFFF8_581C 0xFFF8_5820 0xFFF8_5828 R Interrupt Status Register 0xFFF8_5808 (BDLAB=0) W Smart card FIFO Control Register R/W Smart card Control Register R/W Clock Base Register R Smart Card Status Register R/W Guard Rime Register R/W Extended Control Register R/W Test Mode Register R/W Time out Configuration Register R/W Time out Initial Register 0 R/W Time out Initial Register 1 R/W Time out Initial Register 2 R R R Time out Data Register 0 Time out Data Register 1 Time out Data Register 2 SCHI_TOIR0_1 0xFFF8_582C SCHI_TOIR1_1 0xFFF8_5830 SCHI_TOIR2_1 0xFFF8_5834 SCHI_TOD0_1 0xFFF8_5838 SCHI_TOD1_1 0xFFF8_583C SCHI_TOD2_1 0xFFF8_5840 SCHI_BTOR1 SCHI_BLL1 SCHI_BLH1 SCHI_ID1 0xFFF8_5844 R/W Buffer Time out Data Register 0xFFF8_5800 (BDLAB=1) R/W 0xFFF8_5804 (BDLAB=1) R/W 0xFFF8_5808 (BDLAB=1) R Baud Rate Divisor Latch Lower Byte 0x0000_001F Register Baud Rate Divisor Latch Higher 0x0000_0000 Byte Register Smart Card ID Number Register 0x0000_0070 - 441 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 6.17.2 Register Description Receive Buffer Register (SCHI_RBR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_RBR0 SCHI_RBR1 31 23 15 7 0XFFF8_5000 (DLAB = 0) 0xFFF8_5800 (DLAB = 0) 30 22 14 6 29 21 13 5 R R Receiver Buffer Register 0 Receiver Buffer Register 1 26 18 10 2 25 17 9 1 Undefined Undefined 24 16 8 0 28 27 RESERVED 20 19 RESERVED 12 11 RESERVED 4 3 RxBDATA[7:0] BITS DESCRIPTIONS [31:8] RESERVED 8-bit Received Data [7:0] RxBDATA By reading this register, the SCHI will return an 8-bit data received from SCx_DAT pin. This register is the access port for receiver FIFO. The depth of receiver FIFO is 16 bytes. Transmit Buffer Register (SCHI_TBR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TBR0 SCHI_TBR1 0xFFF8_5000(DLAB = 0) 0xFFF8_5800(DLAB = 0) W W Transmit Buffer Register 0 Transmit Buffer Register 1 Undefined Undefined - 442 - W90P710CD/W90P710CDG 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 RESERVED 4 TxBDATA[7:0] BITS DESCRIPTIONS [31:8] RESERVED 8-bit Transmit Buffer Data [7:0] TxBDATA By writing to this register, the SCHI will send out an 8-bit data through the SCx_DAT pin. This register is the access port for transmitter FIFO. transmitter FIFO is 16 bytes. The depth of Interrupt Enable register (SCHI_IER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_IER0 SCHI_IER1 0xFFF8_5004 (DLAB = 0) 0xFFF8_5804 (DLAB = 0) R/W Interrupt Enable Register 0 R/W Interrupt Enable Register 1 0x0000_0080 0x0000_0080 31 23 15 7 PWRDN 30 22 14 6 Interface 29 21 13 RESERVED 28 20 12 4 27 19 11 3 ESCPTI 26 18 10 ETOR2 2 ESCSRI 25 17 9 ETOR1 1 ETBREI 24 16 8 ETOR0 0 ERDRI RESERVED RESERVED 5 RESERVED - 443 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:11] RESERVED TOR2 interrupt enable bit When 24 bit time-out counter decrease to zero, it will set TO2 flag to high. If we set ETOR2 to high, then the 24 bit time-out counters will interrupt CPU to indicate that the time-out count is reached. TOR1 interrupt enable bit When 16 bit time-out counter decrease to zero, it will set TO1 flag to high. If we set ETOR1 to high, then the 16 bit time-out counters will interrupt CPU to indicate that the time-out count is reached. TOR0 interrupt enable bit When 8 bit time-out counter decrease to zero, it will set TO0 flag to high. If we set ETOR0 to high, then the 8 bit time-out counters will interrupt CPU to indicate that the time-out count is reached. Smart card POWER DOWN bit PWRDN is used when the Smartcard controller needs to be powered down. Powering down must be done whenever the controller needs to switch between class A and B. When this bit is a ‘1’, it will deactivate all contacts to the Smartcard except for SCRST_L which will be discussed later. When the Smartcard is removed, the H/W will also set the POWER DOWN bit. Smart card different interface bit Interface is used for controlling the different power control device signals. When ‘1’, the controller will direct a power control pin is active high. When ‘0’, a power control pin is active low to meet different power control interface. Reserved for future Smart card present toggle interrupt enable bit A rising/falling edge of SCPSNT signal triggers an interrupt if this bit is set to "1". 0 = SCPSNT toggle interrupt is disabled. 1 = SCPSNT toggle interrupt is enabled. Enable SCSR interrupt bit An ESCSRI means interrupt enable bit for SCSR-related events such as silent byte detected error, no stop bit error, parity bit error or overrun error. Any SCSR-related event as described above will trigger an interrupt if this bit is set to "1". 0 = SCSR-related event interrupt is disabled. 1 = SCSR-related event interrupt is enabled. [10] ETOR2 [9] ETOR1 [8] ETOR0 [7] PWRDN [6] Interface [5:4] RESERVED [3] ESCPTI [2] ESCSRI - 444 - W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Enable Transmit Buffer Empty interrupt bit [1] ETBREI An ETBREI means interrupt enable bit for TBR (Transmitter Buffer Register) empty condition. An interrupt is issued when TBR is empty and this bit is set to "1". 0 = TBR empty interrupt is disabled. 1 = TBR empty interrupt is enabled. Enable Receive Data Ready interrupt bit The active FIFO threshold level for this kind of interrupt when FIFO is enabled is specified in RxTL1 and RxTL0 (bit 7 and bit 6 of SCFR at base address + 8. Refer to description of SCFR for details). An interrupt is issued if a data byte is ready for host to read when FIFO is disabled or incoming data from card reaches active FIFO threshold level when FIFO is enabled. [0] ERDRI Interrupt Status Register (SCHI_ISR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_ISR0 SCHI_ISR1 0xFFF8_5008 (DLAB = 0) 0xFFF8_5808 (DLAB = 0) R R Interrupt Status Register 0 Interrupt Status Register 1 0x0000_00C1 0x0000_00C1 31 23 15 7 RESERVED 30 22 14 6 29 21 13 5 SCPSNT 28 RESERVED 27 19 11 3 INTS2 26 18 10 2 INTS1 25 17 9 1 INTS0 24 16 8 0 Interrupt pending 20 RESERVED 12 RESERVED 4 SCPTI This register contains mainly interrupt status including transmission-related interrupts and SCPSNT toggle interrupt. Transmission-related interrupt status is coded and prioritized as in UART implementation. User may also find FIFO enable/disabled status reflecting what is set in bit 0 of SCFR (write only Smart Card FIFO Register at base address + 8 when BDLAB = 0) and SCPSNT line status. - 445 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:6] [5] RESERVED SCPSNT Smart card present line status. User may poll this bit to see SCPSNT pin's voltage level 0 = Smart card has been remove from the reader 1 = Smart card IC is contact with the reader SCPSNT toggle interrupt status. A rising/falling edge of SCPSNT signal triggers an interrupt and set this status bit if ESCPTI (IER bit 3) is set to "1" to enable SCPSNT toggle interrupt. 0= No SCPSNT toggle interrupt. 1 = SCPSNT toggle interrupt occurs. Interrupt Status bit 2 ~0 The combination indicates which kind of transmission-related interrupt has occurred. Refer to the following table for details. 3 0 1 ISR bit 21 0 0 0 0 1 1 0 Interrupt set and function Priority Interrupt Interrupt source Clear interrupt condition type first No interrupt pending SCPTI =1 Card insert or remove Read ISR [4] SCPTI 1 1 1 0 1. TO2 =1 second TIMEOUT 2. TO1 =1 interrupt 3. TO0 =1 third 1. OER = 1 Data receiving 2. PBER = 1 status 3. NSER = 1 4. SBD = 1 RBR data ready Read SCSR [3:1] INTS2 INTS0 ~ 0 1 1 0 Read SCSR 0 1 0 0 fourth 1. RBR data ready 1. Read RBR 2. FIFO interrupt active 2. Read RBR until FIFO level reached is under active level 1 1 0 0 fifth Receiver FIFO is non- Read RBR FIFO data time empty and no activities are occurred in the out receiver FIFO during the TOR defined time duration TBR empty TBR empty 1. Write data to TBR 2. Read ISR (if priority is sixth) 0 0 1 0 sixth [0] Interrupt pending Interrupt pending status bit. This bit is a logical "1" if there is no interrupt pending. If one of the interrupt sources occurs, this bit will be set to a logical "0". 0 = Interrupt pending. 1 = No interrupt occurs. - 446 - W90P710CD/W90P710CDG Smart Card FIFO control Register (SCHI_SCFR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_SCFR0 0xFFF8_5008 (DLAB = 0) SCHI_SCFR1 0xFFF8_5808 (DLAB = 0) W W Interrupt Status Register 0 Interrupt Status Register 1 0x0000_0000 0x0000_0000 31 23 15 7 RxTL1 30 22 14 6 RxTL0 29 21 13 5 PEC2 28 RESERVED 27 19 11 3 PEC0 26 18 10 2 TxFRST 25 17 9 1 RxFRST 24 16 8 0 Reserved 20 RESERVED 12 RESERVED 4 PEC1 BITS DESCRIPTIONS [31:8] RESERVED Receiver FIFO active Threshold Level control bits. These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are at least 4 data characters in the receiver FIFO, an interrupt is activated to notify host to read data from FIFO. Default to be 00b. [7:6] RxTL1, RxTL0 RxTL1 RxTL0 Rx FIFO Interrupt Active Level (Bytes) 0 0 1 1 0 1 0 1 01 04 08 14 - 447 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS [5:3] PEC2, PEC1, PEC0 Parity Error Count. Bits PEC2, PEC1 and PEC0 determine the number of allowed repetitions in reception or in transmission before setting bit PBER in SCSR. The value 000 indicates that, if only one parity error has occurred, bit PE is set; the value 111 indicate that bit PE will be set after 8 parity errors. In protocol T =0: If a correct character is received before the programmed error number is reached, the error counter will be reset If the programmed number of allowed parity errors is reached, bit PBER in register SCSR will be set as long as register SCSR has not been read. If a transmitted character has been NAK by the card, then our smart card host interface will automatically re-transmit it a number of times equal to the value programmed in bits PEC2, PEC1 and PEC0 by generating interrupt to inform CPU to flush the transmit buffer. In transmission mode, if bits PEC2, PEC1 and PEC0 are logic 0, then the automatic re-transmission is invalided. The retransmitted character will start after the gardtime. So if you set guardtime =2 and the card pull 2 etu low, then there will be no guardtime. Set guardtime =3 when T=0 in case of 2 etu pull down NAK by card. In protocol T= 1: The error counter has no action; bit PE is set at the first incorrectly received character. Transmitter FIFO Reset control bit. Setting this bit to a logical "1" resets the transmitter FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1". Default is "0". Receiver FIFO Reset control bit. Setting this bit to a logical "1" resets the receiver FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1". Default is "0". - [2] TxFRST [1] [0] RxFRST RESERVED Smart Card Control Register (SCHI_SCCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_SCCR0 SCHI_SCCR1 0xFFF8_500C 0xFFF8_580C R/W R/W Smart Card Control Register 0 Smart Card Control Register 1 0x0000_0018 0x0000_0018 - 448 - W90P710CD/W90P710CDG 31 23 15 7 BDLAB 30 22 14 6 DIR 29 21 13 5 NSBE 28 20 12 4 EPE 27 19 11 3 PROT 26 18 10 2 CDP 25 17 9 1 Reserved 24 16 8 0 Reserved RESERVED RESERVED RESERVED BITS DESCRIPTIONS [31:8] RESERVED Baud rate Divisor Latch Access Bit. When this bit is set to a logical "1", users may access baud rate divisor (in 16-bit binary format) through divisor latches (BLH and BLL) of baudrate generator during a read/write operation. A special Smart Card ID can also be read at base address + 8 when BDLAB is "1". When this bit is set to "0", accesses to base address + 0, 4 or 8 refer to RBR/TBR, IER or ISR/SCFR respectively. DIRect convention When set as a ‘0’ or ‘1’ will receive data in the direct convention or indirect convention manner respectively. In other words, the controller will need to have this bit set to a ‘1’ if the first byte of the ATR process is 3F (i.e. Indirect convention) and a ‘0’ if the first byte is 3B (i.e. Direct convention). Silent Byte Enable. Receiver detect the data byte, parity bit and stop bit are all zero Even Parity Enable. This bit is only available when bit 3 of SCCR is programmed to "1". It prescribes number of logical 1s in a data word including parity bit. When this bit is set to "1", even parity is required for transmission and reception. Odd parity is demanded when this bit is set to "0". In contrast to its UART counterpart, Smart Card Control Register only controls parity bit setting because data length is fixed at 8-bit long for Smart Card interface protocol. Protocol. [7] BDLAB [6] DIR [5] NSBE [4] EPE [3] Protocol Bit PROT is set if the protocol is T = 1 (asynchronous) and bit PROT = 0 if the protocol is T = 0. - 449 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Contiuned BITS DESCRIPTIONS [2] CDP Card Detect Polarity. We can use the CDP bit to choose the card present input polarity for different socket application. 0 : the input high means card is present. 1 : the input low means card is present. - [1:0] RESERVED Smart Card Host Clock Base Register (SCHI_CBR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_CBR0 SCHI_CBR1 31 23 15 7 30 22 14 6 0xFFF8_5010 0xFFF8_5810 29 21 13 5 R/W R/W Clock base Register 0 Clock base Register 1 28 RESERVED 0x0000_000C 0x0000_00OC 26 18 10 2 25 17 9 1 24 16 8 0 27 19 11 3 20 RESERVED 12 RESERVED 4 8-bit clock base Data BITS DESCRIPTIONS [31:8] RESERVED Clock Base value. It specifies number of internal sampling clock pulses for a data bit. Default to be 0Ch. This register combining with BLH and BLL (baud rate latches) determine internal sampling clock frequency. For example, CBR defaults to be 0Ch and BLH, BLL default to be 1Fh which mean SCCLK clock frequency is 372 (12 x 31) times of internal sampling clock frequency. The default values of CBR, BLH and BLL are corresponding to default values of transmission factors F and D specified in ISO/IEC 7816-3. The value of 0Ch of CBR means there're 12 sampling clock pulses to detect a 1-etu (elementary time unit) data bit on SCIO signal. It is recommended that user sets CBR to be around 16 to maintain better data integrity and transmission stability. [7:0] CBR - 450 - W90P710CD/W90P710CDG Smart Card Host Status Register (SCHI_SCSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_SCSR0 SCHI_SCSR1 0xFFF8_5014 0xFFF8_5814 R R Smart card Status Register 0 Smart card Status Register 1 0x0000_0060 0x0000_0060 31 23 15 7 SC_RESET 30 22 14 6 TSRE 29 21 13 RESERVED 28 RESERVED 27 19 11 3 NSER 26 18 10 TOF2 2 PBER 25 17 9 TOF1 1 OER 24 16 8 TOF0 0 RDR 20 RESERVED 12 4 SBD 5 TBRE BITS DESCRIPTIONS [31:11] RESERVED RESERVED TOF2 is Time-Out Flag of Timer2. When Timer 2 time out, it will set the FLAG (TOF2) When host reads SCSR, it clears this bit to "0". TOF1 is Time-Out Flag of Timer1. When Timer 1 time out, it will set the FLAG (TOF1) When host reads SCSR, it clears this bit to "0". TOF0 is Time-Out Flag of Timer0. When Timer 0 time out, it will set the FLAG (TOF0) When host reads SCSR, it clears this bit to "0". SC_RESET pin status This bit reflects the RESET pin high or low. Transmitter Shift Register Empty This bit is set to "1" when transmitter shift register is empty. TOF2, [10:8] TOF1, TOF0 [7] [6] SC_RESET TSRE - 451 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Contiuned BITS DESCRIPTIONS [5] TBRE Transmitter Buffer Register Empty In non-FIFO mode, this bit will be set to a logical 1 when a data byte is transferred from TBR to TSR. If ETBREI of IER is a logical 1, an interrupt is generated to notify host to write the following data bytes. In FIFO mode, this bit is set to "1" when the transmitter FIFO is empty. It is cleared to "0" when host writes data bytes into TBR or FIFO. Silent Byte Detected This bit is set to "1" to indicate that received data byte are kept in silent state for a full byte time, including start bit, data bits, parity bit, and stop bits. In FIFO mode, it indicates the same condition for the data on top of FIFO. When host reads SCSR, it clears this bit to "0". No Stop bit Error This bit is set to "1" to indicate that received data has no stop bit. In FIFO mode, it indicates the same condition for the data on top of FIFO. When host reads SCSR, it clears this bit to "0". Parity Bit Error This bit is set to "1" to indicate that parity bit of received data is wrong. In FIFO mode, it indicates the same condition for the data on top of the FIFO. When host reads SCSR, it clears this bit to "0". Overrun Error This bit is set to "1" to indicate previously received data is overwritten by the next received data before it is read by host. In FIFO mode, it indicates the same condition instead of FIFO full. When host reads SCSR, it clears this bit to "0". Receiver Data Ready This bit is set to "1" to indicate received data is ready to be read by host in RBR or FIFO. If no data are left in RBR or FIFO, the bit is cleared to "0". [4] SBD [3] NSER [2] PBER [1] OER [0] RDR Smart Card Host Guard Time Register (SCHI_GTR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_GTR0 SCHI_GTR1 0xFFF8_5018 0xFFF8_5818 R/W R/W Guard time Register 0 Guard time Register 1 0x0000_0001 0x0000_0001 - 452 - W90P710CD/W90P710CDG 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 GTR[7:0] 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 RESERVED RESERVED RESERVED BITS DESCRIPTIONS [31:8] RESERVED Guard Time Register value. This register specifies number of stop bits appended in the end of data byte. Bit 7 ~ 0: Guard time values. Default to be 01h. [7:0] GTR Smart Card Host Extended Control Register (SCHI_ECR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_ECR0 SCHI_ECR1 31 23 15 0xFFF8_501C 0xFFF8_581C 30 22 14 29 21 13 RESERVED R/W R/W 28 Extended Control Register 0 Extended Control Register 1 27 19 11 26 18 10 PSCKFS2 4 3 CLKSTP 2 CLKSTPL 25 17 9 0x0000_0052 0x0000_0052 24 16 8 PSCKFS 0 0 Reserved RESERVED 20 RESERVED 12 PSCKF S1 1 7 Reserved 6 SCKFS2 5 SCKFS1 SCKFS0 - 453 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:11] RESERVED PSCK Frequency Selection bit 2, 1 and 0. This selection can adjust power-on /power-offf sequence interval. They select working clock frequency as following table. Default values are 05h. [10:8] PSCKFS2, PSCKFS1, PSCKFS0 SCKFS0, SCKFS1, SCKFS2 000 001 010 011 100 101 110 SCCLK frequency 80MHz 40 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz [6:4] SCKFS2, SCKFS1, SCKFS0 SCCLK Frequency Selection bit 2, 1 and 0. They select working clock frequency as following table. Default values are 05h. SCKFS0, SCKFS1, SCCLK SCKFS2 frequency 000 80MHz 001 40 MHz 010 20 MHz 011 10 MHz 100 5 MHz 101 2.5 MHz 110 1.25 MHz Clock Stop voltage Level 0 = SCCLK stops at low if CLKSTP is also set to "0". 1 = SCCLK stops at high if CLKSTP is also set to "1". Clock Stop control bit Setting "1" to this bit stops SCCLK at a voltage level specified by CLKSTPL (bit 3 of ECR). - [3] CLKSTPL [2] [1:0] CLKSTP RESERVED - 454 - W90P710CD/W90P710CDG Smart Card Host Test Mode Register (SCHI_TMR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TMR0 SCHI_TMR1 0xFFF8_5020 0XFFF8_5820 R/W R/W Test mode Register 0 Test mode Register 1 0x0000_0000 0x0000_0000 This 8 bit register is added in order to allow better testability of the Smart Card host. Currently only bit 1 is utilized. In the future, other bits can be used to program the host to improve testability on the testing platform. 31 23 15 7 30 22 14 6 29 21 13 5 RESERVED 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 SCRST_L 24 16 8 0 POWER_SEQ _SKIP 20 RESERVED 12 RESERVED 4 - 455 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:2] RESERVED Smart card Reset pin control bit Software driver controls this bit directly which in turn determines the SCRST_L signal to the Smart Card. ‘0’ or ‘1’ in this bit drives ‘0’ or ‘1’ respectively on the SCRST_L signal. This feature was first added to allow the SCRST_L to be pulled high at a quicker rate during the reset phase to improve testability. However, upon the attempt to further improve the capability of the Smart Card host, it was found that this bit holds the key in solving one of the major problems of this design. Originally, the SCRST_L signal is pulled high automatically after a fixed period of time (via the use of a hardware counter) when the card is inserted. However, there have been many cases where this signal is pulled high even before power is supplied to the card, which is a clear violation to the ISO 7816 specification. This as a result causes non valid ATR to be read by the host during the initial insertion of the card. Earlier versions of this IP rectified this problem by having the software ignore the invalid ATR during the initial insertion and do either a warm or cold setup to capture the true ATR on its second try. This bit allows a lot of flexibility to fix the problem mentioned above. Software driver now has the ability to determine when the SCRST_L is to be pulled either high or low, avoiding this problem which has plagued earlier versions. With this modification, software ensures that the SCRST_L signal is pulled high only after the power is supplied to the card, thus allowing the true ATR to be always read during the initial insertion of the card. When the bit is low, it is normal case When the bit is high, it will skip the power_on/off_seq so it can speed up the S/W simulation [1] SCRST_L [0] POWER_SE Q_SKIP Smart Card Host Time-out configuration Register (SCHI_TOC) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOC0 SCHI_TOC1 0xFFF8_5028 0xFFF8_5828 R/W R/W Time out Configuration Register 0 Time out Configuration Register 1 0x0000_0000 0x0000_0000 - 456 - W90P710CD/W90P710CDG 31 23 15 7 30 22 14 RESERVED 29 21 13 5 TOC4 28 RESERVED 27 19 11 nDBGACK_EN2 3 26 18 10 TOC8 2 TOC2 25 17 9 TOC7 1 TOC1 24 16 8 TOC6 0 TOC0 20 RESERVED 12 4 6 nDBGACK_EN1 TOC5 TOC3 nDBGACK_EN0 BITS DESCRIPTIONS [31:12] RESERVED ICE Debug mode Acknowledge enable for time-out counter 2 [11] nDBGACK_EN2 0 = When DBGACK is high, the timer clock will be held 1 = No matter what DBGACK is high or not, the timer clock will not be held. - 457 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS TOC8, TOC7, TOC6 (Time Out Configuration) control 24 bit timeout counter 2 configuration. TOC8, TOC7, TOC6 value 000 001 OPERATION MODE 010 TOC8, [10:8] TOC7, TOC6 011 100 24 bit counter 2 is stopped Counting the value stored in register TOIR 2 is started after 001b is written in register in register TOC. An interrupt is given if enabled, and bit TO2 is set within register SCSR when the terminal count is reached. The counter is stopped by writing 000b in register TOC, and should be stopped before reloading new values in register TOC. Counter 2 starts counting the content of register TOIR2 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 2 reaches its terminal count, an interrupt is given if enable. Bit TO2 in register SCSR is set. The counter is reloaded with TOIR2 and starts counting on each subsequent START bit. It is possible to change the content of TOIR2 during a count; the current count will not be affected and the new count value will be taken into account at the next START bit. The count is stopped by writing 000b in register TOC, Counter 2 starts counting the content of register TOIR2 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 2 reaches its terminal count, an interrupt is given if enable. Bit TO2 in register SCSR is set. The count is stopped by writing 000b in register TOC, Same as value 000b, except that counter 2 will be stopped at the end of the 12th ETU following the first START bit detected after 100b has been written in register TOC ICE Debug mode Acknowledge enable for time-out counter 1 0 = When DBGACK is high, the timer clock will be held [7] nDBGACK_EN1 1= No matter what DBGACK is high or not, the timer clock will not be held - 458 - W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS TOC5, TOC4, TOC3 (Time Out Configuration) control 16 bit timeout counter 1 configuration. TOC5, TOC4, TOC3 value 000 001 OPERATION MODE TOC5, [6:4] TOC4, TOC3 010 011 100 16 bit counter 1 is stopped Counting the value stored in register TOIR 1 is started after 001b is written in register in register TOC. An interrupt is given if enabled, and bit TO1 is set within register SCSR when the terminal count is reached. The counter is stopped by writing 000b in register TOC, and should be stopped before reloading new values in register TOC. Counter 1 starts counting the content of register TOIR1 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 1 reaches its terminal count, an interrupt is given if enable. Bit TO1 in register SCSR is set. The counter is reloaded with TOIR1 and starts counting on each subsequent START bit. It is possible to change the content of TOIR1 during a count; the current count will not be affected and the new count value will be taken into account at the next START bit. The count is stopped by writing 000b in register TOC, Counter 1 starts counting the content of register TOIR1 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 1 reaches its terminal count, an interrupt is given if enable. Bit TO1 in register SCSR is set. The count is stopped by writing 000b in register TOC, Same as value 000b, except that counter 1 will be stopped at the end of the 12th ETU following the first START bit detected after 100b has been written in register TOC ICE Debug mode Acknowledge enable for time-out counter 0 [3] nDBGACK_EN0 0 = When DBGACK is high, the timer clock will be held 1 = No matter what DBGACK is high or not, the timer clock will not be held - 459 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS TOC5, TOC4, TOC3 (Time Out Configuration) control 8 bit time-out counter 0 configuration. TOC2, TOC1, TOC0 value 000 001 OPERATION MODE TOC2, [2:0] TOC1, TOC0 010 011 100 8 bit counter 0 is stopped Counting the value stored in register TOIR 0 is started after 001b is written in register in register TOC. An interrupt is given if enabled, and bit TO0 is set within register SCSR when the terminal count is reached. The counter is stopped by writing 000b in register TOC, and should be stopped before reloading new values in register TOC. Counter 0 starts counting the content of register TOIR0 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 0 reaches its terminal count, an interrupt is given if enable. Bit TO0 in register SCSR is set. The counter is reloaded with TOIR0 and starts counting on each subsequent START bit. It is possible to change the content of TOIR0 during a count; the current count will not be affected and the new count value will be taken into account at the next START bit. The count is stopped by writing 000b in register TOC, Counter 0 starts counting the content of register TOIR0 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 0 reaches its terminal count, an interrupt is given if enable. Bit TO0 in register SCSR is set. The count is stopped by writing 000b in register TOC, Same as value 000b, except that counter 0 will be stopped at the end of the 12th ETU following the first START bit detected after 100b has been written in register TOC - 460 - W90P710CD/W90P710CDG Smart Card Host Time-out Initial Register 0 (SCHI_TOIR 0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOIR0_0 SCHI_TOIR0_1 0xFFF8_502C 0xFFF8_582C R/W R/W 8 bit Time out initial Register 0 8 bit Time out initial Register 1 0x0000_0000 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 RESERVED 4 TOIR0[7:0] BITS DESCRIPTIONS [31:8] RESERVED 8 bit Time Out Initial Register 0 The value to load in register TOIR 0 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 8 bit time-out initial register used to initial loading value when every start counting. [7:0] TOIR0 Smart Card Host Time-out Initial Register 1 (SCHI_TOIR 1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOIR1_0 SCHI_TOIR1_1 0xFFF8_5030 0xFFF8_5830 R/W R/W 16 bit Time out initial Register 0 16 bit Time out initial Register 1 0x0000_0000 0x0000_0000 - 461 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 TOIR1[15:8] 4 TOIR1[7:0] BITS DESCRIPTIONS [31:16] RESERVED 16 bit Time Out Initial Register 1 The value to load in register TOIR 1 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 16 bit time-out initial register used to initial loading value when every start counting. [15:0] TOIR1 Smart Card Host Time-out Initial Register 2 (SCHI_TOIR 2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOIR2_0 SCHI_TOIR2_1 31 23 15 7 0xFFF8_5034 0xFFF8_5834 30 22 14 6 29 21 13 5 R/W R/W 24 bit Time out initial Register 0 24 bit Time out initial Register 1 28 RESERVED 0x0000_0000 0x0000_0000 25 17 9 1 24 16 8 0 27 19 11 3 26 18 10 2 20 TOIR2[23:16] 12 TOIR2[15:8] 4 TOIR2[7:0] BITS DESCRIPTIONS [31:24] RESERVED 24 bit Time Out Initial Register 2 The value to load in register TOIR 2 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 24 bit time-out initial register used to initial loading value when every start counting. [23:0] TOIR2 - 462 - W90P710CD/W90P710CDG Smart Card Host Time-Out Data Register 0 (SCHI_TODR0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOD0_0 SCHI_TOD0_1 31 23 15 7 0xFFF8_5038 0xFFF8_5838 30 22 14 6 R R 29 21 13 5 8 bit Time out data Register 0 8 bit Time out data Register 1 28 RESERVED 0x0000_00FF 0x0000_00FF 25 17 9 1 24 16 8 0 27 19 11 3 26 18 10 2 20 RESERVED 12 RESERVED 4 TOD0[7:0] BITS DESCRIPTIONS [31:8] RESERVED 8 bit Time Out Data count Register 0 The value showing in register TOD 0 is the number of ETU to count. The time-out data counters may only be used when a card is active with a running clock. This is 8 bit time-out data register used to show the current counting value. [7:0] TOD0 Smart Card Host Time-Out Data Register 1 (SCHI_TODR1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOD1_0 SCHI_TOD1_1 31 23 15 7 0xFFF8_503C 0xFFF8_583C 30 22 14 6 29 21 13 5 R R 16 bit Time out Data Register 0 16 bit Time out Data Register 1 28 RESERVED 0x0000_00FF 0x0000_00FF 25 17 9 1 24 16 8 0 27 19 11 3 26 18 10 2 20 RESERVED 12 TOD1[15:8] 4 TDO1[7:0] - 463 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:16] RESERVED 16 bit Time Out Data count Register 1 The value showing in register TOD 1 is the number of ETU to count. The time-out data counters may only be used when a card is active with a running clock. This is 16 bit time-out data register used to show the current counting value. [15:0] TOD1 Smart Card Host Time-Out Data Register 2 (SCHI_TODR2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_TOD2_0 SCHI_TOD2_1 0xFFF8_5040 0xFFF8_5840 R R 24 bit Time out Data Register 0 24 bit Time out Data Register 1 0x0000_00FF 0x0000_00FF 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 TOD2[23:16] 12 TOD2[15:8] 4 TDO2[7:0] BITS DESCRIPTIONS [31:24] RESERVED 24 bit Time Out Data count Register 2 The value to load in register TOD 2 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 24 bit time-out data register used to show the current counting value. [23:0] TOR2 - 464 - W90P710CD/W90P710CDG Smart Card Host Buffer Time-Out Data Register (SCHI_BTOR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_BTOR0 SCHI_BTOR1 31 23 15 7 BTOIE 0XFFF8_5044 0XFFF8_5844 30 22 14 6 BTOIC_6 29 21 13 R/W R/W Buffer Time out Data Register 0 Buffer Time out Data Register 1 28 RESERVED 0x0000_0000 0x0000_0000 25 17 9 24 16 8 27 19 11 3 BTOIC_3 26 18 10 2 BTOIC_2 20 RESERVED 12 RESERVED 5 BTOIC_5 4 BTOIC_4 1 0 BTOIC_1 BTOIC_0 BITS DESCRIPTIONS [31:8] RESERVED Buffer Time Out Interrupt Enable The feature of receiver buffer time out interrupt is enabled only when BTOIE[7] = ERDRI =1 . Buffer Time Out Interrupt Comparator The time out counter resets and starts counting (the counting clock = ETU) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if TOR[7] = ERDRI =1. A new incoming data word or BRX FIFO empty clear Irpt_TOUT. [7] BTOIE [6:0] BTOIC Smart Card Host Baud Rate Divider Latch Lower Byte (SCHI_BLL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_BLL0 SCHI_BLL1 0XFFF8_5000 (DLAB = 1) 0XFFF8_5800 (DLAB = 1) R/W Baud rate divisor Latch Lower byte Register 0 0x0000_001F R/W Baud rate divisor Latch Lower byte Register 1 0x0000_001F - 465 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 31 23 15 7 BITS 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 RESERVED 4 BLL[7:0] DESCRIPTIONS [31:8] RESERVED 8 bit Baud rate divider Latch Low byte register This register combining with BLH and CBR determine internal sampling clock frequency. Bit 7 ~ 0: Baud rate divisor latch lower byte values. Default to be 1Fh. [7:0] BLL Baud Rate Divider Latch Higher Byte (SCHI_BLH) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_BLH0 SCHI_BLH1 0XFFF8_5004 (DLAB = 1) 0XFFF8_5804 (DLAB = 1) 30 22 14 6 R/W Baud rate divisor Latch Higher byte Register 0 0x0000_0000 R/W Baud rate divisor Latch Higher byte Register 1 0x0000_0000 31 23 15 7 29 21 13 5 28 RESERVED 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 RESERVED 4 BLH[7:0] - 466 - W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:8] RESERVED 8 bit Baud rate divider Latch High byte register This register combining with BLL and CBR determine internal sampling clock frequency. Bit 7 ~ 0: Baud rate divisor latch higher byte values. Default to be 00h. SMART CARD ID NUMBER (SCHI_ID) [7:0] BLH Register SCHI_ID0 SCHI_ID1 Address 0xFFF8_5008 (DLAB = 1) 0XFFF8_5808 (DLAB = 1) R/W Description Reset Value 0x0000_0070 0x0000_0070 R Smart card ID number Register 0 R Smart card ID number Register 1 31 23 15 7 30 22 14 6 29 21 13 5 28 RESERVED 27 19 11 3 ID[7:0] 26 18 10 2 25 17 9 1 24 16 8 0 20 RESERVED 12 RESERVED 4 BITS DESCRIPTIONS [31:8] [7:0] RESERVED ID 8 bit smart card ID number register This register contains a specific value of 70h for driver to identify Smart Card interface. - 467 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 6.17.3 Functional description The following description uses abbreviations to refer to control/status registers and their contents of Smart Card interface as seen in section 7.12.2 Initialization User needs to program control registers so that ATR (Answer To Reset) data streams can be properly decoded after card insertion. Initialization settings include the following steps where sequential order is irrelevant. 1. BLH, BLL and CBR are written with 00h, 1Fh and 0Ch respectively to comply with default transmission factors Fd and Dd which are 372 and 1 as specified in ISO/IEC 7816-3. 2. GTR is programmed with 01h for one stop bit. 3. Set SCFR bit 1 to "1" to reset receiver FIFO. 4. Set EPE bit in SCCR bit 4 to be “1” for EVEN parity, set EPE bit to be “0” for odd parity. 5. Set SCKFS1 and SCKFS0 to "05" to select 2.5 MHz for SCCLK on 80MHz system clock. Most default values of above control bits are designed as specified in initialization step but it is recommended that user performs all the initialization sequence to avoid any ambiguity. The relationship between transmission factors and settings of BLH, BLL and CBR is best described in the following example. F1 (f means SCCLK frequency) 1etu = × Df Therefore, Fd 372 = = (BLH, BLL) × CBR = 31 × 12 Dd 1 Activation Card insertion pulls up SCPSNT (assuming SCPSNT in ISR bit 5 is active high) and in consequence SCPWR# is pulled down to activate power MOS to supply power to card slot after a delay of about 5 ms. This delay is for card slot mechanism to settle down before power is actually applied. SCCLK starts to output clocks right after SCPWR# is active while SCIO is in reception mode and pulled up externally. SCRST# keeps low initially to reset card but will output high after 512 clock cycles to meet requirement of tb of more than 400 clock cycles (specified in ISO/IEC 7816-3). To meet another timing requirement, tc of ISO/IEC 7816-3, a counter based on SCCLK is implemented to start counting on the rising edge of SCRST#. SCPWR# is deactivated if no ATR (Answer To Reset) is detected after 65536 clock cycles from the rising edge of SCRST#. Answer-to-Reset Answer-to-Reset (ATR) is the data streams sent by the card to the interface as an answer to a reset on SCRST# signal. Refer to ISO/IEC 7816-3 for detailed description of ATR. There're two kinds of cards specified in ISO/IEC 7816-3, inverse convention card and direct convention card. Although these two conventions treat logical meanings (0 or 1) of voltage levels (low or high) differently, Winbond's implementation of Smart Card interface decodes a high voltage level data bit as "1" and low voltage level data bit "0" nevertheless and resorts to software to interpret incoming data. Software driver needs to interpret initial character of ATR first to determine which - 468 - W90P710CD/W90P710CDG convention is for inserted card and chooses a conversion procedure for it. Subsequent incoming data bytes must be passed through a conversion procedure before actually transfers these data bytes to host. Similar conversion procedure must be applied to outgoing data byte before writing to TBR too. For example, the raw data byte for initial character of inverse-convention ATR would be 3Fh. Software driver therefore needs a conversion procedure to reverse bit-significance and polarity to process subsequent raw data bytes. On the other hand, initial character of direct-convention ATR is 3Bh which needs no conversion procedure to process data byte. Data transfer Software driver might need to configure control registers again based on information contained in ATR before process subsequent data transfer. The following guidelines are provided for programming reference. 1. EPE should be set to "1" for direct-convention card and otherwise for inverse-convention card. 2. BLH, BLL and CBR should be set to comply with Fi and Di. 3. GTR is used for various stop bit requirement of different transmission protocols. 4. Use interrupt resources to control communication sequence. 5. Monitor SCSR for transmission integrity. Cold reset and warm reset Cold reset is achieved by writing a "1" to PWRDN (bit 7 of IER). It deactivates SCPWR# to high. Consequentially, SCRST# is pulled down and SCCLK is stopped. User must write a "0" to PWRDN (bit 7 of IER) to resume Smart Card interface to a normal activation state assuming card is still present. The activation sequence and deactivation sequence are done by internal F.S.M When in a normal activation state, writing a "0" SCRST_L (bit 1 of TMR) will force SC_RST pin to low that will triggers a warm reset. Its effect is similar to cold reset except SCPWR# is kept activated and therefore power supply to card stays on. Power states SCHI employs a sophisticated algorithm to partition Smart Card interface's internal circuits to achieve optimal power utilization. However, users must pay extra care in the design of application circuits following guidelines stated below to prevent potential signal conflict and unnecessary power consumption. There're three power states: disabled state, active state, and power down state. Disabled state is the default state when power is first applied to the IC. SCPWD (Smart Card Power Down) controls whether in active state (SCPWD = 0) or in power down state (SCPWD = 1). Disabled state Smart Card interface is in disabled state initially. Clock is stopped in this state and therefore it is the least power-consuming state. To prevent current leakage from floating connections, it is designed to output a predetermined voltage level on all the I/O pins of Smart Card interface as follows: SCPWR# outputs high to disable power supply to socket; SCRST#, SCCLK, and SCIO output low; SCPSNT is tri-stated. Publication Release Date: September 19, 2006 Revision B2 - 469 - W90P710CD/W90P710CDG These I/O conditions also apply to socket in power down state (SCPWD = 1) or deselected socket in idle state. Designers of application circuits must take extra care so that no contention occurs when Smart Card interface is in those power-saving states. Active state Active state is when Smart Card interface is actually performing all its functions: configuration of control and interrupt registers, detection of card insertion/extraction, reception of ATR (Answer To Reset) packet and communication of information between host and card. Refer to section 7.12.3 for detailed function description. This is the most power-consuming state and actual power consumption is dependent on traffic of interface. Power down state Transition from active state to power down state is accomplished by setting SCPWD to "1". Clock is stopped for most internal core circuits except detection circuit for SCPSNT toggle (card insertion/extraction). SCPSNT toggle can interrupt CPU and through this feature Smart Card interface in power down state can be waken up by card insertion/extraction. User may also directly write a "0" to SCPWD to wake up Smart Card interface. Smart Card interface spends a little bit more power to maintain SCPSNT toggle detection circuit in power down state than in disabled state while spares even more power than in active state by stopping clock to core circuit. Users must make sure that all on-going transactions are concluded before putting Smart Card interface into power down state to prevent potential disoperation of internal state machine. - 470 - W90P710CD/W90P710CDG 6.18 I2C Interface I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up to 100 kbit/s in Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. Only 100kbps and 400kbps modes are supported directly. For High-speed mode special IOs are needed. If these IOs are available and used, then High-speed mode is also supported. Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byteby-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). The I2C Master Core includes the following features: • AMBA APB interface compatible • Compatible with Philips I2C standard, support master mode • Multi Master Operation • Clock stretching and wait state generation • Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer • Software programmable acknowledge bit • Arbitration lost interrupt, with automatic transfer cancellation • Start/Stop/Repeated Start/Acknowledge generation • Start/Stop/Repeated Start detection • Bus busy detection • Supports 7 bit addressing mode • Fully static synchronous design with one clock domain • Software mode I2C - 471 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 6.18.1 I2C Protocol Normally, a standard communication consists of four parts: 1) START or Repeated START signal generation 2) Slave address transfer 3) Data transfer 4) STOP signal generation SCL SDA S or Sr 1 2 7 8 9 1 2 3-7 8 9 P A6 A5 A4 - A1 A0 R/W ACK D7 D6 D5 - D1 D0 NACK ACK MSB LSB MSB LSB P or Sr Sr Fig. 6.18.1.1 Data transfer on the I2C-bus S SLAVE ADDRESS R/W A DATA A DATA A/A P '0'(write) from master to slave from slave to master data transfer (n bytes + acknowledge) A = acknowledge (SDA low) A = not acknowledge (SDA high) S = START condition P = STOP condition A master-transmitter addressing a slave receiver with a 7-bit address The transfer direction is not changed S SLAVE ADDRESS R/W A DATA A DATA A P '1'(read) data transfer (n bytes + acknowledge) A master reads a slave immediately after the first byte (address) - 472 - W90P710CD/W90P710CDG START or Repeated START signal When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred to as the S-bit, is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The START signal denotes the beginning of a new data transfer. A Repeated START (Sr) is a START signal without first generating a STOP signal. The master uses this method to communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to reading from a device) without releasing the bus. The I2C core generates a START signal when the START bit in the Command Register (CMDR) is set and the READ or WRITE bits are also set. Depending on the current status of the SCL line, a START or Repeated START is generated. STOP signal The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred to as the P-bit, is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH. SCL SDA START condition STOP condition START and STOP conditions Slave Address Transfer The first byte of data transferred by the master immediately after the START signal is the slave address. This is a 7-bits calling address followed by a RW bit. The RW bit signals the slave the data transfer direction. No two slaves in the system can have the same address. Only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the SDA low at the 9th SCL clock cycle. The core treats a Slave Address Transfer as any other write action. Store the slave device’s address in the Transmit Register (TxR) and set the WRITE bit. The core will then transfer the slave address on the bus. MSB A6 A5 A4 A3 A2 A1 A0 LSB R/W slave address The first byte after the START procedure - 473 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Data Transfer Once successful slave addressing has been achieved, the data transfer can proceed on a byte-bybyte basis in the direction specified by the RW bit sent by the master. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a Not Acknowledge (NACK), the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle. If the master, as the receiving device, does Not Acknowledge (NACK) the slave, the slave releases the SDA line for the master to generate a STOP or Repeated START signal. To write data to a slave, store the data to be transmitted in the Transmit Register (TxR) and set the WRITE bit. To read data from a slave, set the READ bit. During a transfer the core set the I2C_TIP flag, indicating that a Transfer is In Progress. When the transfer is done the I2C_TIP flag is cleared, the IF flag set if enabled, then an interrupt generated. The Receive Register (RxR) contains valid data after the IF flag has been set. The software may issue a new write or read command when the I2C_TIP flag is cleared. SCL SDA data line stable; data valid change of data allowed Bit transfer on the I2C-bus clock pulse for acknowledgement SCL FROM MASTER 1 2 8 9 DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER S START condition acknowledge Acknowledge on the I2C-bus - 474 - W90P710CD/W90P710CDG 6.18.2 I2C Serial Interface Control Registers Map R: read only, W: write only, R/W: both read and write NOTE1: The reset value of I2C_WR0/1 is 0x3F only when SCR, SDR and SER are connected to pull high resistor. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C Interface 0 I2C_CSR0 I2C_CMDR0 I2C_SWR0 I2C_RxR0 I2C_TxR0 I2C_CSR1 I2C_CMDR1 I2C_SWR1 I2C_RxR1 I2C_TxR1 0xFFF8_6000 0xFFF8_6008 0xFFF8_600C 0xFFF8_6010 0xFFF8_6014 0xFFF8_6100 0xFFF8_6108 0xFFF8_610C 0xFFF8_6110 0xFFF8_6114 R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W I2C0 Control and Status Register I2C0 Clock Prescale Register I2C0 Command Register I2C0 Software Mode Control Register I2C0 Data Receive Register I2C0 Data Transmit Register I2C Interface 1 I2C1 Control and Status Register I2C1 Clock Prescale Register I2C1 Command Register I2C1 Software Mode Control Register I2C1 Data Receive Register I2C1 Data Transmit Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_003F 0x0000_0000 0x0000_0000 I2C_DIVIDER1 0xFFF8_6104 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_003F 0x0000_0000 0x0000_0000 I2C_DIVIDER0 0xFFF8_6004 I2C Control and Status Register 0/1 (I2C_CSR0/1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C_CSR0 I2C_CSR1 31 23 15 7 0xFFF8_6000 R/W I2C Control and Status Register 0 0xFFF8_6100 R/W I2C Control and Status Register 1 30 22 14 Reserved 6 5 Tx_NUM 4 29 21 13 28 20 12 27 Reserved 19 Reserved 11 3 Reserved 10 2 IF 9 18 17 26 25 0x0000_0000 0x0000_0000 24 16 8 I2C_TIP 0 I2C_EN I2C_RxACK I2C_BUSY I2C_AL 1 IE Reserved - 475 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:12] [11] Reserved I2C_RxACK Reserved Received Acknowledge From Slave (Read only) This flag represents acknowledge from the addressed slave. 0 = Acknowledge received (ACK). 1 = Not acknowledge received (NACK). I2C Bus Busy (Read only) 0 = After STOP signal detected. 1 = After START signal detected. Arbitration Lost (Read only) This bit is set when the I2C core lost arbitration. Arbitration is lost when: A STOP signal is detected, but no requested. The master drives SDA high, but SDA is low. Transfer In Progress (Read only) 0 = Transfer complete. 1 = Transferring data. NOTE: When a transfer is in progress, you will not allow writing to any register of the I2C master core except SWR. Transmit Byte Counts These two bits represent how many bytes are remained to transmit. When a byte has been transmitted, the Tx_NUM will decrease 1 until all bytes are transmitted (Tx_NUM = 0x0) or NACK received from slave. Then the interrupt signal will assert if IE was set. 0x0 = Only one byte is left for transmission. 0x1 = Two bytes are left to for transmission. 0x2 = Three bytes are left for transmission. 0x3 = Four bytes are left for transmission. Reserved Interrupt Flag The Interrupt Flag is set when: Transfer has been completed. Transfer has not been completed, but slave responded NACK (in multibyte transmit mode). Arbitration is lost. NOTE: This bit is read only, but can be cleared by writing 1 to this bit. Interrupt Enable 0 = Disable I2C Interrupt. 1 = Enable I2C Interrupt. I2C Core Enable 0 = Disable I2C core, serial bus outputs are controlled by SDW/SCW. 1 = Enable I2C core, serial bus outputs are controlled by I2C core. [10] I2C_BUSY [9] I2C_AL [8] I2C_TIP [5:4] Tx_NUM [3] Reserved [2] IF [1] IE [0] I2C_EN - 476 - W90P710CD/W90P710CDG I2C Prescale Register 0/1 (I2C_DIVIDER 0 /1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C_DIVIDER0 I2C_DIVIDER1 0xFFF8_6004 0xFFF8_6104 R/W R/W I2C Clock Prescale Register 0 I2C Clock Prescale Register 1 0x0000_0000 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 DIVIDER[15:8] DIVIDER[7:0] BITS DESCRIPTIONS Clock Prescale Register It is used to prescale the SCL clock line. Due to the structure of the I2C interface, the core uses a 5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus 1). Change the value of the prescale register only when the “I2C_EN” bit is cleared. Example: pclk = 32MHz, desired SCL = 100KHz [15:0] DIVIDER prescale = 32 MHz − 1 = 63 ( dec ) = 3 F ( hex ) 5 ∗ 100 KHz I2C Command Register 0/1 (I2C_CMDR 0/1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C_CMDR0 0xFFF8_6008 R/W I2C Command Register 0 I2C_CMDR1 0xFFF8_6108 R/W I2C Command Register 1 0x0000_0000 0x0000_0000 - 477 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 31 23 15 7 30 22 14 6 Reserved 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 START 27 19 11 3 STOP 26 18 10 2 READ 25 17 9 1 WRITE 24 16 8 0 ACK NOTE: Software can write this register only when I2C_EN = 1. BITS DESCRIPTIONS [31:5] [4] [3] [2] [1] Reserved START STOP READ WRITE Reserved Generate Start Condition Generate (repeated) start condition on I2C bus. Generate Stop Condition Generate stop condition on I2C bus. Read Data From Slave Retrieve data from slave. Write Data To Slave Transmit data to slave. Send Acknowledge To Slave When I2C behaves as a receiver, sent ACK (ACK = ‘0’) or NACK (ACK = ‘1’) to slave. [0] ACK NOTE: The START, STOP, READ and WRITE bits are cleared automatically while transfer finished. READ and WRITE cannot be set concurrently. I2C Software Mode Register 0/1(I2C_SWR 0/1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C_SWR0 I2C_SWR1 0xFFF8_600C 0xFFF8_610C R/W I2C Software Mode Control Register 0 R/W I2C Software Mode Control Register 1 0x0000_003F 0x0000_003F - 478 - W90P710CD/W90P710CDG 31 23 15 7 Reserved 30 22 14 6 29 21 13 5 Reserved 28 Reserved 20 Reserved 12 Reserved 4 SDR 27 19 11 3 SCR 26 18 10 2 Reserved 25 17 9 1 SDW 24 16 8 0 SCW Note: This register is used as software mode of I2C. Software can read/write this register no matter I2C_EN is 0 or 1. But SCL and SDA are controlled by software only when I2C_EN = 0. BITS DESCRIPTIONS [31:6] [5] [4] Reserved Reserved SDR Reserved Reserved Serial Interface SDA Status (Read only) 0 = SDA is Low . 1 = SDA is High. Serial Interface SCK Status (Read only) 0 = SCL is Low . 1 = SCL is High. Reserved Serial Interface SDA Output Control 0 = SDA pin is driven Low . 1 = SDA pin is tri-state. Serial Interface SCK Output Control 0 = SCL pin is driven Low . 1 = SCL pin is tri-state. [3] [2] [1] SCR Reserved SDW [0] SCW I2C Data Receive Register 0/1 (I2C_RxR 0/1) REGISTER OFFSET R/W DESCRIPTION RESET VALUE I2C_RXR0 I2C_RXR1 0xFFF8_6010 0xFFF8_6110 R R I2C Data Receive Register 0 I2C Data Receive Register 1 0x0000_0000 0x0000_0000 - 479 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 Reserved 4 Rx [7:0] 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS [31:8] [7:0] Reserved Rx Reserved Data Receive Register The last byte received via I2C bus will put on this register. The I2C core only used 8-bit receive buffer. I2C Data Transmit Register 0/1 (I2C_TxR 0/1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C_TXR0 I2C_TXR1 31 23 15 7 0xFFF8_6014 R/W I2C Data Transmit Register 0xFFF8_6114 R/W I2C Data Transmit Register 30 22 14 6 29 21 13 5 28 Tx [31:24] 20 Tx [23:16] 12 Tx [15:8] 4 Tx [7:0] 3 2 1 11 10 9 19 18 17 27 26 25 0x0000_0000 0x0000_0000 24 16 8 0 - 481 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG BITS DESCRIPTIONS Data Transmit Register The I2C core used 32-bit transmit buffer and provide multi-byte transmit function. Set CSR[Tx_NUM] to a value that you want to transmit. I2C core will always issue a transfer from the highest byte first. For example, if CSR[Tx_NUM] = 0x3, Tx[31:24] will be transmitted first, then Tx[23:16], and so on. [31:0] Tx In case of a data transfer, all bits will be treated as data. In case of a slave address transfer, the first 7 bits will be treated as 7bit address and the LSB represent the R/W bit. In this case, LSB = 1, reading from slave LSB = 0, writing to slave - 482 - W90P710CD/W90P710CDG 6.19 Universal Serial Interface The USI is a synchronous serial interface performs a serial-to-parallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from CPU. This interface can drive one external peripherals and is seen as the master. It can generate an interrupt signal when data transfer is finished and can be cleared by writing 1 to the interrupt flag. The active level of device/slave select signal can be chosen to low active or high active, which depends on the peripheral it’s connected. Writing a divisor into DIVIDER register can program the frequency of serial clock output. This master core contains four 32-bit transmit/receive buffers, and can provide burst mode operation. The maximum bits can be transmitted/received is 32 bits, and can transmit/receive data up to four times successive. The USI (Microwire/SPI) Master Core includes the following features: • AMBA APB interface compatible • Support USI (Microwire/SPI) master mode • Full duplex synchronous serial data transfer • Variable length of transfer word up to 32 bits • Provide burst mode operation, transmit/receive can be executed up to four times in one transfer • MSB or LSB first data transfer • Rx and Tx on both rising or falling edge of serial clock independently • 1 slave/device select lines • Fully static synchronous design with one clock domain 6.19.1 USI Timing Diagram The timing diagram of USI is shown as following. mw_ss_o mw_sclk_o MSB (Tx[7]) MSB (Rx[7]) LSB (Tx[0]) LSB (Rx[0]) mw_so_o Tx[6] Tx[5] Tx[4] Tx[3] Tx[2] Tx[1] mw_si_i Rx[6] Rx[5] Rx[4] Rx[3] Rx[2] Rx[1] CNTRL[LSB]=0, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08, CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0, SSR[SS_LVL]=0 Fig. 6.19.1.1 USI Timing Publication Release Date: September 19, 2006 Revision B2 - 483 - W90P710CD/W90P710CDG mw_ss_o mw_sclk_o LSB (Tx[0]) LSB (Rx[0]) MSB (Tx[7]) MSB (Rx[7]) mw_so_o Tx[1] Tx[2] Tx[3] Tx[4] Tx[5] Tx[6] mw_si_i Rx[1] Rx[2] Rx[3] Rx[4] Rx[5] Rx[6] CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1, SSR[SS_LVL]=0 Fig. 6.19.1.2 Alternate Phase SCLK Clock Timing 6.19.2 USI Registers Map R: read only, W: write only, R/W: both read and write REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_CNTRL USI_DIVIDER USI_SSR Reserved USI_Rx0 USI_Rx1 USI_Rx2 USI_Rx3 USI_Tx0 USI_Tx1 USI_Tx2 USI_Tx3 0xFFF8_6200 0xFFF8_6204 0xFFF8_6208 0xFFF8_620C 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C R/W R/W R/W N/A R R R R W W W W Control and Status Register Clock Divider Register Slave Select Register Reserved Data Receive Register 0 Data Receive Register 1 Data Receive Register 2 Data Receive Register 3 Data Transmit Register 0 Data Transmit Register 1 Data Transmit Register 2 Data Transmit Register 3 0x0000_0004 0x0000_0000 0x0000_0000 N/A 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 NOTE 1: When software programs CNTRL, the GO_BUSY bit should be written last. - 484 - W90P710CD/W90P710CDG USI_Control and Status Register (USI_CNTRL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_CNTRL 0xFFF8_6200 R/W USI Control and Status Register 31 23 15 7 30 22 14 SLEEP 6 5 Tx_BIT_LEN 4 29 21 13 28 Reserved 20 Reserved 12 11 Reserved 3 10 LSB 2 Tx_NEG 1 19 18 17 IE 9 27 26 25 0x0000_0004 24 16 IF 8 Tx_NUM 0 GO_BUSY Rx_NEG BITS DESCRIPTIONS [31:18] [17] Reserved IE Reserved Interrupt Enable 0 = Disable USI Interrupt. 1 = Enable USI Interrupt. Interrupt Flag 0 = It indicates that the transfer dose not finish yet. 1 = It indicates that the transfer is done. The interrupt flag is set if it was enable. NOTE: This bit is read only, but can be cleared by writing 1 to this bit. Suspend Interval These four bits provide the configuration of suspend interval between two successive transmit/receive in a transfer. The default value is 0x0. When CNTRL [Tx_NUM] = 00, setting this field has no effect on transfer. The desired interval is obtained according to the following equation (from the last falling edge of current sclk to the first rising edge of next sclk): (CNTRL[SLEEP] + 2)*period of SCLK SLEEP = 0x0 … 2 SCLK clock cycle SLEEP = 0x1 … 3 SCLK clock cycle …… SLEEP = 0xe … 16 SCLK clock cycle SLEEP = 0xf … 17 SCLK clock cycle [16] IF [15:12] SLEEP - 485 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS [11] Reserved Reserved Send LSB First 0 = The MSB is transmitted/received first (which bit in TxX/RxX register that is depends on the Tx_BIT_LEN field in the CNTRL register). 1 = The LSB is sent first on the line (bit TxX[0]), and the first bit received from the line will be put in the LSB position in the Rx register (bit RxX[0]). Transmit/Receive Numbers This field specifies how many transmit/receive numbers should be executed in one transfer. 00 = Only one transmit/receive will be executed in one transfer. 01 = Two successive transmit/receive will be executed in one transfer. 10 = Three successive transmit/receive will be executed in one transfer. 11 = Four successive transmit/receive will be executed in one transfer. Transmit Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted. Tx_BIT_LEN = 0x01 … 1 bit Tx_BIT_LEN = 0x02 … 2 bits …… Tx_BIT_LEN = 0x1f … 31 bits Tx_BIT_LEN = 0x00 … 32 bits Transmit On Negative Edge 0 = The mw_so_o signal is changed on the rising edge of mw_sclk_o. 1 = The mw_so_o signal is changed on the falling edge of mw_sclk_o. Receive On Negative Edge 0 = The mw_si_i signal is latched on the rising edge of mw_sclk_o. 1 = The mw_si_i signal is latched on the falling edge of mw_sclk_o. Go and Busy Status 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished. NOTE: All registers should be set before writing 1 to the GO_BUSY bit in the CNTRL register. When a transfer is in progress, writing to any register of the USI(Microwire/SPI) master core has no effect. [10] LSB [9:8] Tx_NUM [7:3] Tx_BIT_LEN [2] Tx_NEG [1] Rx_NEG [0] GO_BUSY - 486 - W90P710CD/W90P710CDG USI Divider Register (USI_DIVIDER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_Divider 0xFFF8_6204 R/W USI Clock Divider Register 31 23 15 7 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 4 11 3 10 2 9 1 19 18 17 27 26 25 0x0000_0000 24 16 8 0 DIVIDER[15:8] DIVIDER[7:0] BITS DESCRIPTIONS Clock Divider Register The value in this field is the frequency divider of the system clock pclk to generate the serial clock on the output usi_sclk_o. The desired frequency is obtained according to the following equation: [15:0] DIVIDER f sclk = (DIVIDER + 1)* 2 f pclk NOTE: Suggest DIVIDER should be at least 1. USI Slave Select Register (USI_SSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_SSR 0xFFF8_6208 R/W USI Slave Select Register 0x0000_0000 - 487 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 31 23 15 7 30 22 14 6 29 21 13 5 Reserved 28 Reserved 20 Reserved 12 Reserved 4 27 19 11 3 ASS 26 18 10 2 SS_LVL 25 17 9 1 SSR[1:0] 24 16 8 0 BITS DESCRIPTIONS [3] ASS Automatic Slave Select 0 = If this bit is cleared, slave select signals are asserted and deasserted by setting and clearing related bits in SSR register. 1 = If this bit is set, usi_ss_o signals are generated automatically. It means that device/slave select signal, which is set in SSR register is asserted by the USI controller when transmit/receive is started by setting CNTRL[GO_BUSY], and is de-asserted after every transmit/receive is finished. Slave Select Active Level It defines the active level of device/slave select signal (usi_ss_o). 0 = The usi_ss_o slave select signal is active Low . 1 = The usi_ss_o slave select signal is active High. Slave Select Register If SSR[ASS] bit is cleared, writing 1 to any bit location of this field sets the proper sui_ss_o line to an active state and writing 0 sets the line back to inactive state. If SSR[ASS] bit is set, writing 1 to any bit location of this field will select appropriate sui_ss_o line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of usi_ss_o is specified in SSR[SS_LVL]). NOTE: This interface can only drive one device/slave at a given time. Therefore, the slave select of the selected device must be set to its active level before starting any read or write transfer. [2] SS_LVL [1:0] SSR - 488 - W90P710CD/W90P710CDG USI Data Receive Register 0/1/2/3 (USI_Rx0/1/2/3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_RX0 USI_RX1 USI_RX2 USI_RX3 31 23 15 7 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C R R R R USI Data Receive Register 0 USI Data Receive Register 1 USI Data Receive Register 2 USI Data Receive Register 3 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 30 22 14 6 29 21 13 5 28 Rx [31:24] 20 Rx [23:16] 12 Rx [15:8] 4 Rx [7:0] 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 BITS DESCRIPTIONS Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if CNTRL[Tx_BIT_LEN] is set to 0x08 and CNTRL[Tx_NUM] is set to 0x0, bit Rx0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same FFs. [31:0] Rx Data Transmit Register 0/1/2/3 (Tx0/1/2/3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_TX0 USI_TX1 USI_TX2 USI_TX3 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C W W W W USI Data Transmit Register 0 USI Data Transmit Register 1 USI Data Transmit Register 2 USI Data Transmit Register 3 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 489 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 31 23 15 7 30 22 14 6 29 21 13 5 28 Tx [31:24] 20 Tx [23:16] 12 Tx [15:8] 4 Tx [7:0] 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 BITS DESCRIPTIONS Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if CNTRL[Tx_BIT_LEN] is set to 0x08 and the CNTRL[Tx_NUM] is set to 0x0, the bit Tx0[7:0] will be transmitted in next transfer. If CNTRL[Tx_BIT_LEN] is set to 0x00 and CNTRL[Tx_NUM] is set to 0x3, the core will perform four 32-bit transmit/receive successive using the same setting (the order is Tx0[31:0], Tx1[31:0], Tx2[31:0], Tx3[31:0]). NOTE: The RxX and TxX registers share the same flip-flops, which means that what is received from the input data line in one transfer will be transmitted on the output data line in the next transfer if no write access to the TxX register is executed between the transfers. [31:0] Tx - 490 - W90P710CD/W90P710CDG 6.20 PWM The W90P710 have 4 channels PWM timers. They can be divided into two groups. Each group has 1 Prescaler, 1 clock divider, 2 clock selectors, 2 16-bit counters, 2 16-bit comparators, 1 Dead-Zone generator. They are all driven by PCLK (80 MHz). Each channel can be used as a timer and issue interrupt independently. Two channels PWM timers in one group share the same prescaler. Clock divider provides each channel with 5 clock sources (1, 1/2, 1/4, 1/8, 1/16). Each channel receives its own clock signal from clock divider which receives clock from 8-bit prescaler. The 16-bit counter in each channel receive clock signal from clock selector and can be used to handle one PWM period. The 16-bit comparator compares number in counter with threshold number in register loaded previously to generate PWM duty cycle. The clock signal from clock divider is called PWM clock. Dead-Zone generator utilize PWM clock as clock source. Once Dead-Zone generator is enabled, output of two PWM timer in one group is blocked. Two output pin are all used as Dead-Zone generator output signal to control off-chip power device. To prevent PWM driving output pin with unsteady waveform, 16-bit counter and 16-bit comparator are implemented with double buffering feature. User can feel free to write data to counter buffer register and comparator buffer register without generating glitch. When 16-bit down counter reaches zero, the interrupt request is generated to inform CPU that time is up. When counter reaches zero, if counter is set as toggle mode, it is reloaded automatically and start to generate next cycle. User can set counter as one-shot mode instead of toggle mode. If counter is set as one-shot mode, counter will stop and generate one interrupt request when it reaches zero. The value of comparator is used for pulse width modulation. The counter control logic changes the output level when down-counter value matches the value of compare register. The PWM timer features are shown as below: Two 8-bit prescalers and two clock dividers Four clock selectors Four 16-bit counters and four 16-bit comparators Two Dead-Zone generator 6.20.1 PWM double buffering and reload automatically W90P710 PWM Timers have a double buffering function, enabling the reload value changed for next timer operation without stopping current timer operation. Although new timer value is set, current timer operation still operate successfully. The counter value can be written into PWM_CNR0, PWM_CNR1, PWM_CNR2, PWM_CNR3 and current counter value can be read from PWM_PDR0, PWM_PDR1, PWM_PDR2, PWM_PDR3. Publication Release Date: September 19, 2006 Revision B2 - 491 - W90P710CD/W90P710CDG The auto-reload operation copies from PWM_CNR0, PWM_CNR1, PWM_CNR2, PWM_CNR3 to down-counter when down-counter reaches zero. If PWM_CNR0~3 are set as zero, counter will be halt when counter count to zero. If auto-reload bit is set as zero, counter will be stopped immediately. 6.20.2 Modulate Duty Ratio The double buffering function allows PWM_CMR written at any point in current cycle. The loaded value will take effect from next cycle. 6.20.3 Dead Zone Generator W90P710 PWM is implemented with Dead Zone generator. They are built for power device protection. This function enables generation of a programmable time gap at the rising of PWM output waveform. User can program PWM_PPR [31:24] and PWM_PPR [23:16] to determine the Dead Zone interval. - 492 - W90P710CD/W90P710CDG Dead zone generator operation PWM_out1 PWM_out1_n PWM_out1_DZ PWM_out1_n_DZ Dead zone interval 6.20.4 PWM Timer Start procedure 1. Setup clock selector (PWM_CSR) 2. Setup prescaler & dead zone interval (PWM_PPR) 3. Setup inverter on/off, dead zone generator on/off, toggle mode /one-shot mode, and PWM timer off. (PWM_PCR) 4. Setup comparator register (PWM_CMR) 5. Setup counter register (PWM_CNR) 6. Setup interrupt enable register (PWM_PIER) 7. Enable PWM timer (PWM_PCR) 6.20.5 PWM Timer Stop procedure Method 1 : Set 16-bit down counter(PWM_CNR) as 0, and monitor PWM_PDR. When PWM_PDR reaches to 0, disable PWM timer (PWM_PCR). (Recommended) Method 2 : Set 16-bit down counter(PWM_CNR) as 0. When interrupt request happen, disable PWM timer (PWM_PCR). (Recommended) Method 3 : Disable PWM timer directly (PWM_PCR). (Not recommended) - 493 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 6.20.6 PWM Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PPR PWM_CSR PWM_PCR PWM_CNR0 PWM_CMR0 PWM_PDR0 PWM_CNR1 PWM_CMR1 PWM_PDR1 PWM_CNR2 PWM_CMR2 PWM_PDR2 PWM_CNR3 PWM_CMR3 PWM_PDR3 PWM_PIER PWM_PIIR 0xFFF8_7000 0xFFF8_7004 0xFFF8_7008 0xFFF8_700C 0xFFF8_7010 0xFFF8_7014 0xFFF8_7018 0xFFF8_701C 0xFFF8_7020 0xFFF8_7024 0xFFF8_7028 0xFFF8_702C 0xFFF8_7030 0xFFF8_7034 0xFFF8_7038 0xFFF8_703C 0xFFF8_7040 R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/C PWM Prescaler Register PWM Clock Select Register PWM Control Register PWM Counter Register 0 PWM Comparator Register 0 PWM Data Register 0 PWM Counter Register 1 PWM Comparator Register 1 PWM Data Register 1 PWM Counter Register 2 PWM Comparator Register 2 PWM Data Register 2 PWM Counter Register 3 PWM Comparator Register 3 PWM Data Register 3 PWM Interrupt Enable Register PWM Interrupt Indication Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 PWM Prescaler Register (PWM_PPR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PPR 31 23 15 7 0xFFF8_7000 R/W PWM Prescaler Register 0x0000_0000 30 22 14 6 29 21 13 5 28 DZI1 20 DZI0 12 CP1 4 CP0 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - 494 - W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:24] DZI1 DZI1: Dead zone interval register 1, these 8-bit determine dead zone length. The 1 unit time of dead zone length is received from clock selector 2. DZI0: Dead zone interval register 0, these 8-bit determine dead zone length. The 1 unit time of dead zone length is received from clock selector 0. CP1 : Clock prescaler 1 for PWM Timer channel 2 & 3 [23:16] DZI0 [15:8] CP1 Clock input is divided by (CP1 + 1) before it is fed to the counter. 2 & 3 If CP1=0, then the prescaler 1 output clock will be stopped. CP0 : Clock prescaler 0 for PWM Timer channel 0 & 1 [7:0] CP0 Clock input is divided by (CP0 + 1) before it is fed to the counter. 0 & 1 If CP0=0, then the prescaler 0 output clock will be stopped. PWM Clock Select Register (PWM_CSR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_CSR 31 23 15 Reserved 7 Reserved BITS 0xFFF8_7004 R/W PWM Clock Select Register 0x0000_0000 30 22 14 6 29 21 13 CSR3 5 CSR1 28 Reserved 20 Reserved 12 4 27 19 11 Reserved 3 Reserved DESCRIPTIONS 26 18 10 2 25 17 9 CSR2 1 CSR0 24 16 8 0 [14:12] [10:8] [6:4] [2:0] CSR3 CSR2 CSR1 CSR0 Select clock input for channel 3 Select clock input for channel 2. Select clock input for channel 1 Select clock input for channel 0 - 495 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG CSR3 INPUT CLOCK DIVIDED BY 000 001 010 011 100 2 4 8 16 1 PWM Control Register (PWM_PCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PCR 31 23 15 PCR15 7 PCR07 0xFFF8_7008 R/W PWM Control Register 0x0000_0000 30 22 Reserved 14 PCR14 6 PCR06 29 21 13 PCR13 5 PCR05 28 Reserved 20 12 PCR12 4 PCR04 27 19 PCR19 11 PCR11 3 PCR03 26 18 PCR18 10 PCR10 2 PCR02 25 17 PCR17 9 PCR09 1 PCR01 24 16 PCR16 8 PCR08 0 PCR00 BITS DESCRIPTIONS Channel 3 toggle/one shot mode [19] PCR 19 1 = toggle mode 0 = one shot mode Channel 3 Inverter on/off [18] PCR 18 1 = inverter on 0 = inverter off [17] PCR 17 Reserved Channel 3 enable/disable [16] PCR 16 1 = enable 0 = disable - 496 - W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Channel 2 toggle/one shot mode [15] PCR 15 1 = toggle mode 0 = one shot mode Channel 2 Inverter on/off [14] PCR 14 1 = inverter on 0 = inverter off [13] PCR 13 Reserved Channel 2 enable/disable [12] PCR 12 1 = enable 0 = disable Channel 1 toggle/one shot mode [11] PCR 11 1 = toggle mode 0 = one shot mode Channel 1 Inverter on/off [10] PCR 10 1 = inverter on 0 = inverter off [09] PCR 09 Reserved Channel 1 enable/disable [08] PCR 08 1 = enable 0 = disable [07] [06] PCR 07 PCR 06 Reserved Reserved Dead-Zone generator 1 enable/disable [05] PCR 05 1 = enable dead-zone generator 0 = disable dead-zone generator Dead-Zone generator 0 enable/disable [04] PCR 04 1 = enable dead-zone generator 0 = disable dead-zone generator - 497 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Channel 0 toggle/one shot mode [03] PCR 03 1 = toggle mode 0 = one shot mode Channel 0 Inverter on/off [02] PCR 02 1 = inverter on 0 = inverter off [01] PCR 01 Reserved Channel 0 enable/disable [00] PCR 00 1 = enable 0 = disable PWM Counter Register 0/1/2/3 (PWM_CNR0/1/2/3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_CNR0 PWM_CNR1 PWM_CNR2 PWM_CNR3 31 23 15 7 0xFFF8_700C 0xFFF8_7018 0xFFF8_7024 0xFFF8_7030 R/W PWM Counter Register 0 R/W PWM Counter Register 1 R/W PWM Counter Register 2 R/W PWM Counter Register 3 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 30 22 14 6 29 21 13 5 28 Reserved 20 Reserved 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 CNRx[15:8] CNRx[7:0] - 498 - W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:16] Reserved CNR: PWM counter/timer buffer. Inserted data range: 65535~0. Unit: 1 PWM clock cycle Note 1: One PWM counter countdown interval = CNR + 1.If CNR is loaded as zero, PWM counter will be stopped. Note 2: Programmer can feel free to write data to CNR at any time, and it will be reloaded when PWM counter reaches zero. [15:0] CNRx PWM Comparator Register 0/1/2/3 (PWM_CMR0/1/2/3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_CMR0 PWM_CMR1 PWM_CMR2 PWM_CMR3 31 23 15 7 0xFFF8_7010 0xFFF8_701C 0xFFF8_7028 0xFFF8_7034 30 22 14 6 29 21 13 5 R/W PWM Comparator Register 0 R/W PWM Comparator Register 1 R/W PWM Comparator Register 2 R/W PWM Comparator Register 3 28 Reserved 20 Reserved 12 4 CMRx[7:0] 11 3 10 2 9 1 19 18 17 27 26 25 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 24 16 8 0 CMRx[15:8] BITS DESCRIPTIONS [31:16] Reserved CMR: PWM comparator register Inserted data range: 65535~0. CMR is used to determine PWM output duty ratio. Note 1: PWM duty = CMR + 1.If CMR is loaded as zero, PWM duty = 1 Note 2: Programmer can feel free to write data to CMR at any time, and it will be reloaded when PWM counter reaches zero. [15:0] CMRx - 499 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG PWM Data Register 0/1/2/3 (PWM_PDR 0/1/2/3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PDR0 PWM_PDR1 PWM_PDR2 PWM_PDR3 31 23 15 7 0xFFF8_7014 0xFFF8_7020 0xFFF8_702C 0xFFF8_7038 30 22 14 6 29 21 13 5 R R R R PWM Data Register 0 PWM Data Register 1 PWM Data Register 2 PWM Data Register 3 28 Reserved 20 Reserved 12 4 PDRx[7:0] 11 3 10 2 9 1 19 18 17 27 26 25 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 24 16 8 0 PDRx[15:8] BITS DESCRIPTIONS [31:16] [15:0] Reserved PDRx PDR: PWM Data register. User can monitor PDR to get current value in 16-bit down counter. PWM Interrupt Enable Register (PWM_PIER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PIER 31 23 15 7 0xFFF8_703C 30 22 14 6 Reserved 29 21 13 5 R/W PWM Interrupt Enable Register 28 Reserved 20 Reserved 12 Reserved 4 3 PIER3 2 PIER2 1 11 10 9 19 18 17 27 26 25 0x0000_0000 24 16 8 0 PIER0 PIER1 - 500 - W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:4] [3] Reserved PIER3 Enable/Disable PWM counter channel 3 interrupt request 1 = enable 0 = disable Enable/Disable PWM counter channel 2 interrupt request 1 = enable 0 = disable Enable/Disable PWM counter channel 1 interrupt request 1 = enable 0 = disable Enable/Disable PWM counter channel 0 interrupt request 1 = enable 0 = disable [2] PIER2 [1] PIER1 [0] PIER0 PWM Interrupt Indication Register (PWM_PIIR) REGISTER ADDRESS R/W/C DESCRIPTION RESET VALUE PWM_PIIR 31 23 15 7 0xFFF8_7040 30 22 14 6 Reserved 29 21 13 5 R/C PWM Interrupt Indication Register 28 Reserved 20 Reserved 12 Reserved 4 3 PIIR3 DESCRIPTIONS 0x0000_0000 25 17 9 1 PIIR1 24 16 8 0 PIIR0 27 19 11 26 18 10 2 PIIR2 BITS [3] [2] [1] [0] PIIR3 PIIR2 PIIR1 PIIR0 PWM counter channel 3 interrupt flag PWM counter channel 2 interrupt flag PWM counter channel 1 interrupt flag PWM counter channel 0 interrupt flag Note: User can clear each interrupt flag by writing a zero to corresponding bit in PIIR - 501 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 6.21 Keypad Interface W90P710 Keypad Interface (KPI) is an APB slave with 4-row scan output and 8-column scan input. KPI scans an array up to 16x8 with an external 4 to 16 decoder. It can also be programmed to scan 8x8 or 4x8 key array. If the 4x8 array is selected then external decoder is not necessary because the scan signals are dived by W90P710 itself. For minimum pin counts application, an auxiliary priority encoder (TTL 74148) can be used to encode 8 columns input to 3 binary code and one indicator flag. Total 8 pins are required to implement 16x8 key scan. Any 1 or 2 keys in the array that pressed are debounced and encoded. The keypad controller scan key matrix from ROW0 COL 0 1 2 …. 7, ROW1 COL 0 1 2… 7 till to ROW 16 (or ROW 8 or ROW 4) COL 0 0 1 …. 7. If more than 2 keys are pressed, only the keys or apparent keys in the array with the lowest address will be decoded. KPI also supports 2-keys scan interrupt and specified 3-keys interrupt or chip reset. If the 3 pressed keys matches with the 3 keys defined in KPI3KCONF, it will generate an interrupt or chip reset to nWDOG reset output depend on the ENRST setting. The interrupt is generated whenever the scanner detects a key is pressed. The interrupt conditions are 1 key, 2 keys and 3keys. W90P710 provides two keypad connecting interface. One is allocated in LCD (GPIO30-41) interface, the other is in Ethernet RMII PHY interface and I2C interface 2 SDA1, SCL1 (GPIO42-51). Software should set KPSEL bit in KPICONF register to decide which interface is used as keypad connection port. The keypad interface has the following features: maximum 16x8 array programmable debounce time low-power wakeup mode programmable three-key reset - 502 - W90P710CD/W90P710CDG KPIR[3:0] 4 :16 DECODER W90P710 ROW[[16:0] KPIC[7:0] COL[7:0] 16x8 key pad matrix Fig. 6.21.1 W90P710 Keypad Interface 6.21.1 KeyPad Interface Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPICONF KPI3KCONF KPILPCONF KPISTATUS 0xFFF8_8000 0xFFF8_8004 0xFFF8_8008 0xFFF8_800C R/W R/W R/W R/O Keypad controller configuration Register Keypad controller 3-keys configuration register Keypad controller configuration register low power 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Keypad controller status register - 503 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 6.21.2 Register Description Keypad Controller Configuration Register (KPI_CONF) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPICONF 0xFFF8_8000 R/O key pad configuration register 0x0000_0000 31 23 15 7 30 22 14 6 29 21 ENCODE 13 5 28 20 ODEN 12 DBTC 4 PRESCALE 27 19 KPSEL 11 3 26 18 ENKP 10 2 25 17 KSIZE 9 1 24 16 8 0 RESERVED RESERVED BITS DESCRIPTION [31:22] RESERVED Enable Encode Function If an auxiliary 8 to 3 encoder is used to minimize keypad interface pin counts, user can connect encoder data to KPCOL[2:0] and indicator flag (low active) to KPCOL[3]. 1 = enable encoder function 0 = default. (8 column inputs) Open Drain Enable If there are more than one key are pressed in the same column, then “short-circuit” will appear between active scan and inactive scan row. Software can set this bit HIGH to enable scan output KPROW[3:0] pins work as “open-drain” to avoid the “short-circuit”. 1 = Open drain 0 = push-pull driver Key pad select W90P710 provide two interfaces for keypad function. Software should set this bit to select which interface is used to connect keypad matrix. 1 = pin#23 ~#34 is used as keypad interface 0 = pin #81~88 and #19,#20 are used as keypad interface [21] ENCODE [20] ODEN [19] KPSEL - 504 - W90P710CD/W90P710CDG Continued BITS DESCRIPTION Key pad scan enable [18] ENKP Setting this bit high enable the key scan function. 1 = enable key pad scan 0 = disable key pad scan Key array size KSIZE [17:16] KSIZE 2’b00 2’b01 2’b1x Key array size 4x8, 3x8, 2x8, 1x8 8x8, 7x8, 6x8, 5x8 16x8, 15x8, 14x8, 13x8, 12x8, 11x8, 10x8, 9x8 Debounce terminal count [15:8] DBTC Debounce counter counts the number of consecutive scans that decoded the same keys. When de-bounce counter counter is equal to terminal count it will generate a key scan interrupt. Row scan cycle pre-scale value This value is used to prescale row scan cycle. The prescale counter is clocked by 0.9375MHz clock. Key array scan time = 1.067us x PRESCALE x16 ROWS [7:0] PRESCALE The following example is the scan time for PRESCALE = 0xFA Tscan_time = 1.067us x 250 x16 = 4.268ms If debounce terminal count = 0x05, key detection interrupt is fired in approximately 21.34ms. The array scan time can range from 17.07us to 1.118 sec. - 505 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 16x8 keys matrix 74138 ROW[15:0] COL[7:0] ROW[3:0] W90P710 COL[0] COL[1] COL[2] COL[3] ENCODER A0 A1 A2 GS IN[7:0] 74148 keypad I/F with 8:3 encoder Fig. 6.21.1 Keypad Interface with row decoder and column encoder Keypad Controller 3-keys Configuration Register (KPI3KCONF) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPI3KCONF 0xFFF8_8004 W/R three-key register configuration 0x0000_0000 31 23 RESERVED 15 RESERVED 7 RESERVED 30 22 14 6 29 21 K32R 13 K31R 5 K30R 28 20 12 4 27 19 11 3 26 18 10 2 25 EN3KY 17 K32C 9 K31C 1 K30C 24 ENRST 16 8 0 RESERVED - 506 - W90P710CD/W90P710CDG BITS DESCRIPTION [31:26] [25] RESERVED EN3KY Enable three-keys detection Setting this bit enables hardware to detect 3 keys specified by software Enable three-key reset Setting this bit enable hardware reset when three-key is detected. [24] ENRST EN3KY 0 1 1 ENRST X 0 1 Function three-key function is disable generate three-key interrupt hardware reset by three-key-reset [23] [22:19] [18:16] [15] [14:11] [10:8] [7] [6:3] [2:0] RESERVED K32R K32C RESERVED K31R K31C RESERVED K30R K30C The #2 key row address The #2 means the row address and the column address is the highest of the specified 3-kyes. The #2 key column address The #1 key row address The #1 means the row address and the column address is the 2nd of the specified 3-kyes. The #1 key column address The #0 key row address The #0 means the row address and the column address is the lowest of the specified 3-kyes. The #0 key column address Application Note: Due to hardware scan from {row[0], col[0]}, {row[0], col[1]}, …, to {row[15], col[7]} the {K30R,K30C} should be filled the lowest address of the three-keys. For example, if {2,0} {4,6}, {1,3} keys are defined as three-keys. Software should set {K30R, K30C} = {1, 3}, {K31R, K31C} = {2, 0} and {K32R, K32C} = {4, 6}. - 507 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG KeyPad Interface Low Power Mode Configuration Register (KPILPCONF) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPILPCOF 31 23 15 7 0xFFF8_8008 30 22 14 6 29 21 13 5 W/R Low power configuration register 28 20 12 LPWCEN 4 3 2 LPWR DESCRIPTION 0x0000_0000 25 17 9 1 24 16 WAKE 8 0 27 19 11 26 18 10 RESERVED RESERVED BITS [31:17] RESERVED Lower power wakeup enable Setting this bit enables low power wakeup 1 = wakeup enable 0 = not enable Low power wakeup column enable Specify columns for low power wakeup. For example, if user wants to use keys in row N and column 0, 2, 5 to wake up W90P710, then the LPWCEN should be fill 8’b00100101. Application restriction: when ENCODE=1 case, LPWCEN should be set as 0xFF ie, all columns in specified row are used as wake up input. In this case, user can not specify special cloumn(s) to wake up W90P710. [16] WAKE [15:8] LPWCEN [7:4] RESERVED Low power wakeup row address Define the row address keys used to wakeup. For 16x8 or 8x8 (with 4:16 or 3:8 decoder) keypad key configuration, LPWR means “Hex” code but for 4x8 (without decoder), LPWR means “binary” code. For example, if user wants to use all keys on row 3 of 16x8 keypad to wakeup W90P710, then 0x3 should be fill into this register but for 4x8 keypad it should be filled as 4’b1000. [3:0] LPWR - 508 - W90P710CD/W90P710CDG Key Pad Interface Status Register (KPISTATUS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPISTATUS 31 23 15 RESERVED 7 RESERVED BITS 0xFFF8_800C 30 22 14 6 29 21 INT 13 5 R/O 28 key pad status register 27 19 PDWAKE 11 3 26 18 3KEY 10 2 0x0000_0000 25 17 2KEY 9 KEY1C 1 KEY0C 0 24 16 1KEY 8 RESERVED 20 3KRST 12 KEY1R 4 KEY0R DESCRIPTION RESERVED [31:22] RESERVED Key interrupt This bit indicates the key scan interrupt is active and that one or two keys have changed status. The interrupt also occur when the three specified keys are detected if ENRST bit in KPI3KFCON is cleared. It will be cleared by hardware automatically when software read KPISTATUS register. 3-Keys reset flag This bit is a record flag for software reference, it will be set after 3keys reset occur. 1 = 3 keys reset 0 = not reset. This bit is cleared while it is read. Power Down Wakeup flag This flag indicates the chip is wakeup from power down by keypad 1 =wakeup up by keypad 0 = not wakeup Specified three-key is detected. This flag indicates specified-three-keys was detected. Software can read this bit to know the keypad interrupt is 3 key or not. [21] INT [20] 3KRST [19] PDWAKE [18] 3KEY - 509 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Continued BITS DESCRIPTION Double-key press [17] 2KEY This bit indicates that 2 keys have been detected. Software can read {KEY1R, KEY1C} and {KEY0R, KEY0C} to know which two keys are pressed. Single-key press [16] [15] 1KEY RESERVED This bit indicates that 1 key has been detected. Software can read {KEY0R, KEY0C} to know which key is pressed. KEY1 row address [14:11] KEY1R This value indicates key1 row address. The keypad controller scan keypad matrix from row 0, column0 1 2 …. 7 and then row1 column 0 1 2 7 so the lowest key address will be stored in {KEY0R, KEY0C}. This register stores the 2nd address, if more than one key is pressed. KEY1 column address This value indicates key1 column address.. KEY1 row address This value indicates key0 row address. This value indicates key0 row address. This value indicates key1 row address. The keypad controller scan keypad matrix from row 0, column0 1 2 …. 7 and then row1 col 0 1 2 … 7 still to row16 (or 8, or 4) column 0 1 2 ….. 7 so the lowest key address will be stored in {KEY0R, KEY0C}. KEY1 column address This value indicates key0 row address. [10:8] [7] KEY1C RESERVED [6:3] KEY0R [2:0] KEY0C - 510 - W90P710CD/W90P710CDG 6.22 PS2 Host Interface Controller W90P710 PS2 host controller interface is an APB slave consisted of PS2 protocol. It is used to connect to your IBM keyboard or other device through PS2 interface. For example, the IBM keyboard will sends scan codes to the host controller, and the scan codes will tell your Keyboard Bios what keys you have pressed or released. Besides Scan codes, commands can also be sent to the keyboard from host. The most common commands would be the setting/resetting of the status indicators (i.e. the Num lock, Caps Lock & Scroll Lock LEDs). The PS2 interface implements a bi-directional protocol. The keyboard can send data to the Host and the Host can send data to the Keyboard using two PS2 Clock and PS2 Data lines. Both the PS2 Clock and Data lines are Open Collector bi-directional I/O lines. The Host has the ultimate priority over direction. The keyboard is free to send data to the host when both the PS2 Data and PS2 Clock lines are high (Idle). If the host takes the PS2 Clock line low, the keyboard will buffer any data until the PS2 Clock is released, ie goes high. The transmission of data in the forward direction, ie Keyboard to Host is done with a frame of 11 bits. The first bit is a Start Bit (Logic 0) followed by 8 data bits (LSB First), one Parity Bit (Odd Parity) and a Stop Bit (Logic 1). Each bit should be read on the falling edge of the clock. The Keyboard will generate the clock. The frequency of the clock signal typically ranges from 20 to 30 KHz. The Host to Keyboard Protocol is initiated by taking the PS2 data line low. It is common to take the PS2 Clock line low for more than 60us and then the KBD data line is taken low, while the KBD clock line is released. After that, the keyboard will start generating a clock signal on its PS2 clock line. After the first falling edge has been detected, host will load the first data bit on the PS2 Data line. This bit will be read into the keyboard on the next falling edge, after which host place the next bit of data. This process is repeated for the 8 data bits. It will follow an Odd Parity Bit after the data byte. - 511 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 6.22.1 PS2 Host Controller Interface Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PS2CMD PS2STS 0xFFF8_9000 0xFFF8_9004 R/W R/W RO RO PS2 Host Controller Command Register PS2 Host Controller Status Register 0x0000_0000 0x0000_0000 PS2SCANCODE 0xFFF8_9008 PS2ASCII 0xFFF8_900C PS2 Host Controller RX Scan Code 0x0000_0000 Register PS2 Host Controller RX ASCII Code 0x0000_0000 Register 6.22.2 Register Description PS2 Host Controller Command Register (PS2_CMD) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PS2CMD 31 23 15 7 0xFFF8_9000 30 22 14 6 13 5 29 21 R/W Command register 28 20 27 19 11 RESERVED 4 PS2CMD 3 2 26 18 10 25 17 9 0x0000_0000 24 16 8 EnCMD 0 RESERVED RESERVED 12 TRAP_SHIFT 1 BITS DESCRIPTIONS [31:10] RESERVED Trap Shift Key Output to Scan Code Register If the shift key scan code (0x12 0r 0x59) is received by host, software can indicate host whether to update to scan code register or not. No ASCII or SCAN codes will be reported for the shift keys if this bit is set. In this condition, host will only report the shift keys at the RX_shift_key bit of Status register and no interrupt will occur for the shift keys. This is useful for those who wish to use the ASCII data stream and don’t want to “manually” filter out the shift key codes. This bit is clear by default. [9] TRAP_SHIFT - 512 - W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Enable write PS2 Host Controller Commands [8] EnCMD This bit enables the write function of Host controller command to device. Set this bit will start the write process of PS2CMD content and hardware will automatically clear this bit while write process is finished. PS2 Host Controller Commands [7:0] PS2CMD This command filed is sent by the Host to the Keyboard. The most common command would be the setting/resetting of the Status Indicators (i.e. the Num lock, Caps Lock & Scroll Lock LEDs). PS2 Host Controller Status Register (PS2_STS) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PS2STS 31 23 15 7 0xFFF8_9004 30 22 14 6 29 21 13 5 TX_err R/W Status register 28 20 12 4 TX_IRQ 27 19 11 3 26 18 10 2 RESERVED DESCRIPTIONS 0x0000_0000 25 17 9 1 24 16 8 0 RX_IRQ RESERVED RESERVED RESERVED RESERVED BITS [31:6] RESERVED This Transmit Error Status bit indicates software that device doesn’t response ACK after Host wrote a command to it. [5] TX_err This bit is valid when TX_IRQ is asserted. It will automatically reset after software starts next command writing process. This bit is read only. This Transmit Complete Interrupt bit indicates software that the process of Host controller writing command to device is finished. Software needs to write one to this bit to clear this interrupt. [4] TX_IRQ - 513 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS [3:1] Reserved This Receive Interrupt bit indicates software that Host controller receives one byte data from device. This data is stored at PS2_SCANCODE register. Software needs to write one to this bit to clear this interrupt after reading receiving data in RX_SCAN_CODE register. Note that the reception of the Extend (0xE0) and Release (0xF0) scan code will not cause an interrupt by host. The case of the shift key codes will be determined by the TRAP_SHIFT bit of PS2_CMD register. [0] RX_IRQ PS2 Host Controller RX Scan Code Register (PS2_SCANCODE) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PS2SCANCODE 0xFFFF_9008 R/W key pad c RX Scan Code Register 27 26 18 10 RX_shift_key 0x0000_0000 31 23 15 7 30 22 14 6 29 21 13 RESERVED 5 28 20 12 4 25 17 9 1 24 16 8 0 RESERVED 19 RESERVED 11 3 RX_releaseRX_extend 2 RX_SCAN_CODE BITS DESCRIPTIONS [31:11] [10] RESERVED RX_shift_key This Receive Shift Key bit indicates that left or right shift key on the keyboard is hold. This bit is read only and will clear by host when the release shift key codes are received. Receive Released Byte When one key has been released, the keyboard will send F0 (hex) to inform Host controller. This bit indicates software that Host controller receives release byte (F0). This bit is read only and will update when host has received next data byte. [9] RX_release - 514 - W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Receive Extend Byte [8] RX_extend A handful of the keys on keyboard are extended keys and thus require two more scan code. These keys are preceded by an E0 (hex). This bit indicates software that Host controller receives extended byte (E0). This bit is read only and will update when host has received next data byte. PS2 Host Controller Received Data Field This field stores the original data content transmitted from device. This filed is valid when RX_IRQ is asserted. Note that host will not report “Extend” or “Release” scan code to this field and not generate interrupt if they are received by host, i.e. 0xE0 and 0xF0. The case of the shift key codes will be determined by the TRAP_SHIFT bit of PS2_CMD register. [7:0] RX_SCAN_CODE PS2 Host Controller RX ASCII Code Register (PS2_ASCII) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PS2ASCII 31 23 15 7 0xFFF8_900C 30 22 14 6 R/W 29 21 13 5 key pad c RX ASCII Code Register 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 0x0000_0000 24 16 8 0 RESERVED RESERVED RESERVED RX_ASCII_CODE BITS DESCRIPTIONS [31:8] RESERVED PS2 Host Controller Received Data Filed [7:0] RX_ASCII_CODE This field stores the ASCII data content transmitted from device. Therefore, this part translates the scan code into an ASCII value. It will be read as 0x2E when there is no ASCII code mapped to the scan code stored in RX_SCAN_CODE register. This filed is valid when RX_IRQ is asserted. - 515 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 7. ELECTRICAL SPECIFICATIONS 7.1 Absolute Maximum Ratings Ambient temperature .................................……………............................. Storage temperature ..................................................…….................... Voltage on any pin ...............................................................…….......... Power supply voltage (Core logic) ..............................…...........………..….. Power supply voltage (IO Buffer) ...............................…...........………..….. Injection current (latch-up testing) ..............................................……….. Crystal Frequency ...............................................…...........………..………… TBD -40 °C ~ +125°C -0.5V ~ 6V -0.5V ~ 1.92V -0.5V ~ 3.6V 100mA 4MHz ~ 30MHz 7.2 7.2.1 DC Specifications Digital DC Characteristics (Normal test conditions: VDD33/USBVDD = 3.3V+/- 0.3V, VDD18/DVDD18/AVDD18 = 1.8V+/- 0.18V TA = -40 °C ~ +85 °C unless otherwise specified) SYMBOL PARAMETER CONDITION MIN. MAX. UNIT VDD33/ USB1VDD Power Supply USB2VDD VDD18/ DVDD18/ Power Supply AVDD18/ RTCVDD18 VIL Input Low Voltage VIH Input High Voltage VT+ VTVOL VOH ICC1 ICC2 ICCRTC IIH IIL IIHP IILP IIHD IILD Schmitt Trigger positive-going threshold Schmitt trigger negative-going threshold Output Low Voltage Depend on driving Output High Voltage 1.8V Supply Current 3.3V Supply Current RTC 1.8V Supply Current Input High Current Input Low Current Input High Current (pull-up) Input Low Current (pull-up) Input High Current (pull-down) Input Low Current (pull-down) Depend on driving FCPU = 80MHz FCPU = 80MHz FRTC = 32.768KHZ VIN = 2.4 V VIN = 0.4 V VIN = 2.4 V VIN = 0.4 V VIN = 2.4 V VIN = 0.4 V 3.00 3.60 V 1.62 -0.3 2.0 1.47 0.89 2.4 -1 -1 -15 -55 25 5 1.98 0.8 5.5 1.5 0.95 0.4 150 60 7 1 1 -10 -25 60 10 V V V V V V V mA mA uA µA µA µA µA µA µA - 516 - W90P710CD/W90P710CDG Table 7.2.1TSMC IO DC Characteristics PARAMETER MIN. TYP. MAX. VIL VIH VT VT+ VTII Ioz RPU RPD VOL VOH Input Low Voltage Input High Voltage Threshold point Schmitt trig low to high threshold point Schmitt trig, high to low threshold point Input leakage current @VI= 3.3V or 0V Tri-state output leakage current @Vo =3.3V or 0V Pull-up resister Pull-down resister Output low voltage @IOL(min) Output high voltage @IOH (min) Low level output current @VOL = 0.4V 4mA -0.3V 2V 1.46V 1.47V 0.90V 1.59V 1.50V 0.94V 0.8V 5.5V 1.75V 1.50V 0.96V +/- 10uA +/- 10UA 44KΩ 25KΩ 66KΩ 50KΩ 110KΩ 110KΩ 0.4V 2.4V 4.9mA 9.7mA 14.6mA 6.3mA 12.7mA 19.0mA 7.4mA 14.9mA 22.3mA 12.8mA 25.6mA 38.4mA 9.8mA 19.5mA 29.3mA 21.2mA 42.4mA 63.6mA IOL Low level output current @VOL = 0.4V 8mA Low level output current @VOL = 0.4V 12mA High level output current @VOH = 2.4V 4mA IOH High level output current @VOH = 2.4V 8mA High level output current @VOH = 2.4V 12mA NOTE: The values in this table are copied from TSMC 1P5M IO library tpz937g_240b silicon report. This table is just for reference. More precision DC vaule should refer to Alpha-Test result. - 517 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 7.2.2 VDI VCM VSE VOL VOH VCRS ZDRV CIN USB Transceiver DC Characteristics PARAMETER CONDITIONS MIN. MAX. UNIT SYMBOL Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Static Output Low Voltage Static Output High Voltage Output Signal Crossover Voltage Driver Output Resistance Pin Capacitance DP − DM Includes VDI range RL of 1.5 KΩ to 3.6 V RL of 15 KΩ to VSS Steady state drive 0.2 0.8 0.8 2.8 1.3 28 2.5 2.0 0.3 3.6 2.0 43 20 V V V V V V Ω pF 7.3 7.3.1 AC Specifications EBI/SDRAM Interface AC Characteristics 1.5V MCLK TDSU TDH D[31:0] 1.5V Iutput Valid SDRAM input to W90P710 MCLK D[31:0] 1.5V TDO 1.5V Output Valid W90P710 write to SDRAM SYMBOL PARAMETER MIN. MAX. UNIT TDSU TDH TDO D [31:0] Setup Time D [31:0] Hold Time D [31:0], A [24:0], nSCS [1:0], SDQM [3:0], CKE, nSWE, nSRAS, nSCAS 2 2 2 7 ns ns ns - 518 - W90P710CD/W90P710CDG 7.3.2 EBI/(ROM/SRAM/External I/O) AC Characteristics MCLK TNECSO nECS[3:0] TADDO A[21:0] Address Valid TNECSO nOE TNOEO TNOEO TDSU TDH R Data D[31:0] nWAIT TNWASU TNWAH TNWBO TDO D[31:0] Write Data Vaild nWBE[3:0] TNWBO SYMBOL DESCRIPTION MIN MAX UNIT TADDO TNCSO TNOEO TNWBO TDH TDSU TDO TNWASU TNWAH Address Output Delay Time ROM/SRAM/Flash or External I/O Chip Select Delay Time ROM/SRAM or External I/O Bank Output Enable Delay ROM/SRAM or External I/O Bank Write Byte Enable Delay Read Data Hold Time Read Data Setup Time Write Data Output Delay Time (SRAM or External I/O) External Wait Setup Time External Wait Hold Time 2 2 2 2 7 0 2 3 1 7 7 7 7 ns ns ns ns ns ns 7 ns ns ns - 519 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 7.3.3 USB Transceiver AC Characteristics Rise Time CL Differential Data Lines 90% 10% 90% Fall Time 10% CL Full Speed: 4 to 20ns at CL = 50pF tR tF Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF Data Signal Rise and Fall Time USB Transceiver AC Characteristics SYMBOL DESCRIPTION CONDITIONS MIN MAX UNIT TR TF TRFM TDRATE Rise Time Fall Time Rise/Fall Time Matching Full Speed Data Rate CL = 50 pF CL = 50 pF Average bit rate (12 Mb/s ± 0.25%) 4 4 90 11.97 20 20 110 12.03 ns ns % Mbps - 520 - W90P710CD/W90P710CDG 7.3.4 EMC RMII AC Characteristics The signal timing characteristics conforms to the guidelines specified in IEEE Std. 802.3. TFREQ PHY_REFCLK TTXO PHY_TXEN PHY_TXD[1:0] TTXH valid data TDUTY PHY_RXERR PHY_RXD[1:0] PHY_CRSDV TRXS valid data TRXH SYMBOL DESCRIPTION MIN TYP MAX UNIT TFREQ TDUTY TTXO TTXH TRXS TRXH RMII reference clock frequency RMII clock duty Transmit data output delay Transmit data hold time Receive data setup time Receive data hold time 35% 5 2 4 2 50 50% 65% 15 - MHz ns ns ns ns ns - 521 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG PHY_MDC TMDO TMDH PHY_MDIO (Write) valid data TMDS PHY_MDIO (Read) TMDH valid data SYMBOL DESCRIPTION MIN MAX UNIT TMDO TMDSU TMDH MDIO Output Delay Time MDIO Setup Time MDIO Hold Time 0 5 5 15 ns ns ns - 522 - W90P710CD/W90P710CDG 7.3.5 LCD Interface AC Characteristics TPIXCLK VCLK TDELAY VSYNC HSYNC VDEN VD[23:0] valid data THOLD SYMBOLS DESCRIPTION MIN MAX UNIT TPIXCLK TDELAY THOLD Pixel clock frequency VSYNC, HSYNC, VDEN and VD[23:0] output delay from VCLK rising edge VSYNC, HSYNC, VDEN and VD[23:0] output data hold time from VCLK rising edge 5 0 40 15 5 MHz ns ns - 523 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 7.3.6 SD Interface AC Characteristics SD_CLK Twh Twl Tpp SD_CMD SD_DAT (Input) Toh SD_CMD SD_DAT (Output) Tisu Tih Tod(max) SYMBOLS DESCRIPTION MIN. TYP. MAX. UNIT Tpp Twh Twl SD Clock Frequency SD Clock High Time SD Clock Low Time -10 10 ---- 20 --- MHz ns ns Input CMD, DAT (reference to SD_CLK rising edge) Tisu Tih Input Setup Time Input Hold Time 5 5 ----ns ns Output CMD, DAT (reference to SD_CLK falling edge) Tod Output Delay Time 0 -14 ns - 524 - W90P710CD/W90P710CDG 7.3.7 AC97/I2S Interface AC Characteristics TCLK_PERIOD AC97_BCLK TOD AC97_DATAO AC97_SYNC TISU AC97_DATAI TIHD TOH SYMBOLS DESCRIPTION MIN TYP. MAX UNIT TCLK_PERIOD TOD TOH TISU TIHD AC97 Bit Clock Frequency AC97_DATAO and AC97_SYNC output delay from AC97_BCLK rising edge AC97_DATAO and AC97_SYNC output hold time from AC97_BCLK rising edge AC97_DATAI input setup time to AC97_BCLK falling edge AC97_DATAI input hold AC97_BCLK falling edge time from --5 10 5 12.288 ----- -30 ---- MHz ns ns ns ns - 525 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG TBCLK_PERIOD I2S_BCLK Tout_delay I2S_DATAO I2S_RLCLK TDOH TDIS TDIH I2S_DATAI SYMBOLS DESCRIPTION MIN MAX UNIT TBCLK_PERIOD Tout_delay TDOH TDIS TDIH IIS Bit Clock Frequency IIS_DATAO and IIS_RLCLK output delay from IIS_BCLK falling edge IIS_DATAO and IIS_RLCLK data output hold time from IIS_BCLK falling edge IIS_DATAI input setup time to IIS_BCLK rising edge IIS_DATAI input hold time from IIS_BCLK rising edge Note:depend on codec spec. and register setting -0 10 100 30 ---- MHz ns ns ns ns - 526 - W90P710CD/W90P710CDG 7.3.8 Smart Card Interface AC Characteristics SC_RST TR SC_CLK Tclkh SC_DAT Tclkl TF FSC Tclk_rst Tclk_dat SYMBOL DESCRIPTION CONDITION MIN TYP MAX UNIT TR and TF for RST TR and TF for CLK TR and TF for DAT (Transmit) TR and TF for DAT (Receive) FSC Tclkh Tclkl Tclk_dat Tclk_rst Rising and falling time of RST signal Rising and falling time of CLK signal Rising and falling time of DAT signal in transmission mode Rising and falling time of DAT siganl in receive mode Smart card clock frequency Smart card clock high time Smart card clock low time DAT output delay from SC_CLK falling edge RST output delay from SC_CLK falling edge CL = 30pF (Max) CL = 30pF (Max) CL = 30pF (Max) 4 0.8 8% of clock period 0.8 1.2 1 40% 40% 5 5 2.5 50% 50% 20 60% 60% 20 10 us us us MHz clock clock ns ns - 527 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 7.3.9 I2C Interface AC Characteristics THIGH TLOW TSU:STO SCL Thd:STA TSU:DAT TSU:DAT2 SDA Thd:DAT SCL TSU:SAT SDA - 528 - W90P710CD/W90P710CDG SYMBOL DESCRIPTION MIN MAX UNIT THIGH TLOW Thd:STA TSU:DAT I2C Clock high time I2C clock low time Start condition hold time Receive data setup time Transmit data output delay Receive data hold time Transmit data hold time SDA setup time (before STOP condition) Stop condition setup time Restart condition setup time 1 1 1 0.1 1 0 0.5 1 1.5 0.5 0.9 - us us us us us us us us us us THD:DAT TSU:DAT2 TSU:STO TSU:STA 7.3.10 USI Interface AC Characteristics FUSI SFRM Tlead SCLK TCLKH SSPTXD (TX_NEG =1) Tlag TCLKL TOD SSPTXD (TX_NEG =0) TOD - 529 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG FUSI SFRM Tlead SCLK TCLKH TCLKL SSPRXD (RX_NEG =1) Tlag TIH TISU SSPRXD (RX_NEG =0) TIH TISU SYMBOL DESCRIPTION MIN MAX UNIT FUSI TCLKH TCLKL TISU TIH Tlead Tlag TOD USI clock frequency USI clock high time USI clock low time Data input setup time Data input hold time USI enable lead time USI enable lag time USI output data valid time 12.5 0 12.5 12.5 - 20 14 30 MHz ns ns ns ns ns ns ns - 530 - W90P710CD/W90P710CDG 7.3.11 PS2 Interface AC Characteristics T3 1st CLK T4 PS2_CLK 2nd CLK 10th CLK 11th CLK T5 T1 T2 PS2_DATA Start Bit Bit 0 Parity Bit Timing for data received from the auxiliary device T7 T8 2nd CLK 9th CLK 10th CLK 11th CLK PS2_CLK 1st CLK T9 PS2_DATA Bit 0 Parity Bit STOP Bit Timing for data send to the auxiliary device SYMBOL DESCRIPTION MIN. MAX. UNIT T1 T2 T3 T4 T5 T7 T8 T9 Time from DATA transition to falling edge of CLK Time form rising edge of CLK to DATA transition Duration of CLK inactive Duration of clock active Time to auxiliary device inhibit after clock 11 to ensure the auxiliary device does not start another transmission Duration of CLK inactive Duration of CLK active Time to fom inactive to active CLK transition, used to time when the auxiliary device samples DATA 5 5 30 30 0 30 30 30 25 T4-5 50 50 50 50 50 50 us us us us us us us us - 531 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 8. ORDERING INFORMATION PART NUMBER NAME PACKAGE DESCRIPTION W90P710CD W90P710CDG LQFP176 LQFP176 176 Leads, body 22 x 22 x 1.4 mm 176 Leads, body 22 x 22 x 1.4 mm, Lead free package - 532 - W90P710CD/W90P710CDG 9. PACKAGE SPECIFICATIONS 176L LQFP (20X20X1.4 mm footprint 2.0mm) - 533 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG 10. APPENDIX A: W90P710 REGISTERS MAPPING TABLE R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written System Manager Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PDID ARBCON PLLCON CLKSEL PLLCON1 I2SCKCON 0xFFF0_0000 R Product Identifier Register 0xX090.0710 0x0000_0000 0x0000_2F01 0x1FFF_3FX8 0x0001_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFF0_0004 R/W Arbitration Control Register 0xFFF0_0008 R/W PLL Control Register 0xFFF0_000C R/W Clock Select Register 0xFFF0_0010 R/W PLL Control Register 2 0xFFF0_0014 R/W Audio IIS Clock Control Register IRQWAKECON 0xFFF0_0020 R/W IRQ Wakeup Control register IRQWAKEFLAG 0xFFFF_0024 R/W IRQ wakeup Flag Register PMCON USBTxrCON 0xFFF0_0028 R/W Power Manager Control Register 0xFFF0_0030 R/W USB Transceiver Control Register External Bus Interface Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EBICON ROMCON SDCONF0 SDCONF1 SDTIME0 SDTIME1 EXT0CON EXT1CON EXT2CON EXT3CON CKSKEW 0xFFF0_1000 0xFFF0_1004 0xFFF0_1008 0xFFF0_100C 0xFFF0_1010 0xFFF0_1014 0xFFF0_1018 0xFFF0_101C 0xFFF0_1020 0xFFF0_1024 0xFFF0_1F00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W EBI control register ROM/FLASH control register SDRAM bank 0 configuration register SDRAM bank 1 configuration register SDRAM bank 0 timing control register SDRAM bank 1 timing control register External I/O 0 control register External I/O 1 control register External I/O 2 control register External I/O 3 control register Clock skew control register (for testing) 0x0001_0000 0x0000_0XFC 0x0000_0800 0x0000_0800 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_0038 - 534 - W90P710CD/W90P710CDG Cache Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAHCNF CAHCON CAHADR 0xFFF0_2000 0xFFF0_2004 0xFFF0_2008 R/W R/W R/W Cache configuration register Cache control register Cache address register 0x0000_0000 0x0000_0000 0x0000_0000 EMC Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAMCMR CAMEN CAM0M CAM0L CAM1M CAM1L CAM2M CAM2L CAM3M CAM3L CAM4M CAM4L CAM5M CAM5L CAM6M CAM6L CAM7M CAM7L CAM8M CAM8L CAM9M CAM9L CAM10M CAM10L CAM11M CAM11L 0xFFF0_3000 0xFFF0_3004 0xFFF0_3008 0xFFF0_300C 0xFFF0_3010 0xFFF0_3014 0xFFF0_3018 0xFFF0_301C 0xFFF0_3020 0xFFF0_3024 0xFFF0_3028 0xFFF0_302C 0xFFF0_3030 0xFFF0_3034 0xFFF0_3038 0xFFF0_303C 0xFFF0_3040 0xFFF0_3044 0xFFF0_3048 0xFFF0_304C 0xFFF0_3050 0xFFF0_3054 0xFFF0_3058 0xFFF0_305C 0xFFF0_3060 0xFFF0_3064 R/W CAM Command Register R/W CAM Enable Register R/W CAM0 Most Significant Word Register R/W CAM0 Least Significant Word Register R/W CAM1 Most Significant Word Register R/W CAM1 Least Significant Word Register R/W CAM2 Most Significant Word Register R/W CAM2 Least Significant Word Register R/W CAM3 Most Significant Word Register R/W CAM3 Least Significant Word Register R/W CAM4 Most Significant Word Register R/W CAM4 Least Significant Word Register R/W CAM5 Most Significant Word Register R/W CAM5 Least Significant Word Register R/W CAM6 Most Significant Word Register R/W CAM6 Least Significant Word Register R/W CAM7 Most Significant Word Register R/W CAM7 Least Significant Word Register R/W CAM8 Most Significant Word Register R/W CAM8 Least Significant Word Register R/W CAM9 Most Significant Word Register R/W CAM9 Least Significant Word Register R/W CAM10 Most Significant Word Register R/W CAM10 Least Significant Word Register R/W CAM11 Most Significant Word Register R/W CAM11 Least Significant Word Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 535 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG EMC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM12M CAM12L CAM13M CAM13L CAM14M CAM14L CAM15M CAM15L TXDLSA RXDLSA MCMDR MIID MIIDA FFTCR TSDR RSDR DMARFC MIEN MISTA MGSTA MPCNT MRPC MRPCC MREPC DMARFS CTXDSA CTXBSA CRXDSA CRXBSA 0xFFF0_3068 0xFFF0_306C 0xFFF0_3070 0xFFF0_3074 0xFFF0_3078 0xFFF0_307C 0xFFF0_3080 0xFFF0_3084 0xFFF0_3088 0xFFF0_308C 0xFFF0_3090 0xFFF0_3094 0xFFF0_3098 0xFFF0_309C 0xFFF0_30A0 0xFFF0_30A4 0xFFF0_30A8 0xFFF0_30AC 0xFFF0_30B0 0xFFF0_30B4 0xFFF0_30B8 0xFFF0_30BC 0xFFF0_30C0 0xFFF0_30C4 0xFFF0_30C8 0xFFF0_30CC 0xFFF0_30D0 0xFFF0_30D4 0xFFF0_30D8 R/W CAM12 Most Significant Word Register R/W CAM12 Least Significant Word Register R/W CAM13 Most Significant Word Register R/W CAM13 Least Significant Word Register R/W CAM14 Most Significant Word Register R/W CAM14 Least Significant Word Register R/W CAM15 Most Significant Word Register R/W CAM15 Least Significant Word Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 R/W Transmit Descriptor Link List Start Address Register 0xFFFF_FFFC R/W Receive Descriptor Link List Start Address 0xFFFF_FFFC Register 0x0000_0000 0x0000_0000 0x0000_0101 Undefined Undefined 0x0000_0800 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_7FFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 R/W MAC Command Register R/W MII Management Data Register R/W FIFO Threshold Control Register W W Transmit Start Demand Register Receive Start Demand Register R/W MII Management Control and Address Register 0x0090_0000 R/W Maximum Receive Frame Control Register R/W MAC Interrupt Enable Register R/W MAC Interrupt Status Register R/W MAC General Status Register R/W Missed Packet Count Register R R R MAC Receive Pause Count Register MAC Receive Pause Current Count Register MAC Remote Pause Count Register R/W DMA Receive Frame Status Register R R R R Current Transmit Descriptor Start Address 0x0000_0000 Register Current Transmit Buffer Start Address Register 0x0000_0000 Current Receive Descriptor Start Address 0x0000_0000 Register Current Receive Buffer Start Address Register 0x0000_0000 - 536 - W90P710CD/W90P710CDG EMC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RXFSM TXFSM FSM0 FSM1 DCR DMMIR BISTR 0xFFF0_3200 0xFFF0_3204 0xFFF0_3208 0xFFF0_320C 0xFFF0_3210 0xFFF0_3214 0xFFF0_3300 R R R R R Receive Finite State Machine Register Transmit Finite State Machine Register Finite State Machine Register 0 Finite State Machine Register 1 Debug Mode MAC Information Register 0x0081_1101 0x0101_1101 0x0001_0101 0x1100_0100 0x0000_003F 0x0000_0000 0x0000_0000 R/W Debug Configuration Register R/W BIST Mode Register GDMA Registers Map REGISTER ADDRESS R/W DESCRIPTION Channel 0 Control Register Channel 0 Source Base Address Register Channel 0 Destination Base Address Register Channel 0 Transfer Count Register Channel 0 Current Source Address Register Channel 0 Current Destination Address Register RESET VALUE GDMA_CTL0 GDMA_SRCB0 GDMA_DSTB0 GDMA_TCNT0 GDMA_CSRC0 GDMA_CDST0 GDMA_CTCNT 0 GDMA_CTL1 GDMA_SRCB1 GDMA_DSTB1 GDMA_TCNT1 GDMA_CSRC1 GDMA_CDST1 GDMA_CTCNT 1 0xFFF0_4000 0xFFF0_4004 0xFFF0_4008 0xFFF0_400C 0xFFF0_4010 0xFFF0_4014 0xFFF0_4018 0xFFF0_4020 0xFFF0_4024 0xFFF0_4028 0xFFF0_402C 0xFFF0_4030 0xFFF0_4034 0xFFF0_4038 R/W R/W R/W R/W R R R R/W R/W R/W R/W R R R 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Channel 0 Current Transfer Count Register Channel 1 Control Register Channel 1 Source Base Address Register Channel 1 Destination Base Address Register Channel 1 Transfer Count Register Channel 1 Current Source Address Register Channel 1 Current Destination Address Register Channel 1 Current Transfer Count Register - 537 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG USB Host Controller Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE 0x0000_0010 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_2EDF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0628 0x0100_0002 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 OpenHCI Registers HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnbale HcInterruptDisbale HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadEd HcBulkCurrentED HcDoneHeadED HcFmInterval HcFrameRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus [1] HcRhPortStatus [2] 0xFFF0_5000 0xFFF0_5004 0xFFF0_5008 0xFFF0_500C 0xFFF0_5010 0xFFF0_5014 0xFFF0_5018 0xFFF0_501C 0xFFF0_5020 0xFFF0_5024 0xFFF0_5028 0xFFF0_502C 0xFFF0_5030 0xFFF0_5034 0xFFF0_5038 0xFFF0_503C 0xFFF0_5040 0xFFF0_5044 0xFFF0_5048 0xFFF0_504C 0xFFF0_5050 0xFFF0_5054 0xFFF0_5058 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Host Controller Revision Register Host Controller Control Register Host Controller Command Status Register Host Controller Interrupt Status Register Host Controller Interrupt Enable Register Host Controller Interrupt Disable Register Host Controller Communication Area Register Host Controller Period Current ED Register Host Controller Control Head ED Register Host Controller Control Current ED Register Host Controller Bulk Head ED Register Host Controller Bulk Current ED Register Host Controller Done Head Register Host Controller Frame Interval Register Host Controller Frame Remaining Register Host Controller Frame Number Register Host Controller Periodic Start Register Host Controller Low Speed Threshold Register Host Controller Root Hub Descriptor A Register Host Controller Root Hub Descriptor B Register Host Controller Root Hub Status Register Host Controller Root Hub Port Status [1] Host Controller Root Hub Port Status [2] USB Configuration Registers TestModeEnable 0xFFF0_5200 R/W R/W USB Test Mode Enable Register USB Operational Mode Enable Register 0x0XXX_XXXX 0x0000_0000 OperationalModeEnable 0xFFF0_5204 - 538 - W90P710CD/W90P710CDG USB Device Register Map REGISTER USB_CTL VCMD USB_IE USB_IS USB_IC USB_IFSTR USB_ODATA0 USB_ODATA1 USB_ODATA2 USB_ODATA3 USB_IDATA0 USB_IDATA1 USB_IDATA2 USB_IDATA3 USB_SIE USB_ENG USB_CTLS USB_CONFD EPA_INFO EPA_CTL EPA_IE EPA_IC EPA_IS EPA_ADDR EPA_LENTH EPB_INFO EPB_CTL EPB_IE EPB_IC EPB_IS EPB_ADDR EPB_LENTH OFFSET 0xFFF0_6000 0xFFF0_6004 0xFFF0_6008 0xFFF0_600C 0xFFF0_6010 0xFFF0_6014 0xFFF0_6018 0xFFF0_601C 0xFFF0_6020 0xFFF0_6024 0xFFF0_6028 0xFFF0_602C 0xFFF0_6030 0xFFF0_6034 0xFFF0_6038 0xFFF0_603C 0xFFF0_6040 0xFFF0_6044 0xFFF0_6048 0xFFF0_604C 0xFFF0_6050 0xFFF0_6054 0xFFF0_6058 0xFFF0_605C 0xFFF0_6060 0xFFF0_6064 0xFFF0_6068 0xFFF0_606C 0xFFF0_6070 0xFFF0_6074 0xFFF0_6078 0xFFF0_607C R/W R/W R/W R/W R R/W R/W R R R R R/W R/W R/W R/W R R/W R R/W R/W R/W R/W W R R/W R/W R/W R/W R/W W R R/W R/W DESCRIPTION USB control register USB class or vendor command register USB interrupt enable register USB interrupt status register USB interrupt status clear register USB interface and string register USB control transfer-out port 0 register USB control transfer-out port 1 register USB control transfer-out port 2 register USB control transfer-out port 3 register USB transfer-in data port0 register USB control transfer-in data port 1 USB control transfer-in data port 2 USB control transfer-in data port 3 USB SIE status Register USB Engine Register USB control transfer status register USB Configured Value register USB endpoint A information register USB endpoint A control register USB endpoint A Interrupt Enable register USB endpoint A interrupt clear register USB endpoint A interrupt status register USB endpoint A address register USB endpoint A transfer length register USB endpoint B information register USB endpoint B control register USB endpoint B Interrupt Enable register USB endpoint B interrupt clear register USB endpoint B interrupt status register USB endpoint B address register USB endpoint B transfer length register RESET VALUE 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 539 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG USB Device Register Map, continued REGISTER EPC_INFO EPC_CTL EPC_IE EPC_IC EPC_IS EPC_ADDR EPC_LENTH EPA_XFER EPA_PKT EPB_XFER EPB_PKT EPC_XFER EPC_PKT OFFSET 0xFFF0_6080 0xFFF0_6084 0xFFF0_6 088 0xFFF0_608C 0xFFF0_6090 0xFFF0_6094 0xFFF0_6098 0xFFF0_609C 0xFFF0_60A0 0xFFF0_60A4 0xFFF0_60A8 0xFFF0_60AC 0xFFF0_60B0 R/W R/W R/W R/W W R R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION USB endpoint C information register USB endpoint C control register USB endpoint C Interrupt Enable register USB endpoint C interrupt clear register USB endpoint C interrupt status register USB endpoint C address register USB endpoint C transfer length register RESET VALUE 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 USB endpoint A remain transfer length register 0x0000_0000 USB endpoint A remain packet length register 0x0000_0000 USB endpoint B remain transfer length register 0x0000_0000 USB endpoint B remain packet length register 0x0000_0000 USB endpoint C remain transfer length register 0x0000_0000 USB endpoint C remain packet length register 0x0000_0000 SD Control Register Map REGISTER OFFSET R/W DESCRIPTION RESET VALUE SDGCR SDDSA SDBCR SDGIER SDGISR SDBIST SDCR SDHINI SDIER SDISR SDAUG SDRSP0 SDRSP1 SDBLEN 0xFFF0_7000 0xFFF0_7004 0xFFF0_7008 0xFFF0_700C 0xFFF0_7010 0xFFF0_7014 0xFFF0_7300 0xFFF0_7304 0xFFF0_7308 0xFFF0_730C 0xFFF0_7310 0xFFF0_7314 0xFFF0_7318 0xFFF0_731C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W SD Global Control Register SD DMA Register Transfer Starting Address 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0018 0x0000_0000 0x0000_00XX 0x0000_0000 0xXXXX_XXXX 0x0000_XXXX 0x0000_0000 SD DMA Byte Count Register SD Global Interrupt Enable Register SD Global Interrupt Status Register SD BIST Register SD Control Register SD Host Initial Register SD Interrupt Enable Register SD Interrupt Status Register SD Command Argument Register SD Receive Response Token Register 0 SD Receive Response Token Register 1 SD Block Length Register - 540 - W90P710CD/W90P710CDG SD Control Register Map, continued REGISTER OFFSET R/W DESCRIPTION RESET VALUE FB0_0 ….. FB0_127 FB1_0 ….. FB1_127 0xFFF0_7400 ….. 0xFFF0_75FC 0xFFF0_7800 ... 0xFFF0_79FC R/W Flash Buffer 0 Undefined R/W Flash Buffer 1 Undefined LCDC Control Register Map REGISTER LCD Controller LCDCON LCD Interrupt Control LCDINTENB LCDINTS LCDINTC LCD Pre-processing OSDUPSCF VDUPSCF OSDDNSCF VDDNSCF LCD FIFO Control FIFOCON FIFOSTATUS FIFO1PRM FIFO2PRM FIFO1SADDR FIFO2SADDR FIFO1DREQCNT FIFO2DREQCNT FIFO1CURADR FIFO2CURADR 0xFFF0_8020 0xFFF0_8024 0xFFF0_8028 0xFFF0_802C 0xFFF0_8030 0xFFF0_8034 0xFFF0_8038 0xFFF0_803C 0xFFF0_8040 0xFFF0_8044 R/W R R/W R/W R/W R/W R/W R/W R R R/W R/W FIFOs control FIFOs status FIFO1 parameters FIFO2 parameters FIFO1 start address FIFO2 start address FIFO1 data request count FIFO2 data request count FIFO1 current access address FIFO2 current access address FIFO1 real column count FIFO2 real column count 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFF0_8010 0xFFF0_8014 0xFFF0_8018 0xFFF0_801C R/W R/W R/W R/W OSD Horizontal/Vertical up-scaling factor Video Horizontal/Vertical up-scaling factor OSD Horizontal/Vertical down-scaling factor Video Horizontal/Vertical down-scaling factor 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFF0_8004 0xFFF0_8008 0xFFF0_800C R/W R W LCD Interrupt Enable LCD Interrupt Status LCD Interrupt Clear 0x0000_0000 0x0000_0000 0x0000_0000 0XFFF0_8000 R/W LCD Control 0x0000_0000 ADDRESS R/W DESCRIPTION RESET VALUE FIFO1RELACOLCNT 0xFFF0_8048 FIFO2RELACOLCNT 0xFFF0_804C - 541 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG LCDC Control Register Map, continued. REGISTER Color Generation VDLUTENTRY1 VDLUTENTRY2 VDLUTENTRY3 VDLUTENTRY4 ADDRESS 0xFFF0_8050 0xFFF0_8054 0xFFF0_8058 0xFFF0_805C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION Video lookup table entry index 1 Video lookup table entry index 2 Video lookup table entry index 3 Video lookup table entry index 4 OSD lookup table entry index 1 OSD lookup table entry index 2 OSD lookup table entry index 3 OSD lookup table entry index 4 Gray level dithered data duty pattern 1 Gray level dithered data duty pattern 2 Gray level dithered data duty pattern 3 Gray level dithered data duty pattern 4 Gray level dithered data duty pattern 5 Gray level dithered data duty pattern 6 Gray level dithered data duty pattern 7 Dummy Display Color Pattern Video Window Starting Coordinate Video Window Ending Coordinate OSD Window Starting Coordinate OSD Window Ending Coordinate OSD Overlay Control OSD Overlay Color-Key Pattern OSD Overlay Color-Key Mask LCD Timing Control 1 LCD Timing Control 2 LCD Timing Control 3 LCD Timing Control 4 LCD Timing Control 5 RESET VALUE 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0101_0001 0x1111_0841 0x4949_2491 0x5555_52A5 0xB6B6_B556 0xEEEE_DB6E 0xEFEF_EFBE 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 OSDLUTENTRY1 0xFFF0_8060 OSDLUTENTRY2 0xFFF0_8064 OSDLUTENTRY3 0xFFF0_8068 OSDLUTENTRY4 0xFFF0_806C DITHP1 DITHP2 DITHP3 DITHP4 DITHP5 DITHP6 DITHP7 DDISPCP VWINS VWINE OSDWINS OSDWINE OSDOVCN OSDCKP OSDCKM LCDTCON1 LCDTCON2 LCDTCON3 LCDTCON4 LCDTCON5 0xFFF0_8070 0xFFF0_8074 0xFFF0_8078 0xFFF0_807C 0xFFF0_8080 0xFFF0_8084 0xFFF0_8088 0xFFF0_8090 0xFFF0_8094 0xFFF0_8098 0xFFF0_809C 0xFFF0_80A0 0xFFF0_80A4 0xFFF0_80A8 0xFFF0_80AC 0xFFF0_80B0 0xFFF0_80B4 0xFFF0_80B8 0xFFF0_80BC 0xFFF0_80C0 LCD Post-processing LCD Timing Generation LCDTCON6 BIST 0xFFF0_80C4 0xFFF0_80D0 R R/W LCD Timing Control 6 0x0000_0000 0x0000_0000 Lookup Table SRAM Build In Self Test - 542 - W90P710CD/W90P710CDG LCDC Control Register Map, continued. REGISTER ADDRESS 0xFFF0_0100 … 0xFFF0_84FF R/W DESCRIPTION RESET VALUE Lookup Table SRAM R/W Look-Up Table RAM 0xXXXX_XXXX Audio Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_CON ACTL_RESET ACTL_RDSTB 0xFFF0_9000 R/W 0xFFF0_9004 R/W 0xFFF0_9008 R/W Audio controller control register Sub block reset control register DMA destination base address register for record DMA destination length register for record DMA destination current address register for record Record status register DMA destination base address register for play DMA destination length register for play DMA destination current address register for play Play status register IIS control register AC-link control register AC-link out slot 0 AC-link out slot 1 AC-link out slot 2 AC-link in slot 0 AC-link in slot 1 AC-link in slot 2 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0004 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0080 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 ACTL_RDST_LENGTH 0xFFF0_900C R/W ACTL_RDSTC ACTL_RSR ACTL_PDSTB 0xFFF0_9010 R 0xFFF0_9014 R/W 0xFFF0_9018 R/W ACTL_PDST_LENGTH 0xFFF0_901C R/W ACTL_PDSTC ACTL_PSR ACTL_IISCON ACTL_ACCON ACTL_ACOS0 ACTL_ACOS1 ACTL_ACOS2 ACTL_ACIS0 ACTL_ACIS1 ACTL_ACIS2 0xFFF0_9020 R 0xFFF0_9024 R/W 0xFFF0_9028 R/W 0xFFF0_902C R/W 0xFFF0_9030 R/W 0xFFF0_9034 R/W 0xFFF0_9038 R/W 0xFFF0_903C R 0xFFF0_9040 R 0xFFF0_9044 R Cache Controller Test Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CTEST0 CTEST1 0xFFF6_0000 R/W 0xFFF6_0004 R Cache test register 0 Cache test register 1 0x0000_0000 0x0000_0000 - 543 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG UART0 Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART0_RBR UART0_THR UART0_IER UART0_DLL UART0_DLM UART0_IIR UART0_FCR UART0_LCR UART0_LSR UART0_TOR 0xFFF8_0000 0xFFF8_0000 0xFFF8_0004 0xFFF8_0000 0xFFF8_0004 0xFFF8_0008 0xFFF8_0008 0xFFF8_000C 0xFFF8_0014 0xFFF8_001C R W R/W R/W R/W R W R/W R R Receive Buffer Register (DLAB = 0) Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) Interrupt Identification Register FIFO Control Register Line Control Register Line Status Register Time Out Register Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 0x6060_6060 0x0000_0000 High Speed UART1 Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART1_RBR UART1_THR UART1_IER UART1_DLL UART1_DLM UART1_IIR UART1_FCR UART1_LCR UART1_MCR UART1_LSR UART1_MSR UART1_TOR 0xFFF8_0100 0xFFF8_0100 0xFFF8_0104 0xFFF8_0100 0xFFF8_0104 0xFFF8_0108 0xFFF8_0108 0xFFF8_010C 0xFFF8_0110 0xFFF8_0114 0xFFF8_0118 0xFFF8_011C R W R/W R/W R/W R W R/W R/W R R R R/W Receive Buffer Register (DLAB = 0) Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register MODEM Status Register Time Out Register UART1 Bluetooth Control Register Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 0x0000_0000 0x6060.6060 0x0000_0000 0x0000_0000 0x0000_0000 UART1_UBCR 0xFFF8_0120 - 544 - W90P710CD/W90P710CDG UART2 Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART2_RBR 0xFFF8_0200 UART2_THR 0xFFF8_0200 UART2_IER R W Receive Buffer Register (DLAB = 0) Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register MODEM Status Register Time Out Register IrDA Control Register Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 0x0000_0000 0x6060_6060 0x0000_0000 0x0000_0000 0x0000_0040 0xFFF8_0204 R/W UART2_DLL 0xFFF8_0200 R/W UART2_DLM 0xFFF8_0204 R/W UART2_IIR 0xFFF8_0208 R W UART2_FCR 0xFFF8_0208 UART2_LCR 0xFFF8_020C R/W UART2_MCR 0xFFF8_0210 R/W UART2_LSR 0xFFF8_0214 UART2_MSR 0xFFF8_0218 UART2_TOR 0xFFF8_021C R R R UART2_IRCR 0xFFF8_0220 R/W UART3 Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART3_RBR 0xFFF8_0300 UART3_THR 0xFFF8_0300 UART3_IER R W Receive Buffer Register (DLAB = 0) Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register MODEM Status Register Time Out Register Undefined Undefined 0x0000_0000 0x0000_0000 0x0000_0000 0x8181_8181 Undefined 0x0000_0000 0x0000_0000 0x6060_6060 0x0000_0000 0x0000_0000 0xFFF8_0304 R/W UART3_DLL 0xFFF8_0300 R/W UART3_DLM 0xFFF8_0304 R/W UART3_IIR 0xFFF8_0308 R W UART3_FCR 0xFFF8_0308 UART3_LCR 0xFFF8_030C R/W UART3_MCR 0xFFF8_0310 R/W UART3_LSR 0xFFF8_0314 UART3_MSR 0xFFF8_0318 UART3_TOR 0xFFF8_031C R R R - 545 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Timer Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TCR0 TCR1 TICR0 TICR1 TDR0 TDR1 TISR WTCR 0xFFF8_1000 0xFFF8_1004 0xFFF8_1008 0xFFF8_1010 0xFFF8_1014 0xFFF8_1018 R/W R/W R/W R R R/C Timer Control Register 0 Timer Control Register 1 Timer Initial Control Register 0 Timer Initial Control Register 1 Timer Data Register 0 Timer Data Register 1 Timer Interrupt Status Register Watchdog Timer Control Register 0x0000_0005 0x0000_0005 0x0000_00FF 0x0000_00FF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFF8_100C R/W 0xFFF8_101C R/W AIC Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR1 AIC_SCR2 AIC_SCR3 AIC_SCR4 AIC_SCR5 AIC_SCR6 AIC_SCR7 AIC_SCR8 AIC_SCR9 AIC_SCR10 AIC_SCR11 AIC_SCR12 AIC_SCR13 AIC_SCR14 AIC_SCR15 0xFFF8_2004 0xFFF8_2008 0xFFF8_2010 0xFFF8_2014 0xFFF8_2018 0xFFF8_2020 0xFFF8_2024 0xFFF8_2028 0xFFF8_2030 0xFFF8_2034 0xFFF8_2038 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Source Control Register 1 Source Control Register 2 Source Control Register 3 Source Control Register 4 Source Control Register 5 Source Control Register 6 Source Control Register 7 Source Control Register 8 Source Control Register 9 Source Control Register 10 Source Control Register 11 Source Control Register 12 Source Control Register 13 Source Control Register 14 Source Control Register 15 Source Control Register 16 Source Control Register 17 Source Control Register 18 Source Control Register 19 Source Control Register 20 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0047 0x0000_0047 0xFFF8_200C R/W 0xFFF8_201C R/W 0xFFF8_202C R/W 0xFFF8_203C R/W AIC_SCR16 0xFFF8_2040 R/W AIC_SCR17 0xFFF8_2044 R/W AIC_SCR18 0xFFF8_2048 R/W AIC_SCR19 0xFFF8_204C R/W AIC_SCR20 0xFFF8_2050 R/W - 546 - W90P710CD/W90P710CDG AIC Control Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR21 0xFFF8_2054 R/W AIC_SCR22 0xFFF8_2058 R/W AIC_SCR23 0xFFF8_205C R/W AIC_SCR24 0xFFF8_2060 R/W AIC_SCR25 0xFFF8_2064 R/W AIC_SCR26 0xFFF8_2068 R/W AIC_SCR27 0xFFF8_206C R/W AIC_SCR28 0xFFF8_2070 R/W AIC_SCR29 0xFFF8_2074 R/W AIC_SCR30 0xFFF8_2078 R/W AIC_SCR31 0xFFF8_207C R/W AIC_IRSR AIC_IASR AIC_ISR AIC_IPER AIC_ISNR AIC_IMR AIC_OISR AIC_MECR AIC_MDCR AIC_SSCR AIC_SCCR AIC_EOSCR Source Control Register 21 Source Control Register 22 Source Control Register 23 Source Control Register 24 Source Control Register 25 Source Control Register 26 Source Control Register 27 Source Control Register 28 Source Control Register 29 Source Control Register 30 Source Control Register 31 Interrupt Raw Status Register Interrupt Active Status Register Interrupt Status Register Interrupt Priority Encoding Register Interrupt Source Number Register Interrupt Mask Register Output Interrupt Status Register Mask Enable Command Register Mask Disable Command Register Source Set Command Register Source Clear Command Register End of Service Command Register ICE/Debug mode Register 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0047 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Undefined Undefined Undefined Undefined Undefined Undefined 0xFFF8_2100 0xFFF8_2104 0xFFF8_2108 0xFFF8_210C 0xFFF8_2110 0xFFF8_2114 0xFFF8_2118 0xFFF8_2120 0xFFF8_2124 0xFFF8_2128 0xFFF8_212C 0xFFF8_2130 0xFFF8_2200 R R R R R R R W W W W W W AIC_TEST - 547 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG GPIO Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG0 GPIO_DIR0 GPIO_DATAIN0 GPIO_CFG1 GPIO_DIR1 GPIO_DATAIN1 GPIO_CFG2 GPIO_DIR2 GPIO_DATAIN2 GPIO_CFG3 GPIO_DIR3 GPIO_DATAIN3 GPIO_CFG4 GPIO_DIR4 GPIO_DATAIN4 GPIO_CFG5 GPIO_DIR5 GPIO_DATAIN5 GPIO_CFG6 GPIO_DIR6 GPIO_DATAIN6 GPIO_XICFG GPIO_XISTATUS 0xFFF8_3000 R/W 0xFFF8_3004 R/W 0xFFF8_300C R 0xFFF8_3010 R/W 0xFFF8_3014 R/W 0xFFF8_301C R 0xFFF8_3020 R/W 0xFFF8_3024 R/W 0xFFF8_302C R 0xFFF8_3030 R/W 0xFFF8_3034 R/W 0xFFF8_303C R 0xFFF8_3040 R/W 0xFFF8_3044 R/W 0xFFF8_304C R 0xFFF8_3050 R/W 0xFFF8_3054 R/W 0xFFF8_305C R 0xFFF8_3060 R/W 0xFFF8_3064 R/W 0xFFF8_306C R 0xFFF8_3074 R/W 0xFFF8_3078 R/W GPIO port0 configuration register GPIO port0 direction control register GPIO port0 data output register GPIO port0 data input register GPIO port1 configuration register GPIO port1 direction control register GPIO port1 data output register GPIO port1 data input register GPIO port2 configuration register GPIO port2 direction control register GPIO port2 data output register GPIO port2 data input register GPIO port3 configuration register GPIO port3 direction control register GPIO port3 data output register GPIO port3 data input register GPIO port4 configuration register GPIO port4 direction control register GPIO port4 data output register GPIO port4 data input register GPIO port5 configuration register GPIO port5 direction control register GPIO port5 data output register GPIO port5 data input register GPIO port6 configuration register GPIO port6 direction control register GPIO port6 data output register GPIO port6 data input register GPIO input debounce control register Extend Interrupt Configure Register Extend Interrupt Status Register 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_5555 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0015_5555 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0x0000_0000 0x0000_0000 0xXXXX_XXXX 0x0000_0000 0xXXXX_XXX0 0xXXXX_XXX0 GPIO_DATAOUT0 0xFFF8_3008 R/W GPIO_DATAOUT1 0xFFF8_3018 R/W GPIO_DATAOUT2 0xFFF8_3028 R/W GPIO_DATAOUT3 0xFFF8_3038 R/W GPIO_DATAOUT4 0xFFF8_3048 R/W GPIO_DATAOUT5 0xFFF8_3058 R/W GPIO_DATAOUT6 0xFFF8_3068 R/W GPIO_DBNCECON 0xFFF8_3070 R/W - 548 - W90P710CD/W90P710CDG RTC Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_INIR RTC_AER RTC_FCR RTC_TLR RTC_CLR RTC_TSSR RTC_DWR RTC_TAR RTC_CAR RTC_LIR RTC_RIER RTC_RIIR RTC_TTR 0xFFF8_4000 R/W RTC Initiation Register 0xFFF8_4004 R/W RTC Access Enable Register 0xFFF8_4008 R/W RTC Frequency Compensation Register 0xFFF8_400C R/W Time Loading Register 0xFFF8_4010 R/W Calendar Loading Register 0xFFF8_4014 R/W Time Scale Selection Register 0xFFF8_4018 R/W Day of the Week Register 0xFFF8_401C R/W Time Alarm Register 0xFFF8_4020 R/W Calendar Alarm Register 0xFFF8_4024 R Leap year Indicator Register 0xFFF8_4028 R/W RTC Interrupt Enable Register 0xFFF8_402C R/C RTC Interrupt Indicator Register 0xFFF8_4030 R/W RTC Tick Time Register 0x0000_0000 0x0000_0700 0x0000_0000 0x0005_0101 0x0000_0001 0x0000_0006 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Smart card Host Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE Smartcard Host Interface 0 SCHI_RBR0 SCHI_TBR0 SCHI_IER0 SCHI_ISR0 SCHI_SCFR0 SCHI_SCCR0 SCHI_CBR0 SCHI_SCSR0 SCHI_GTR0 SCHI_ECR0 SCHI_TMR0 SCHI_TOC0 0xFFF8_5000(BDLAB=0) 0xFFF8_5000 (BDLAB=0) 0xFFF8_5008 (BDLAB=0) 0xFFF8_5008 (BDLAB=0) 0xFFF8_500C 0xFFF8_5010 0xFFF8_5014 0xFFF8_5018 0xFFF8_501C 0xFFF8_5020 0xFFF8_5028 R Receiver Buffer Register Undefined Undefined 0x0000_0080 0x0000_00C1 0x0000_0000 0x0000_0010 0x0000_000C 0x0000_0060 0x0000_0001 0x0000_0052 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 W Transmitter Buffer Register R Interrupt Status Register 0xFFF8_5004 (BDLAB=0) R/W Interrupt Enable Register W Smart card FIFO Control Register R/W Smart card Control Register R/W Clock Base Register R Smart Card Status Register R/W Guard Rime Register R/W Extended Control Register R/W Test Mode Register R/W Time out Configuration Register R/W Time out Initial Register 0 R/W Time out Initial Register 1 R/W Time out Initial Register 2 SCHI_TOIR0_0 0xFFF8_502C SCHI_TOIR1_0 0xFFF8_5030 SCHI_TOIR2_0 0xFFF8_5034 - 549 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG Smart card Host Control Register Map, continued. REGISTER ADDRESS R/W DESCRIPTION RESET VALUE Smartcard Host Interface 0 SCHI_TOD0_0 SCHI_TOD1_0 SCHI_TOD2_0 SCHI_BTOR_0 SCHI_BLL_0 SCHI_BLH_0 SCHI_ID_0 SCHI_RBR1 SCHI_TBR1 SCHI_IER1 SCHI_ISR1 SCHI_SCFR1 SCHI_SCCR1 SCHI_CBR1 SCHI_SCSR1 SCHI_GTR1 SCHI_ECR1 SCHI_TMR1 SCHI_TOC1 0xFFF8_5038 0xFFF8_503C 0xFFF8_5040 0xFFF8_5044 R R R Time out Data Register 0 Time out Data Register 1 Time out Data Register 2 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_0000 R/W Buffer Time out Data Register 0xFFF8_5000 (BDLAB=1) R/W 0xFFF8_5004 (BDLAB=1) R/W 0xFFF8_5008 (BDLAB=1) 0xFFF8_5800 (BDLAB=0) 0xFFF8_5800 (BDLAB=0) 0xFFF8_5808 (BDLAB=0) 0xFFF8_5808 (BDLAB=0) 0xFFF8_580C 0xFFF8_5810 0xFFF8_5814 0xFFF8_5818 0xFFF8_581C 0xFFF8_5820 0xFFF8_5828 R R Baud Rate Divisor Latch Lower 0x0000_001F Byte Register Baud Rate Divisor Latch Higher 0x0000_0000 Byte Register Smart Card ID Number Register Receiver Buffer Register 0x0000_0070 Undefined Undefined 0x0000_0080 0x0000_00C1 0x0000_0000 0x0000_0010 0x0000_000C 0x0000_0060 0x0000_0001 0x0000_0052 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_00FF 0x0000_00FF 0x0000_00FF 0x0000_0000 Smartcard Host Interface 1 W Transmitter Buffer Register R Interrupt Status Register 0xFFF8_5804 (BDLAB=0) R/W Interrupt Enable Register W Smart card FIFO Control Register R/W Smart card Control Register R/W Clock Base Register R Smart Card Status Register R/W Guard Rime Register R/W Extended Control Register R/W Test Mode Register R/W Time out Configuration Register R/W Time out Initial Register 0 R/W Time out Initial Register 1 R/W Time out Initial Register 2 R R R Time out Data Register 0 Time out Data Register 1 Time out Data Register 2 SCHI_TOIR0_1 0xFFF8_582C SCHI_TOIR1_1 0xFFF8_5830 SCHI_TOIR2_1 0xFFF8_5834 SCHI_TOD0_1 SCHI_TOD1_1 SCHI_TOD2_1 SCHI_BTOR1 SCHI_BLL1 SCHI_BLH1 SCHI_ID1 0xFFF8_5838 0xFFF8_583C 0xFFF8_5840 0xFFF8_5844 R/W Buffer Time out Data Register 0xFFF8_5800 (BDLAB=1) R/W 0xFFF8_5804 (BDLAB=1) R/W 0xFFF8_5808 (BDLAB=1) R Baud Rate Divisor Latch Lower 0x0000_001F Byte Register Baud Rate Divisor Latch Higher 0x0000_0000 Byte Register Smart Card ID Number Register 0x0000_0070 - 550 - W90P710CD/W90P710CDG I2C Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C Interface 0 I2C_CSR0 I2C_DIVIDER0 I2C_CMDR0 I2C_SWR0 I2C_RxR0 I2C_TxR0 I2C_CSR1 I2C_DIVIDER1 I2C_CMDR1 I2C_SWR1 I2C_RxR1 I2C_TxR1 0xFFF8_6000 0xFFF8_6004 0xFFF8_6008 0xFFF8_600C 0xFFF8_6010 0xFFF8_6014 0xFFF8_6000 0xFFF8_6004 0xFFF8_6008 0xFFF8_600C 0xFFF8_6010 0xFFF8_6014 R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W I2C0 Control and Status Register I2C0 Clock Prescale Register I2C0 Command Register I2C0 Software Mode Control Register I2C0 Data Receive Register I2C0 Data Transmit Register I2C Interface 1 I2C1 Control and Status Register I2C1 Clock Prescale Register I2C1 Command Register I2C1 Software Mode Control Register I2C1 Data Receive Register I2C1 Data Transmit Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_003F 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_003F 0x0000_0000 0x0000_0000 USI Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_CNTRL USI_DIVIDER USI_SSR Reserved USI_Rx0 USI_Rx1 USI_Rx2 USI_Rx3 USI_Tx0 USI_Tx1 USI_Tx2 USI_Tx3 0xFFF8_6200 R/W 0xFFF8_6204 R/W 0xFFF8_6208 R/W 0xFFF8_620C 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C 0xFFF8_6210 0xFFF8_6214 0xFFF8_6218 0xFFF8_621C N/A R R R R W W W W Control and Status Register Clock Divider Register Slave Select Register Reserved Data Receive Register 0 Data Receive Register 1 Data Receive Register 2 Data Receive Register 3 Data Transmit Register 0 Data Transmit Register 1 Data Transmit Register 2 Data Transmit Register 3 0x0000_0004 0x0000_0000 0x0000_0000 N/A 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 551 - Publication Release Date: September 19, 2006 Revision B2 W90P710CD/W90P710CDG PWM Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PPR PWM_CSR PWM_PCR PWM_CNR0 PWM_CMR0 PWM_PDR0 PWM_CNR1 PWM_CMR1 PWM_PDR1 PWM_CNR2 PWM_CMR2 PWM_PDR2 PWM_CNR3 PWM_CMR3 PWM_PDR3 PWM_PIER PWM_PIIR 0xFFF8_7000 0xFFF8_7004 0xFFF8_7008 0xFFF8_700C 0xFFF8_7010 0xFFF8_7014 0xFFF8_7018 0xFFF8_701C 0xFFF8_7020 0xFFF8_7024 0xFFF8_7028 0xFFF8_702C 0xFFF8_7030 0xFFF8_7034 0xFFF8_7038 0xFFF8_703C 0xFFF8_7040 R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/C PWM Prescaler Register PWM Clock Select Register PWM Control Register PWM Counter Register 0 PWM Comparator Register 0 PWM Data Register 0 PWM Counter Register 1 PWM Comparator Register 1 PWM Data Register 1 PWM Counter Register 2 PWM Comparator 2 PWM Data Register 2 PWM Counter Register 3 PWM Comparator Register 3 PWM Data Register 3 PWM Interrupt Enable Register PWM Interrupt Indication Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 KPI Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE KPICONF 0xFFF8_8000 R/W Keypad controller configuration Register Keypad controller low power configuration register Keypad controller status register 0x0000_0000 KPI3KCONF 0xFFF8_8004 R/W Keypad controller 3-keys configuration register 0x0000_0000 KPILPCONF 0xFFF8_8008 R/W KPISTATUS 0xFFF8_800C R/O PS2 Control Register Map REGISTER ADDRESS R/W/C DESCRIPTION RESET VALUE 0x0000_0000 0x0000_0000 PS2CMD PS2STS 0xFFF8_9000 0xFFF8_9004 R/W R/W RO RO PS2 Host Controller Command Register PS2 Host Controller Status Register PS2 Host Controller RX Scan Code Register PS2 Host Controller RX ASCII Code Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 PS2SCANCODE 0xFFF8_9008 PS2ASCII 0xFFF8_900C - 552 - W90P710CD/W90P710CDG Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. - 553 - Publication Release Date: September 19, 2006 Revision B2