W921E840A

W921E840A/W921C840 4-BIT MICROCONTROLLER Table of Contents1. GENERAL DESCRIPTION .........................................................................................................................3 2. FEATURES.................................................................................................................................................3 3. PIN CONFIGURATIONS.............................................................................................................................6 40-pin DIP..................................................................................................................................................6 48-pin QFP.................................................................................................................................................7 4. PIN DESCRIPTION.....................................................................................................................................9 5. BLOCK DIAGRAM ....................................................................................................................................10 6. FUNCTIONAL DESCRIPTION .................................................................................................................11 6.1 ROM Memory Map ...........................................................................................................................11 6.2 RAM Memory Map............................................................................................................................12 6.2.1 Special Control Register Area .................................................................................................12 6.2.2 Stack Register Area ................................................................................................................14 6.2.3 Working Register Area............................................................................................................15 6.3 Internal Oscillator Circuit ...................................................................................................................15 6.4 Initial State ........................................................................................................................................16 6.5 Input/Output ......................................................................................................................................17 6.5.1 Normal/Special Function Selection of I/O ................................................................................17 6.5.2 Pull High and Open Drain Control of I/O .................................................................................19 6.6 Serial Port .........................................................................................................................................21 6.7 DTMF Generator...............................................................................................................................24 6.8 Beep Tone Generator .......................................................................................................................25 6.9 D/A Converter ...................................................................................................................................26 6.10 Comparator.....................................................................................................................................27 6.11 Timer/Counter .................................................................................................................................28 6.11.1 TM0......................................................................................................................................28 6.11.2 TM1......................................................................................................................................30 6.11.3 TM2......................................................................................................................................32 6.11.4 TM3......................................................................................................................................34 6.11.5 Arbitrary Waveform Generator ..............................................................................................35 -1- Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 6.12 Interrupt...........................................................................................................................................35 6.12.1 Interrupt Control Register......................................................................................................35 6.12.2 Interrupt Enable Flag ............................................................................................................36 6.13 Operating Mode ..............................................................................................................................37 6.13.1 Normal Mode........................................................................................................................37 6.13.2 Hold Mode ............................................................................................................................37 6.13.3 Stop Mode ............................................................................................................................39 6.14 Initial Condition Register of EPROM Program Method ....................................................................41 6.15 Reset ..............................................................................................................................................41 6.15.1 Reset by RESET ...................................................................................................................41 6.15.2 Reset by Watch Dog Timer ...................................................................................................41 7. ABSOLUTION MAXIMUM RATINGS .......................................................................................................42 8. ELECTRICAL CHARACTERISTICS.........................................................................................................42 8.1 DC Characteristics ............................................................................................................................42 8.2 AC Characteristics ............................................................................................................................45 9. ADDRESSING MODE ..............................................................................................................................47 9.1 ROM Addressing Mode.....................................................................................................................47 9.1.1 Indirect Call Addressing Mode: (1 word/2 cycles) ....................................................................47 9.1.2 Long Call/Jump Addressing Mode: (2 words/2 cycles).............................................................47 9.2 RAM Addressing Mode .....................................................................................................................47 9.2.1 Direct Addressing Mode: (2 words/2 cycles) ............................................................................48 9.2.2 Indirect Addressing Mode: (1 word/1 cycle) .............................................................................48 9.2.3 Working Register Addressing Mode: (1 word/1 cycle)..............................................................48 9.3 Look-up Table Addressing Mode (1 word/2 cycles) ..........................................................................48 10. INSTRUCTION CODE MAP ...................................................................................................................50 11. INSTRUCTION SET SUMMARY ............................................................................................................53 12. PACKAGE DIMENSIONS.......................................................................................................................57 40-pin DIP................................................................................................................................................57 48-pin QFP...............................................................................................................................................57 -2- W921E840A/W921C840 1. GENERAL DESCRIPTION The W921E840A/W921C840 is single-chip CMOS 4-bit microcontroller that is subset of W921E880A/W921C880. They features four multi-function timers, one channel DTMF generator, an 8-bit D/A converter circuit, ten interrupt sources, 48-level subroutine nesting, and built in four by one channel comparator circuit. Two power down modes, hold and stop mode, reduce power dissipation. The excellent memory structure, 8K super EPROM in W921E840A and 8K mask ROM in W921C840 for program code and 512 x 4 bit RAM minimize the need for external memory devices. The W921E840A/W921C840 are powerful microcontroller for wide range consuming applications, requiring few external components, which is especially suited for telecommunication design. 2. FEATURES Operating Voltage • 2.8 to 5.5V operating voltage for W921E840A EPROM Type • 2.4 to 5.5V operating voltage for W921C840 Mask ROM Type Operating Frequency • Crystal or RC for main system clock − Crystal for 400 K, 800 K, 2 M, 3.58 M, 4 MHz − RC up to 4 MHz Memory • • 8K × 10-bit ROM (super EPROM) 512 × 4-bit RAM − 64 × 4-bit special registers − 16 × 4-bit working registers − 128 × 4-bit general registers − 304 × 4-bit multi-purpose registers Stack • 8-bit stack pointer I/O Pins • 20 bidirectional and individually controllable I/O lines − P2 Port: P2.0 to P2.3 large sink current pins and open drain option − P3 Port: P3.0 to P3.3 multi-function I/O − P4 Port: P4.0 to P4.3 open drain and pull high resistor option, multi-function I/O − P5 Port: P5.0 to P5.3 multi-function I/O − P6 Port: P6.0 to P6.3 open drain and pull high resistor option, multi-function I/O • 14 bidirectional I/O lines − PA Port: PA.0 to PA.3 open drain and pull high resistor option Publication Release Date: July 1999 Revision A3 -3- W921E840A/W921C840 − PB Port: PB.0 to PB.3 open drain and pull high resistor option − PC Port: PC.1 to PC.3 open drain and pull high resistor option − PD Port: PD.0 to PD.1 open drain and pull high resistor option Serial I/O Interface • Clock synchronous multi-nibbles serial transmitter/receiver interface DTMF Generator • One channel DTMF generator Beep Tone Generator • One channel beep tone generator 8-bit D/A Converter • One channel 8-bit D/A converter Voltage Comparator • Multiplexed four channel voltage comparator Timer/Counter • Timer 0: 2 to 19 order divider Auto-reload timer Watch-dog timer • Timer 1: 2 to 19 order divider Auto-reload timer Arbitrary waveform generator External event counter • Timer 2: 2 to 19 order divider Auto-reload timer Arbitrary waveform generator Period/pulse width measurement function • Timer 3: 2 to 19 order divider Auto-reload timer Interrupt • • Four external sources: INT0 (P4.3), P4 Port (P4.0 to P4.2) Six internal sources: Timer 0, Timer 1, Timer 2, Timer 3, Comparator, Serial Port Operating Mode (System Clock) • • • Normal mode: system clock operating HOLD mode: no operation except for oscillator (system clock stops only) STOP mode: no operation including oscillator -4- W921E840A/W921C840 Addressing Mode • ROM: Indirect call addressing mode Long jump/call addressing mode • RAM: Direct addressing mode Indirect addressing mode Working register addressing mode • Look-up table addressing mode Instruction Sets • 117 instruction sets 40-pin DIP, 48-pin QFP Package Type • The W921E840A/W921C840 microcontroller series are shown in the following table: PART NO. W921E840A/ W921C840 W921E841A/ W921C841 W921E842A/ W921C842 W921E843A/ W921C843 W921E844A/ W921C844 PACKAGE TYPE 40-pin DIP 40-pin DIP 40-pin DIP 40-pin DIP 48-pin QFP FUNCTION With pin PD.0, PD.1, BTG without dual clock XT , XT, PC.0 With dual clock XT , XT, PC.0 without pin PD.0, PD.1, BTG With pin PD.0, PD.1, PC.0 without dual clock XT , XT, BTG With dual clock XT , XT, BTG without pin PD.0, PD.1, PC.0 With pin PD.0, PD.1, PC.0, BTG, dual clock XT , XT -5- Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 3. PIN CONFIGURATIONS 40-pin DIP 21 W921E840A - 843A /W921C840 - 843 1 PIN NAME P2.0 P2.1 P2.2 P2.3 P3.0/ANI0 P3.1/ANI1 P3.2/ANI2 P3.3/ANI3 P4.0 P4.1 P4.2 P4.3/INT0 P5.0/TM1 P5.1/TM2 P5.2/VREF P5.3/DAOUT P6.0/WDATA P6.1/WCLK P6.2/RDATA VSS DIP40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME P6.3/RCLK PA.0 PA.1 PA.2 PA.3 PB.0 PB.1 PB.2 PB.3 PC.0 or BTG PC.1 PC.2 PC.3 DTMF PD.0 or XT PD.1 or XT RESET OSCO DIP40 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 OSCI VDD -6- W921E840A/W921C840 3. Pin Configurations, continued 48-pin QFP P 3 . 0 / A N I 0 PP 22 .. 32 P 2 . 1 / P OO V SS 2 . D CC 0DIO / R E S/ EXXN TTTC NC P3.1/ANI1 P3.2/ANI2 P3.3/ANI3 P4.0 P4.1 P4.2 P4.3/INT0 P5.0/TM1 P5.1/TM2 P5.2/Vref NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 2 34 3 33 4 5 32 6 31 W921E844A 30 7 / W921C844 29 8 28 9 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 1 PD.1 PD.0 DTMF PC.3 PC.2 PC.1 PC.0 BTG PB.3 PB.2 PB.1 PB.0 NPP C56 .. 30 // DW AD OA UT TA P 6 . 1 / W C L K PV PP 6s 6A .s.. 30 2 / / R R C D L A K T A P A . 1 P A . 2 PN AC . 3 PIN NAME NC P3.1/ANI1 P3.2/ANI2 P3.3/ANI3 QFP 48 1 2 3 4 PIN NAME PB.0 PB.1 PB.2 PB.3 QFP 48 25 26 27 28 -7- Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 Continued PIN NAME P4.0 P4.1 P4.2 P4.3/INT0 P5.0/TM1 P5.1/TM2 P5.2/VREF NC NC P5.3/DAOUT P6.0/WDATA P6.1/WCLK P6.2/RDATA VSS P6.3/RCLK PA.0 PA.1 PA.2 PA.3 NC QFP 48 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME BTG PC.0 PC.1 PC.2 PC.3 DTMF PD.0 PD.1 NC XT XT RESET OSCO QFP 48 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 OSCI VDD P2.0 P2.1 P2.2 P2.3 P3.0/ANI0 -8- W921E840A/W921C840 4. PIN DESCRIPTION SYMBOL OSCI OSCO I/O I O I/O V FUNCTION Main oscillator input pin with internal capacitor Main oscillator output pin I/O port 2 with large sink current I/O port 3 or analog input (ANI0 to ANI3) pins I/O pin P4.0 or the input pin of interrupt port I/O pin P4.1 or the input pin of interrupt port I/O pin P4.2 or the input pin of interrupt port I/O pin P4.3 or INT0 input pin I/O pin P5.0 or the controlled pin of timer 1 I/O pin P5.1 or the controlled pin of timer 2 I/O pin P5.2 or the VREF input pin of the comparator I/O pin P5.3 or the output pin of 8-bit D/A converter I/O pin P6.0 or the data output pin of serial interface I/O pin P6.1 or the clock I/O pin of WDATA I/O pin P6.2 or the data input pin of serial interface I/O pin P6.3 or the clock I/O pin of RDATA I/O port A with wake up stop mode function I/O port B with wake up stop mode function I/O port C. PC.3 can be as 32.768 KHz output buffer I/O pin PD.0 or 32.768 KHz subsystem clock output pin (with internal capacitor) I/O pin PD.1 or 32.768 KHz subsystem clock input pin Dual tone multi-frequency output pin Beep tone generator output pin Reset input pin with low active Positive power supply input pin Negative power supply input pin P2.0 to P2.3 P3.0/ANI0 to P3.3/ANI3 P4.0 P4.1 P4.2 P4.3/INT0 P5.0/TM1 P5.1/TM2 P5.2/VREF P5.3/DAOUT P6.0/WDATA P6.1/WCLK P6.2/RDATA P6.3/RCLK PA.0 to PA.3 PB.0 to PB.3 PC.0 to PC.3 PD.0 or XT PD.1 or XT DTMF BTG RESET VDD VSS I/O I/O I/O I/O I/O K K K K I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I I I K K I/OK K K K K K K Notes: V open drain option by software K open drain and pull high resistor option by software -9- Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 5. BLOCK DIAGRAM W Reg. V Reg. Co-V Reg. U Reg. Co-U Reg. Port P2 P2.0-P2.3 Port P3 Program Counter P3.0-P3.3 B Reg. A Reg. Port P4 P4.0-P4.3 EPROM 8K x 10 ALU Port P5 P5.0-P5.3 Decoder and Control Circuit Stack Pointer RAM 512 x 4 Timer 0 OSCI OSCO XT XT RESET MUX Port P6 Port Mode Register Port PA P6.0-P6.3 PA.0-PA.3 Port PB PB.0-PB.3 Oscillator and System Control Prescaler Timer 1 Port PC Timer 2 Timer 3 (ANI0 to ANI3) PC.0-PC.3 Port PD PD.0-PD.1 VDD VSS + MUX P5.2/V REF or P5.3/DAOUT DTMF Generator DTMF Beep Tone Generator BTG D/A Convertor D/A MSB D/A LSB - 10 - W921E840A/W921C840 6. FUNCTIONAL DESCRIPTION 6.1 ROM Memory Map 0000H Interrupt Area 000FH 0010H Indirect Call and Look-up Table Area Long Call/Jump Area 0FFFH 1000H 1FFFH 8192 x 10-bit 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH JMPL Instruction (Reset) XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX JMPL Instruction (INT0) JMPL Instruction (TM0) JMPL Instruction (TM1) JMPL Instruction (TM2) JMPL Instruction (Comparator / TM3) JMPL Instruction (P4.0 to P4.2) JMPL Instruction (Serial Port) Priority: Reset > INT0 > TM0 > TM1 > TM2 > (Comparator / TM3) > P4.0 to 4.2 > Serial Port - 11 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 6.2 RAM Memory Map 000H 000 Speical Control Registers 03FH 040H 063 064 Working Registers 04FH 050H 079 080 07FH 080H Serial Buffer Registers Stack Registers or General Registers Stack Registers (040H to 0FFH) 127 128 Serial Buffer Registers (050H to 14EH) General Registers (040H to 1FFH) 0FFH 100H 255 256 Serial Buffer Registers or General Registers 17FH 180H 383 384 General Registers 1FFH 511 (512 x 4-bit) 6.2.1 Special Control Register Area There are 64 × 4-bit registers in the special control register area. All control registers such as DTMF control register, serial speed control register, ..., etc. are in this area. Please refer to the following table for detailed register map. ADDR. 000H 001H 002H 003H 004H 005H 006H 007H 008H 009H DESCRIPTION Reserved or System Clock Control Register Reserved Reserved Port P4 Pull High Resistor Register Port P4 Output Type Register Port P6 Pull High Resistor Register Port P6 Output Type Register Port PABCD Pull High Resistor Register Port PABCD Output Type Register Serial LSB Nibble Register ABBREVIATION (SYSCCR) (P4PH) (P4TP) (P6PH) (P6TP) (PABCDPH) (PABCDTP) (SRLNR) INITIAL VALUE 00H 00H 00H 00H 00H 00H 00H 02H - 12 - W921E840A/W921C840 6.2.1 Special Control Register Map, continued ADDR. 00AH 00BH 00CH 00DH 00EH 00FH 010H 011H 012H 013H 014H 015H 016H 017H 018H 019H 01AH 01BH 01CH 01DH 01EH 01FH 020H 021H 022H 023H 024H 025H 026H 027H 028H 029H 02AH 02BH DESCRIPTION Serial MSB Nibble Register Serial Speed Control Register Serial Clock Inverter Control Register Port P2 Output Type Register Reserved Port P3 I/O Status Control Register Port P4 I/O Status Control Register Port P5 I/O Status Control Register Port P6 I/O Status Control Register DTMF Oscillation Control Register DTMF Register Row/Column Frequency Control Register D/A Control Register D/A Converter LSB Data Register D/A Converter MSB Data Register Comparator Analog Input Multiplexer Comparator Control Register Reserved TM1 Read Only MSB Data Register TM1 Read Only LSB Data Register TM2 Read Only MSB Data Register TM2 Read Only LSB Data Register TM0 Control Register TM0 MSB Data Register TM0 LSB Data Register TM0 Status Register Reserved or Timer 0 Low Speed Register TM1 Control Register TM1 MSB Data Register TM1 LSB Data Register TM1 Status Register TM1 Trigger Condition Register TM2 Control Register TM2 MSB Data Register ABBREVIATION (SRMNR) (SRSPC) (SRINV) (P2TP) ( P3IO ) ( P4IO ) ( P5IO ) ( P6IO ) (OSCCTR) (DTMF) (RCCTL) (DACTL) (DALSB) (DAMSB) (ANIMUX) (COMPTR) (TM1RM) (TM1RL) (TM2RM) (TM2LM) (TM0CR) (TM0MSB) (TM0LSB) (STTM0) (TM0LSR) (TM1CR) (TM1MSB) (TM1LSB) (STTM1) (TGTM1) (TM2CR) (TM2MSB) INITIAL VALUE 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 04H 0FH 0FH 0FH 0FH 00H 0FH 0FH 00H 00H 00H 0FH 0FH 00H 00H 00H 0FH - 13 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 6.2.1 Special Control Register Map, continued ADDR. 02CH 02DH 02EH 02FH 030H 031H 032H 033H 034H 035H 036H 037H 038H 039H 03AH 03BH 03CH 03DH 03EH 03FH DESCRIPTION TM2 LSB Data Register TM2 Status Register TM2 Trigger Condition Register TM3 Control Register TM3 MSB Data Register TM3 LSB Data Register TM3 Status Register Reserved Interrupt Enable Flag Stop Mode Released Flag Hold Mode Released Flag 1 Hold Mode Released Flag 2 Hold Mode Released Flag 3 Interrupt Control Register 1 Interrupt Control Register 2 Interrupt Control Register 3 Hold Released Status Flag 1 Hold Released Status Flag 2 Hold Released Status Flag 3 Beep Tone Generator Register ABBREVIATION (TM2LSB) (STTM2) (TGTM2) (TM3CR) (TM3MSB) (TM3LSB) (STTM3) (ENINT) (STPRF) (HMRF1) (HMRF2) (HMRF3) (INTCT1) (INTCT2) (INTCT3) (HRSTS1) (HRSTS2) (HRSTS3) (BTGR) INITIAL VALUE 0FH 00H 00H 00H 0FH 0FH 00H 00H 08H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 6.2.2 Stack Register Area A 8-bit stack pointer indicates the stack located address from 040H to 0FFH. After power on reset the stack pointer will be set to 0FFH. The stack pointer will be decreased by 4 when the CALL/ CALLP or interrupt is accepted, and will be increased by 4 when the RTN or RTNI instruction is executed. The format of the stack content is shown in the following table. 0F8H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH Z PC11 PC7 PC3 Z PC11 PC7 PC3 C PC10 PC6 PC2 C PC10 PC6 PC2 PC9 PC5 PC1 PC9 PC5 PC1 PC12 PC8 PC4 PC0 PC12 PC8 PC4 PC0 Stack 1 Stack 0 - 14 - W921E840A/W921C840 6.2.3 Working Register Area The located area from 040H to 04FH is known as working register. The instruction MOV WRn, A or MOV A, WRn can move the A accumulator data to the working register or move working register data to the A accumulator directly within the 1 word / 1 machine cycle. The other direct instructions such as MOV Mx, A or MOV A, Mx instruction are 2 words / 2 machine cycles. Therefore the working register can save the program memory size in ROM and improve the control speed in µC application circuit. Only the WR0 to WR7 are available in the arithmetic and logic operation (I. e. only 040H to 047H can be active). The instructions are as follows: ADD ADC SUB SBC ANL ORL XRL CMP A, A, A, A, A, A, A, A, WRx WRx WRx WRx WRx WRx WRx WRx where x = 0 to 7. 6.3 Internal Oscillator Circuit There are dual clocks in this chip, one high speed, the other low speed. The block diagram is shown below: f TM0 T M0 TM1 TM2 TM3 f SYS1 MUX0' f SYS0 MUX0 f TM1 MUX1 f TM2 MUX2 f TM3 MUX3 SYSCCR.0 11-bit Prescaler f SYS System Clock f OSC (1/4) f1 f2 Mask Option fH OSCI Crystal Type or RC Type OSCO SYSCCR.3 Enable (SYSCCR.1) 5-bit Prescaler f SUB 2-bit scaler (1/4) fL 1-bit scaler (1/2) XT Crystal Type XT Enable (SYSCCR.2) - 15 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 The detail function of the system clock control register (SYSCCR) is shown as below: SYSCCR register: (address = 000H, default data = 0H, only for W921E841A, 843A, 844A) b3 b2 b1 b0 0: f TM0 = f SYS0 1: f TM0 = f SYS1 0: f H enable 1: f H disable 0: f L enable 1: f L disable 0: f OSC = f 1: f OSC = f 1 2 The W921E840A/W921C840 provides a crystal or RC oscillation circuit selected by bit0 of INI register (refer to section 6.14) to generate the system clock through external connections. If a crystal oscillator is used, a crystal or ceramic resonator must be connected to OSCI and OSCO , and the capacitor is added optionally. The oscillator configuration is shown as follows. OSCI or OSCO Crystal Type OSCI OSCO RC type 6.4 Initial State The W921E840A/W921C840 is reset either by a power-on reset or by using the external RESET pin. The initial state of the W921E840A/W921C840 after the reset function is executed is described below. The EVF interrupt request signal register value is random, so user must do CLR EVF, #11111111b instruction to clear all interrupt request signals after power-on reset. Program counter (PC) Stack pointer Special function registers TM0, TM1, TM2, TM3 input clock TM0, TM1, TM2, TM3 contents Input/Output PM registers DTMF output EVF interrupt request signal register 0000H 0FFH Refer to section 6.2.1 Fosc/8 0FFH Input mode 1111B Disable (H-Z) Random - 16 - W921E840A/W921C840 6.5 Input/Output There are 34 I/O pins including 4 large sink current pins in this chip. All the I/O pins will remain in the input mode after power on reset. The I/O instructions are described as follows: MOV MOV MOV MOV A, Px B, Px Px, A Px, B Input port x to A accumulator Input port x to B accumulator Output A accumulator data to port x. Output B accumulator data to port x. The input or output status of port 2 to port 6 can be pin controlled by port mode register (PMx, where x = 2 to 6). Data 0 of PMx indicates the corresponding pin as output mode, and data 1 indicates the relative pin as input mode. For example, MOV PM2, #0101B, it sets P2.0 and P2.2 in input mode and P2.1 and P2.3 in output mode. The I/O instructions don't affect the I/O status in Port 2 to Port 6. The input or output mode of port A to port D only can be decided by I/O instructions. For example, MOV A, Px will change Px to input mode and MOV Px, A will change it to output mode. 6.5.1 Normal/Special Function Selection of I/O Some of the I/O ports can be programmed to special function via special control register. The detail functions are as follows: • P2.0 to P2.3: Four 15mA sink current normal I/O pins only • P3.0 to P3.3: Multi-function I/O pins (selected by P3IO register) − Normal function I/O pins − Special function input pins P3IO register: (address = 00FH, default data = 0H) b3 b2 b1 b0 0: Normal I/O P3.0 1: Analog input pin 0 (ANI0) 0: Normal I/O P3.1 1: Analog input pin 1 (ANI1) 0: Normal I/O P3.2 1: Analog input pin 2 (ANI2) 0: Normal I/O P3.3 1: Analog input pin 3 (ANI3) - 17 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 • P4.0 to P4.3: Multi-function I/O pins (selected by P4IO register) − Normal function I/O pins − Special function input pins P4IO register: (address = 010H, default data = 0H) b3 b2 b1 b0 0: Normal I/O P4.0, interrupt disable 1: Interrupt port P4.0 0: Normal I/O P4.1, interrupt disable 1: Interrupt port P4.1 0: Normal I/O P4.2, interrupt disable 1: Interrupt port P4.2 0: Normal I/O P4.3, interrupt disable 1: INT0 • P5.0 to P5.3: Multi-function I/O pins (selected by P5IO register) − Normal function I/O pins − Special function I/O pins P5IO register: (address = 011H, default data = 0H) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: Normal I/O P5.0 Work as the timer 1 control pin Normal I/O P5.1 Work as the timer 2 control pin Normal I/O P5.2 Work as the Vref input pin of the comparator Normal I/O P5.3 Work as the output pin of D/A converter (DAOUT) - 18 - W921E840A/W921C840 • P6.0 to P6.3: Multi-function I/O pins (selected by P6IO register) − Normal function I/O pins − Special function I/O pins P6IO register: (address = 012H, default data = 0H) b3 b2 b1 b0 0: Normal I/O P6.0 1: Work as the data output pin of the WCLK pin (WDATA) 0: Normal I/O P6.1 1: W ork as the clock I/O pin of the WDATA pin (WCLK) 0: Normal I/O P6.2 1: Work as the data input pin of the RCLK pin (RDATA) 0: Normal I/O P6.3 1: Work as the clock I/O pin of the RDATA pin (RCLK) • PA.0 to PA.3: Normal function I/O pins only • PB.0 to PB.3: Normal function I/O pins only • PC.1 to PC.3: Normal function I/O pins only • PD.0 to PD.1: Normal function I/O pins only 6.5.2 Pull High and Open Drain Control of I/O Some of the above I/O ports can be controlled with pull-high resistor or open drain by programming the special register. All pull-high resistors of the following descriptions are 400KΩ under 3.0 voltage test condition. After power-on reset the following special register will all reset to 0H. • P4.0 to P4.3: P4PH register: (address = 003H, default data = 0H) b3 b2 b1 b0 0: P4.0 without pull-high resistor 1: P4.0 with pull-high resistor 0: P4.1 without pull-high resistor 1: P4.1 with pull-high resistor 0: P4.2 without pull-high resistor 1: P4.2 with pull-high resistor 0: P4.3 without pull-high resistor 1: P4.3 with pull-high resistor - 19 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 P4TP register: (address = 004H, default data = 0H) b3 b2 b1 b0 0: P4.0 work as CMOS type 1: P4.0 work as open-drain type 0: P4.1 work as CMOS type 1: P4.1 work as open-drain type 0: P4.2 work as CMOS type 1: P4.2 work as open-drain type 0: P4.3 work as CMOS type 1: P4.3 work as open-drain type • P6.0 to P6.3 : P6PH register: (address = 005H, default data = 0H) b3 b2 b1 b0 0: P6.0 without pull-high resistor 1: P6.0 with pull-high resistor 0: P6.1 without pull-high resistor 1: P6.1 with pull-high resistor 0: P6.2 without pull-high resistor 1: P6.2 with pull-high resistor 0: P6.3 without pull-high resistor 1: P6.3 with pull-high resistor P6TP register: (address = 006H, default data = 0H) b3 b2 b1 b0 0: P6.0 work as CMOS type 1: P6.0 work as open-drain type 0: P6.1 work as CMOS type 1: P6.1 work as open-drain type 0: P6.2 work as CMOS type 1: P6.2 work as open-drain type 0: P6.3 work as CMOS type 1: P6.3 work as open-drain type - 20 - W921E840A/W921C840 • PA, PB, PC, PD: PABCDPH register: (address = 007H, default data = 0H) b3 b2 b1 b0 0: PA (4 pins) without pull-high resistor 1: PA (4 pins) with pull-high resistor 0: PB (4 pins) without pull-high resistor 1: PB (4 pins) with pull-high resistor 0: PC (3 pins) without pull-high resistor 1: PC (3 pins) with pull-high resistor 0: PD (2 pins) without pull-high resistor 1: PD (2 pins) with pull-high resistor PABCDTP register: (address = 008H, default data = 0H) b3 b2 b1 b0 0: PA (4 pins) work as CMOS type 1: PA (4 pins) work as open-drain type 0: PB (4 pins) work as CMOS type 1: PB (4 pins) work as open-drain type 0: PC (3 pins) work as CMOS type 1: PC (3 pins) work as open-drain type 0: PD (2 pins) work as CMOS type 1: PD (2 pins) work as open-drain type • P2: P2TP register: (address = 00DH, default data = 0H) b3 b2 b1 b0 0: P2 (4 pins) work as CMOS type 1: P2 (4 pins) work as open-drain type 0: PC.3 works as normal I/O port (CMOS type) 1: PC.3 works as 32.768KHz output buffer (open-drain type) only for W921E841A, 843A, 844A Reserved Reserved 6.6 Serial Port The W921E840A/W921C840 has a clock-synchronous serial interface which transmits and receives 8-bit data as default. User can program the P6IO register to select port P6 as the serial port. The serial transmitter/receiver function can be operated with multi-nibble function and the LSB of every nibble is transmitted/received first. The serial transmitted/received data are come from or are stored into the serial buffer registers (address 050H to 14EH); how many nibbles will be transmitted/received is decided by the serial MSB nibble register (SRMNR, address = 00AH) and serial LSB nibble register (SRLNR, address = 009H). - 21 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 SRMNR register: (address = 00AH, default data = 0H) b3 b2 b1 b0 SRLNR register: (address = 009H, default data = 2H) b3 b2 b1 b0 The default data in SRMNR and SRLNR are 0 and 2, meaning that the default serial interface is used to transmit/receive 8-bit data serially. As soon as the above two register are programmed and the instructions such as SOP or SIP are executed, the serial transmitter/receiver multi-nibble function will be performed. The transmitted/received number will be auto increased by one when each nibble is transmitted/received until the number is equal to SRLNR, SRMNR registers. Even if the HOLD instruction is executed, the SOP or SIP function will continue executing until the transmitter/receiver function has been completed. However, executing the STOP instruction will stop all serial transmitter/receiver function. The transceiver data will be latched on the rising or falling edge of the clock; this is determined by the serial clock inverter control register (SRINV, address = 00CH). Before SOP or SIP instruction is executed the SRINV register must be set to the exact value. Once the bit3 and bit2 of SRINV register are both cleared to zero, the serial transceiver function will be reset to initial status immediately. SRINV register: (address = 00CH, default data = 0H) b3 b2 b1 b0 0: Serial data latch at SCLK1/SCLK2 rising edge (normal high) 1: Serial data latch at SCLK1/SCLK2 falling edge (normal low) 0: SCLK1and SCLK2 pins work as the internal clock output pin 1: SCLK1and SCLK2 pins work as the external clock input pin 0: SCLK2 and SDATA2 disable (H-Z) 1: SCLK2 and SDATA2 enable 0: SCLK1 and SDATA1 disable (H-Z) 1: SCLK1 and SDATA1 enable - 22 - W921E840A/W921C840 The serial interface configuration is shown below: To Port P6 Normal I/O Register P6.3 P6.2 P6.1 P6.0 Port P6 Pull-High Resisters VDD WDATA WCLK SRINV.3 RDATA RCLK SRINV.2 SCLK P6IO.3 P6IO.2 P6IO.1 P6IO.0 P6PH To Port P6 Clock Source and Latch Control Circuit SDATA Serial Clock Speed Control Circuit f SYS System Clock 1/4 High Speed Clock Serial/Parallel I/O Buffer Serial Buffer Registers 050H 14EH The internal serial clock can be controlled by the serial clock speed control register (SRSPC); the format is as follows: SRSPC register: (address = 00BH, default data = 0H) b3 b2 b1 b0 b3 b2 b1 b0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Input frequency Reserved fsys/4 Hz fsys/8 Hz fsys/16 Hz fsys/32 Hz fsys/64 Hz fsys/128 Hz fsys/256 Hz fsys/512 Hz fsys/1024 Hz fsys/2048 Hz - 23 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 Normally the WCLK or RCLK pin will remain in high state and the serial data will be latched at the rising edge of the WCLK or RCLK signal, but the serial clock inverter control register (SRINV) will invert the above function. In this case WCLK or RCLK pin will remain in low state and the serial data will be latched at the falling edge of the WCLK or RCLK signal. The transmitting serial clock can come from WCLK or RCLK, depending on which one is enable. If the serial function is disabled, it will cause the relative pins to be high impendance and it will not affect the contents of serial buffer registers (start at address 050H). 6.7 DTMF Generator There is one dual tone multi-frequency (DTMF) generator channel in this chip. The correct DTMF output frequency is decided by the OSCCTR register as shown below: OSCCTR register: (address = 013H, default data = 0H) b3 b2 b1 b0 b2 0 0 0 0 1 1 b1 0 0 1 1 0 0 b0 0 1 0 1 0 1 Osc. Selection 400 KHz 800 KHz 2 MHz 4 MHz Reserved 3.58MHz Reserved There are four bits in the DTMF register; the functions are described in the following table: DTMF register: (address = 014H, default data = 0H) b3 b2 b1 b0 XX00 XX01 XX10 XX11 00XX 01XX 10XX 11XX Note: X Ä don't care Function Description Column 1 (1209 Hz) output Column 2 (1336 Hz) output Column 3 (1477 Hz) output Column 4 (1633 Hz) output Row 1 (697 Hz) output Row 2 (770 Hz) output Row 3 (852 Hz) output Row 4 (941 Hz) output - 24 - W921E840A/W921C840 The output frequency of the row and column will be controlled by the row/column frequency control register (RCCTL). RCCTL register: (address = 015H, default data = 0H) b3 b2 b1 b0 0: Row frequency disable 1: Row frequency enable 0: Column frequency disable 1: Column frequency enable 0: DTMF disable (H-Z) 1: DTMF enable Reserved The following table shows the DTMF keypad and its frequency. C1 1 4 7 * C2 2 5 8 0 C3 3 6 9 # C4 A B C D R1 R2 R3 R4 Key R1 R2 R3 R4 C1 C2 C3 C4 Frequency 697 Hz 770 Hz 852 Hz 941 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz 6.8 Beep Tone Generator There are four kinds of frequency that can output from the BTG pin that works as beep tone generator. The BTG pin can output the special frequency2 KHz, 1 KHz, 630 Hz or 520 Hz, and the correct output frequency is decided by the OSCCTR register (address = 013H) and BTGR register (address = 03FH) as shown below: BTGR register: (address = 03FH, default data = 0H) b3 b2 b1 b0 b1 0 b0 0 1 0 1 Output Freq. 2K Hz 1K Hz 630 Hz 520 Hz Reserved 0 1 1 0: Disable beep tone generator (BTG pin keep in high state) 1: Enable beep tone generator If the beep tone generator is disabled by setting bit 3 of the BTGR register to zero or after power on reset, the BTG output pin will remain in high state. - 25 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 6.9 D/A Converter The content of 8-bit D/A converter is divided into D/A MSB data register (DAMSB) and D/A LSB data register (DALSB). The block diagram is shown below. ANIMUX Register Vani ANI3 ANI2 ANI1 ANI0 Vpos Vrang = 1.5 V or (2/3)V DD DACTL.2 COMPTR.1 Vneg COMPTR.2 COMPTR.3 8bit D/A Converter Vref P5.2/Vref P5.3/DAOUT DAMSB 4-bit Register DALSB 4-bit Register • D/A Converter Control Register: DACTL register: (address = 016H, default data = 0H) b3 b2 b1 b0 0: D/A converter stop 1: D/A converter start Reserved Reserved 0:Vrang = (2/3)VDD 1:Vrang = 1.5V When the DACTL register bit0 is set by software, the 8-bit D/A converter starts converting. The only way to disable the D/A converter is to reset the bit0 of the DACTL register using the software control. The analog signal will be output to the P5.3 pin in this chip if the I/O port works as the D/A output pin. The power source of the D/A converter can be selected from the (2/3)VDD or 1.5V by programming the DACTL register bit2. • D/A Converter LSB Data Register DALSB register: (address = 017H, default data = 0H) b3 b2 b1 b0 - 26 - W921E840A/W921C840 • D/A Converter MSB Data Register DAMSB register: (address = 018H, default data = 0H) b3 b2 b1 b0 6.10 Comparator There are 4-channel inputs to the comparator negative (can be programmed to positive) terminal, but only one channel will be active at a time. The control register is shown below. ANIMUX register: (address = 019H, default data = 0H) b3 b2 b1 b0 b1 b0 00 01 10 11 Enable ANI0 ANI1 ANI2 ANI3 Reserved Reserved COMPTR register: (address = 01AH, default data = 4H) b3 b2 b1 b0 0: Compare stop 1: Compare start 0: Vneg = Vref; Vpos = Vani 1: Vneg = Vani; Vpos = Vref (Read Only) 0: Vpos voltage < Vneg voltage 1: Vpos voltage >= Vneg volatge 0: Vref = P5.2/Vref 1: Vref = P5.3/DAOUT When the COMPTR register bit0 is set by software, the comparator starts and the bit2 of the COMPTR register will be set to "1" initially. The comparing result will be stored in the bit2 of the COMPTR register and will keep this value until the bit0 of the COMPTR register is set again. The only way to disable the comparator is to reset the bit0 of the COMPTR register using the software control. The initial value of the COMPTR bit2 is "1", the falling edge of COMPTR bit2 will cause the comparator interrupt to become active if the enable flag of the comparator interrupt is set. The bit3 of the COMPTR register controls the source of Input voltage reference (Vref). The input reference voltage (Vref) comes from external pin (P5.2/Vref) or D/A converter analog signal output (P5.3/DAOUT). - 27 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 6.11 Timer/Counter There are four timers (TM0, TM1, TM2 and TM3) in this chip, and all can be initialized at any time by writing data into the TM0, TM1, TM2 and TM3 set register. 6.11.1 TM0 TM0 can perform the following functions: 1. 2 to19 order divider 2. Auto-reload timer 3. Watch-dog timer High Speed Clock TM0 Control Register System Clock 1/4 f SYS 11-bit Prescaler Interrupt Control Register TM0 Interrupt Logic fSYS0 f SYS1 f TM0 8 Order Divider Watch Dog Timer TM0 Set Register (8 bits) TM0 Control Logic 1/8 f SUB 5-bit Prescaler Low Speed Clock TM0 Low Speed Register The format of the TM0 control register (TM0CR) is described below: TM0CR register: (address = 020H, default data = 0H) b3 b2 b1 b0 b1 0 0 Reserved Reserved 1 1 b0 Input frequency (fSYS0 ) 0 1 0 1 fsys/2 Hz fsys/256 Hz fsys/1024 Hz fsys/2048 Hz The TM0 set register is divided into TM0 MSB data register (TM0MSB register, address = 021H, default = 0FH) and TM0 LSB data register (TM0LSB register, address = 022H, default = 0FH). - 28 - W921E840A/W921C840 TM0 will underflow when TM0 set register is from 00H to 0FFH and the value in the TM0MSB and TM0LSB will be auto reloaded to the TM0 set register when the STTM0 bit2 is set. TM0 will decrease by 1 at the frequency of timer 0 clock after timer 0 has started. If at any time the STTM0 bit3 is from 0 to 1 (disable to enable) in the timer mode, the TM0MSB and TM0LSB will be auto reloaded to the TM0 set register again and restart the timer 0. TM0 will stop operating while the STTM0 bit3 is reset to 0. The format of the TM0 low speed register (TM0LSR) is described below: TM0LSR register: (address = 024H, default data = 0H, only for W921E841A, 843A, 844A) b3 b2 b1 b0 b1 0 0 Reserved Reserved 1 1 b0 0 1 0 1 Input frequency (fsys1) fsub/2 Hz fsub/8 Hz fsub/16 Hz fsub/32 Hz The TM0 starts to down count when the STTM0 register bit3 is set. When TM0 underflows, the STTM0 bit3 will be reset by hardware to stop TM0 if the auto-reload is disabled, but the STTM0 bit3 will not be reset if the auto-reload is enabled. When the TM0 normal function is performed, the watch-dog timer function will be disabled automatically. The format of the TM0 status register (STTM0) is described below: STTM0 register: (address = 023H, default data = 0H) b3 b2 b1 b0 0:TM0 normal function selected 1:Watch-dog timer (WDT) selected 0:WDT not underflow 1:WDT underflow 0:TM0 auto-reload disable 1:TM0 auto-reload enable 0:TM0 stop 1:TM0 start If TM0 works as the watch-dog timer (WDT), the bit1 of the STTM0 register will be set when the WDT is underflow, in the meanwhile, the system is reset just as with power on reset except the STTM0 bit1. The WDT (STTM0 bit1) will be reset to zero only with the power on reset or the RAM write mode. In the timer mode or event counter mode the time out will be the programming data subtract 1 ([TM0MSB, TM0LSB]-1). It is the same in the TM1, TM2 and TM3. - 29 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 6.11.2 TM1 TM1 can perform the following functions: 1. 2 to19 order divider 2. Auto-reload timer 3. Arbitrary waveform generator 4. Event counter System Clock 1/4 f SYS 11-bit Prescaler f TM1 TM1 Read Register Interrupt Control Register High Speed Clock TM1 Control Register 2 8 Order Divider TM1 Interrupt Logic Port 5.0 Event Counter Logic TM1 Set Register (8 bits) Arbitrary Waveform Generator TM1 Control Logic The format of the TM1 control register (TM1CR) is described below: TM1CR register: (address = 025H, default data = 0H) b3 b2 b1 b0 b3 b2 b1 b0 Input frequency (fT M1 ) 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 fsys/2 Hz fsys/4 Hz fsys/8 Hz fsys/16 Hz fsys/32 Hz fsys/64 Hz fsys/128 Hz fsys/256 Hz fsys/512 Hz fsys/1024 Hz fsys/2048 Hz The TM1 set register is divided into TM1 MSB data register (TM1MSB register, address = 026H, default = 0FH) and TM1 LSB data register (TM1LSB register, address = 027H, default = 0FH). - 30 - W921E840A/W921C840 The TM1 read register is divided into TM1 read only MSB data register (TM1RM register, address = 01CH, default = 0FH) and TM1 read only LSB data register (TM1RL register, address = 01DH, default = 0FH). The format of the TM1 status register (STTM1) is described below: STTM1 register: (address = 028H, default data = 0H) b3 b2 b1 b0 0: TM1 normal function selected 1: Special function selected Reserved 0:TM1 auto-reload disable 1:TM1 auto-reload enable 0:TM1 stop 1:TM1 start If the TM1 is in the timer mode, TM1 will underflow when it is from 00H to 0FFH and the value in the TM1MSB and TM1LSB will be auto reloaded into the TM1 set register when the STTM1 bit2 is set. TM1 will decrease by 1 at the frequency of timer 1 clock after timer 1 has started. At any time the STTM1 bit3 is from 0 to 1 (disable to enable) the TM1MSB and TM1LSB will be auto reloaded to the TM1 set register again and restart the TM1. TM1 will stop operating while the STTM1 bit3 is reset to 0. The TM1 starts to down count when the STTM1 register bit3 is set. When TM1 underflows, the STTM1 bit3 will be reset by hardware to stop TM1 if the auto-reload is disabled, but the STTM1 bit3 will not be reset if the auto-reload is enable. When the TM1 normal timer function is performed, the special function (event counter or arbitrary waveform generator) will be disabled automatically. The special function input or output is from or to P5.0 and the debounce time is one system clock (fSYS). The format of the TM1 trigger/event counter condition register (TGTM1) is described below: TGTM1 register: (address = 029H, default data = 0H) b3 b2 b1 b0 0: Event counter is falling edge trigger 1: Event counter is rising edge trigger 0: Special function work as event counter 1: Special function work as arbitrary waveform generator 0: Arbitrary waveform type 0 1: Arbitrary waveform type 1 Reserved - 31 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 6.11.3 TM2 TM2 can perform the following functions: 1. 2 to19 order divider 2. Auto-reload timer 3. Arbitrary waveform generator 4. Period/pulse width measurement function f SYS f TM2 System Clock 1/4 11-bit Prescaler TM2 Read Register Interrupt Control Register High Speed Clock TM2 Control Register 8 Order Divider TM2 Interrupt Logic Port 5.1 Period/Pulse Width Measurement TM2 Set Register (8 bits) Arbitrary Waveform Generator TM2 Control Logic TM2CR register: (address = 02AH, default data = 0H) b3 b2 b1 b0 b3 b2 b1 b0 Input frequency (f TM2 ) 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 fsys/2 Hz fsys/4 Hz fsys/8 Hz fsys/16 Hz fsys/32 Hz fsys/64 Hz fsys/128 Hz fsys/256 Hz fsys/512 Hz fsys/1024 Hz fsys/2048 Hz The TM2 set register is divided into TM2 MSB data register (TM2MSB register, address = 02BH, default = 0FH) and TM2 LSB data register (TM2LSB register, address = 02CH, default = 0FH). The TM2 read register is divided into TM2 read only MSB data register (TM2RM register, address = 01EH, default = 0FH) and TM2 read only LSB data register (TM2RL register, address = 01FH, default = 0FH). - 32 - W921E840A/W921C840 The format of the status of TM2 register (STTM2) is described below: STTM2 register: (address = 02DH, default data = 0H) b3 b2 b1 b0 0: TM2 normal function selected 1: Special function selected Reserved 0: TM2 auto-reload disable 1: TM2 auto-reload enable 0: TM2 stop 1: TM2 start If the TM2 is in the timer mode, TM2 will underflow when it is from 00H to 0FFH and the value in the TM2MSB and TM2LSB will be auto reloaded to the TM2 set register. TM2 will decrease by 1 at the frequency of timer 2 clock after timer 2 has started. If at any time the STTM2 bit3 is from 0 to 1 (disable to enable) the TM2MSB and TM2LSB will be auto reloaded to the TM2 set register again and restart the TM2. TM2 will stop operating when the STTM2 bit3 is reset to 0 The TM2 starts to count when the STTM2 register bit3 is set. When TM2 underflows, the STTM2 bit3 will be reset by hardware to stop TM2 if the auto-reload is disabled, but the STTM2 bit3 will not be reset if the auto-reload is enabled. When the TM2 normal function is performed, the special function will be disabled automatically. The format of the TM2 trigger condition register (TGTM2) is shown below: TGTM2 register: (address = 02EH, default data = 0H) b3 b2 b1 b0 b1 0 0 1 1 b0 0 1 0 1 Rising Falling Both Trigger 0: Special function work as pulse/period width measurement 1: Special function work as arbitrary waveform generator 0: Arbitrary waveform type 0 1: Arbitrary waveform type 1 In the pulse/period width measurement mode the measuring-data is the 1'S complement of the exact data and the TM2 interrupt flag is set every 255 timer clock past or the 2nd trigger condition occurs. So the measured pulse/period width is (255(N − 1) + TM2) * T , N is the number of interrupt flag occurs, TM2 is the 1'S complement of timer2 register, T is the period of timer 2 clock. The special function input or output is from or to P5.1. - 33 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 6.11.4 TM3 TM3 can perform the following functions: 1. 2 to19 order divider 2. Auto-reload timer Interrupt Control Register System Clock 1/4 f SYS 11-bit Prescaler f TM3 8 Order Divider TM3 Interrupt Logic High Speed Clock TM3 Control Register TM3 Set Register (8 bits) TM3 Control Logic TM3CR register: (address = 02FH, default data = 0H) b3 b2 b1 b0 b3 b2 b1 b0 Input frequency (fTM3 ) 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 fsys/2 Hz fsys/4 Hz fsys/8 Hz fsys/16 Hz fsys/32 Hz fsys/64 Hz fsys/128 Hz fsys/256 Hz fsys/512 Hz fsys/1024 Hz fsys/2048 Hz The TM3 set register is divided into TM3 MSB data register (TM3MSB register, address = 030H, default = 0FH) and TM3 LSB data register (TM3LSB register, address = 031H, default = 0FH). The format of the status of TM3 register (STTM3) is described below: STTM3 register: (address = 032H, default data = 0H) b3 b2 b1 b0 Reserved Reserved 0: TM3 auto-reload disable 1: TM3 auto-reload enable 0: TM3 stop 1: TM3 start - 34 - W921E840A/W921C840 6.11.5 Arbitrary Waveform Generator The TM1 and TM2 have the arbitrary waveform generator circuit. Both have the same function as the following description. Type 0: NT 256T N = 0 will keep the waveform in the high state Type 1: T NT N = 1 will keep the waveform in the low state Note: N is the value stored in the TM1 Set Reg. (TM1MSB, TM1LSB) or TM2 Set Reg. (TM2MSB, TM2LSB) 6.12 Interrupt There are ten interrupt sources (four external and six internal sources) in the W921E840A/W921C840. All the pins of external sourcesÄINT0 (P4.3) and port P4 (P4.0 to P4.2)Äare falling edge active. The priority of those interrupts is INT0 > TM0 > TM1 > TM2 > ( Comparator / TM3 ) > P4.0 to P4.2 > SERIAL. 6.12.1 Interrupt Control Register Which interrupt is enabled is controlled by the interrupt control register1 to 3 (INTCT1 to INTCT3). The formats are shown below: INTCT1 register: (address = 039H, default data = 0H) b3 b2 b1 b0 0: TM0 interrupt disable 1: TM0 interrupt enable 0: TM1 interrupt disable 1: TM1 interrupt enable 0: TM2 interrupt disable 1: TM2 interrupt enable 0: TM3 interrupt disable 1: TM3 interrupt enable - 35 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 INTCT2 register: (address = 03AH, default data = 0H) b3 b2 b1 b0 0: INT0 pin interrupt disable 1: INT0 pin interrupt enable 0: Serial port interrupt disable 1: Serial port interrupt enable Reserved 0: Comparator interrupt disable 1: Comparator interrupt enable INTCT3 register: (address = 03BH, default data = 0H) b3 b2 b1 b0 0: Pin P4.0 interrupt disable 1: Pin P4.0 interrupt enable 0: Pin P4.1 interrupt disable 1: Pin P4.1 interrupt enable Reserved 0: Pin P4.2 interrupt disable 1: Pin P4.2 interrupt enable 6.12.2 Interrupt Enable Flag When the interrupt is enabled by the event, the program counter will jump to the interrupt address and the enable interrupt flag (ENINT) bit0 is cleared, at the same time, all the interrupt will be disabled. The only way to enable the interrupt again is to set the ENINT bit0 or execute the RTNI instruction. ENINT register: (address = 034H, default data = 0H) b3 b2 b1 b0 0: Disable all interrupt 1: Enable all interrupt Reserved Reserved Reserved When the interrupt is enabled by the event, the individual interrupt request signal is cleared by the hardware automatically, but the other interrupt request signals will remain the same condition. The only method of resetting the interrupt request signal is to execute the instruction CLR EVF, #I (I is a 8bits data, for example, CLR EVF, #00000001b instruction implies to clear TM0 interrupt request signal), it is a 2 words / 2 cycles instruction; the format of the immediate data is shown below. i7 i6 i5 i4 i3 i2 i1 i0 1: TM0 interrupt request signal is cleared 1: TM1 interrupt request signal is cleared 1: TM2 interrupt request signal is cleared 1: TM3 interrupt request signal is cleared 1: INT0 pin interrupt request signal is cleared 1: Serial port interrupt request signal is cleared 1: Comparator interrupt request signal is cleared 1: P4.0 to P4.2 interrupt request signal is cleared - 36 - W921E840A/W921C840 6.13 Operating Mode There are three types of operating mode in this chip  normal mode, hold mode and stop mode. 6.13.1 Normal Mode All functions works well and the µC operates according to the clock generated by the system clock. 6.13.2 Hold Mode In hold mode, all operations of µC cease, except for the operation of the oscillator, timer/counter, serial port and interrupt active pins. The µC enters hold mode when the HOLD instruction is executed. The hold mode can be released only by the RESET pin or the interrupt request signal. Before The device enters the hold mode, the hold mode release flag1, 2, 3 (HMRF1, 2, 3, address = 036H, 037H, 038H) must be set to define the hold mode release conditions. If interrupt condition is met and enabled in hold mode, the interrupt will be accepted to release hold mode and jump to interrupt vector to execute interrupt service routine. For more details, refer to the following flags and flow chart. HMRF1 register: (address = 036H, default data = 0H) LSB MSB 0 NOP MOV B, A 1 MOV A, B 2 MOV A, Mx MOV B, Mx 3 MOV A, @M MOV B, @M 4 MOV A, W 5 MOV A, V 6 MOV A, U 7 8 SRL A SRH A 9 INC B INC DP A ADD A, Mx ADC A, Mx B ADD A, @M ADC A, @M C D CLRB Mx, bit CLRB @M, bit SETB Mx, bit SETB @M, bit E F 0 1 2 3 4 5 6 7 8 9 A B C D E F MOV Mx, A MOV Mx, B SLL A DEC B SUB A, Mx SUB A, @M MOV @M, A MOV @M, B SLH A DEC DP SBC A, Mx SBC A, @M MOV W, A RRC A ANL A, Mx ANL A, @M CLR EVF XCH A, B MOV DP, #I SOP MOV V, A ORL A, Mx ORL A, @M SIP MOV U, A RLC A XRL A, B XRL A, Mx XRL A, @M SET CF XCH V, CV HOLD RTN CMP A, B CMP A, MX CMP A, @M CLR CF XCH U, CU STOP RTNI ADD A, #I ADC A, #I SUB A, #I SBC A, #I ANL A, #I ORL A, #I XRL A, #I CMP A, #I 1W/1C 2W/2C Undecided 1W/2C 2W/3C 1W/3C 3W/3C HMRF2 register: (address = 037H, default data = 0H) b3 b2 b1 b0 0: INT0 pin hold released disable 1: INT0 pin hold released enable 0: Serial port hold released disable 1: Serial port hold released enable Reserved 0: Comparator hold released disable 1: Comparator hold released enable HMRF3 register: (address = 038H, default data = 0H) b3 b2 b1 b0 0: Pin P4.0 hold released disable 1: Pin P4.0 hold released enable 0: Pin P4.1 hold released disable 1: Pin P4.1 hold released enable Reserved 0: Pin P4.2 hold released disable 1: Pin P4.2 hold released enable - 37 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 Hold mode operation flow chart TM0 toTM3; Serial;Comparator; Falling change occurs at INT0, P4.0 to P4.2 Yes In Hold Mode? No Interrupt Enable? Yes No Interrupt Enable? Yes No INTCTx Interrupt Flag Set? Yes No INTCTx Interrupt Flag Set? Yes No Reset ENINT Flag and Individual Request Flag Execute Interrupt Service Routine No HMRFx Hold Release Flag Set? Yes Reset ENINT Flag and Individual Request Flag Execute Interrupt Service Routine Hold PC PC + 1 note: x is the corresponding flag bit of interrupt enable or hold mode release register - 38 - W921E840A/W921C840 The hold released status flag1, 2, 3 (HRSTS1, 2, 3, address = 03CH, 03DH, 03EH) indicate by which interrupt source the hold mode has been released, and is loaded by hardware. When any bit of HRSTS1, 2, 3 is "1," the hold mode will be released and HOLD instruction in invalid. The bit descriptions are as follows: HRSTS1 register: (address = 03CH, read only, default data = 0H) b3 b2 b1 b0 1: Hold was released by TM0 1: Hold was released by TM1 1: Hold was released by TM2 1: Hold was released by TM3 HRSTS2 register: (address = 03DH, read only, default data = 0H) b3 b2 b1 b0 1: Hold was released by the INT0 pin 1: Hold was released by serial port Reserved 1: Hold was released by comparator HRSTS3 register: (address = 03EH, read only, default data = 0H) b3 b2 b1 b0 1: Hold was released by pin P4.0 1: Hold was released by pin P4.1 Reserved 1: Hold was released by pin P4.2 HRSTS1, 2 and 3 are read only registers and can be reset by the instruction CLR EVF, #I. When EVF has been reset, the corresponding bit of HRSTSn (n = 1 to 3) is reset simultaneously. 6.13.3 Stop Mode The µC enters the stop mode only when the STOP instruction is executed. Because the oscillator is stopped, all functions in this chip are stopped. The stop mode can be released by the RESET pin, INT0 pin, P4.0 to P4.2, PA port or PB port. The stop condition release flag (STPRF, address = 035H) is the stop mode release control register. - 39 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 STPRF register: (address = 035H, default data = 8H) b3 b2 b1 b0 0: Stop released by any pin of PA is disable 1: Stop released by any pin of PA is enable 0: Stop released by any pin of PB is disable 1: Stop released by any pin of PB is enable 0: Stop released by any pin of P4.0 to P4.2 is disable 1: Stop released by any pin of P4.0 to P4.2 is enable 0: Stop released by INT0 (P4.3) is disable 1: Stop released by INT0 (P4.3) is enable When stop mode is active, if the stop condition release flag (STPRF) is set before the STOP instruction is executed, the low level signal on the P4, PA or PB ports will release the stop mode and a delay of 256 machine cycles occurs right after the stop mode is released, then the next instruction is executed or the program counter (PC) jumps to interrupt subroutine if the interrupt is enabled and interrupt request exists. The control flow chart is shown below: Stop mode operation flow chart START Enter STOP Mode PC STOP No STOP Release Yes System will Delay 256 Machine Cycle Automatically (Only falling signal on INT0 or P4.0 - P4.2) Yes INT Enable? No (PA, PB Ports on low level state) PC + 1 Next Instruction INT Vector RTNI - 40 - W921E840A/W921C840 6.14 Initial Condition Register of EPROM Program Method There is one 4-bit of the initial condition register (not part of the RAM) in W921E840A to control the micro-controller initial status after power-on. The format is described as following: INI register: (initial value = 0FH) b3 b2 b1 b0 0: f osc acts as RC oscillator type 1: f osc acts as crystal type 0: f1 = f L , f2 = f 1: f1 = f H, f2 = f Reserved Reserved H L only for W921E841A, 843A, 844A 6.15 Reset W921E840A/W921C840 provides two reset methods, pull low RESET pin and watch dog timer reset. 6.15.1 Reset by RESET 256 machine cycle Program executed from address 000H Reset all control reg. As RESET pin is pulled low, system and all control registers are reset to initial state. After RESET pin is in high level, system will delay 256 machine cycle time, then program is executed from address 000H. 6.15.2 Reset by Watch Dog Timer STTM0.1 256 machine cycle Program executed from address 000H Reset all control regs except STTM0.1. As watch dog timer underflows, the STTM0.1 is set, in the meantime, system and all control registers, except data 1 in STTM0.1 bit is reserved, are reset to initial state, then after a delay of 256 machine cycle time program is executed from address 000H. After system reset, user can detect STTM0.1 to recognize which method of reset was used before. - 41 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 7. ABSOLUTION MAXIMUM RATINGS PARAMETER DC Supply Voltage Input/Output Voltage SYMBOL VDD−VSS VIL VIH VOL VOH Power Dissipation Operating Temperature Storage Temperature PD TOPR TSTG RATING -0.3 to +7.0 VSS − 0.3 VDD + 0.3 VSS − 0.3 VDD + 0.3 120 0 to +70 -55 to +150 mW °C °C V UNIT V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 8. ELECTRICAL CHARACTERISTICS 8.1 DC Characteristics W921E840A EPROM Type (VDD−VSS = 3.0V, FOSC = 4.0 MHz, TA = 25° C, all outputs unloaded) PARAMETER Operating Voltage Operating Current SYM. VDD IOP1 IOP2 CONDITIONS − Analog active, VDD = 5V, FOSC = 4 MHz Analog disable, VDD = 5V, FOSC = 4 MHz Analog active, VDD = 3V, FOSC = 800 KHz Analog disable, VDD = 3V, FOSC = 800 KHz Analog active, VDD = 3V, FOSC = 400 KHz Analog disable, VDD = 3V, FOSC = 400 KHz VDD = 5V, FOSC = 4 MHz VDD = 3V, FOSC = 800 KHz VDD = 3V, FOSC = 400 KHz VDD = 3V, FOSC = 32.768 KHz MIN. 2.8 − − − − − − − − − − TYP. 3.0 9 5 3.1 0.6 1.0 0.4 1.2 0.3 0.25 50 MAX. 5.5 12 7 4.3 1.8 2.0 1.2 3.5 0.7 0.5 80 UNIT V mA mA mA mA mA mA mA mA mA µA Operating Current (Active Mode) IOP3 IOP4 IOP5 IOP6 IHM1 Hold Mode Current IHM2 IHM3 IHM4 - 42 - W921E840A/W921C840 W921E840A EPROM Type DC Characteristics, continued PARAMETER Stop Mode Current SYM. ISM1 ISM2 ISM3 ISM4 CONDITIONS VDD = 5V, FOSC = 4 MHz VDD = 3V, FOSC = 800 KHz VDD = 3V, FOSC = 400 KHz VDD = 3V, FOSC = 32.768 KHz − − VDD = 3V IOH = -0.5 mA IOL = 15 mA, port P2 IOL = 0.4 mA, Other ports VIN = 0V, RESET pin VDD = 2.8 to 5.5V VDD = 2.8 to 5.5V ROW Group, RL = 5 KΩ COL/ROW − − MIN. − − − − 0.7 VDD 0 − VDD 1.0 TYP. 2.0 1.0 1.0 1.0 − − 400 − − − − − -30 150 2 − 1/256 MAX. 3.0 3.0 3.0 3.0 VDD 0.3 VDD − − 2.0 0.4 1 3.0 -23 170 3 2/3 − UNIT µA µA µA µA VDD VDD KΩ V Input High Voltage Input Low Voltage Pull-high Resistor (P2, P4, P6, PA, PB, PC, PD) VIH VIL RPH VOH VOL1 VOL2 VIL VTDC THD VTO VREF VRSL Output High Voltage Output Low Voltage Input Leakage Current DTMF Output DC Level DTMF Distortion DTMF Output Voltage Pre-emphasis D/A DC Reference Voltage D/A Resolution Voltage − − − 1.0 130 1 0 − V µA V dB mVrms dB VDD VDAC W921C840 Mask ROM Type (VDD−VSS = 3.0V, FOSC = 4.0 MHz, TA = 25° C, all outputs unloaded) PARAMETER Operating Voltage SYM. VDD CONDITIONS 4 MHz 2 MHz 400 KHz MIN. 2.4 2.0 2.0 ------- TYP. 1.0 0.7 0.4 2.5 2.2 1.5 MAX. 5.5 5.5 5.5 ------- UNIT V V V mA mA mA mA mA mA Operating Current (Active Mode) (Analog all off) IOP VDD = 3V 4 MHz 2 MHz 400 KHz 4 MHz VDD = 5V 2 MHz 400 KHz - 43 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 W921C840 Mask ROM Type, continued PARAMETER Hold Mode Current (Analog all off) Hold Mode Current (Analog all off) Stop Mode Current SYM. IHM1 IHM2 CONDITIONS VDD = 3V, FOSC = 4 MHz VDD = 5V, FOSC = 4 MHz VDD = 3V, FOSC = 32.768 KHz VDD = 5V, FOSC = 32.768 KHz MIN. ----− − 0.7 VDD 0 − VDD – 1.0 TYP. 0.5 2.0 10 50 1.0 1.0 − − 400 − − − − − -30 150 2 − 1/256 MAX. ----3.0 3.0 VDD 0.3 VDD − − 2.0 0.4 1 3.0 -23 170 3 2/3 − UNIT mA mA µA µA µA µA VDD VDD KΩ V ISM VDD = 3V VDD = 5V − − VDD = 3V IOH = -0.5 mA IOL = 15 mA, port P2 IOL = 0.4 mA, Other ports VIN = 0V, RESET pin VDD = 2.8 to 5.5V VDD = 2.8 to 5.5V ROW Group, RL = 5 KΩ Col/Row VDD = 3.0 to 5.5V Input High Voltage Input Low Voltage Pull-high Resistor (P2, P4, P6, PA, PB, PC, PD) VIH VIL RPH VOH VOL1 VOL2 Output High Voltage Output Low Voltage − − − 1.0 130 1 V µA V dB mVrms Input Leakage Current DTMF Output DC Level DTMF Distortion DTMF Output Voltage Pre-emphasis D/A DC Reference Voltage D/A Resolution Voltage VIL VTDC THD VTO dB VDD VDAC VREF VRSL − − 0 − - 44 - W921E840A/W921C840 8.2 AC Characteristics W921E840A EPROM Type (VDD−VSS = 3.0V, FOSC = 4.0 MHz, TA = 25° C, all outputs unloaded) PARAMETER SYM. FOSC1 FOSC2 CONDITIONS MIN. − − TYP. 400 800 2 3.58 4 32.768 4/FOSC − − − − MAX. − − − − − − − − − − +0.5 UNIT KHz KHz MHz MHz MHz KHz S nS nS TI % Operating Frequency FOSC3 FOSC4 FOSC5 OSCI, OSCO − − − − − 200 200 2 -0.5 Operating Sub-frequency Instruction Cycle Time Serial Port Data Ready Time Serial Port Data Hold Time RESET Active Width FSUB TI TDR TDH TRAW FROW1 XT, XT One Machine Cycle − − − FOSC = 4 Mhz, 2MHz, 800 KHz, 400 KHz FOSC = 3.58 MHz Same as ROW1 Same as ROW1 Same as ROW1 Same as ROW1 Same as ROW1 Same as ROW1 Same as ROW1 ROW 1 Frequency (697Hz) -0.92 -0.5 -0.92 -0.5 -0.92 -0.5 -0.92 -0.5 -0.92 -0.5 -0.92 -0.5 -0.92 -0.5 -0.92 − 17 − − − − − − − − − − − − − − − 2 /FOSC +0.92 +0.5 +0.92 +0.5 +0.92 +0.5 +0.92 +0.5 +0.92 +0.5 +0.92 +0.5 +0.92 +0.5 +0.92 − mS % % % % % % % ROW 2 Frequency (770 Hz) ROW 3 Frequency (852 Hz) ROW 4 Frequency (941 Hz) COL 1 Frequency (1209 Hz) COL 2 Frequency (1336 Hz) COL 3 Frequency (1477 Hz) COL 4 Frequency (1633 Hz) Oscillator Start Time FROW2 FROW3 FROW4 FCOL1 FCOL2 FCOL3 FCOL4 TOST OSCO - 45 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 W921C840 Mask ROM Type (VDD−VSS = 3.0V, FOSC = 4.0 MHz, TA = 25° C, all outputs unloaded) PARAMETER SYMBO L FOSC1 FOSC2 CONDITIONS MIN. − − TYP. 400 800 2 3.58 4 32.768 4/FOSC − − − − MAX. − − − − − − − − − − +0.5 UNIT KHz KHz MHz MHz MHz KHz S nS nS TI % Operating Frequency FOSC3 FOSC4 FOSC5 OSCI, OSCO − − − − − 200 200 2 -0.5 Operating Sub-frequency Instruction Cycle Time Serial Port Data Ready Time Serial Port Data Hold Time RESET Active Width FSUB TI TDR TDH TRAW FROW1 XT, XT One Machine Cycle − − − FOSC = 4 MHz, 2 MHz, 800 KHz, 400 KHz FOSC = 3.58 MHz Same as ROW1 Same as ROW1 Same as ROW1 Same as ROW1 Same as ROW1 Same as ROW1 Same as ROW1 ROW 1 Frequency (697Hz) -0.92 -0.5 -0.92 -0.5 -0.92 -0.5 -0.92 -0.5 -0.92 -0.5 -0.92 -0.5 -0.92 -0.5 -0.92 − 17 − − − − − − − − − − − − − − − 2 /FOSC +0.92 +0.5 +0.92 +0.5 +0.92 +0.5 +0.92 +0.5 +0.92 +0.5 +0.92 +0.5 +0.92 +0.5 +0.92 − mS % % % % % % % ROW 2 Frequency (770 Hz) ROW 3 Frequency (852 Hz) ROW 4 Frequency (941 Hz) COL 1 Frequency (1209 Hz) COL 2 Frequency (1336 Hz) COL 3 Frequency (1477 Hz) COL 4 Frequency (1633 Hz) Oscillator Start Time FROW2 FROW3 FROW4 FCOL1 FCOL2 FCOL3 FCOL4 TOST OSCO - 46 - W921E840A/W921C840 9. ADDRESSING MODE There are ROM, RAM, and Look-up table addressing modes in this chip. 9.1 ROM Addressing Mode There are two types of ROM addressing mode in this chip: • Indirect call addressing mode (0000H to 0FFFH) • Long call/jump addressing mode (0000H to 1FFFH) 9.1.1 Indirect Call Addressing Mode: (1 word/2 cycles) ROM CODE b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 decoder code i3 i2 i1 i0 B Register A Register PC b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 i3 i2 i1 i0 b3 b2 b1 b0 a3 a2 a1 a0 Instruction: CALLP 9.1.2 Long Call/Jump Addressing Mode: (2 words/2 cycles) ROM CODE b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 decoder code PC b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Instruction: CALL, JMPL, JB0, JB1, JB2, JB3, JC, JNC, JZ, JNZ 9.2 RAM Addressing Mode There are three types of RAM addressing mode in this chip: • Direct addressing mode • Indirect addressing mode • Working register addressing mode - 47 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 9.2.1 Direct Addressing Mode: (2 words/2 cycles) ROM CODE b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 decoder code RAM ADDRESS b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Instruction: MOV A, Mx; MOV B, Mx; MOV Mx, A; MOV Mx, B; ..., etc. 9.2.2 Indirect Addressing Mode: (1 word/1 cycle) W Register b1 b0 V Register b3 b2 b1 b0 U Register b3 b2 b1 b0 RAM ADDRESS b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Instruction: MOV A, @M; MOV B, @M; MOV @M, A; ..., etc. 9.2.3 Working Register Addressing Mode: (1 word/1 cycle) ROM CODE b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 decoder code RAM ADDRESS 0 0 0 1 0 0 m3 m2 m1 m0 Instruction: MOV A, WRn; MOV WRn, A; ..., etc. 9.3 Look-up Table Addressing Mode (1 word/2 cycles) There is one special function look-up table addressing mode in this chip; the instruction is TBL I and the function is shown in the following table. - 48 - W921E840A/W921C840 ROM CODE b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 I3 to I0 decoder code 0 b3 b2 b1 b0 B register b3 b2 b1 b0 A register ROM ADDRESS (0 to 4K) b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ROM CODE b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 XY b3 b2 b1 b0 OP2 b3 b2 b1 b0 OP1 ROM Code Output to Register or Port X 0 0 1 1 Y 0 1 0 1 OP2 Disable B register Port P2 Both OP1 Disable A register Disable A register Example: . . . MOV MOV TBL . . . A, #03H B, #01H 02H ; A = 0CH, B = Port2 = 0DH ORG DC . . . 213H 3DCH - 49 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 10. INSTRUCTION CODE MAP b9 = 0 b8 = 0 LSB MSB 0 NOP MOV B, A 1 MOV A, B 2 MOV A, Mx MOV B, Mx 3 MOV A, @M MOV B, @M 4 MOV A, W 5 MOV A, V 6 MOV A, U 7 8 SRL A SRH A 9 INC B INC DP A ADD A, Mx ADC A, Mx B ADD A, @M ADC A, @M C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F CLRB Mx, bit CLRB @M, bit SETB Mx, bit SETB @M, bit CLR EVF XCH A, B MOV DP, #I SOP MOV Mx, A MOV Mx, B SLL A DEC B SUB A, Mx SUB A, @M MOV @M, A MOV @M, B SLH A DEC DP SBC A, Mx SBC A, @M MOV W, A RRC A ANL A, Mx ANL A, @M MOV V, A ORL A, Mx ORL A, @M SIP MOV U, A RLC A XRL A, B XRL A, Mx XRL A, @M SET CF XCH V, CV HOLD RTN CMP A, B CMP A, MX CMP A, @M CLR CF XCH U, CU STOP RTNI ADD A, #I ADC A, #I SUB A, #I SBC A, #I ANL A, #I ORL A, #I XRL A, #I CMP A, #I 1W/1C 2W/2C Undecided 1W/2C 2W/3C 1W/3C 3W/3C - 50 - W921E840A/W921C840 b9 = 1 b8 = 0 LSB MSB 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F MOV PMx, #I JB0 JB2 JC JZ JMPL CALLP TBL JB1 JB3 JNC JNZ CALL 1W/1C 2W/2C Undecided 1W/2C 2W/3C 1W/3C 3W/3C - 51 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 b9 = 1 b8 = 1 LSB MSB 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F MOV A, #I MOV B, #I MOV Mx, #I MOV @M, #I ADD A, WRn SUB A, WRn ANL A, WRn XRL A, WRn MOV A, WRn MOV A, Px MOV B, WRn MOV B, Px MOV WRn, A MOV Px, A MOV WRn, B MOV Px, B ADC A, WRn SBC A, WRn ORL A, WRn CMP A, WRn 1W/1C 2W/2C Undecided 1W/2C 2W/3C 1W/3C 3W/3C - 52 - W921E840A/W921C840 11. INSTRUCTION SET SUMMARY Machine code Arithmetic 00 0000 1010, xxxxxxxxxx 11 0100 0 i i i 00 0000 1011 00 0001 1010, xxxxxxxxxx 11 0100 1 i i i 00 0001 1011 00 0010 1010, xxxxxxxxxx 11 0101 0 i i i 00 0010 1011 00 0011 1010, xxxxxxxxxx 11 0101 1 i i i 00 0011 1011 00 1000 i i i i 00 1001 i i i i 00 1010 i i i i 00 1011 i i i i 00 1010 0001 00 0010 1001 00 0011 1001 00 1000 0001 00 0000 1001 00 0001 1001 Logic 00 0100 1010, xxxxxxxxxx 11 0110 0 i i i 00 0100 1011 00 0101 1010, xxxxxxxxxx 11 0110 1 i i i 00 0101 1011 00 0110 1010, xxxxxxxxxx 11 0111 0 i i i 00 0110 1011 00 0111 1010, xxxxxxxxxx 11 0111 1 i i i ANL A, Mx ANL A, WRx ANL A, @M ORL A, Mx ORL A, WRx ORL A, @M XRL A, Mx XRL A, WRx XRL A, @M CMP A, Mx CMP A, WRx A ^ Mx → A A ^ WRx → A A ^ @M → A A ∨ Mx → A A ∨ WRx → A A ∨ @M → A A ⊕ Mx → A A ⊕ WRx → A A ⊕ @M → A A - Mx A - WRx A A A A A A A A A U V U V U V Z Z WZ Z Z WZ Z Z WZ Z, C Z, C 2/2 1/1 1/1 2/2 1/1 1/1 2/2 1/1 1/1 2/2 1/1 x=0… 7 x=0… 7 x=0… 7 x=0… 7 ADD A, Mx ADD A, WRx ADD A, @M ADC A, Mx ADC A, WRx ADC A,@M SUB A, Mx SUB A, WRx SUB A, @M SBC A, Mx SBC A, WRx SBC A, @M ADD A, #I ADC A, #I SUB A, #I SBC A, #I DEC A DEC B DEC DP INC A INC B INC DP A + Mx → A A + WRx → A A + @M → A A + Mx + C → A A + WRx + C → A A+ @M + C → A A - Mx → A A - WRx → A A - @M → A A - Mx - C → A A - WRx - C → A A - @M - C → A A+I→A A + I +C → A A-I→A A-I-C→A A-1→A B-1→B DP - 1 → DP A + 1→ A B+1→B DP + 1 → D P A B U V A A A A A A A A A A A A A A A A A B U V U V U V U V U V Z, C Z, C W Z, C Z, C Z, C W Z, C Z, C Z, C W Z, C Z, C Z, C W Z, C Z, C Z. C Z, C Z, C Z, C Z, C WC Z, C Z, C WC 2/2 1/1 1/1 2/2 1/1 1/1 2/2 1/1 1/1 2/2 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 ADD A, #1 SUB A, #1 x=0… 7 x=0… 7 x=0… 7 x=0…7 Mnemonic Function A B U V W Status W/C Memo - 53 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 11. Instruction Set, continued Machine code 00 0111 1011 00 0110 1001 00 0111 1001 00 1100 i i i i 00 1101 i i i i 00 1110 i i i i 00 1111 i i i i 00 1110 1111 Move 00 0000 0001 00 0000 0010, xxxxxxxxxx 00 0000 0011 00 0000 0100 00 0000 0101 00 0000 0110 00 0001 0000 00 0010 0000, xxxxxxxxxx 00 0011 0000 00 0100 0000 00 0101 0000 00 0110 0000 00 0001 0010, xxxxxxxxxx 00 0001 0011 00 0010 0001, xxxxxxxxxx 00 0011 0001 11 0000 i i i i 11 0001 i i i i 11 0010 i i i i, xxxxxxxxxx 11 0011 i i i i 11 1000 nnnn 11 1001 xxxx 11 1010 nnnn 11 1011 xxxx 11 1100 nnnn 11 1101 nnnn 11 1110 xxxx MOV A, B MOV A, Mx MOV A, @M MOV A, W MOV A, V MOV A, U MOV B, A MOV Mx, A MOV @M, A MOV W, A MOV V, A MOV U, A MOV B, Mx MOV B, @M MOV Mx, B MOV @M,B MOV A, #I MOV B, #I MOV Mx, #I MOV @M, #I MOV A, WRn MOV A, Px MOV B, WRn MOV B, Px MOV WRn, A MOV Px, A MOV WRn, B B→A Mx → A @M → A W→A V→A U→A A→B A → Mx A → @M A→W A→V A→U Mx→ B @M → B B → Mx B → @M I→A I→B I → Mx I → @M WRn → A Px → A WRn → B Px → B A → WRn A → Px B → WRn A A B A A B B U V W Z Z A B A A A A A A A A A A A A B B B B U V W Z U V W U V U V W W B U V U V B Z Z WZ WZ Z Z 1/1 2/2 1/1 1/1 1/1 1/1 Mnemonic CMP A, @M XRL A, B CMP A, B ANL A, #I ORL A, #I XRL A, #I CMP A, #I NOT A Function A - @M A⊕B→A A-B A^I→A A∨I→A A⊕I→A A-I NOT A → A A A A A A A B U U B V V W Status W Z, C Z Z, C Z Z Z Z, C Z W/C 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 XRL A, #F Memo − − − − − − − − − − − − − 1/1 2/2 1/1 1/1 1/1 1/1 2/2 1/1 2/2 1/1 1/1 1/1 2/2 1/1 1/1 1/1 − − − − − 1/1 1/1 1/1 1/1 1/1 - 54 - W921E840A/W921C840 11. Instruction Set, continued Machine code 11 1111 xxxx 10 0xxx i i i i Serial I/O 00 0100 1111 00 0101 1111 Rotate or Shift 00 0000 1000 00 0001 1000 00 0010 1000 00 0011 1000 00 0100 1000 00 0110 1000 Branch 10 1000 0aaa, aaaaaaaaaa 10 1000 1aaa, aaaaaaaaaa 10 1001 0aaa, aaaaaaaaaa 10 1001 1aaa, aaaaaaaaaa 10 1010 0aaa, aaaaaaaaaa 10 1010 1aaa, aaaaaaaaaa 10 1011 0aaa, aaaaaaaaaa 10 1011 1aaa, aaaaaaaaaa 10 1100 0aaa, aaaaaaaaaa 10 1100 1aaa, aaaaaaaaaa 10 1101 aaaa 10 1110 aaaa JB0 addr JB1 addr JB2 addr JB3 addr JC addr JNC addr JZ addr JNZ addr JMPL addr CALL addr CALLP addr TBL addr Addr → PC Addr → PC Addr → PC Addr → PC Addr → PC Addr → PC Addr → PC Addr → PC Addr → PC Addr → PC @Addr → PC A A B B Z SRL A SRH A SLL A SLH A RRC A RLC A An→An-1, 0→A3 An→An-1, 1→A3 An→An+1, 0 →A0 An→An+1, 1 →A0 A A A A Z Z Z Z Z, C Z, C 1/1 1/1 1/1 1/1 1/1 1/1 n = 3 to 1 n = 3 to 1 n = 0 to 2 n = 0 to 2 n = 3 to 1 n = 0 to 2 SOP SIP Mnemonic MOV Px, B MOV PMx, #I Function B → Px I → PMx A B B U V W Status W/C Memo − − − − 1/1 1/1 Mode of Port 2 to 6 − − *1 *1 An→An-1, A0→C, C→A3 A An→An+1, A3 →C, C→A0 A − − − − − − − − − − − 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 1/2 1/2 Indirect address call Look-up table Long jump − *1: Depends on the SRMNR, SRLNR register - 55 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 11. Instruction Set, continued Machine code Other 00 0110 1111 00 0111 1111 00 0000 0000 00 0110 1110 00 0111 1110 00 0001 11bb 00 0000 11bb, xxxxxxxxxx 00 0011 11bb 00 0010 11bb, xxxxxxxxxx 00 0111 1100 11 0000 0000 00 0100 1100, 00i i i i i i i i 00 0110 1100 00 0100 1110, i i i i i i i i i i 00 0111 1101 00 0110 1101 00 0100 1101 RTN RTNI NOP HOLD STOP CLRB @M, bit CLRB Mx, bit SETB @M, bit SETB Mx, bit CLR CF CLR A CLR EVF, #I SET CF MOV DP, #I XCH U, CU XCH V, CV XCH A, B C=1 I → DP U ↔ CU V ↔ CV A↔B A B U U V Z V W Stack → PC Stack → PC, Z, C Mnemonic Function A B U V W Status W/C Memo − Z, C 1/3 1/3 1/1 1/1 1/1 1/1 2/2 1/1 2/2 1/1 1/1 MOV A, #0 ENINT active again − − − 0 → @M(b) 0 → Mx(b) 1 → @M(b) 1 → Mx(b) 0→C 0→A A C Z U V W U V W − − − − − − − − C − − − − 2/2 1/1 2/2 1/1 1/1 1/1 Notes: DP = {W, V, U} @M = @{W, V, U} @Addr = { I, B, A} to be a target address for the CALLP instruction - 56 - W921E840A/W921C840 12. PACKAGE DIMENSIONS 40-pin DIP Dimension in Inches Dimension in mm 5.334 0.254 Symbol Min. Nom. Max. Min. Nom. Max. 0.210 0.010 0.150 0.016 0.048 0.155 0.160 0.018 0.022 0.050 0.054 0.014 2.070 D 40 21 A A1 A2 B B1 c D E E1 e1 L a 3.81 3.937 4.064 0.406 0.457 0.559 1.219 1.27 1.372 0.008 0.010 2.055 0.590 0.600 0.540 0.090 0.120 0 0.203 0.254 0.356 52.20 52.58 0.610 14.986 15.24 15.494 13.97 2.794 2.54 0.545 0.550 13.72 13.84 0.100 0.110 2.286 0.130 0.140 3.048 15 0.090 0 3.302 3.556 15 16.51 17.01 2.286 1 E eA S 1 20 0.630 0.650 0.670 16.00 Notes: E c 1 Base Plane S 2 AA L B B1 e1 A Seating Plane a eA 1. Dimension D Max & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inch. 6.General appearance spec. should be based on final visual inspection spec. 48-pin QFP Symbol Min. Nom. Max. Min. Nom. Max. Dimension in Inches 0.083 Dimension in mm 2.10 0.05 2.20 0.20 2.00 E EH e A A1 A2 b c D E e HD HE L L1 y θ 0.087 0.090 0.014 2.30 0.35 0.002 0.008 0.080 0.008 0.013 0.004 0.006 0.390 0.394 0.390 0.394 0.024 0.030 0.580 0.590 0.580 0.590 0.061 0.066 0.110 0.098 0.017 0.008 0.398 0.398 0.036 0.20 0.10 9.90 9.90 0.60 0.33 0.15 0.40 0.20 10.00 10.10 10.00 10.10 0.75 0.90 0.600 14.75 0.600 14.75 0.072 0.126 0.003 1.55 2.79 15.00 15.25 15.00 15.25 1.70 2.50 1.85 3.20 0.75 0 7 0 7 AA Seating Plane See Detail F y L L1 θ - 57 - Publication Release Date: July 1999 Revision A3 W921E840A/W921C840 Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 58 -