W921E880

W921E880A/W921C880 4-BIT MICROCONTROLLER Table of Contents1. GENERAL DESCRIPTION .........................................................................................................................3 2. FEATURES.................................................................................................................................................3 3. PIN CONFIGURATION ...............................................................................................................................6 4. PIN DESCRIPTION.....................................................................................................................................7 5. BLOCK DIAGRAM ......................................................................................................................................9 6. FUNCTIONAL DESCRIPTION .................................................................................................................10 6.1 ROM Memory Map .........................................................................................................................10 6.2 RAM Memory Map..........................................................................................................................11 6.2.1 Special Control Reg. Area..................................................................................................11 6.2.2 Stack Reg. Area.................................................................................................................12 6.2.3 Working Reg. Area ............................................................................................................12 6.3 Internal Oscillator Circuit .................................................................................................................13 6.4 Initial State ......................................................................................................................................14 6.5 Input/Output ....................................................................................................................................14 6.5.1 I/O Pull High and Open Drain Control.................................................................................17 6.6 Serial Port.......................................................................................................................................19 6.7 DTMF Generator.............................................................................................................................21 6.8 Beep Tone Generator.....................................................................................................................22 6.9 8-bit D/A Converter.........................................................................................................................23 6.10 Comparator...................................................................................................................................24 6.11 Timer 0−3......................................................................................................................................25 6.11.1 Arbitrary Waveform Generator.........................................................................................32 6.12 Interrupt.........................................................................................................................................33 6.12.1 Interrupt Control Register ..................................................................................................33 6.12.2 Interrupt Enable Flag........................................................................................................34 6.13 Operating Mode............................................................................................................................34 6.14 Initial Condition Register of EPROM Program Method .................................................................39 6.15 Reset ............................................................................................................................................39 -1- Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 7. ADDRESSING MODE ..............................................................................................................................40 7.1 ROM Addressing Mode ..................................................................................................................40 7.2 RAM Addressing Mode...................................................................................................................40 7.3 Look-up Table Addressing Mode (1 Word/2 Cycles) ......................................................................42 8. SPECIAL CONTROL REG. FORMAT ......................................................................................................43 9. INSTRUCTION MAP.................................................................................................................................45 10. INSTRUCTION SETS .............................................................................................................................48 11. ABSOLUTE MAXIMUM RATINGS .........................................................................................................51 12. ELECTRICAL CHARACTERISTICS.......................................................................................................52 12.1 AC Characteristics ........................................................................................................................52 12.2 DC Characteristics........................................................................................................................54 13. PACKAGE DIMENSIONS.......................................................................................................................56 80-pin QFP ............................................................................................................................................56 -2- W921E880A/W921C880 1. GENERAL DESCRIPTION The W921E880A/W921C880 are 4-bit micro-processor fabricated by CMOS process. With a single channel DTMF generator, an 8-bit D/A converter circuit, a built in four by one channel comparator circuit and four multi-function timers. The excellent memory structure, 8K super EPROM in W921E880A and 8K mask ROM in W921C880 for program code and 1536 x 4 bit RAM minimize the need for external memory devices. The W921E880A/W921C880 provides good solution for consumming application, especially for telecommunication design with few external components. Using the serial transmit/receive function, the W921E880A/W921C880 can interface with the Winbond LCD driver IC using the serial control circuit. 2. FEATURES Memory • ROM (Super EPROM): 8K × 10 bits • RAM: 1536 × 4 bits − − − − − 64 × 4 bit Special registers 16 × 4 bit Working registers 128 × 4 bit General registers 304 × 4 bit Multi-purpose registers4 bit serial buffer registers 512 × 4-bit × 2 banks Dual-clock Operation • Crystal or RC for the main system clock: RC up to 4 MHz Crystal for 400 K, 800 K, 2 M, 3.58 M, 4 MHz • Crystal for subsystem clock: 32.768 KHz I/O Pins • 32 bidirectional and individually controllable I/O lines: − P0 Port: P0.0−P0.3 large drive current Pins − P1 Port: P1.0−P1.3 large drive current Pins − P2 Port: P2.0−P2.3 large sink current pins and open drain option − P3 Port: P3.0−P3.3 multi-function I/O − P4 Port: P4.0−P4.3 open drain and pull high resistor option, multi-function I/O − P5 Port: P5.0−P5.3 multi-function I/O − P6 Port: P6.0−P6.3 open drain and pull high resistor option, multi-function I/O − P7 Port: P7.0−P7.3 large sink current pins and open drain option • 32 bidirectional I/O lines: − P8 Port: P8.0−P8.3 large drive current pins − P9 Port: P9.0−P9.3 large sink current pins and open drain option Publication Release Date: July 1999 Revision A3 -3- W921E880A/W921C880 − PA Port: PA.0−PA.3 open drain and pull high resistor option − PB Port: PB.0−PB.3 open drain and pull high resistor option − PC Port: PC.1−PC.3 open drain and pull high resistor option − PD Port: PD.0−PD.3 open drain and pull high resistor option − PE Port: PE.0−PE.3 − PF Port: PF.0−PF.3 Interrupt • Four External sources: INT0 ( P4.3 ) P4 Port ( P4.0−P4.2 ) • Six Internal sources: Timer 0 Timer 1 Timer 2 Timer 3 Comparator Serial Port Timer/Counter • Timer 0: 2−19 order divider (double source) Auto-reload timer Watch-dog timer • Timer 1: 2−19 order divider Auto-reload timer Arbitrary waveform generator External event counter • Timer 2: 2−19 order divider Auto-reload timer Arbitrary waveform generator Period/Pulse width measurement function • Timer 3: 2−19 order divider Auto-reload timer Operating Mode (System Clock) • Normal mode: System clock operating • HOLD mode: no operation except for oscillator (System clock stops only) • STOP mode: no operation including oscillator -4- W921E880A/W921C880 DTMF Generator and 8-bit D/A Converter • One Channel DTMF Generator • One Channel 8-bit D/A Converter Voltage Comparator • Four by one Channel Voltage Comparator Serial I/O Interface • Clock Synchronous multi-nibbles Serial Transmitter/Receiver Interface Stack • 8-bit Stack Pointer Address Mode • ROM: Indirect call addressing mode Long jump/call addressing mode • RAM: Direct addressing mode Indirect addressing mode Working reg. addressing mode • Look-up table addressing mode Instruction Sets • 117 Instruction sets Operating Voltage • 2.8 to 5.5V operating voltage for W921E880A EPROM Type • 2.4 to 5.5V operating voltage for W921C880 Mask ROM Type Package Type • Packaged in 80-pin QFP -5- Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 3. PIN CONFIGURATION D B T T NM GCF P x C . 3 P x C . 2 P x C . 1 P x C . 0 P x F . 3 P x F . 2 P x F . 1 P PPP x xxx VEEE F . D. . . 0D321 P x E . 0 PxD.0 PxD.1 PxD.2 PxD.3 RESET OSCO OSCI VDD Px0.0 Px0.1 Px0.2 Px0.3 Px1.0 Px1.1 Px1.2 Px1.3 Px2.0 Px2.1 Px2.2 Px2.3 Px3.0/ANI0 Px3.1/ANI1 Px3.2/ANI2 Px3.3/ANI3 8 777777777 76 6666 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 64 63 2 62 3 61 4 60 5 59 6 58 7 57 8 56 9 55 10 54 11 53 12 W921E880A 52 13 / W921C880 51 14 50 15 49 16 48 17 47 18 46 19 45 20 44 21 43 22 42 23 24 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 41 5678901234567890 NX/ NPPP CT XCx x x 444 T ... 012 PNVPPP x CSx x x 4 S777 ... . 3 012 / I N T 0 P x 7 . 3 P x 5 . 0 / T M 1 P x 5 . 1 / T M 2 PxB.3 PxB.2 PxB.1 PxB.0 NC PxA.3 PxA.2 PxA.1 PxA.0 Px9.3 Px9.2 Px9.1 Px9.0 Vss Px6.3/RCLK Px6.2/RDATA Px6.1/WCLK Px6.0/WDATA Px8.3 Px8.2 Px8.1 Px8.0 Px5.3/DAOUT Px5.2/Vref -6- W921E880A/W921C880 4. PIN DESCRIPTION SYMBOL OSCI OSCO I/O I O * * * * FUNCTION Main-oscillator input pin with internal cap. Main-oscillator output pin. I/O port A. I/O port B. I/O port C. PC.3 can be as 32.768 KHz output buffer. I/O port D. I/O port E. I/O port F. I/O with large drive current pin. I/O with large drive current pin. I/O with large sink current pin. I/O port 3 or Analog input pins (ANI0−ANI3). PA.0−PA.3 PB.0−PB.3 PC.0−PC.3 PD.0−PD.3 PE.0−PE.3 PF.0−PF.3 P0.0−P0.3 P1.0−P1.3 P2.0−P2.3 P3.0/ANI0 | P3.3/ANI3 P4.0 P4.1 P4.2 P4.3/INT0 P5.0/TM1 P5.1/TM2 P5.2/VREF P5.3/DAOUT P6.0/WDATA P6.1/WCLK P6.2/RDATA P6.3/RCLK P7.0−P7.3 P8.0−P8.3 P9.0−P9.3 I/O I/O I/O I/O I/O I/O I/O I/O > I/O I/O * * * * I/O I/O I/O I/O I/O port 4.0 or the port P4.0 interrupt input pin. I/O port 4.1 or the port P4.1 interrupt input pin. I/O port 4.2 or the port P4.2 interrupt input pin. I/O port 4.3 or the INT0 input pin. I/O port 5.0 or the control pin of the TIMER 1. I/O port 5.1 or the control pin of the TIMER 2. I/O port 5.2 or the Vref input pin of the comparator. I/O port 5.3 or the output pin of the 8bit D/A. I/O port 6.0 or the data output pin of the serial interface. I/O port 6.1 or the clock I/O pin of WDATA. I/O port 6.2 or the data input pin of the serial interface. I/O port 6.3 or the clock I/O pin of RDATA. I/O with large sink current pin. I/O with large drive current pin. I/O with large sink current pin. I/O I/O I/O I/O * * * * I/O I/O I/O I/O I/O > I/O > I/O -7- Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 4. Pin Description, continued SYMBOL DTMF BTG RESET VDD VSS XT XT Notes: I/O O O I I I I O FUNCTION Dual tone multi-frequency output pin. Beep Tone Generator output pin. Reset input pin with low active. Positive power supply input pin. Negative power supply input pin. 32.768 KHz subsystem clock input pin with internal cap. 32.768 KHz subsystem clock output pin. * open drain and pull high resistor option by software > open drain option by software -8- W921E880A/W921C880 5. BLOCK DIAGRAM PORT P0 P0.0-P0.3 PROGRAM COUNTER PORT P1 Co-V REG. Co-U REG. P1.0-P1.3 PORT P2 EPROM 10 * 8K W REG. V REG. U REG. P2.0-P2.3 PORT P3 DECODER & CONTROL RESET STACK POINTER ALU PORT P5 B REG. A REG. PORT P4 P3.0-P3.3 P4.0-P4.3 P5.0-P5.3 RAM 4 * 1536 PORT P6 PORT MODE REGISTER P6.0-P6.3 PORT P7 PE.0-PE.3 PORT PE PF.0-PF.3 PORT PF PORT P9 PORT P8 P7.0-P7.3 P8.0-P8.3 P9.0-P9.3 PORT PD XT OSCILLATOR PD.0-PD.3 XT OSCI OSCO and SYSTEM PRESCALER TIMER 0 TIMER 1 TIMER 2 TIMER 3 PORT PA PA.0-PA.3 PORT PB PB.0-PB.3 PORT PC VDD VSS DTMF GENERATOR P3.0(ANI0) P3.1(ANI1) P3.2(ANI 2) P3.3(ANI3) P5.2/VREF PC.0-PC.3 DTMF + DAMSB BEEP TONE GENERATOR BTG DALSB D/A CONVERTOR P5.3/DAOUT -9- Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 6. FUNCTIONAL DESCRIPTION 6.1 ROM Memory Map 0000H Interrupt Area 000FH 0010H Indirect Call and Look-up Table Area Long Call/Jump Area 0FFFH 1000H 1FFFH 8192 x 10-bit 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH JMPL Instruction (RESET) XXXXX XXXXX JMPL Instruction (INT0) XXXXX XXXXX JMPL Instruction (TM 0) XXXXX XXXXX JMPL Instruction (TM1) XXXXX XXXXX JMPL Instruction (TM 2) XXXXX XXXXX JMPL Instruction (Comparator / TM 3) XXXXX XXXXX JMPL Instruction (P4.0 to P4.2 - 3 PINS) XXXXX XXXXX (SERIAL PORT) JMPL Instruction XXXXX XXXXX PRIORITY: RESET > INT0 > TM0 > TM1 > TM2 > ( Comparator / TM3 ) > P4.0 to P4.2 > SERIAL PORT - 10 - W921E880A/W921C880 6.2 RAM Memory Map 000H 000 SPECIAL CONTROL REG. 03FH 040H 063 064 WORKING REG. 04FH 050H 07FH 080H 079 080 SERIAL CONTROL REG. STACK REG. OR GENERAL REG. 127 128 STACK REG. (40H - FFH) 0FFH 100H 255 256 SERIAL CONTROL REG. OR GENERAL REG. 17FH 180H 383 384 SERIAL CONTROL REG. (50H - 14EH) GENERAL REG. GENERAL REG. 1FFH 200H 511 512 BANK0 BANK1 3FFH 1023 6.2.1 Special Control Reg. Area There are 64 reg. × 4 bits in the special control register area. All control registers such as the DTMF Control Reg., System Clock Control Reg. ...etc. are in this area. Please refer to the Spesial Control Reg. Format. Bank Select Reg. BKSR REG: (ADDRESS = 001H) (Default data = 0H) b3 b2 b1 b0 b1 0 0 1 Reserved Reserved 1 b0 0 1 0 1 BANK NO. 0 1 Reserved Reserved The Bank Select Reg. can select the active bank. The memory size of each bank is 512*4 bits. Bank 0 and bank 1 are normal SRAM. - 11 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 6.2.2 Stack Reg. Area There are 8 bit stack pointers in this chip located at addresses 040H − 0FFH. After a power on reset the stack pointer will be set to 0FFH. The stack pointer will be decreased by 4 each time a CALLP or interrupt occurs, and will be increased by 4 each time the RTN or RTNI instruction is executed. The format of the stack pointer is shown in the following table. 0F8H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH Z PC11 PC7 PC3 Z PC11 PC7 PC3 C PC10 PC6 PC2 C PC10 PC6 PC2 PC9 PC5 PC1 PC9 PC5 PC1 PC12 PC8 PC4 PC0 PC12 PC8 PC4 PC0 STACK 1 STACK 0 6.2.3 Working Reg. Area The area located from 040H to 04FH is known as the Working Reg. The instruction MOV WRn, A or MOV A, WRn can move the A reg. data to the Working reg. or move the Working reg. data to the A reg. directly within 1 word/1 machine cycle. Unlike other direct instructions such as MOV Mx, A or MOV A, Mx, these instructions use 2 words/2 machine cycles. Therefore, the Working reg. can reduce the ROM program memory size and improve the control speed of the application circuit. For arithmetic and logic operations only WR0−WR7 are available, that is only 040H to 047H can be active. The instructions are as follow: ADD ADC SUB SBC ANL ORL XRL CMP A, A, A, A, A, A, A, A, WRx WRx WRx WRx WRx WRx WRx WRx where x = 0 -- 7. - 12 - W921E880A/W921C880 6.3 Internal Oscillator Circuit There are dual clocks in this chip, one is a high speed clock, the other a low speed clock. The block diagram is shown below: f TM0 TM0 TM1 TM2 TM3 f SYS1 MUX0 f SYS0 MUX0 f TM1 MUX1 f TM2 MUX2 f TM3 MUX3 SYSCCR.0 11-bit Prescaler f SYS System Clock f OSC (1/4) SYSCCR.3 f1 f2 * fH OSCI Crystal Type or RC Type OSCO Enable (SYSCCR.1) 5-bit Prescaler 2-bit Scaler (1/4) fL 1-bit Scaler (1/2) XT Crystal Type XT Enable (SYSCCR.2) * Default: cystal type, f1=f H, f2=fL (refer to 6.14 INI register) The format of the system clock control reg. (SYSCCR) is shown below: SYSCCR REG: ( ADDRESS = 000H, Default data = 0H) b3 b2 b1 b0 0 : f TM0 = fsys0 1 : f TM0 = fsys1 0 : f H enable 1 : f H disable 0:f 1:f L L enable disable 1 2 0 : fosc = f 1 : fosc = f The W921E880A/W921C880 provides a crystal or RC oscillation circuit selected by bit0 of the INI register (refer to 6.14 INITIAL CONDITION Section) to generate the system clock through external connections. If a crystal oscillator is used, a crystal or ceramic resonator must be connected to OSCI and OSCO , and the capacitor must be connected if an accurate frequency is needed. The oscillator configuration is shown as follows. OSCI or OSCO Crystal Type OSCO RC Type OSCI - 13 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 6.4 Initial State The W921E880A/W921C880 is reset either by power-on reset or by using the external RESET pin. The initial state of the W921E880A/W921C880 after the reset function is executed is described below. The EVF interrupt request signal register value is random, so user must do CLR EVF, #11111111b instruction to clear all interrupt request signals after power-on reset. Program counter (PC) Stack pointer Special function registers TM0, TM1, TM2, TM3 input clock TM0, TM1, TM2, TM3 contents Input/Output PM registers DTMF output EVF interrupt request signal register 0000H 0FFH Refer to special control register table FOSC/8 0FFH Input mode 1111B Disable (H-Z) Random 6.5 Input/Output There are 64 I/O pins (4 pins × 16 ports) including 12 large drive current pins, and 12 large sink current pins in this chip. All the I/O pins will remain in an input mode after a power on reset. The input or output status of port 0 to port 7 can be controlled by the port mode register PMx, where x = 0 to 7. A zero indicates the corresponding pin is an output, a one indicates the relative pin is an input. For example, MOV PM0, #0101B sets P0.0 and P0.2 as inputs and P0.1 and P0.3 as outputs. The I/O instructions cannot affect the I/O status in Port 0 to Port 7. The input or output mode of port 8 to port F only can be decided by I/O instructions. For example, MOV A, Px will change Px to input mode and MOV Px, A will change it to output mode. The I/O instructions are described as follows: MOV MOV MOV MOV A, Px B, Px Px, A Px, B input Port x to A reg. input Port x to B reg. output A reg. data to Port x. output B reg. data to Port x. * P0.0−P0.3: * P1.0−P1.3: Four 10 mA drive current pins Normal I/O pins only. Four 10 mA drive current pins Normal I/O pins only. Normal function is the same as port P0 Four 15 mA sink current pins Normal I/O pins only. Normal function is the same as port P0 * P2.0−P2.3: - 14 - W921E880A/W921C880 * P7.0−P7.3: Four 15 mA sink current pins Normal I/O pins only. Normal function is the same as port P0 Multi-function I/O pins. Normal function is the same as port P0 Special function input pins P3IO REG: (ADDRESS = 00FH) (Default data = 0H) b3 b2 b1 b0 0: Normal I/O P3.0 1: Analog input pin 0 -- ANI0 0: Normal I/O P3.1 1: Analog input pin 1 -- ANI1 0: Normal I/O P3.2 1: Analog input pin 2 -- ANI2 0: Normal I/O P3.3 1: Analog input pin 3 -- ANI3 * P3.0−P3.3: * P4.0−P4.3: Multi-function I/O pins. Normal function is the same as port P0 Special function input pins P4IO REG: (ADDRESS = 010H) (Default data = 0H) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: Normal I/O P4.0, interrupt disable Interrupt port P4.0 Normal I/O P4.1, interrupt disable Interrupt port P4.1 Normal I/O P4.2, interrupt disable Interrupt port P4.2 Normal I/O P4.3, interrupt disable INT0 - 15 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 * P5.0−P5.3: Multi-function I/O pins. Normal function is the same as port P0 Special function P5IO REG: (ADDRESS = 011H) (Default data = 0H) b3 b2 b1 b0 0: Normal I/O P5.0 1: Work as the timer 1 control pin 0: Normal I/O P5.1 1: Work as the timer 2 control pin 0: Normal I/O P5.2 1: Work as the Vref input pin of the comparator 0: Normal I/O P5.3 1: Work as the output pin of D/A converter (DAOUT) * P6.0−P6.3 : Multi-function I/O pins. Normal function is the same as port P0 Special function P6IO REG: (ADDRESS = 012H) (Default data = 0H) b3 b2 b1 b0 0: Normal I/O P6.0 1: Work as the data output pin of the WCLK pin (WDATA) 0: Normal I/O P6.1 1: W ork as the clock I/O pin of the WDATA pin (WCLK) 0: Normal I/O P6.2 1: Work as the data input pin of the RCLK pin (RDATA) 0: Normal I/O P6.3 1: Work as the clock I/O pin of the RDATA pin (RCLK) * P8.0−P8.3 : Four 10 mA drive current pins Normal I/O pins only. Normal function is the same as port P0 Four 15 mA sink current pins Normal I/O pins only. Normal function is the same as port P0 Normal I/O pins only. Normal function is the same as port P0 Normal I/O pins only. * P9.0−P9.3 : * PA.0−PA.3 : * PB.0−PB.3 : - 16 - W921E880A/W921C880 Normal function is the same as port P0 * PC.0−PC.3: * PD.0−PD.3: * PE.0−PE.3: * PF.0−PF.3: Normal I/O pins only. Normal function is the same as port P0 Normal I/O pins only. Normal function is the same as port P0 Normal I/O pins only. Normal function is the same as port P0 Normal I/O pins only. Normal function is the same as port P0 6.5.1 I/O Pull High and Open Drain Control Some of the above I/O ports can be set up with a pull-high resistor or as an open drain. The user can program the I/O through the special register so that the I/O can have a pull-high resistor or open drain characteristics. All pull-high resistors in the following table are 400 KΩ in a 3.0 voltage test condition. After a power on reset the following special reg. will all reset to "0000". * P4.0−P4.3: P4PH REG: (ADDRESS = 003H) (Default data = 0H) b3 b2 b1 b0 0: P4.0 without pull-high resistor 1: P4.0 with pull-high resistor 0: P4.1 without pull-high resistor 1: P4.1 with pull-high resistor 0: P4.2 without pull-high resistor 1: P4.2 with pull-high resistor 0: P4.3 without pull-high resistor 1: P4.3 with pull-high resistor P4TP REG: (ADDRESS = 004H) (Default data = 0H) b3 b2 b1 b0 0: P4.0 work as CMOS type 1: P4.0 work as Open-drain type 0: P4.1 work as CMOS type 1: P4.1 work as Open-drain type 0: P4.2 work as CMOS type 1: P4.2 work as Open-drain type 0: P4.3 work as CMOS type 1: P4.3 work as Open-drain type - 17 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 * P6.0−P6.3: P6PH REG: (ADDRESS = 005H) (Default data = 0H) b3 b2 b1 b0 0: P6.0 without pull-high resistor 1: P6.0 with pull-high resistor 0: P6.1 without pull-high resistor 1: P6.1 with pull-high resistor 0: P6.2 without pull-high resistor 1: P6.2 with pull-high resistor 0: P6.3 without pull-high resistor 1: P6.3 with pull-high resistor P6TP REG: (ADDRESS = 006H) (Default data = 0H) b3 b2 b1 b0 0: P6.0 work as CMOS type 1: P6.0 work as Open-drain type 0: P6.1 work as CMOS type 1: P6.1 work as Open-drain type 0: P6.2 work as CMOS type 1: P6.2 work as Open-drain type 0: P6.3 work as CMOS type 1: P6.3 work as Open-drain type * PA, PB, PC, PD: PABCDPH REG: (ADDRESS = 007H) (Default data = 0H) b3 b2 b1 b0 0: PA(4PINS) without pull-high resistor 1: PA(4PINS) with pull-high resistor 0: PB(4PINS) without pull-high resistor 1: PB(4PINS) with pull-high resistor 0: PC(4PINS) without pull-high resistor 1: PC(4PINS) with pull-high resistor 0: PD(4PINS) without pull-high resistor 1: PD(4PINS) with pull-high resistor - 18 - W921E880A/W921C880 PABCDTP REG: (ADDRESS = 008H) (Default data = 0H) b3 b2 b1 b0 0: PA(4PINS) work as CMOS type 1: PA(4PINS) work as Open-drain type 0: PB(4PINS) work as CMOS type 1: PB(4PINS) work as Open-drain type 0: PC(4PINS) work as CMOS type 1: PC(4PINS) work as Open-drain type 0: PD(4PINS) work as CMOS type 1: PD(4PINS) work as Open-drain type * P2, P7, P9: P279TP REG: (ADDRESS = 00DH) (Default data = 0H) b3 b2 b1 b0 0: P2(4PINS) work as CMOS type 1: P2(4PINS) work as Open-drain type 0: P7(4PINS) work as CMOS type 1: P7(4PINS) work as Open-drain type 0: P9(4PINS) work as CMOS type 1: P9(4PINS) work as Open-drain type 0: PC.3 work as normal I/O port (CMOS type) 1: PC.3 work as 32.768 KHz output buffer (Open-drain Type) 6.6 Serial Port The W921E880A/W921C880 has a clock-synchronous serial interface which transmits or receives 8bit data as default. The user can program the P6IO register to select port P6 as the serial port. The serial transmitter/receiver function can be operated with a multi-nibble function where the LSB of every nibble is being transmitted/received first. The serial transmitted/received data is come from or stored in the serial buffer registers (address 050H to 14EH). The number of nibbles to be transmitted/received is decided by the serial MSB nibble register (SRMNR, address = 00AH) and the serial LSB nibble register (SRLNR, address = 009H). SRMNR register: (address = 00AH, default data = 0H) b3 b2 b1 b0 SRLNR register: (address = 009H, default data = 2H) b3 b2 b1 b0 The default data in the SRMNR and SRLNR registers are 0 and 2 respectively which means the default serial interface is used to transmit/receive 8-bit data serially. As soon as these two registers are programmed and the instructions such as SOP or SIP are executed, the serial transmitter/receiver multi-nibble function will be performed. The transmitted/received number will be Publication Release Date: July 1999 Revision A3 - 19 - W921E880A/W921C880 automatically increased by one when each nibble is transmitted/received until the number is equal to the value in the SRLNR, SRMNR registers. Even if the HOLD instruction is executed, the SOP or SIP function will continue to execute until completion of the transmitter/receiver function. However, execution of the STOP instruction will stop all serial transmitter/receiver functions. Whether transceiver data will be latched on the rising or falling edge of the clock is determined by the serial clock inverter control register (SRINV, address = 00CH). Before the SOP or SIP instructions are executed the SRINV register must be set to the exact value. Once both the SRINV.3 and SRINV.2 are clear, the serial transceiver function will be forced to reset to initial status immediately. SRINV register: (address = 00CH, default data = 0H) b3 b2 b1 b0 0: Serial data latch at WCLK/RCLK rising edge (normal high) 1: Serial data latch at WCLK/RCLK falling edge (normal low) 0: WCLK and RCLK pins work as the internal clock output pin 1: WCLK and RCLK pins work as the external clock input pin 0: RCLK and RDATA disable (H-Z) 1: RCLK and RDATA enable 0: WCLK and WDATA disable (H-Z) 1: WCLK and WDATA enable The serial interface configuration is shown below: To Port P6 Normal I/O Register P6.3 P6.2 P6.1 P6.0 Port P6 Pull-High Resisters VDD WDATA WCLK SRINV.3 RDATA RCLK SRINV.2 SCLK P6IO.3 P6IO.2 P6IO.1 P6IO.0 P6PH To Port P6 Clock Source and Latch Control Circuit SDATA Serial Clock Speed Control Circuit f SYS System Clock 1/4 High Speed Clock Serial/Parallel I/O Buffer Serial Buffer Registers 050H 14EH - 20 - W921E880A/W921C880 The internal serial clock can be controlled by the serial clock speed control register (SRSPC) is described as follows: SRSPC register: (address = 00BH, default data = 0H) b3 b2 b1 b0 b3 b2 b1 b0 Input frequency 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Reserved fsys/4 Hz fsys/8 Hz fsys/16 Hz fsys/32 Hz fsys/64 Hz fsys/128 Hz fsys/256 Hz fsys/512 Hz fsys/1024 Hz fsys/2048 Hz Normally the WCLK or RCLK pin will remain in a high state and the serial data will be latched at the rising edge of the WCLK or RCLK signal, but the serial clock inverter control register (SRINV) will invert the above function. In this case the WCLK or RCLK pin will remain in a low state and the serial data will be latched at the falling edge of the the WCLK or RCLK signal. The transmitting serial clock can come from WCLK or RCLK depending upon which one is enabled. If the serial function is disabled, it will cause the relative pins to be in a high impedance state and it will not affect the contents of the serial buffer registers (start at address 050H). 6.7 DTMF Generator One channel of the dual tone multi-frequency (DTMF) generator is in this chip. The exact frequency must be decided by the OSCCTR REG to get the exact DTMF generator. OSCCTR REG: (ADDRESS = 013H, Default data = 0H) b3 Reserved. b2 b1 b0 b2 0 0 0 0 1 1 b1 0 0 1 1 0 0 b0 0 1 0 1 0 1 Osc. Selection 400 KHz 800 KHz 2 MHz 4 MHz Reserved 3.58MHz There are four bits in the DTMF REG; the functions are described in the following table - 21 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 DTMF REG: (ADDRESS = 014H), (Default data = 0H) b3 b2 b1 b0 X X X X 0 0 1 1 X0 X0 X1 X1 0 1 0 1 0 1 0 1 FUNCTION DESCRIPTION Col 1 ( 1209 Hz ) output Col 2 ( 1336 Hz ) output Col 3 ( 1477 Hz ) output Col 4 ( 1633 Hz ) output Row 1 ( 697 Hz ) output Row 2 ( 770 Hz ) output Row 3 ( 852 Hz ) output Row 4 ( 941 Hz ) output XX XX XX XX Note : X --- Don't care The output of the ROW and COL is controlled by the R/C CONTROL REG. RCCTL REG: (ADDRESS = 015H) (Default data = 0H) b3 b2 b1 b0 0: ROW frequency disable 1: ROW frequency enable 0: COL frequency disable 1: COL frequency enable 0: DTMF disable (H-Z) 1: DTMF enable Reserved The following table shows the DTMF keypad and its frequency. C1 1 4 7 * C2 2 5 8 0 C3 3 6 9 # C4 A B C D R1 R2 R3 R4 KEY FREQUENCY R1 697 Hz R2 770 Hz R3 852 Hz R4 941 Hz C1 1209 Hz C2 1336 Hz C3 1477 Hz C4 1633 Hz 6.8 Beep Tone Generator There are 4 kinds of frequency outputs from the BTG pin that operate as a beep tone generator. Control of the OSCCTR REG. (ADDR = 013H) and the BTGR REG. (ADDR = 03FH) will enable the BTG pin to output the special frequencies -- 2 KHz, 1 KHz, 630 Hz or 520 Hz. - 22 - W921E880A/W921C880 BTGR REG: ADDRESS = 03FH) (Default data = 0H) b3 b2 b1 b0 b1 0 0 1 1 b0 0 1 0 1 Output-Freq. 2 KHz 1 KHz 630 Hz 520 Hz Reserved 0: Beep Tone Generator disable (Keep in High state) 1: Beep Tone Generator enable If the Beep Tone Generator is disabled by setting the BTGR REG. bit3 to "0" or after a power on reset, the BTG output pin will remain in a high state. 6.9 8-bit D/A Converter The content of 8-bit D/A converter is divided into D/A MSB data register (DAMSB) and D/A LSB data register (DALSB). The block diagram is shown below. ANIMUX Register Vani ANI3 ANI2 ANI1 ANI0 Vpos Vrang = 1.5 V or (2/3)VDD DACTL.2 COMPTR.1 Vneg COMPTR.2 COMPTR.3 8bit D/A Converter Vref P5.2/Vref P5.3/DAOUT DAMSB 4-bit Register DALSB 4-bit Register ù D/A Converter Control Register: DACTL register: (ADDRESS = 016H, Default data = 0H) b3 b2 b1 b0 0: D/A converter stop 1: D/A converter start Reserved Reserved 0:Vrang = (2/3)VDD 1:Vrang = 1.5V - 23 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 When the DACTL register bit0 is set by software, the 8-bit D/A converter starts converting. The only way to disable the D/A converter is to reset the bit0 of the DACTL register using the software control. The analog signal will be output to the P5.3 pin in this chip if the I/O port works as the D/A output pin. The power source of the D/A converter can be selected from the (2/3)VDD or 1.5V by programming the DACTL register bit2. ù D/A Converter LSB Data Register DALSB register: (ADDRESS = 017H, Default data = 0H) b3 b2 b1 b0 ù D/A Converter MSB Data Register DAMSB register: (ADDRESS = 018H, Default data = 0H) b3 b2 b1 b0 6.10 Comparator There are 4-channel inputs to the comparator negative (can be programmed to positive) terminal, but only one channel will be active at a time. The control register is shown below. ANIMUX register: (ADDRESS = 019H, Default data = 0H) b3 b2 b1 b0 b1 b0 00 01 10 11 Enable ANI0 ANI1 ANI2 ANI3 Reserved Reserved COMPTR register: (ADDRESS = 01AH, Default data = 4H) b3 b2 b1 b0 0: Compare stop 1: Compare start 0: Vneg = Vref; Vpos = Vani 1: Vneg = Vani; Vpos = Vref (Read Only) 0: Vpos voltage < Vneg voltage 1: Vpos voltage >= Vneg volatge 0: Vref = P5.2/Vref 1: Vref = P5.3/DAOUT - 24 - W921E880A/W921C880 When the COMPTR register bit0 is set by software, the comparator starts and the bit2 of the COMPTR register will be set to "1" initially. The comparing result will be stored in the bit2 of the COMPTR register and will keep this value until the bit0 of the COMPTR register is set again. The only way to disable the comparator is to reset the bit0 of the COMPTR register using the software control. The initial value of the COMPTR bit2 is "1", the falling edge of COMPTR bit2 will cause the comparator interrupt to become active if the enable flag of the comparator interrupt is set. The bit3 of the COMPTR register controls the source of Input voltage reference (Vref). The input reference voltage (Vref) comes from external pin (P5.2/Vref) or D/A converter analog signal output (P5.3/DAOUT). 6.11 Timer 0− 3 There are four timers (TM0, TM1, TM2 and TM3) in this chip, and all are initialized at any time by writing data into the TM0, TM1, TM2 and TM3 Set Reg. TM0 can perform the following function: 1. 2−19 order divider 2. Auto-reload Timer 3. Watch-dog timer High Speed Clock TM0 Control Register System Clock 1/4 f SYS 11-bit Prescaler Interrupt Control Register TM0 Interrupt Logic fSYS0 f SYS1 f TM0 8 Order Divider Watch Dog Timer TM0 Set Register (8 bits) TM0 Control Logic 1/8 f SUB 5-bit Prescaler Low Speed Clock TM0 Low Speed Register - 25 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 The format of the Timer 0 Control Register is described as follows: TM0CR REG: (ADDRESS = 020H) (Default data = 0H) b3 b2 b1 b0 b1 0 0 1 1 Reserved Reserved b0 0 1 0 1 Input frequency (fsys0) fsys/2 fsys/256 fsys/1024 fsys/2048 Hz Hz Hz Hz The format of the Timer 0 Low Speed Register is described as follows: TM0LSR REG: (ADDRESS = 024H) (Default data = 0H) b3 b2 b1 b0 b1 0 0 Reserved Reserved 1 1 b0 0 1 0 1 Input frequency (fsys1) fsub/2 fsub/8 fsub/16 fsub/32 Hz Hz Hz Hz The Timer 0 Set REG. is divided into TIMER 0 MSB DATA REG.(TM0MSB REG, ADDRESS = 021H, Default = 0FH) and TIMER 0 LSB DATA REG.(TM0LSB REG, ADDRESS = 022H, Default = 0FH). Timer 0 will underflow when Timer 0 Set REG. goes from 00H to 0FFH. The value in the TM0MSB and TM0LSB will be auto reloaded to the Timer 0 Set REG. when the STTM0 bit2 is set. Timer 0 will decrease by 1 continuously during each clock transition after the timer has started. At any time, if the STTM0 bit3 goes from 0 to 1 (disable to enable) in the timer mode, the TM0MSB and TM0LSB will be auto reloaded to the Timer 0 Set Reg. again and the Timer 0 is restarted. Timer 0 will stop operating while the STTM0 bit3 is reset to 0. The Timer 0 starts to count when the STTM0 REG. bit3 is set. When Timer 0 underflows, the STTM0 bit3 will be reset by hardware to stop Timer 0 if the auto-reload is disabled, but the STTM0 bit3 will not be reset if the auto-reload is enabled. When the Timer 0 function is performed, the watch-dog timer function will be disabled automatically. - 26 - W921E880A/W921C880 The format of the Status of Timer 0 Register is shown as follows: STTM0 REG: (ADDRESS = 023H) (Default data = 0H) b3 b2 b1 b0 0:Timer 0 normal function select 1:Watch-dog timer select 0:WDT not underflow 1:WDT underflow 0:Timer 0 auto-reload disable 1:Timer 0 auto-reload enable 0:Timer 0 stop 1:Timer 0 start If Timer 0 works as a Watch Dog Timer, then bit1 of the STTM0 REG will be set when WDT underflows. Meanwhile, the system is reset just as in a power on reset except for the STTM0 bit1. The WDT (STTM0 bit1) will only be reset to zero during a power on reset or during the RAM write mode. In the timer mode or event counter mode a time out will be the programming data subtract 1 ([TM0MSB,TM0LSB]-1). It is the same for timers TM1, TM2 and TM3. TM1 can perform the following functions: 1. 2−19 order divider 2. Auto-reload timer. 3. Arbitrary waveform generator. 4. Event counter. System Clock 1/4 f SYS 11-bit Prescaler f TM1 TM1 Read Register Interrupt Control Register High Speed Clock TM1 Control Register 2 8 Order Divider TM1 Interrupt Logic Port 5.0 Event Counter Logic TM1 Set Register (8 bits) Arbitrary Waveform Generator TM1 Control Logic - 27 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 The format of the Timer 1 Control Register is shown as follows: TM1CR REG: (ADDRESS = 025H) (Default data = 0H) b3 b2 b1 b0 b3 b2 b1 b0 Input frequency (fsys0) 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 fsys/2 fsys/4 fsys/8 fsys/16 fsys/32 fsys/64 fsys/128 fsys/256 fsys/512 fsys/1024 fsys/2048 Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz The Timer 1 Set REG. is divided into TIMER 1 MSB DATA REG.(TM1MSB REG, ADDRESS = 026H, Default = 0FH) and TIMER 1 LSB DATA REG. (TM1LSB REG, ADDRESS = 027H, Default = 0FH). The Timer 1 READ REG. is divided into TIMER 1 READ ONLY MSB DATA REG. (TM1RM REG, ADDRESS = 01CH, Default = 0FH) and TIMER 1 READ ONLY LSB DATA REG. (TM1RL REG, ADDRESS = 01DH, Default = 0FH). The format of the Status of Timer 1 Register is shown as follows: STTM1 REG: (ADDRESS = 028H) (Default data = 0H) b3 b2 b1 b0 0: Timer 1 normal function select 1: Special function select Reserved 0:Timer 1 auto-reload disable 1:Timer 1 auto-reload enable 0:Timer 1 stop 1:Timer 1 start If Timer 1 is in the timer mode, the Timer 1 will underflow when it goes from 00H to 0FFH. The value in the TM1MSB and TM1LSB will be auto reloaded to the Timer 1 Set REG. when the STTM1 bit2 is set. Timer 1 will decrease by 1 continuously at each clock transition after the timer has started. At any time the STTM1 bit3 goes from 0 to 1 (disable to enable), the TM1MSB and TM1LSB will be auto reloaded to the Timer 1 Set Reg. again and Timer 1 is restarted. Timer 1 will stop operating while the STTM1 bit3 is reset to 0. - 28 - W921E880A/W921C880 The Timer 1 starts to count when the STTM1 REG. bit3 is set. When Timer 1 underflows, the STTM1 bit3 will be reset by hardware to stop Timer 1 if the auto-reload is disabled, but the STTM1 bit3 will not be reset if the auto-reload is enabled. When the Timer 1 function is performed, the special function will be disabled automatically. The special function input or output is from or to P5.0. The format of the Timer 1 event counter condition is shown as follows TGTM1 REG: (ADDRESS = 029H) (Default data = 0H) b3 b2 b1 b0 0: Event counter is falling edge trigger Reserved 1: Event counter is rising edge trigger 0: Special function work as event counter 1: Special function work as arbitrary waveform generator 0: Arbitrary waveform type 0 1: Arbitrary waveform type 1 TM2 can perform the following functions: 1. 2−19 order divider 2. Auto-reload timer. 3. Arbitrary waveform generator. 4. Pulse/Period width measurement function System Clock 1/4 f SYS 11-bit Prescaler f TM2 TM2 Read Register Interrupt Control Register High Speed Clock TM2 Control Register 8 Order Divider TM2 Interrupt Logic Port 5.1 Period/Pulse Width Measurement TM2 Set Register (8 bits) Arbitrary Waveform Generator TM2 Control Logic - 29 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 TM2CR REG: (ADDRESS = 02AH) (Default data = 0H) b3 b2 b1 b0 b3 b2 b1 b0 Input frequency (fTM2) 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 fsys/2 fsys/4 fsys/8 fsys/16 fsys/32 fsys/64 fsys/128 fsys/256 fsys/512 fsys/1024 fsys/2048 Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz The Timer 2 Set REG. is divided into TIMER 2 MSB DATA REG. (TM2MSB REG, ADDRESS = 02BH, Default = 0FH) and TIMER 2 LSB DATA REG. (TM2LSB REG, ADDRESS = 02CH, Default = 0FH). The Timer 2 READ REG. is divided into TIMER 2 READ ONLY MSB DATA REG. (TM2RM REG, ADDRESS = 01EH, Default = 0FH) and TIMER 2 READ ONLY LSB DATA REG. (TM2RL REG, ADDRESS = 01FH, Default = 0FH). The format of the Status of Timer 2 Register is shown as follows: STTM2 REG: (ADDRESS = 02DH) (Default data = 0H) b3 b2 b1 b0 0: Timer 2 mormal function select 1: Special function select Reserved 0:Timer 2 auto-reload disable 1:Timer 2 auto-reload enable 0:Timer 2 stop 1:Timer 2 start If Timer 2 is in the timer mode, the Timer 2 will underflow when it goes from 00H to FFH. The value in TM2MSB and TM2LSB will be auto reloaded to the Timer 2 Set REG. Timer 2 will decrease by 1 continuously at each clock transition after the timer has started. At any time the STTM2 bit3 goes from 0 to 1 (disable to enable), TM2MSB and TM2LSB will be auto reloaded to the Timer 2 Set Reg. again and the Timer 2 is restarted. Timer 2 will stop operating when the STTM2 bit3 is reset to 0. - 30 - W921E880A/W921C880 Timer 2 starts to count when the STTM2 REG. bit3 is set. When Timer 2 underflows, the STTM2 bit3 will be reset by hardware to stop Timer 2 if the auto-reload is disabled, but the STTM2 bit3 will not be reset if the auto-reload is enabled. When the Timer 2 function is performed, the special function is automatically disabled. The format of the trigger condition of the Timer 2 Register is shown as follows: TGTM2 REG: (ADDRESS = 02EH) (Default data = 0H) b3 b2 b1 b0 b1 0 0 1 1 b0 0 1 0 1 Trigger ----Rising Falling Both 0: Special function work as pulse/period width measurement 1: Special function work as arbitrary waveform generator 0: Arbitrary waveform type 0 1: Arbitrary waveform type 1 In pulse/period width measurement mode, the measuring-data is the 1'S complement of the exact data and the TM2 interrupt flag is set at every 255 timer clock occurences or if the 2nd trigger condition occurs. So the measured pulse/period width is (255(N − 1) + TM2) * T , where N is the b3 b2 b1 b0 0: ROW frequency disable 1: ROW frequency enable 0: COL frequency disable 1: COL frequency enable 0: D TMF disable (H-Z) 1: DTMF enable number of interrupt flag occurences, is the 1'S complement of timer2 register, and T is the period of the timer 2 clock. The special function input or output is from or to P5.1. Reserved TM3 can perform the following functions: 1. 2−19 order divider 2. Auto-reload timer. Interrupt Control Register System Clock 1/4 f SYS 11-bit Prescaler f TM3 8 Order Divider TM3 Interrupt Logic High Speed Clock TM3 Control Register TM3 Set Register (8 bits) TM3 Control Logic - 31 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 TM3CR REG: (ADDRESS = 02FH) (Default data = 0H) b3 b2 b1 b0 b3 b2 b1 b0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Input frequency (fTM3) fsys/2 fsys/4 fsys/8 fsys/16 fsys/32 fsys/64 fsys/128 fsys/256 fsys/512 fsys/1024 fsys/2048 Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz The Timer 3 Set REG. is divided into TIMER 3 MSB DATA REG. (TM3MSB REG, ADDRESS = 030H, Default = 0FH) and TIMER 3 LSB DATA REG. (TM3LSB REG, ADDRESS = 031H, Default = 0FH). The format of the Status of Timer 3 Register is shown as follows: STTM3 REG: (ADDRESS = 032H) (Default data = 0H) b3 b2 b1 b0 Reserved Reserved 0:Timer 3 auto_reload disable 1:Timer 3 auto-reload enable 0:Timer 3 stop 1:Timer 3 start 6.11.1 Arbitrary Waveform Generator Both TM1 and TM2 have arbitrary waveform generator circuits. The following description describes their opeation. TYPE 0 : NT 256T N = 0 Will keep the waveform in the high state. TYPE 1 : T NT N = 1 Will keep the waveform in the low state. Note: N is the value stored in the TM1 Set Reg. (TM1MSB, TM1LSB) or TM2 Set Reg. (TM2MSB, TM2LSB) - 32 - W921E880A/W921C880 6.12 Interrupt There are 10 interrupt sources. There are four external sources: INT0 (P4.3) and P4 Port (P4.0−P4.2), triggered by the falling edge signals of external sources, and six internal sources: Timer0, Timer1, Timer2, Timer3, Comparator and Serial Port. The priority of those interrupts is INT0 > TM0 > TM1 > TM2 > ( Comparator / TM3 ) > P4.0 to P4.2 > SERIAL. 6.12.1 Interrupt Control Register The INTERRUPT CONTROL REG.1−3 (INTCT1−INTCT3) controls which interrupt is enabled. The formats are shown below: INTCT1 REG: (ADDRESS = 039H) (Default data = 0H) b3 b2 b1 b0 0: TM0 interrupt disable 1: TM0 interrupt enable 0: TM1 interrupt disable 1: TM1 interrupt enable 0: TM2 interrupt disable 1: TM2 interrupt enable 0: TM3 interrupt disable 1: TM3 interrupt enable INTCT2 REG: (ADDRESS = 03AH) (Default data = 0H) b3 b2 b1 b0 0: INT0 pin interrupt disable 1: INT0 pin interrupt enable 0: SERIAL interrupt disable 1: SERIAL interrupt enable Reserved 0: COMPARATOR interrupt disable 1: COMPARATOR interrupt enable INTCT3 REG: (ADDRESS = 03BH) (Default data = 0H) b3 b2 b1 b0 0: P4.0 PORT interrupt disable 1: P4.0 PORT interrupt enable 0: P4.1 PORT interrupt disable 1: P4.1 PORT interrupt enable Reserved 0: P4.2 PORT interrupt disable 1: P4.2 PORT interrupt enable - 33 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 6.12.2 Interrupt Enable Flag When the interrupt is enabled by an event, the program counter will jump to the interrupt address and the Enable InterruptT Flag (ENINT) bit0 is cleared. All the interrupts will also be disabled at the same time. The only method to enable the interrupt again is to set the ENINT bit0 or to execute the RTNI instruction. ENINT REG: (ADDRESS = 034H) (Default data = 0H) b3 b2 b1 b0 0: Disable all interrupt 1: Enable all interrupt Reserved Reserved Reserved When the interrupt is enabled by an event, the individual interrupt request signal is automatically cleared by the hardware with the other interrupt request signals kept in the same condition. The only way to reset the interrupt request signal is to execute the instruction CLR EVF, #I (I is a 8bits data, for example, CLR EVF, #00000001b instruction implies to clear TM0 interrupt request signal). This instruction is a 2 word / 2 cycle instruction; the format of the immediate data is shown as follows: i7 i6 i5 i4 i3 i2 i1 i0 1: TM0 int. request signal is cleared 1: TM1 int. request signal is cleared 1: TM2 int. request signal is cleared 1: TM3 int. request signal is cleared 1: INT0 int. request signal is cleared 1: SERIAL int. request signal is cleared 1: COMPARATOR int. request signal is cleared 1: P4 int. request signal is cleared 6.13 Operating Mode There are 3 types of operating mode, Normal Mode , Hold Mode, and Stop Mode. 6.13.1 Normal Mode All functions operate with the µP functioning according to the system clock. 6.13.2 Hold Mode The µP enters the HOLD MODE when the HOLD instruction is executed from NORMAL MODE. In this mode, the system clock is stopped, so the program counter (PC) will also stop. But the oscillator, timer/ counter, serial port and interrupt active pins continue to function. The HOLD MODE can be released only by the RESET pin or by an interrupt request signal. When the hold mode is released, either the hold mode is released only, or the hold mode is released and the interrupt subroutine (interrupt vector) is serviced. The HOLD MODE RELEASES FLAG 1, 2, 3 (HMRF1, 2, 3) (ADDRESS = 036H, 037H, 038H) which can control the flow. The formats of these three flags are shown below. - 34 - W921E880A/W921C880 HMRF1 REG: (ADDRESS = 036H) (Default data = 0H) ANI3 ANI2 ANI1 ANI0 ANIMUX Register Vani Vpos Vrang = 1.5 V or (2/3)V DACTL.2 DD COMPTR.2 COMPTR.1 Vneg COMPTR.3 8bit D/A Converter Vref P5.2/Vref P5.3/DAOUT DAMSB 4-bit Register DALSB 4-bit Register HMRF2 REG: (ADDRESS = 037H) (Default data = 0H) b3 b2 b1 b0 b1 0 0 1 1 b0 0 1 0 1 Trigger ----Rising Falling Both 0: Special function work as pulse/period width measurement 1: Special function work as arbitrary waveform generator 0: Arbitrary waveform type 0 1: Arbitrary waveform type 1 HMRF3 REG: (ADDRESS = 038H) (Default data = 0H) b3 b2 b1 b0 0: P4.0 PORT hold released disable 1: P4.0 PORT hold released enable 0: P4.1 PORT hold released disable 1: P4.1 PORT hold released enable Reserved 0: P4.2 PORT hold released disable 1: P4.2 PORT hold released enable The HOLD RELEASED STATUS FLAG 1, 2, 3 (HRSTS1, 2, 3) (ADDRESS = 03CH, 03DH, 03EH) stores the information that caused the HOLD MODE to be released. The format is shown below. - 35 - Publication Release Date: July 1999 Revision A3 W921E880A/W921C880 HRSTS1 REG: (ADDRESS = 03CH) (Read Only) (Default data = 0H) b3 b2 b1 b0 1: HOLD has released by TM0 1: HOLD has released by TM1 1: HOLD has released by TM2 1: HOLD has released by TM3 HRSTS2 REG: (ADDRESS = 03DH) (Read Only) (Default data = 0H) b3 b2 b1 b0 1: HOLD has released by the INT0 pin 1: HOLD has released by SERIAL Port Reserved 1: HOLD has released by COMPARATOR HRSTS3 REG: (ADDRESS = 03EH) (Read Only) (Default data = 0H) b3 b2 b1 b0 1: HOLD has released by P4.0 1: HOLD has released by P4.1 Reserved 1: HOLD has released by P4.2 HRSTS1, 2, and 3 are read only registers and cleared by the instruction CLR EVF #I. - 36 - W921E880A/W921C880 Hold Mode Operation Flow Chart TM0 to TM3 Serial; Comparator; Falling change occurs at INT0, P4.0-P4.2 Yes In HOLD Mode ? No INTCT Interrupt Flag Set? Yes No INTCT Interrupt Flag Set? Yes No Reset ENINT Flag and individual Request Flag Execute Interrupt Service Routine No HMRF Hold Release Flag Set? Yes Reset ENINT Flag and individual Request Flag Execute Interrupt Service Routine HOLD PC