W967D6HBGX7I

W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 1. GENERAL DESCRIPTION Winbond CellularRAM™ products are high-speed, CMOS pseudo-static random access memories developed for low-power, portable applications. The device has a DRAM core organized. These devices include an industrystandard burst mode Flash interface that dramatically increases read/write bandwidth compared with other lowpower SRAM or Pseudo SRAM offerings. To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device READ/WRITE performance. Two user-accessible control registers define device operation. The Bus Configuration Register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The Refresh Configuration Register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature compensated refresh (TCR) uses an on-chip sensor to adjust the refresh rate to match the device temperature—the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system configurable refresh mechanisms are accessed through the RCR. This CellularRAM device is compliant with the industry-standard CellularRAM 1.5 generation feature set established by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with 3 output-device drivestrength settings, additional wrap options, and a device ID register (DIDR). 2. FEATURES •Supports asynchronous, page, and burst operations • VCC, VCCQ Voltages: • Low-power features On-chip temperature compensated refresh (TCR) 1.7V–1.95V VCC Partial array refresh (PAR) 1.7V–1.95V VCCQ Deep power-down (DPD) mode • Random access time: 70ns  Package: • Burst mode READ and WRITE access:  Active current (ICC1) =150 us normal operation Vcc VccQ Device ready for Device Initialization 8.2 Bus Operating Modes CellularRAM products incorporate a burst mode interface found on flash products targeting low-power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]). 8.2.1 Asynchronous Modes CellularRAM products power up in the asynchronous operating mode. This mode uses the industry- standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations occur when CE#, WE#, and LB#/UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a “don't care,” and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can either use the ADV input to latch the address, or ADV can be driven LOW during the entire READ/WRITE operation. During asynchronous operation, the CLK input must be held static LOW. WAIT will be driven while the device is enabled and its state should be ignored. WE# LOW time must be limited to tCEM. - 11 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 8.2.1.1 READ Operation(ADV# LOW) CE # OE # WE # Address Valid ADDRESS DATA Data Valid LB # / UB # tRC = READ Cycle Time Don ‘ t Care Note : ADV must remain LOW for PAGE MODE operation. 8.2.1.2 WRITE Operation (ADV# LOW) CE # OE # 20ns. - 60 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.20 Burst WRITE at End of Row (Wrap off) CLK V IH V IL tCLK V IH A [ max : 0 ] V IL V IH ADV # V IL V IH LB # / UB # V IL WE # V IH V IL V IH OE # V IL tKHTL tHZ V OH WAIT V OL High - Z *2 V IH CE # V IL DQ [ 15:0 ] V IH V IL tSP tHD VALID INPUT VALID INPUT VALID INPUT END OF ROW Don’t Care Note : 1. Non-default BCR settings for burst WRITE at end row; fixed or variable latency ; WAIT active LOW; WAIT asserted during delay. 2. For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins (before the 2 nd CLK after WAIT asserts with BCR[8] = 0, or before the third CLK after WAIT asserts with BCR[8] = 1. - 61 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.21 Burst WRITE Row Boundary Crossing CLK VIH VIL A[max:0 ] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL WE# VIH VIL OE# VIH VIL CE# VIH VIL WAIT VOH VOL DQ[15:0] VIH VIL tCLK tKHTL tSP Note 2 tHD Valid input Valid input Valid input Valid input End of row Valid input Don’t Care Notes : 1. Non-default BCR settings for burst WRITE at end of row : foxed or variable latency, WAIT active LOW, WAIT asserted during delay (shown as solid line). 2. WAIT will be asserted for LC cycles for variable latency, or LC cycles for fixed latency. - 62 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.22 Burst WRITE Followed by Burst READ CLK V IH V IL V IH A [ max : 0 ] V IL V IH ADV # V IL V IH LB # / UB # V IL V IH CE # V IL V IH OE # V IL WE # V IH V IL V OH WAIT V OL DQ [ 15:0 ] V IH IN / OUT V IL tSP tHD tSP tHD Valid Address Valid Valid Address tSP tHD tSP tHD tSP tHD tCSP tKADV*3 tHD tCBPH *2 tCSP tSP tHD tSP High - Z tSP tHD High - Z tOHZ V OH D0 D1 D2 D3 V OL tBOE tHD tACLK High - Z Valid Output High - Z tKOH Valid Output Don’t Care Valid Output Valid Output Undefined Note : 1. Non-default BCR settings for burst WRITE followed by burst READ: Fixed or variable latency; latency code 2(3clocks); WAIT active LOW; WAIT asserted during delay. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. CE# can stay LOW between burst READ and burst WRITE operations, but CE# must not remain LOW longer than tCEM. See burst interrupt diagrams for cases where CE# stays LOW between bursts. - 63 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.23 Burst READ Interrupted by Burst READ or WRITE tCLK V IH CLK V IL V IH A [ max : 0 ] V IL V IH ADV # V IL CE # tSP tHD tSP tHD Valid Address Valid Address tSP tHD V OH WAIT V OL OE # V IH 2 nd Cycle READ V IL LB # / UB # V IH 2 nd Cycle READ V IL DQ [ 15:0 ] V OH 2 nd Cycle READ V OL tSP tHD tCEM*3 V IH V IL WE # V IH V IL READ Burst interrupted with new READ or WRITE. *2 tCSP tSP tHD tSP tHD tHD tKHTL tBOE tBOE High - Z tOHZ tCEW tOHZ tACLK High - Z tKOH tBOE High - Z Valid Output OE# 2 nd Cycle WRITE LB#/UB# 2 nd Cycle WRITE V IH V IL V IH V IL DQ[15:0]IN V IH 2 nd Cycle WRITE V IL Valid Output Valid Output tACLK Valid Output Valid Output tSP tHD High-Z D0 D1 Don’t Care D2 D3 Undefined Note : 1. Non-default BCR settings for burst READ interrupted by burst READ or WRITE: Fixed or variable latency code 2(3 clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision. 2. Burst interrupt shown on first allowable clock (i.e., after the first data received by the controller). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM. - 64 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.24 Burst WRITE Interrupted by Burst WRITE or READ–Variable Latency Mode tCLK V IH CLK V IL A [ max : 0 ] ADV # CE # WE # WAIT OE # 2 nd Cycle WRITE LB # / UB # 2 nd Cycle WRITE DQ [ 15:0 ]IN 2 nd Cycle WRITE V IH V IL V IH V IL V IH V IL V IH V IL V OH V OL V IH V IL V IH V IL V IH V IL WRITE Burst interrupted with new WRITE or READ *2. tSP tHD tSP tHD Valid Address Valid Address tSP tHD tSP tHD tCEM*3 tCSP tSP tHD tHD tSP tHD tKHTL High - Z High - Z tCEW tSP tHD tSP tHD High - Z tSP tHD D0 D0 D1 D2 tOHZ tBOE OE# V IH 2nd Cycle READ V IL tSP LB#/UB# V IH 2nd Cycle READ V IL tHD tACLK DQ[15:0] OUT V OH High - Z 2nd Cycle READ V OL D3 V OH V OL tKOH Vaild Output Vaild Output Don’t Care Vaild Output Vaild Output Undefined Note : 1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in variable latency mode: Variable latency; latency code 2(3 clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision. 2. Burst interrupt shown on first allowable clock (i.e., after first data word written). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM. - 65 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.25 Burst WRITE Interrupted by Burst WRITE or READ-Fixed Latency Mode CLK A [ max : 0 ] ADV # CE # WE # WAIT OE # 2 nd Cycle WRITE LB # / UB # 2 nd Cycle WRITE DQ [ 15:0 ]IN 2 nd Cycle WRITE tCLK WRITE Burst interrupted with new WRITE or READ *2. V IH V IL tSP tHD tSP tHD V IH Valid Valid Address Address V IL tSP tHD tAVH tSP tHD tAVH V IH V IL tCEM*3 V IH tCSP tHD V IL tHD tSP tHD V IH tSP V IL tKHTL V OH High - Z High - Z V OL tCEW V IH V IL tSP tHD V IH V IL tSP tHD tSP tHD High - Z V IH D2 D3 D0 D0 D1 V IL tOHZ tBOE OE# 2nd Cycle READ LB#/UB# 2nd Cycle READ V IH V IL V IH V IL DQ[15:0] OUT V OH 2nd Cycle READ V OL tSP V OH V OL High - Z tHD tKOH tACLK Vaild Output Vaild Output Vaild Output Vaild Output Don’t Care Undefined Note : 1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in fixed latency mode: Fixed latency; latency code 2(3 clocks); WAIT active LOW; WAIT asserted during delay. 2. Burst interrupt shown on first allowable clock(i, e., after first data word written). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM. - 66 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.26 Asynchronous WRITE Followed by Burst READ V IH CLK V IL V IH A [ max : 0 ] V IL V IH ADV # V IL LB # / UB # V IH V IL V IH CE # V IL V IH OE # V IL WE # V IH V IL tCLK tWC tWC tSP tHD Valid Address Valid Address Valid Address tAVS tAW tAVH tVS tVP tSP tBW tCVS tCW tCBPH tAS tWP tWC tWPH tHD tCSP tOHZ *2 tSP tHD tAS tCEM V OH WAIT V OL DQ [ 15:0 ] V IH IN / OUT V IL tWR tSP tHD tBOE High - Z tACLK High - Z Data Data tDH tDW V OH V OL High - Z tKOH Valid Valid Valid Valid Output Output Output Output Don’t Care Undefined Note : 1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Fixed or variable latency; latency code 2(3 clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. - 67 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.27 Asynchronous WRITE (ADV# LOW) Followed by Burst READ CLK tCLK V IH V IL V IH A [ max : 0 ] V IL tWC tWC tSP tHD Vaild Address Vaild Address Vaild Address V IH ADV # V IL LB # / UB # V IH V IL V IH CE # V IL tSP tHD tBW tSP tCBPH tCW tWP tWC tWPH tCSP tOHZ tSP V IL tHD tCEW V OH WAIT V OL DQ [ 15:0 ] V IH IN / OUT V IL tHD *2 V IH OE # V IL WE # V IH tAW tWR tBOE High - Z tACLK tKOH High - Z Data Data tDH tDW V OH V OL High - Z Valid Output Valid Output Don’t Care Valid Output Valid Output Undefined Note : 1. Non-default BCR settings for asynchronous WRITE ,with ADV# LOW, followed by burst READ: Fixed or variable latency; latency code 2(3 clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. - 68 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.28 Burst READ Followed By Asynchronous WRITE (WE# - Controlled) tCLK CLK V IH V IL V IH A [ max : 0 ] V IL ADV # CE # V IH V IL V IH V IL V IH OE # V IL WE # V IH V IL LB # / UB # V IH V IL V OH WAIT V OL DQ [ 15:0 ] V OH V OL tSP tHD tWC Vaild Address Valid Address tSP tHD tAW tCSP tCBPH tHZ tHD tCW *2 tOHZ tBOE tSP tHD tSP tAS tOLZ tWPH tWP tBW tHD tCEW tWR tKHTL tCEW tHZ High - Z High - Z tACLK tKOH High - Z Valid Output V IH V IL Don’t Care READ Burst Identified (WE# = HIGH) tDW tDH Valid Output Undefined Note : 1. Non-default BCR settings for burst READ followed by asynchronous WE#-controlled WRITE : Fixed or variable latency; latency code 2(3 clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. Asynchronous operation begins at the falling edge of ADV#.A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. - 69 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.29 Burst READ Followed By Asynchronous WRITE Using ADV# tCLK CLK V IH V IL V IH A [ max : 0 ] V IL ADV # tSP tHD Vaild Address Vaild Address tAVS tAVH tVS tVP tSP tHD V IH V IL V IH CE # V IL V IH OE # V IL WE # V IH V IL LB # / UB # V IH V IL V OH WAIT V OL DQ [ 15:0 ] V OH V OL tHD tCSP tCBPH tAS tHZ tAW tCW *2 tOHZ tBOE tSP tHD tAS tOLZ tHD tSP tCEW tKHTL tWPH tWP tBW tCEW High - Z tHZ High - Z tACLK High - Z tKOH Valid Output V IH V IL Don’t Care READ Burst Identified (WE# = HIGH) tDW tDH Valid Input Undefined Note : 1. Non-default BCR settings for burst READ followed by asynchronous WRITE using ADV#: Fixed or variable latency; latency code 2(3 clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. Asynchronous operation begins at the falling edge of ADV#.A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. - 70 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.30 Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW V IH V IL V IH ADV # V IL A [ max : 0 ] LB # / UB # V IH V IL CE # V IH V IL Valid Address tAW tWR V IL tHZ tCPH tCW *1 tWP tLZ tOHZ tOE tWC tWPH tAS tHZ tHZ V OH High - Z tBHZ tBLZ WAIT V OL DQ [ 15:0 ] V IH IN / OUT V IL tAA tBW V IH OE # V IL WE # V IH Valid Address Valid Address tWHZ Data tDH Data High - Z tDW V OH V OL tOLZ Don’t Care Valid Output Undefined Note : 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval, Otherwise, tCPH is only required after CE#-controlled WRITEs. - 71 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 10.2.31 Asynchronous WRITE Followed by Asynchronous READ V IH Valid Address V IH tAVS tAVH tAW tWR tVS tVP A [ max : 0 ] V IL ADV # V IL tCVS V IL OE # tCPH tCW tHZ *1 tLZ tAS V IH V IL WE # V IH V IL V OH WAIT V OL DQ [ 15:0 ] V IH IN / OUT V IL tBHZ tBLZ tBW LB # / UB # V IH V IH CE # V IL Valid Address tAA Valid Address tAS tWC tWPH tWP tOHZ tOLZ tHZ High - Z tWHZ Data tDH Data High - Z tDW V OH V OL tOE Don’t Care Valid Output Undefined Note : 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval, Otherwise, tCPH is only required after CE#-controlled WRITEs. - 72 - Publication Release Date : May 29, 2013 Revision : A01-003 W967D6HB 128Mb Async./Page,Syn./Burst CellularRAM 11. PACKAGE DESCRIPTION 11.1 Package Dimension 54 Ball VFBGA (6X8 mm^2,Ball pitch:0.75mm, Ø =0.4mm) Note: 1. Ball land:0.45mm. Ball opening:0.35mm. PCB ball land suggested