W972GG8JB

W972GG8JB 32M  8 BANKS  8 BIT DDR2 SDRAM Table of Contents1. 2. 3. 4. 5. 6. 7. 7.1 7.2 GENERAL DESCRIPTION ................................................................................................................... 4 FEATURES ........................................................................................................................................... 4 KEY PARAMETERS ............................................................................................................................. 5 BALL CONFIGURATION ...................................................................................................................... 6 BALL DESCRIPTION ............................................................................................................................ 7 BLOCK DIAGRAM ................................................................................................................................ 8 FUNCTIONAL DESCRIPTION .............................................................................................................. 9 Power-up and Initialization Sequence ................................................................................................... 9 Mode Register and Extended Mode Registers Operation ................................................................... 10 7.2.1 7.2.2 7.2.2.1 7.2.2.2 7.2.2.3 7.2.2.4 7.2.3 7.2.3.1 7.2.3.2 7.2.3.3 7.2.4 7.2.5 7.2.5.1 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.4 Mode Register Set Command (MRS)............................................................................... 10 Extend Mode Register Set Commands (EMRS) .............................................................. 11 Extend Mode Register Set Command (1), EMR (1)................................................ 11 DLL Enable/Disable ................................................................................................ 12 Extend Mode Register Set Command (2), EMR (2) ................................................ 13 Extend Mode Register Set Command (3), EMR (3) ................................................ 14 Off-Chip Driver (OCD) Impedance Adjustment ................................................................ 15 Extended Mode Register for OCD Impedance Adjustmen t .................................... 16 OCD Impedance Adjust .......................................................................................... 16 Drive Mode ............................................................................................................. 17 On-Die Termination (ODT) ............................................................................................... 18 ODT related timings ......................................................................................................... 18 MRS command to ODT update delay ..................................................................... 18 Bank Activate Command.................................................................................................. 20 Read Command ............................................................................................................... 21 Write Command ............................................................................................................... 21 Burst Read with Auto-precharge Command..................................................................... 21 Burst Write with Auto-precharge Command ..................................................................... 21 Precharge All Command .................................................................................................. 21 Self Refresh Entry Command .......................................................................................... 21 Self Refresh Exit Command ............................................................................................. 22 Refresh Command ........................................................................................................... 22 No-Operation Command .................................................................................................. 23 Device Deselect Command .............................................................................................. 23 Command Function ............................................................................................................................. 20 Read and Write access modes ........................................................................................................... 23 7.4.1 7.4.1.1 Posted C AS .................................................................................................................... 23 Examples of posted C AS operation ..................................................................... 23 -1- Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 7.4.2 7.4.3 7.4.4 7.4.5 7.5 7.6 Burst mode operation ....................................................................................................... 24 Burst read mode operation ............................................................................................... 25 Burst write mode operation .............................................................................................. 25 Write data mask ............................................................................................................... 26 Burst Interrupt ..................................................................................................................................... 26 Precharge operation............................................................................................................................ 27 7.6.1 7.6.2 Burst read operation followed by precharge ..................................................................... 27 Burst write operation followed by precharge .................................................................... 27 Burst read with Auto-precharge ....................................................................................... 28 Burst write with Auto-precharge ....................................................................................... 28 7.7 Auto-precharge operation ................................................................................................................... 27 7.7.1 7.7.2 7.8 7.9 Refresh Operation ............................................................................................................................... 29 Power Down Mode .............................................................................................................................. 29 7.9.1 7.9.2 Power Down Entry ........................................................................................................... 30 Power Down Exit .............................................................................................................. 30 7.10 8. 8.1 8.2 8.3 8.4 8.5 9. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 Input clock frequency change during precharge power down ............................................................. 30 OPERATION MODE ........................................................................................................................... 31 Command Truth Table ........................................................................................................................ 31 Clock Enable (CKE) Truth Table for Synchronous Transitions ........................................................... 32 Data Mask (DM) Truth Table ............................................................................................................... 32 Function Truth Table ........................................................................................................................... 33 Simplified Stated Diagram ................................................................................................................... 36 ELECTRICAL CHARACTERISTICS ................................................................................................... 37 Absolute Maximum Ratings ................................................................................................................ 37 Operating Temperature Condition ....................................................................................................... 37 Recommended DC Operating Conditions ........................................................................................... 37 ODT DC Electrical Characteristics ...................................................................................................... 38 Input DC Logic Level ........................................................................................................................... 38 Input AC Logic Level ........................................................................................................................... 38 Capacitance ........................................................................................................................................ 39 Leakage and Output Buffer Characteristics ........................................................................................ 39 DC Characteristics .............................................................................................................................. 40 IDD Measurement Test Parameters.................................................................................................... 42 AC Characteristics .............................................................................................................................. 43 9.11.1 9.11.2 AC Characteristics and Operating Condition for -18 speed grade ................................... 43 AC Characteristics and Operating Condition for -25/25I/-3 speed grades........................ 45 9.12 9.13 9.14 AC Input Test Conditions .................................................................................................................... 65 Differential Input/Output AC Logic Levels ........................................................................................... 65 AC Overshoot / Undershoot Specification ........................................................................................... 66 9.14.1 9.14.2 AC Overshoot / Undershoot Specification for Address and Control Pins: ........................ 66 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins: .......... 66 10. 10.1 TIMING WAVEFORMS ....................................................................................................................... 67 Command Input Timing ....................................................................................................................... 67 -2- Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.2 Timing of the CLK Signals ................................................................................................................... 67 10.3 ODT Timing for Active/Standby Mode ................................................................................................. 68 10.4 ODT Timing for Power Down Mode .................................................................................................... 68 10.5 ODT Timing mode switch at entering power down mode .................................................................... 69 10.6 ODT Timing mode switch at exiting power down mode ...................................................................... 70 10.7 Data output (read) timing .................................................................................................................... 71 10.8 Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................ 71 10.9 Data input (write) timing ...................................................................................................................... 72 10.10 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4) ........................................................... 72 10.11 Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) ...................................... 73 10.12 Seamless burst write operation: RL = 5 ( WL = 4, BL = 4) ......................................................... 73 10.13 Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) ............................................................. 74 10.14 Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) .................................................. 74 10.15 Write operation with Data Mask: WL=3, AL=0, BL=4) ............................................................... 75 10.16 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≤ 2clks) ............ 76 10.17 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............ 76 10.18 Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≤ 2clks) ............ 77 10.19 Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≤ 2clks) ............ 77 10.20 Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) ............ 78 10.21 Burst write operation followed by precharge: WL = (RL -1) = 3 .................................................. 78 10.22 Burst write operation followed by precharge: WL = (RL-1) = 4 .................................................. 79 10.23 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............... 79 10.24 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) ............... 80 10.25 Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) ....................................................................................... 80 10.26 Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) ....................................................................................... 81 10.27 Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3 ................................. 81 10.28 Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 ....................... 82 10.29 Self Refresh Timing ................................................................................................................... 82 10.30 Active Power Down Mode Entry and Exit Timing ....................................................................... 83 10.31 Precharged Power Down Mode Entry and Exit Timing .............................................................. 83 10.32 Clock frequency change in precharge Power Down mode ........................................................ 84 11. 12. PACKAGE SPECIFICATION .............................................................................................................. 85 Package Outline WBGA60 (11x11.5 mm ) ...................................................................................................... 85 REVISION HISTORY .......................................................................................................................... 86 2 -3- Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 1. GENERAL DESCRIPTION The W 972GG8JB is a 2G bits DDR2 SDRAM, organized as 33,554,432 words  8 banks  8 bits. This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2 -1066) for general applications. W 972GG8JB is sorted into the following speed grades: -18, -25, 25I and -3. The -18 is compliant to the DDR2-1066 (7-7-7) specification. The -25/25I are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -3 is compliant to the DDR2-667 (5-5-5) specification. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of diffe rential clocks (CLK rising and CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS - DQS pair in a source synchronous fashion. 2. FEATURES           Power Supply: VDD, VDDQ = 1.8 V  0.1 V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data Edge-aligned with Read data and center -aligned with W rite data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK and CLK ) Data masks (DM) for write data . Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS Posted CAS programmable additive latency supported to make command and data bus efficiency Read Latency = Additive Latency plus CAS Latency (RL = AL + CL) Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality Auto-precharge operation for read and write bursts Auto Refresh and Self Refresh modes Precharged Power Down and Active Power Down W rite Data Mask W rite Latency = Read Latency - 1 (W L = RL - 1) Interface: SSTL_18 Packaged in W BGA 60 Ball (11x11.5 mm ), using Lead free materials with RoHS compliant 2           -4- Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 3. KEY PARAMETERS SPEED GRADE SYM. Bin(CL-tRCD-tRP) Part Number Extension Min. @CL = 7 Max. Min. @CL = 6 Max. Min. Max. @CL = 4 Min. Max. @CL = 3 tRCD t RP tRC tRAS IDD0 IDD1 IDD4R IDD4W IDD5B IDD6 IDD7 Active to Read/Write Command Delay Time Precharge to Active Command Period Active to Ref/Active Command Period Active to Precharge Command Period Operating one bank active-precharge current Operating one bank active-read-precharge current Operating burst read current Operating burst write current Burst refresh current Self refresh current (TCASE ≤ 85°C) Operating bank interleave read current Min. Max. Min. Min. Min. Min. Max. Max. Max. Max. Max. Max. Max. DDR2-1066 7 -7 -7 -18 1.875 nS 7.5 nS 2.5 nS 7.5 nS 3 nS 7.5 nS 3.75 nS 7.5 nS   13.125 nS 13.125 nS 58.125 nS 45 nS 85 mA 85 mA 165 mA 145 mA 175 mA 12 mA 220 mA DDR2-800 5-5-5/6-6-6 -25/25I   2.5 nS 8 nS 2.5 nS 8 nS 3.75 nS 8 nS 5 nS 8 nS 12.5 nS 12.5 nS 57.5 nS 45 nS 72 mA 80 mA 135 mA 120 mA 160 mA 12 mA 200 mA DDR2-667 5 -5 -5 -3     3 nS 8 nS 3.75 nS 8 nS 5 nS 8 nS 15 nS 15 nS 60 nS 45 nS 69 mA 75 mA 120 mA 110 mA 150 mA 12 mA 180 mA tCK(avg) Average clock period @CL = 5 -5- Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 4. BALL CONFIGURATION 1 VDD DQ6 VDDQ DQ4 VDDL 2 NU/RDQS 3 VSS 4 5 A B C D E F G H J K L 6 7 VSSQ DQS VDDQ DQ2 VSSDL 8 DQS VSSQ DQ0 VSSQ CLK CLK CS A0 A4 A8 A13 9 VDDQ DQ7 VDDQ DQ5 VDD ODT VSSQ DM/RDQS DQ1 VSSQ VREF CKE VDDQ DQ3 VSS WE BA1 A1 A5 A9 A14 RAS CAS A2 A6 A11 NC BA2 BA0 A10/AP VDD VSS A3 A7 VSS VDD A12 -6- Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 5. BALL DESCRIPTION BALL NUMBER H8,H3,H7,J2,J8,J3, J7,K2,K8,K3,H2,K7, L2,L8,L3 SYMBOL FUNCTION DESCRIPTION Provide the row address for active commands, and the column address and Auto-precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. Row address: A0−A14. Column address: A0−A9. (A10 is used for Auto-precharge) BA0−BA2 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Bi-directional data bus. ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. A0−A14 Address G2,G3,G1 C8,C2,D7,D3,D1,D9, B1,B9 F9 BA0−BA2 DQ0−DQ7 ODT DQS, Bank Select Data Input / Output On Die Termination Control B7,A8 DQS Output with read data, input with write data for source synchronous Data Strobe / operation. Edge-aligned with read data, center-aligned with write Differential Read Data data. DQS is only used when differential data strobe mode is Strobe enabled via the control bit at EMR (1) [A10] = 0. All commands are masked when CS is registered G8 CS Chip Select HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. F7,G7,F3 R AS , C AS , Command Inputs WE R AS , CAS and WE (along with CS ) define the command being entered. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. The DM loading matches the DQ and DQS loading. RDQS/ RDQS are used as strobe signals during reads is enabled by EMR (1) [A11] = 1. If RDQS/ RDQS is enabled, the DM function is disabled. B3 DM/RDQS Input Data Mask/ Read Data Strobe A2 NU/ RDQS Not Use/Differential Read Data Strobe RDQS is only used when RDQS is enabled and differential data strobe mode is enabled. If differential data strobe mode is disabled via the control bit at EMR (1) [A10] = 1, then ball A2 and A8 are not used. CLK and C LK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of C LK . Output (read) data is referenced to the crossings of CLK and C LK (both directions of crossing). E8,F8 CLK, C LK Differential Clock Inputs F2 E2 A1,E9,H9,L1 A3,E3,J1,K9 A9,C1,C3,C7,C9 A7,B2,B8,D2,D8 L3,L7 E1 E7 CKE VREF VDD VSS VDDQ VSSQ NC VDDL VSSDL Clock Enable Reference Voltage Power Supply Ground DQ Power Supply DQ Ground No Connection DLL Power Supply DLL Ground CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. VREF is reference voltage for inputs. Power Supply: 1.8V  0.1V. Ground. DQ Power Supply: 1.8V  0.1V. DQ Ground. Isolated on the device for improved noise immunity. No connection. DLL Power Supply: 1.8V  0.1V. DLL Ground. -7- Publication Release Date: Feb. 18, 2011 Revision A02 CLK CLK DLL CLOCK BUFFER 6. BLOCK DIAGRAM CKE CONTROL CS SIGNAL RAS COMMAND DECODER CAS WE COLUMN DECODER COLUMN DECODER COLUMN DECODER GENERATOR COLUMN DECODER ROW DECODER ROW DECODER ROW DECODER A0 ADDRESS BUFFER SENSE AMPLIFIER SENSE AMPLIFIER SENSE AMPLIFIER MODE REGISTER ROW DECODER A10 CELL ARRAY BANK #0 CELL ARRAY BANK #1 CELL ARRAY BANK #4 CELL ARRAY BANK #5 SENSE AMPLIFIER A9 A11 A12 A13 A14 BA2 BA1 BA0 PREFETCH REGISTER DATA CONTROL CIRCUIT REFRESH COLUMN COUNTER COUNTER ROW DECODER ROW DECODER ROW DECODER SENSE AMPLIFIER SENSE AMPLIFIER ROW DECODER -8COLUMN DECODER COLUMN DECODER COLUMN DECODER CELL ARRAY BANK #2 CELL ARRAY BANK #3 CELL ARRAY BANK #6 SENSE AMPLIFIER ODT DQ BUFFER ODT CONTROL DQ0 | DQ7 DQS DQS RDQS RDQS DM COLUMN DECODER CELL ARRAY BANK #7 SENSE AMPLIFIER W972GG8JB Publication Release Date: Feb. 18, 2011 Revision A02 NOTE: The cell array configuration is 32768 * 1024 * 8 W972GG8JB 7. FUNCTIONAL DESCRIPTION 7.1 Power-up and Initialization Sequence DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for Power-up and Initialization. 1. Apply power and attempt to maintain CKE below 0.2 × V DDQ and ODT at a LOW state (all other inputs may be undefined.) Either one of the following sequence is required for Power -up. A. The VDD voltage ramp time must be no greater than 200 m S from when VDD ramps from 300 mV to VDD min; and during the VDD voltage ramp, |VDD -VDDQ| ≤ 0.3 volts.  VDD, VDDL and VDDQ are driven from a single power converter output  VTT is limited to 0.95V max *2  VREF tracks VDDQ/2 VDDQ ≥ VREF must be met at all times B. Voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be maintained and is applicable to both AC and DC levels until the ramping of the supply voltages is complete. *3  Apply VDD/VDDL before or at the same time as VDDQ *4  Apply VDDQ before or at the same time as VTT *2  VREF tracks VDDQ/2  *1 VDDQ ≥ VREF must be met at all times. 2. Start Clock and maintain stable condition for 200 µ S (min.).  3. After stable power and clock (CLK, CLK ), apply NOP or Deselect and take CKE HIGH. 4. W ait minimum of 400 nS then issue precharge all command. NOP or Deselect applied during 400 nS period. 5. Issue an EMRS command to EMR (2). (To issue EMRS command to EMR (2), provide LOW to BA0 and BA2, HIGH to BA1.) 6. Issue an EMRS command to EMR (3). (To issue EMRS command to EMR (3), provide LOW to BA2, HIGH to BA0 and BA1.) 7. Issue EMRS to enable DLL. (To issue DLL Enable command, provide LOW to A0, HIGH to BA0 and LOW to BA1-BA2 and A13-A14. And A9=A8=A7=LOW must be used when issuing this command.) 8. Issue a Mode Register Set command for DLL reset. (To issue DLL Reset command, provide HIGH to A8 and LOW to BA0-BA2 and A13-A14.) 9. Issue a precharge all command. 10. Issue 2 or more Auto Refresh commands. 11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program oper ating parameters without resetting the DLL.) 12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRS to EMR (1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit OCD Calibration Mode (A9=A8=A7=LOW ) must be issued with other operating parameters of EMR(1). 13. The DDR2 SDRAM is now ready for normal operation. -9- Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB Notes: 1. To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin. 2. VREF must be within  300 mV with respect to VDDQ/2 during supply ramp time. 3. VDD/VDDL voltage ramp time must be no greater than 200 mS from when VDD ramps from 300 mV to VDD min. 4. The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be no greater than 500 mS. tCH tCL CLK CLK tIS tIS CKE ODT Command NOP PRE ALL EMRS MRS PRE ALL REF REF MRS EMRS EMRS ANY CMD 400nS tRP tMRD DLL Enable DLL Reset tMRD tRP tRFC min 200 Cycle tRFC tMRD Follow OCD Flow chart tOIT OCD CAL. Mode Exit OCD Default Figure 1 – Initialization sequence after power-up 7.2 Mode Register and Extended Mode Registers Operation For application flexibility, burst length, burst type, CAS Latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS Latency, ODT (On Die Termination), single-ended strobe and OCD (off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MR) or Extended Mode Registers EMR (1), EMR (2) and EMR (3) can be altered by re-executing the MRS or EMRS Commands. Even if the user chooses to modify only a subset of the MR or EMR (1), EMR (2) and EMR (3) variables, all variables within the addressed register must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which mean re-initialization including those can be executed at any time after power-up without affecting array contents. 7.2.1 Mode Register Set Command (MRS) ( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "L", BA2 = "L", A0 to A14 = Register Data) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS Latency, burst length, burst sequence, test mode, DLL reset, Write Recovery (WR) and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value in the Mode Register after power-up is not defined, therefore the Mode Register must be programmed during initialization for proper operation. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the p recharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by Publication Release Date: Feb. 18, 2011 Revision A02 - 10 - W972GG8JB A[2:0] with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2 does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the table for specific codes. BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 0 0 0 0 0 PD WR DLL TM CAS Latency BT Burst Length Mode Register A8 0 1 BA1 0 0 1 1 BA0 0 1 0 1 A12 0 1 DLL Reset No Yes A7 0 1 Mode Normal Test A3 0 1 Burst Type Sequential Interleave A2 0 0 CAS Latency A6 0 0 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Burst Length A1 1 1 A0 0 1 BL 4 8 MRS mode MR EMR (1) EMR (2) EMR (3) Active power down exit time Fast exit (use tXARD) Slow exit (use tXARDS) Write recovery for Auto-precharge A11 0 0 0 0 1 1 1 1 A10 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 0 1 WR * Reserved 2 3 4 5 6 7 8 Latency Reserved Reserved Reserved 3 4 5 6 7 DDR2-667 DDR2-800 0 DDR2-1066 1 1 1 Note: 1. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min. WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this value. This is also used with tRP to determine tDAL. Figure 2 – Mode Register Set (MRS) 7.2.2 7.2.2.1 Extend Mode Register Set Commands (EMRS) Extend Mode Register Set Command (1), EMR (1) ( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L, BA2 = "L" A0 to A14 = Register data) The extended mode register (1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended mode register (1) is not defined, therefore the extended mode register (1) must be programmed during initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register (1). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1). Extended mode register (1) contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used fo r DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the additive latency, A[9:7] are used for OCD control, A10 is used for DQS disable. A2 and A6 are used for ODT setting. - 11 - Publication Release Date: Feb. 18, 2011 Revision A02 DDR2-1066 1 DDR2-800 0 DDR2-667 W972GG8JB 7.2.2.2 DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self Refresh operation and is automatically re-enabled and reset upon exit of Self Refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the t AC or tDQSCK parameters. BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 0 0 1 0 0 Qoff RDQS DQS OCD program Rtt Additive Latency WR BT Rtt D.I.C DLL Extended Mode Register (1) A6 BA1 0 0 1 1 BA0 0 1 0 1 MRS mode MRS EMR (1) EMR (2) EMR (3) 0 0 1 1 A2 0 1 0 1 Rtt (nominal) ODT disabled 75 ohm 150 ohm 50 ohm*1 A1 A0 0 1 DLL Enable Enable Disable Driver strength control Output driver impedance control Normal Reduced Additive Latency A5 0 0 0 A4 0 0 1 1 0 0 1 1 A3 0 1 0 1 0 1 0 1 Latency 0 1 2 3 4 5 6 Resesved DDR2-667/800 Driver size 100% 60% Driver impedance adjustment A9 0 0 0 1 1 A8 0 0 1 0 1 A7 0 1 0 0 1 OCD Calibration Program OCD calibration mode exit ; matain setting Drive (1) Drive (0) Adjust mode*2 OCD Calibration default *3 0 1 A12 0 1 Qoff Output duffers enabled Output duffers disabled 0 1 1 1 A10 0 1 1 DQS Enable Disable A11 A10 (DQS Enable) 0 (Enable ) 1 (Disable) 0 (Enable) 1 (Disable) RDQS/DM DM DM RDQS RDQS Strobe Function Matrix RDQS Hi-z Hi-z RDQS Hi-z DQS DQS DQS DQS DQS DQS DQS Hi-z DQS Hi-z A11 0 1 RDQS Enable*4 Disable Enable (RDQS Enable) 0 (Disable) 0 (Disable) 1 (Enable) 1 (Enable) Notes: 1. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066. 2. When Adjust mode is issued, AL from previously set value must be applied. 3. After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. Refer to the section 7.2.3 for detailed information. 4. If RDQS is enabled, the DM function is disabled. RDQS is active for reads and don‟t care for writes. Figure 3 – EMR (1) - 12 - Publication Release Date: Feb. 18, 2011 Revision A02 DDR2-1066 W972GG8JB 7.2.2.3 Extend Mode Register Set Command (2), EMR (2) ( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "H", BA2 = "L" A0 to A14 = Register data) The extended mode register (2) controls refresh related features. The default value of the extended mode register (2) is not defined, therefore the extended mode register (2) must be programmed during initialization for proper operation. The DDR2 SDRAM should be in all bank precharge state with CKE already high prior to writing into the extended mode register (2). The mode register set command cycle time (t MRD) must be satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 0*1 1 0 0*1 SELF 0*1 Extended Mode Register (2) BA1 BA0 0 0 1 1 0 1 0 1 MRS mode MRS EMR (1) EMR (2) EMR (3) A7 0 1 High Temperature Self Refresh Rate Enable Disable Enable*2 Notes: 1. The rest bits in EMR (2) is reserved for future use and all bits in EMR (2) except A7, BA0, BA1 and BA2 must be programmed to 0 when setting the extended mode register (2) during initialization. 2. When DRAM is operated at 85°C < TCASE ≤ 95°C the extended Self Refresh rate must be enabled by setting bit A7 to "1" before the Self Refresh mode can be entered. Figure 4 – EMR (2) - 13 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 7.2.2.4 Extend Mode Register Set Command (3), EMR (3) ( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "H", BA2 = "L", A0 to A14 = Register data) No function is defined in extended mode register (3). The default value of the EMR (3) is not defined, therefore the EMR (3) must be programmed during initialization for proper operation. BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 0*1 1 1 0*1 Extended Mode Register (3) Note: 1. All bits in EMR(3) except BA0 and BA1 are reserved for future use and must be set to "0" when programming the EMR(3). Figure 5 – EMR (3) - 14 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 7.2.3 Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart in Figure 6 is an example of the sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before any other command being issued. MRS should be set before entering OCD impedance adjustment and On Die Termination (ODT) should be carefu lly controlled depending on system environment. All MR shoud be programmed before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS: OCD calibration mode exit EMRS: Drive(1) DQ &DQS High; DQS Low EMRS: Drive(0) DQ &DQS Low; DQS High Test ALL OK ALL OK Test Need Calibration Need Calibration EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: Enter Adjust Mode EMRS: Enter Adjust Mode BL=4 code input to all DQs Inc, Dec or NOP BL=4 code input to all DQs Inc, Dec or NOP EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End Figure 6 – OCD Impedance Adjustment Flow Chart - 15 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 7.2.3.1 Extended Mode Register for OCD Impedance Adjustment OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMR bit enabling RDQS operation. In Drive (1) mode, all DQ, DQS (and RDQS) signals are driven HIGH and all DQS signals are driven LOW. In Drive (0) mode, all DQ, DQS (and RDQS) signals are driven LOW and all DQS signals are driven HIGH. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 Ω during nominal temperature and voltage conditions. OCD applies only to normal full strength output drive setting defined by EMR (1) and if reduced strength is set, OCD default driver characteristic s are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS commands not intended to adjust OCD chara cteristics must specify A[9:7] as ‟000‟ in order to maintain the default or calibrated value. Table 1 – OCD Drive Mode Program A9 0 0 0 1 1 A8 0 0 1 0 1 A7 0 1 0 0 1 Operation OCD calibration mode exit Drive (1) DQ, DQS, (RDQS) HIGH and DQS LOW Drive (0) DQ, DQS, (RDQS) LOW and DQS HIGH Adjust mode OCD calibration default 7.2.3.2 OCD Impedance Adjust To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4 bit burst code to DDR2 SDRAM as in table 2. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 in table 2 means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs and DQS‟s of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the 16 step range. When Adjust mode command is issued, AL from previously set value must be applied. Table 2 – OCD Adjust Mode Program 4 bit burst code inputs to all DQs DT0 DT1 DT2 DT3 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 Other Combinations Operation Pull-up driver strength Pull-down driver strength NOP (No operation) NOP (No operation) Increase by 1 step NOP Decrease by 1 step NOP NOP Increase by 1 step NOP Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step Decrease by 1 step Reserved - 16 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as shown in Figure 7. For input data pattern for adjustment, DT0 - DT3 is a fixed order and is not affected by burst type (i.e., sequential or interleave). CLK CLK CMD EMRS WL NOP NOP DQS NOP NOP NOP WR NOP EMRS NOP DQS_in tDS tDH DQ_in DT0 DT1 DT2 DT3 DM OCD adjust mode OCD calibration mode exit Figure 7 – OCD Adjust Mode 7.2.3.3 Drive Mode Drive mode, both Drive (1) and Drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers are turned-off tOIT after “OCD calibration mode exit” command as shown in Figure 8. CLK CLK CMD EMRS tOIT NOP NOP NOP NOP EMRS tOIT NOP NOP NOP DQS DQS DQS high & DQS low for Drive (1), DQS low & DQS high for Drive (0) DQs high for Drive (1) HI-Z DQ DQs low for Drive (0) Enter Drive mode OCD calibration mode exit Figure 8 – OCD Drive Mode - 17 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 7.2.4 On-Die Termination (ODT) On-Die Termination (ODT) is a new feature on DDR2 components that allows a DRAM to turn on/off termination resistance for each DQ, DQS/ DQS , RDQS/ RDQS , and DM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance f or any or all DRAM devices. The ODT function can be used for all active and standby modes. ODT is turned off and n ot supported in Self Refresh mode. (Example timing waveforms refer to 10.3, 10.4 ODT Timing for Active/Standby/Power Down Mode and 10.5, 10.6 ODT timing mode switch at entering/exiting power down mode diagram in Chapter 10) VDDQ VDDQ VDDQ sw1 Rval1 DRAM Input Buffer Rval1 sw2 Rval2 sw3 Rval3 Input Pin Rval2 Rval3 sw1 sw2 sw3 VSSQ VSSQ VSSQ Switch (sw1, sw2, sw3) is enabled by ODT pin. Selection among sw1, sw2, and sw3 is determined by “Rtt (nominal)” in EMR (1). Termination included on all DQs, DM, DQS, DQS , RDQS, and RDQS pins. Figure 9 – Functional Representation of ODT 7.2.5 ODT related timings 7.2.5.1 MRS command to ODT update delay During normal operation the value of the effective termination resistance can b e changed with an EMRS command. The update of the Rtt setting is done between t MOD,min and tMOD,max, and CKE must remain HIGH for the entire duration of tMOD window for proper operation. The timings are shown in the following timing diagram . - 18 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB CMD EMRS NOP NOP NOP NOP NOP CLK CLK ODT tIS tMOD,max tAOFD tMOD,min Rtt Old setting Updating New setting 1) EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal). 2) "setting" in this diagram is the Register and I/O setting, not what is measured from outside. Figure 10 – ODT update delay timing - tMOD However, to prevent any impedance glitch on the channel, the following conditions must be met.  tAOFD must be met before issuing the EMRS command.  ODT must remain LOW for the entire duration of tMOD window, until tMOD,max is met. Now the ODT is ready for normal operation with the new setting, and the ODT signal may be raised again to turned on the ODT. Following timing diagram shows the proper Rtt update procedure . CLK CLK CMD EMRS NOP NOP NOP NOP NOP ODT tIS tAOFD tMOD,max tAOND Rtt Old setting New setting 1) EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal). 2) "setting" in this diagram is what is measured from outside. Figure 11 – ODT update delay timing - tMOD, as measured from outside - 19 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 7.3 7.3.1 Command Function Bank Activate Command ( CS ="L", RAS ="L", CAS ="H", WE ="H", BA0, BA1, BA2=Bank, A0 to A14 be row address) The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a Read/Write command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay when the Read/Write command is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 and 6 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between Bank Activate commands is tRRD. In order to ensure that components with 8 internal memory banks do not exceed the instantaneous current supplying capability, certain restrictions on operation of the 8 banks must be observed. There are two rules. One for restricting the number of sequential ACT commands that can be issued and another for allowing more time for RAS precharge for a Precharge All command. The rules are as follows:  Sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling t FAW window. Converting to clocks is done by dividing t FAW[nS] by tCK(avg)[ns], and rounding up to next integer value. As an example of the rolling window, if RU{ (t FAW / tCK(avg) } is 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued at or between clock N+1 and N+9.  Precharge All Allowance: tRP for a Precharge All command is equal to tnRP + 1 x nCK, where tnRP = RU{ tRP / tCK(avg) } and tRP is the value for a single bank precharge. T0 CLK CLK T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 Internal RAS - RAS delay (≥ tRCDmin) Bank A Row Addr. Bank A Col. Addr. Bank B Row Addr. Bank B Col. Addr. Bank A Addr. Bank B Addr. Bank A Row Addr. Address CAS - CAS delay time(tCCD) tRCD = 1 Additive Latency delay(AL) Read Begins RAS - RAS delay time(≥ tRRD) Command Bank A Activate Bank A Post CAS Read Bank B Activate Bank Active (≥ tRAS) Bank B Post CAS Read Bank A Precharge Bank B Precharge Bank Precharge time (≥ tRP) Bank A Activate RAS Cycle time (≥ tRC) Figure 12 – Bank activate command cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2 - 20 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 7.3.2 Read Command ( CS ="L", RAS ="H", CAS ="L", WE ="H", BA0, BA1, BA2=Bank, A10="L", A0 to A9=Column Address) The READ command is used to initiate a burst read access to an active row. The value on BA0, BA1, BA2 inputs selects the bank, and the A0 to A9 address inputs determine the starting column address . The address input A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected, the row being accessed will be precharged at the end of the READ burst; if Auto-precharge is not selected, the row will remain open for subsequent accesses. 7.3.3 Write Command ( CS ="L", RAS ="H", CAS ="L", WE ="L", BA0, BA1, BA2=Bank, A10="L", A0 to A9=Column Address) The W RITE command is used to initiate a burst write access to an active row. The value on BA0, BA 1, BA2 inputs selects the bank, and the A0 to A9 address inputs determine the starting column address . The address input A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if Auto-precharge is not selected, the row will remain open for subsequent accesses. 7.3.4 Burst Read with Auto-precharge Command ( CS ="L", RAS ="H", CAS ="L", WE ="H", BA0, BA1, BA2=Bank, A10="H", A0 to A9=Column Address) If A10 is HIGH when a Read Command is issued, the Read with Auto-precharge function is engaged. The DDR2 SDRAM starts an Auto-precharge operation on the rising edge which is (AL + BL/2) cycles later than the read with AP command if tRAS(min) and tRTP(min) are satisfied. 7.3.5 Burst Write with Auto-precharge Command ( CS ="L", RAS ="H", CAS ="L", WE ="L", BA0, BA1, BA2=Bank, A10="H", A0 to A9=Column Address) If A10 is HIGH when a Write Command is issued, the Write with Auto-precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (WR) programmed in the mode register. 7.3.6 Precharge All Command ( CS ="L", RAS ="L", CAS ="H", WE ="L", BA0, BA1, BA2=Don‟t Care, A10="H", A0 to A9 and A11 to A14=Don‟t Care) The Precharge All command precharge all banks simultaneously. Then all banks are switched to the idle state. 7.3.7 Self Refresh Entry Command ( CS ="L", RAS ="L", CAS ="L", WE ="H", CKE="L", BA0, BA1, BA2, A0 to A14=Don‟t Care) The Self Refresh command can be used to retain data, even if the rest of the system is powered down. When in the Self Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin LOW or using an EMRS command. Once the command is registered, CKE must be held LOW to keep the device in Self Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is autom atically enabled upon exiting Self Refresh. When the DDR2 SDRAM has entered Self Refresh mode, all of the external signals except CKE, are “Don‟t Care”. The clock is internally disabled during self refresh operation to save power. The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered; however, the clock must be restarted and stable before the device can exit self refresh operation. - 21 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 7.3.8 Self Refresh Exit Command (CKE="H", CS ="H" or CKE="H", CS ="L", RAS ="H", CAS ="H", WE ="H", BA0, BA1, BA2, A0 to A14=Don‟t Care) The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least t XSNR must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period t XSRD for proper operation except for self refresh re-entry. Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after waiting at least tXSNR period and issuing one refresh command (refresh period of tRFC). NOP or Deselect commands must be registered on each positive clock edge during the Self Refresh exit interval t XSNR. ODT should be turned off during tXSRD. The use of Self Refresh mode introduces the possibility that an internally timed refre sh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh mode. 7.3.9 Refresh Command ( CS ="L", RAS ="L", CAS ="L", WE ="H", CKE="H", BA0, BA1, BA2, A0 to A14=Don‟t Care) Refresh is used during normal operation of the DDR2 SDRAM. This command is non persistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don‟t Care” during an Auto Refresh command. The DDR2 SDRAM requires Auto Refresh cycles at an average periodic interval of tREFI (max.). W hen the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A delay between the auto refresh command (REF) and the next activate command or subsequent auto refresh command must be greater than or equal to the auto refresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 9 x tREFI. T0 CLK/CLK T1 T2 T3 Tm Tn Tn + 1 "HIGH" CKE ≥ tRP ≥ tRFC ≥ tRFC CMD Precharge NOP NOP REF REF NOP ANY Figure 13 – Refresh command - 22 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 7.3.10 No-Operation Command ( CS ="L", RAS ="H", CAS ="H", WE ="H", CKE, BA0, BA1, BA2, A0 to A14=Don‟t Care) The No-Operation command simply performs no operation (same command as Device Deselect). 7.3.11 Device Deselect Command ( CS ="H", RAS , CAS , WE , CKE, BA0, BA1, BA2, A0 to A14=Don‟t Care) The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 7.4 Read and Write access modes The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. The 32 Mbit x 8 I/O x 8 Bank chip has a page length of 1024 bits (defined by CA0 to CA9) . The page length of 1024 is divided into 256 or 128 uniquely addressable boundary segments depending on burst length, 256 for 4 bit burst, 128 for 8 bit burst respectively. A 4-bit or 8-bit burst operation will occur entirely within one of the 256 or 128 groups beginning with the column address supplied to the device during the Read or Write Command (CA0 to CA9). The second, third and fourth access will also occur within this group segment. However, the burst order is a function of the starting address, and the burst sequence. A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundary respectively. The minimum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles. Note: Page length is a function of I/O organization and column addressing 32M bits × 8 organization (CA0 to CA9); Page Length = 1024 bits * 7.4.1 Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command (or any time during the RAS - CAS -delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS Latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL (greater than 0) must be written into the EMR (1). The Write Latency (WL) is always defined as RL -1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS Latency (RL = AL + CL). Read or Write operations using AL allow seamless bursts . (Example timing waveforms refer to 10.11 and 10.12 seamless burst read/write operation diagram in Chapter 10) 7.4.1.1 Examples of posted CAS operation Examples of a read followed by a write to the same bank where AL = 2 and where AL = 0 are shown in Figures 14 and 15, respectively. - 23 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB -1 CLK /CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 CMD Active A-Bank Read A-Bank Write A-Bank WL=RL-1=4 AL=2 DQS/DQS ≥ tRCD RL=AL+CL=5 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 CL=3 [AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4] Figure 14 – Example 1: Read followed by a write to the same bank, where AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4 -1 CLK/CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 AL=0 CMD Active A-Bank Read A-Bank Write A-Bank WL=RL-1=2 CL=3 DQS/DQS ≥ tRCD RL=AL+CL=3 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4] Figure 15 – Example 2: Read followed by a write to the same bank, where AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4 7.4.2 Burst mode operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by MR A[2:0]. The burst type, either sequential or interleaved, is programmable and defined by MR [A3]. Seamless burst read or write operations are supported. Publication Release Date: Feb. 18, 2011 Revision A02 - 24 - W972GG8JB Unlike DDR1 devices, interruption of a burst read or writes cycle during BL = 4 mode operation is prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write. (Example timing waveforms refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in Chapter 10) Therefore the Burst Stop command is not supported on DDR2 SDRAM devices. Table 3 – Burst Length and Sequence Burst Length Starting Address (A2 A1 A0) x00 4 x01 x10 x11 000 001 010 8 011 100 101 110 111 Sequential Addressing (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 Interleave Addressing (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 7.4.3 Burst read mode operation Burst Read is initiated with a READ command. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven LOW one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS Latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register EMR (1). (Example timing waveforms refer to 10.7 and 10.8 Data output (read) timing and Burst read operation diagram in Chapter 10) 7.4.4 Burst write mode operation Burst W rite is initiated with a W RITE command. The address inputs determine the starting column address for the burst. W rite Latency (WL) is defined by a Read Latency (RL) minus one and is equal to (AL + CL -1); and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first DQS str obe. A data strobe signal (DQS) should be driven LOW (preamble) nominally half clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (WR). (Example timing waveforms refer to 10.9 and 10.10 Data input (write) timing and Burst write operation diagram in Chapter 10) Publication Release Date: Feb. 18, 2011 Revision A02 - 25 - W972GG8JB 7.4.5 Write data mask One write data mask (DM) pin for each 8 data bits (DQ) wi ll be supported on DDR2 SDRAM, consistent with the implementation on DDR1 SDRAM. It has identical timings on write operations as the data bits, and though used in a unidirectional manner, is internally loaded identically to data bits to insure matched system timing. DM function is disabled, when RDQS / RDQS are enabled by EMRS(1). (Example timing waveform refer to 10.15 Write operation with Data Mask diagram in Chapter 10) 7.5 Burst Interrupt Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by W rite or Precharge Command is prohibited. 2. W rite burst of 8 can only be interrupted by another Write command. Write burst interruption by Read or Precharge Command is prohibited. 3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings are prohibited. 4. W rite burst interrupt must occur exactly two clocks after the previous Write command. Any other W rite burst interrupt timings are prohibited. 5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM. 6. Read or Write burst with Auto-precharge enabled is not allowed to interrupt. 7. Read burst interruption is allowed by a Read with Auto-precharge command. 8. W rite burst interruption is allowed by a Write with Auto-precharge command. 9. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For example below:  Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not from the end of the actual burst end.  (Example timing waveforms refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in Chapter 10) - 26 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 7.6 Precharge operation The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Four address bits A10, BA0 and BA1 and BA2 are used to define which bank to precharge when the command is issued. Table 4 – Bank selection for precharge by address bits A10 LOW LOW LOW LOW LOW LOW LOW LOW HIGH BA2 LOW LOW LOW LOW HIGH HIGH HIGH HIGH Don‟t Care BA1 LOW LOW HIGH HIGH LOW LOW HIGH HIGH Don‟t Care BA0 LOW HIGH LOW HIGH LOW HIGH LOW HIGH Don‟t Care Precharge Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 4 only Bank 5 only Bank 6 only Bank 7 only All Banks 7.6.1 Burst read operation followed by precharge Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max( RTP, 2) - 2 clks For the earliest possible precharge, the precharge command may be issued on the rising edge which is “Additive Latency (AL) + BL/2 + max(RTP, 2) - 2 clocks” after a Read command. A new bank active (command) may be issued to the same bank after the RAS precharge time (t RP). A precharge command cannot be issued until tRAS is satisfied. The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command. (Example timing waveforms refer to 10.16 to 10.20 Burst read operation followed by precharge diagram in Chapter 10) 7.6.2 Burst write operation followed by precharge Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR For write cycles, a delay must be satisfied from the completion of the l ast burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay. (Example timing waveforms refer to 10.21 to 10.22 Burst write operation followed by precharge diagram in Chapter 10) 7.7 Auto-precharge operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command or the Auto-precharge function. When a Read or a Write command is given to the DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is LOW when the READ or WRITE command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is HIGH when the Read or Write command is issued, then the Auto-precharge function is engaged. During Auto-precharge, a Read command will execute as norm al with the exception that the - 27 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB active bank will begin to precharge on the rising edge which is CAS Latency (CL) clock cycles before the end of the read burst. Auto-precharge is also implemented during Write commands. The precharge operation engaged by the Auto-precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS Latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed (tRAS satisfied) so that the Auto-precharge command may be issued with any read or write command. 7.7.1 Burst read with Auto-precharge If A10 is HIGH when a Read Command is issued, the Read with Auto-precharge function is engaged. The DDR2 SDRAM starts an Auto-precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if tRAS(min) and tRTP(min) are satisfied. (Example timing waveform refer to 10.23 Burst read operation with Auto-precharge diagram in Chapter 10) If tRAS(min) is not satisfied at the edge, the start point of Auto-precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the start point of Auto-precharge operation will be delayed until tRTP(min) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where tRTP ends (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Autoprecharge to the next Activate command becomes AL + RU{ (tRTP + tRP) / tCK } (Example timing waveform refer to 10.24 Burst read operation with Auto-precharge diagram in Chapter 10.), for BL = 8 the time from Read with Auto-precharge to the next Activate command is AL + 2 + RU{ (tRTP + tRP) / tCK }, where RU stands for “rounded up to the next integer”. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. A new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously. The RAS precharge time (tRP) has been satisfied from the clock at which the Auto -precharge begins.  The RAS cycle time (tRC) from the previous bank activation has been satisfied. (Example timing waveforms refer to 10.25 to 10.26 Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit) and (tRP Limit) diagram in Chapter 10)  7.7.2 Burst write with Auto-precharge If A10 is HIGH when a Write Command is issued, the Write with Auto -Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (WR) programmed in the mode register. The bank undergoing Autoprecharge from the completion of the write burst may be reactivated if the following two conditions are satisfied.  The data-in to bank activate delay time (WR + tRP) has been satisfied.  The RAS cycle time (tRC) from the previous bank activation has been satisfied. (Example timing waveforms refer to 10.27 to 10.28 Burst write with Auto-precharge (tRC Limit) and (WR + tRP Limit) diagram in Chapter 10) - 28 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB Table 5 – Precharge & Auto-precharge clarifications From Command Read To Command Precharge (to same Bank as Read) Precharge All Read w/AP Precharge (to same Bank as Read w/AP) Precharge All Write Precharge (to same Bank as Write) Precharge All Write w/AP Precharge (to same Bank as Write w/AP) Precharge All Precharge Precharge (to same Bank as Precharge) Precharge All Precharge All Precharge Precharge All Minimum Delay between “From Command” to “To Command” AL + BL/2 + max(RTP, 2) - 2 AL + BL/2 + max(RTP, 2) - 2 AL + BL/2 + max(RTP, 2) - 2 AL + BL/2 + max(RTP, 2) - 2 WL + BL/2 + tWR WL + BL/2 + tWR WL + BL/2 + W R WL + BL/2 + W R 1 1 1 1 Unit clks clks clks clks clks clks clks clks clks clks clks clks Notes 1, 2 1, 2 1, 2 1, 2 2 2 2 2 2 2 2 2 Notes: 1. RTP[cycles] = RU{ tRTP[nS] / tCK(avg)[nS] }, where RU stands for round up. 2. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRPall (= tRP + 1 x tCK) depending on the latest precharge command issued to that bank. 7.8 Refresh Operation DDR2 SDRAM requires a refresh of all rows in any rolling 64 ms interval. The necessary refresh can be generated in one of two ways: by explicit Auto Refresh commands or by an internally timed Self Refresh mode. Self Refresh mode enters issuing the Self Refresh command (CKE asserted "LOW ") while all banks are in the idle state. The device is in Self Refresh mode for as long as CKE held "LOW ". In the case of 8192 burst Auto Refresh commands, 8192 burst Auto Refresh commands must be performed within 7.8 µ S before entering and after exiting the Self Refresh mode. In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8 µ S and the last distributed Auto Refresh commands must be performed within 7.8 µ S before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 7.8 µ S. In Self Refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except CKE buffer). (Example timing waveform refer to 10.29 Self Refresh diagram in Chapter 10) 7.9 Power Down Mode Power-down is synchronously entered when CKE is registered LOW, along with NOP or Deselect command. CKE is not allowed to go LOW while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go LOW while any other operation such as row activation, Precharge or Auto-precharge or Auto Refresh is in progress, but power down IDD specification will not be applied until finishing those operations. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. - 29 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 7.9.1 Power Down Entry Two types of Power Down Mode can be performed on the device: Precharge Power Down Mode and Active Power Down Mode. If power down occurs when all banks are idle, this mode is referred to as Precharge Power Down; if power down occurs when there is a row active in any bank, this mode is referred to as Active Power Down. Entering power down deactivates the input and output buffers, excluding C LK, CLK , ODT and CKE. Also the DLL is disabled upon entering Precharge Power Down or slow exit Active Power Down, but the DLL is kept enabled during fast exit Active Power Down. In power down mode, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and ODT should be in a valid state but all other input signals are “Don‟t Care”. CKE LOW must be maintained until tCKE has been satisfied. Maximum power down duration is limited by the refresh requirements of the device, which allows a maximum of 9 x tREFI if maximum posting of REF is utilized immediately before entering power down. (Example timing waveforms refer to 10.30 to 10.31 Active and Precharged Power Down Mode Entry and Exit diagram in Chapter 10) 7.9.2 Power Down Exit The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes HIGH. Power-down exit latency is defined at AC Characteristics table of this data sheet. 7.10 Input clock frequency change during precharge power down DDR2 SDRAM input clock frequency can be changed under following condition: DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL must be RESET via MRS command after precharge power down exit. Depending on new clock frequency an additional MRS or EMRS command may need to be issued to appropriately set the WR, CL etc… During DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency. (Example timing waveform refer to 10.32 Clock frequency change in precharge Power Down mode diagram in Chapter 10) - 30 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 8. OPERATION MODE 8.1 Command Truth Table CKE Previous Current Cycle Cycle H H H H H H H H H H H H H H BA2 BA1 BA0 BA BA X BA BA BA BA X X Column Column Column Column A14-A11 A10 A9-A0 CS RA S CA S COMMAND Bank Activate Single Bank Precharge Precharge All Banks Write Write with Autoprecharge Read Read with Autoprecharge (Extended) Mode Register Set No Operation Device Deselect Refresh Self Refresh Entry Self Refresh Exit Power Down Mode Entry Power Down Mode Exit Notes: WE H L L L L H H NOTES 1,2 1,2 1 1,2,3 1,2,3 1,2,3 1,2,3 Row Address L H L H L H X X Column Column Column Column L L L L L L L L L L H H H H H H H L L L L H H H H H L H X X H L H BA X X X X X X X X X X OP Code X X X X X X X X X X L L H L L H L H L H L H X L L X H X H X H L H X L L X H X H X H L H X H H X H X H X 1,2 1 1 1 1,4 1,4,5 H L X X X X 1,6 L H X X X X L H 1,6 1. All DDR2 SDRAM commands are defined by states of C S , RAS , C AS , WE and CKE at the rising edge of the clock. 2. Bank addresses BA [2:0] determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. 3. Burst reads or writes at BL = 4 can not be terminated or interrupted. See Burst Interrupt in section 7.5 for details. 4. VREF must be maintained during Self Refresh operation. 5. Self Refresh Exit is asynchronous. 6. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in section 7.9. - 31 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 8.2 Clock Enable (CKE) Truth Table for Synchronous Transitions CKE CURRENT STATE2 Previous Cycle (N-1) L Power Down L L Self Refresh L Bank(s) Active H H All Banks Idle H H Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N). All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t XSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. Self Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as defined in the Command Truth Table. Valid commands for Power Down Entry and Exit are NOP and DESELECT only. Valid commands for Self Refresh Exit are NOP and DESELECT only. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge operations are in progress. See section 7.9 "Power Down Mode" and section 7.3.7/7.3.8 "Self Refresh Entry/Exit Command" for a detailed list of restrictions. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in section 7.9. “X” means “don‟t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMR (1)). VREF must be maintained during Self Refresh operation. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See section 7.2.4. CKE must be maintained HIGH while the SDRAM is in OCD calibration mode. L H REFRESH H L L DESELECT or NOP DESELECT or NOP DESELECT or NOP Self Refresh Exit Active Power Down Entry Precharge Power Down Entry Self Refresh Entry 4, 5, 9, 14 4, 8, 10, 11, 12 4, 8, 10, 11, 12 6, 9, 11, 12 7 H L DESELECT or NOP X Power Down Exit Maintain Power Down 4, 8, 11, 12 11, 13, 14 1 COMMAND (N) 3 Current Cycle (N) L 1 RA , CA , WE , CS S S ACTION (N) 3 NOTES X Maintain Power Down 11, 12, 13 Refer to the Command Truth Table 11. 12. 13. 14. 15. 16. 8.3 Data Mask (DM) Truth Table FUNCTION Write enable Write inhibit DM L H DQS Valid X NOTE 1 1 Note: 1. Used to mask write data, provided coincident with the corresponding data. - 32 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 8.4 Function Truth Table CS R AS C AS CURRENT STATE WE X H H L H L H L X H H L H L H L X H H L H L H L X H H L H L H L ADDRESS X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code COMMAND DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS ACTION NOP or Power down NOP or Power down ILLEGAL ILLEGAL Row activating Precharge/ Precharge all banks Auto Refresh or Self Refresh Mode/Extended register accessing NOP NOP Begin read Begin write ILLEGAL Precharge/ Precharge all banks ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst interrupt ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL Burst interrupt ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOTES H L L L Idle L L L L H L L Banks Active L L L L L H L L Read L L L L L H L L Write L L L L L X H H H L L L L X H H H L L L L X H H H L L L L X H H H L L L L X H L L H H L L X H L L H H L L X H L L H H L L X H L L H H L L 1 1 2 2 1 1,3 1 1 1 1 1,3 1 1 - 33 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB Function Truth Table, continued CURRENT STATE CS R AS C AS WE X H H L H L H L X H H L H L H L X H H L H L H L X H H L H L H L ADDRESS X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code COMMAND DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS ACTION Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after tRP NOP-> Idle after tRP ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after tRP ILLEGAL ILLEGAL NOP-> Row active after tRCD NOP-> Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOTES H L L Read with Autoprecharge L L L L L H L L Write with Autoprecharge L L L L L H L L L Precharge L L L L H L L Row Activating L L L L L X H H H L L L L X H H H L L L L X H H H L L L L X H H H L L L L X H L L H H L L X H L L H H L L X H L L H H L L X H L L H H L L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 34 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB Function Truth Table, continued CURRENT STATE CS R AS C AS WE X H H L H L H L X H H L H L H L X H H L H L H L X H H L H L H L ADDRESS X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code COMMAND DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS ACTION NOP-> Bank active after tWR NOP-> Bank active after tWR ILLEGAL New write ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Precharge after tWR NOP-> Precharge after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after tRC NOP-> Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after tMRD NOP-> Idle after tMRD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOTES H L L Write Recovering L L L L L H L L Write Recovering with Autoprecharge L L L L L H L L Refreshing L L L L L H L L Mode Register Accessing L L L L L Notes: X H H H L L L L X H H H L L L L X H H H L L L L X H H H L L L L X H L L H H L L X H L L H H L L X H L L H H L L X H L L H H L L 1 1 1 1 1 1 1 1. This command may be issued for other banks, depending on the state of the banks . 2. All banks must be in "IDLE". 3. Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8 . Burst read/write can only be interrupted by another read/write with 4 bit burst boundary. Any other case of read/write interrupt is not allowed. Remark: H = High level, L = Low level, X = High or Low level (Don‟t Care), V = Valid data. - 35 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 8.5 Simplified Stated Diagram OCD calibration Initialization Sequence CKEL Self Refreshing SELF PRE Setting MR,EMR (1) EMR (2) EMR (3) (E)MRS Idle All banks Precharged CKEL ACT CKEH CKEL Precharge Power Down CKEL CKEH REF Refreshing Activating CKEL CKEL Autoomatic Sequence Command Sequence Active Power Down CKEH CKEL Bank Active Write Write WRITA READA Read Write Read Read CKEL = CKE LOW, enter Power Down CKEH = CKE HIGH, exit Power Down CKEH = CKE HIGH, exit Self Refresh ACT = Activate WRITA = Write with Auto-precharge READA = Read (with Auto-precharge PREA = Precharge All (E)MRS = (Extended) Mode Register Set SELF = Enter Self Refresh REF = Refresh Writing Reading WRITA READA WRITA Writing with Auto-precharge PRE, PREA PRE, PREA PRE, PREA READA Reading with Auto-precharge Precharging - 36 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for e xtended periods may affect reliability. 2. When VDD and VDDQ and VDDL are less than 500mV; VREF may be equal to or less than 300mV. 3. Storage temperature is the case surface temperature on the center/top side of the DRAM. SYMBOL VDD VDDQ VDDL VIN, VOUT TSTG RATING -1.0 ~ 2.3 -0.5 ~ 2.3 -0.5 ~ 2.3 -0.5 ~ 2.3 -55 ~ 100 UNIT V V V V °C NOTES 1, 2 1, 2 1, 2 1, 2 1, 2, 3 9.2 Operating Temperature Condition PARAMETER SYMBOL TOPR TOPR RATING 0 ~ 85 -40 ~ 95 UNIT °C °C NOTES 1, 2, 3 1, 2, 3, 4 Operating Temperature (for -18/-25/-3) Operating Temperature (for 25I) Notes: 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. 2. Supporting 0 ~ 85°C with full JEDEC AC and DC specifications . 3. Supporting 0 ~ 85°C and being able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS period ( tREFI = 3.9 µ S), the High Temperature Self Refresh has to be enabled by setting EMR (2) bit A7 to 1. When the High Temperature Self Refresh is enabled there is an increase of I DD6 by approximately 50%. 4. During operation, the DRAM case temperature must be maintained between -40 to 95°C for Industrial parts under all specification parameters. 9.3 VDD Recommended DC Operating Conditions PARAMETER Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage (System) SYM. VDDL VDDQ VREF VTT Notes: MIN. 1.7 1.7 1.7 0.49 x VDDQ VREF - 0.04 TYP. 1.8 1.8 1.8 0.5 x VDDQ VREF M AX. 1.9 1.9 1.9 0.51 x VDDQ VREF + 0.04 UNIT V V V V V NOTES 1 5 1, 5 2, 3 4 1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions V DDQ must than or equal to VDD. 2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of V REF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 3. Peak to peak AC noise on VREF may not exceed ± 2 % VREF(dc). 4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and device must track VREF of receiving device. 5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. - 37 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 9.4 ODT DC Electrical Characteristics PARAMETER/CONDITION Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 Ω Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 Ω Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 Ω Deviation of VM with respect to VDDQ/2 Notes: 1. Test condition for Rtt measurements. 2. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066. SYM. Rtt1(eff) Rtt2(eff) Rtt3(eff) ΔVM MIN. 60 120 40 -6 NOM. 75 150 50 MAX. 90 180 60 +6 UNIT Ω Ω Ω % NOTES 1 1 1, 2 1 Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and I(VIL (ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18. Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)) Measurement Definition for ΔVM: Measure voltage (VM) at test pin (midpoint) with no load. ΔVM = ((2 x Vm / VDDQ) – 1) x 100% 9.5 Input DC Logic Level SYM. VIH(dc) VIL(dc) PARAMETER DC input logic HIGH DC input logic LOW MIN. VREF + 0.125 -0.3 M AX. VDDQ + 0.3 VREF - 0.125 UNIT V V 9.6 Input AC Logic Level SYM. VIH (ac) VIL (ac) PARAMETER AC input logic HIGH AC input logic LOW Note: -18 MIN. VREF + 0.200  -25/25I/-3 M AX.  VREF - 0.200 MIN. VREF + 0.200 VSSQ - VPEAK 1 M AX. VDDQ + VPEAK1 VREF - 0.200 UNIT V V 1. Refer to the page 66 sections 9.14.1 and 9.14.2 AC Overshoot/Undershoot specification table for VPEAK value: maximum peak amplitude allowed for Overshoot/Undershoot. - 38 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 9.7 Capacitance PARAMETER Input Capacitance , CLK and CLK Input Capacitance delta , CLK and CLK input Capacitance, all other input-only pins Input Capacitance delta, all other input-only pins Input/output Capacitance, DQ, DM, DQS, DQS ,RDQS, RDQS Input/output Capacitance delta, DQ, DM, DQS, DQS ,RDQS, RDQS MIN. 1.0  1.0  2.5  M AX. 2.0 0.25 2.0 0.25 3.5 0.5 UNIT pF pF pF pF pF pF SYM. CCK CDCK CI CDI CIO CDIO 9.8 Leakage and Output Buffer Characteristics PARAMETER Input Leakage Current IIL (0V ≤ VIN ≤ VDD) Output Leakage Current (Output disabled, 0V ≤ VOUT ≤ VDDQ) Minimum Required Output Pull-up Maximum Required Output Pull-down Output Minimum Source DC Current Output Minimum Sink DC Current -2 2 µA 1 MIN. M AX. UNIT NOTES SYM. IOL VOH VOL IOH(dc) IOL(dc) Notes: -5 VTT + 0.603  -13.4 13.4 5  VTT - 0.603   µA V V mA mA 2 3, 5 4, 5 1. All other pins not under test = 0 V. 2. DQ, DQS, DQS , RDQS, RDQS are disabled and ODT is turned off. 3. VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT - VDDQ)/IOH must be less than 21 Ω for values of VOUT between VDDQ and VDDQ 0.28V. 4. VDDQ = 1.7 V; VOUT = 0.28V. VOUT/IOL must be less than 21 Ω for values of VOUT between 0 V and 0.28V. 5. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 3 and 4. They are used to test drive current capability to ensure VIHmin plus a noise margin and VILmax minus a noise margin are delivered to an SSTL_18 receiver. - 39 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 9.9 DC Characteristics 18 25/25I MAX. 3 UNIT MAX. Operating Current - One Bank Active-Precharge tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); SYM. CONDITIONS MAX. NOTES IDD0 IDD1 CKE is HIGH, C S is HIGH between valid commands; Address and control inputs are SWITCHING; Databus inputs are SWITCHING. Operating Current - One Bank Active-ReadPrecharge IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, C S is HIGH between valid commands; Address and control inputs are SWITCHING; Data bus inputs are SWITCHING. Precharge Power-Down Current All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address inputs are STABLE; Data Bus inputs are FLOATING. (TCASE ≤ 85°C) Precharge Standby Current All banks idle; tCK = tCK(IDD); CKE is HIGH, C S is HIGH; Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING. Precharge Quiet Standby Current All banks idle; tCK = tCK(IDD); CKE is HIGH, C S is HIGH; Other control and address inputs are STABLE; Data bus inputs are FLOATING. Active Power-Down Current Fast PDN Exit All banks open; MRS(12) = 0 tCK = tCK(IDD); CKE is LOW; Other control and address inputs are Slow PDN Exit STABLE; Data bus inputs are FLOATING. MRS(12) = 1 (TCASE ≤ 85°C) Active Standby Current All banks open; tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, C S is HIGH between valid commands; Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING. 85 72 69 mA 1,2,3,4,5, 6 85 80 75 mA 1,2,3,4,5, 6 IDD2P 12 12 12 mA 1,2,3,4,5, 6,7 IDD2N 55 50 46 mA 1,2,3,4,5, 6 IDD2Q 50 45 42 mA 1,2,3,4,5, 6 IDD3PF 16 16 16 mA 1,2,3,4,5, 6 IDD3PS 16 16 16 mA 1,2,3,4,5, 6,7 IDD3N 60 55 50 mA 1,2,3,4,5, 6 - 40 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB Operating Burst Read Current All banks open, Continuous burst reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, C S is HIGH between valid commands; Address inputs are SWITCHING; Data Bus inputs are SWITCHING. Operating Burst Write Current All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, C S is HIGH between valid commands; Address inputs are SWITCHING; Data Bus inputs are SWITCHING. Burst Refresh Current tCK = tCK(IDD); Refresh command every tRFC = tRFC(IDD) interval; CKE is HIGH, C S is HIGH between valid commands; Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING. Distributed Refresh Current tCK = tCK(IDD); Refresh command every tREFI = 7.8 μS interval; CKE is LOW, C S is HIGH between valid commands; Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING. Self Refresh Current CKE ≤ 0.2 V, external clock off, CLK and C LK at 0 V; Other control and address inputs are FLOATING; Data bus inputs are FLOATING. (TCASE ≤ 85°C) Operating Bank Interleave Read Current All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, C S is HIGH between valid commands; Address bus inputs are STABLE during deselects; Data Bus inputs are SWITCHING. Notes: 1. 2. 3. 4. VDD = 1.8 V 0.1V; VDDQ = 1.8 V 0.1V. IDD specifications are tested after the device is properly initialized. Input slew rate is specified by AC Parametric Test Condition. IDD parameters are specified with ODT disabled. 175 160 150 mA IDD4R 165 135 120 mA 1,2,3,4,5, 6 IDD4W 145 120 110 mA 1,2,3,4,5, 6 IDD5B 1,2,3,4,5, 6 IDD5D 16 16 16 mA 1,2,3,4,5, 6 IDD6 12 12 12 mA 1,2,3,4,5, 6,7 IDD7 220 200 180 mA 1,2,3,4,5, 6 5. Data Bus consists of DQ, DM, DQS, DQS , RDQS, RDQS . 6. Definitions for IDD LOW = Vin ≤ VIL (ac) (max) HIGH = Vin ≥ VIH (ac) (min) STABLE = inputs stable at a HIGH or LOW level FLOATING = inputs at VREF = VDDQ/2 SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. 7. The following IDD values must be derated (IDD limits increase), when TCASE ≥ 85°C IDD2P must be derated by 20 %; IDD3P(slow) must be derated by 30 % and IDD6 must be derated by 80 %. (IDD6 will increase by this amount if TCASE < 85°C and the 2X refresh option is still enabled) - 41 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 9.10 IDD Measurement Test Parameters SPEED GRADE Bin(CL-tRCD-tRP) CL(IDD) tCK(IDD) tRCD(IDD) tRP(IDD) tRC(IDD) tRASmin(IDD) tRASmax(IDD) tRRD(IDD)-1KB tFAW (IDD)-1KB tRFC(IDD) DDR2-1066 (-18) 7 -7 -7 7 1.875 13.125 13.125 58.125 45 70000 7.5 35 195 DDR2-800 (-25/25I) 5-5-5/6-6-6 5/6 2.5 12.5 12.5 57.5 45 70000 7.5 35 195 DDR2-667 (-3) 5 -5 -5 5 3 15 15 60 45 70000 7.5 37.5 195 UNIT tCK nS nS nS nS nS nS nS nS nS - 42 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 9.11 AC Characteristics 9.11.1 AC Characteristics and Operating Condition for -18 speed grade SPEED GRADE SYM. tRCD tRP tRC tRAS tRFC tREFI tCCD DDR2-1066 (-18) 7-7-7 MIN. 13.125 13.125 58.125 45 195   2 3.75 3 2.5 1.875 0.48 0.48 -350 -325  3 7.5 35 15 WR + tnRP 7.5 7.5 125 200 325 325 0.6 -0.25 0.2 0.2 0.35 0.35          0.25     Bin(CL-tRCD-tRP) PARAMETER Active to Read/Write Command Delay Time Precharge to Active Command Period Active to Ref/Active Command Period Active to Precharge Command Period Auto Refresh to Active/Auto Refresh command period Average periodic refresh Interval 0°C ≤ TCASE ≤ 85°C 85°C < TCASE ≤ 95°C UNIT25 MAX.    70000  7.8 3.9  7.5 7.5 7.5 7.5 0.52 0.52 350 325 175   nS nS nS nS nS μS μS nCK nS nS nS nS tCK(avg) tCK(avg) pS pS pS nCK nS nS nS nCK nS nS pS pS pS pS tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) NOTES 23 23 23 4,23 5 5 5,6 C AS to C AS command delay tCK(avg) @ CL=4 tCK(avg) @ CL=5 tCK(avg) @ CL=6 tCK(avg) @ CL=7 30,31 30,31 30,31 30,31 30,31 30,31 35 35 13 7 8,23 23 23 24 9,23 4,23 10,26, 40,42,43 11,26, 40,42,43 10,26, 40,42,43 11,26, 40,42,43 28 28 28 tCK(avg) Average clock period tCH(avg) tCL(avg) tAC tDQSCK tDQSQ tCKE tRRD tFAW tWR tDAL tWTR tRTP tIS(base) tIH(base) tIS(ref) tIH(ref) tIPW tDQSS tDSS tDSH tDQSH tDQSL Average clock high pulse width Average clock low pulse width DQ output access time from CLK/ CLK DQS output access time from CLK / CLK DQS-DQ skew for DQS & associated DQ signals CKE minimum high and low pulse width Active to active command period for 1KB page size Four Activate Window for 1KB page size Write recovery time Auto-precharge write recovery + precharge time Internal Write to Read command delay Internal Read to Precharge command delay Address and control input setup time Address and control input hold time Address and control input setup time Address and control input hold time Address and control input pulse width for each input DQS latching rising transitions to associated clock edges DQS falling edge to CLK setup time DQS falling edge hold time from CLK DQS input high pulse width DQS input low pulse width - 43 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB AC Characteristics and Operating Condition for -18 speed grade, continued SPEED GRADE SYM. tWPRE tWPST tRPRE tRPST tDS(base) tDH(base) tDS(ref) tDH(ref) tDIPW tHZ tLZ(DQS) tLZ(DQ) tHP tQHS tQH tXSNR tXSRD tXP tXARD tXARDS tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tMRD tMOD tOIT tDELAY Write preamble Write postamble Read preamble Read postamble DQ and DM input setup time DQ and DM input hold time DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width for each input Data-out high-impedance time from CLK/ CLK DQS/ DQS -low-impedance time from CLK/ CLK DQ low-impedance time from CLK/ CLK Clock half pulse width Data hold skew factor DQ/DQS output hold time from DQS Exit Self Refresh to a non-Read command Exit Self Refresh to a Read command Exit precharge power down to any command Exit active power down to Read command Exit active power down to Read command (slow exit, lower power) ODT turn-on delay ODT turn-on ODT turn-on (Power Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power Down mode) ODT to power down Entry Latency ODT Power Down Exit Latency Mode Register Set command cycle time MRS command to ODT update delay OCD Drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW DDR2-1066 (-18) 7-7-7 MIN. 0.35 0.4 0.9 0.4 0 75 200 200 0.35  tAC,min 2 x tAC,min Min. (tCH(abs), tCL(abs))  tHP - tQHS tRFC + 10 200 3 3 10 - AL 2 tAC,min tAC,min + 2 2.5 tAC,min tAC,min + 2 4 11 2 0 0 tIS+tCK(avg)+tIH  12 12  Bin(CL-tRCD-tRP) PARAMETER UNITS25 MAX.  0.6 1.1 0.6      tAC,max tAC,max tAC,max  250       2 tCK(avg) tCK(avg) tCK(avg) tCK(avg) pS pS pS pS tCK(avg) pS pS pS pS pS pS nS nCK nCK nCK nCK nCK nS nS nCK nS nS nCK nCK nCK nS nS nS NOTES 12 14,36 14,37 16,27,29, 41,42,44 17,27,29, 41,42,44 16,27,29, 41,42,44 17,27,29, 41,42,44 15,35 15,35 15,35 32 33 34 23 18 18,19 20 20,35 tAC,max + 2.575 3 x tCK(avg) + tAC,max+1 2.5 tAC,max + 0.6 2.5 x tCK(avg) + tAC,max + 1  21,39 21,38,39 23 23 22 - 44 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 9.11.2 AC Characteristics and Operating Condition for -25/25I/-3 speed grades SPEED GRADE SYM. tRCD tRP tRC tRAS tRFC tREFI tCCD DDR2-800 (-25/25I) DDR2-667 (-3) Bin(CL-tRCD-tRP) PARAMETER Active to Read/Write Command Delay Time Precharge to Active Command Period Active to Ref/Active Command Period Active to Precharge Command Period Auto Refresh to Active/Auto Refresh command period Average periodic refresh Interval -40°C ≤ TCASE ≤ 85°C 85°C < TCASE ≤ 95°C 5-5-5/6-6-6 MIN. 12.5 12.5 57.5 45 195   2 5 3.75 2.5 2.5 0.48 0.48 -400 -350  3 7.5 35 15 7.5 7.5 175 250 375 375 0.6 -0.25 0.2 0.2 0.35 0.35 5-5-5 MIN. 15 15 60 45 195   2 5 3.75 3  0.48 0.48 -450 -400  3 7.5 37.5 15 WR + tnRP 7.5 7.5 200 275 400 400 0.6 -0.25 0.2 0.2 0.35 0.35 UNITS25 NOTES MAX.    nS nS nS nS nS μS μS nCK nS nS nS nS tCK(avg) tCK(avg) pS pS pS nCK nS nS nS nCK nS nS pS pS pS pS tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) 28 28 28 30,31 30,31 30,31 30,31 30,31 30,31 35 35 13 7 8,23 23 23 24 9,23 4,23 10,26, 40,42,43 11,26, 40,42,43 10,26, 40,42,43 11,26, 40,42,43 23 23 23 4,23 5 5 5,6 MAX.    70000  7.8 3.9  8 8 8 8 0.52 0.52 400 350 200             0.25     70000  7.8 3.9  8 8 8  0.52 0.52 450 400 240             0.25     C AS to C AS command delay tCK(avg) @ CL=3 tCK(avg) @ CL=4 tCK(avg) @ CL=5 tCK(avg) @ CL=6 tCK(avg) Average clock period tCH(avg) tCL(avg) tAC tDQSCK tDQSQ tCKE tRRD tFAW tWR tDAL tWTR tRTP tIS (base) tIH (base) tIS (ref) tIH (ref) tIPW tDQSS tDSS tDSH tDQSH tDQSL Average clock high pulse width Average clock low pulse width DQ output access time from CLK/ CLK DQS output access time from CLK / CLK DQS-DQ skew for DQS & associated DQ signals CKE minimum high and low pulse width Active to active command period for 1KB page size Four Activate Window for 1KB page size Write recovery time Internal Write to Read command delay Internal Read to Precharge command delay Address and control input setup time Address and control input hold time Address and control input setup time Address and control input hold time Address and control input pulse width for each input DQS latching rising transitions to associated clock edges DQS falling edge to CLK setup time DQS falling edge hold time from CLK DQS input high pulse width DQS input low pulse width Auto-precharge write recovery + precharge time WR + tnRP - 45 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB AC Characteristics and Operating Condition for -25/25I/-3 speed grades, continued SYM. tWPRE tWPST tRPRE tRPST SPEED GRADE Bin(CL-tRCD-tRP) PARAMETER Write preamble Write postamble Read preamble Read postamble DDR2-800 (-25/25I) DDR2-667 (-3) 5-5-5/6-6-6 MIN. MAX. 0.35 0.4 0.9 0.4 50 125 250 250 0.35   0.6 1.1 0.6      tAC,max 5-5-5 MIN. 0.35 0.4 0.9 0.4 100 175 300 300 0.35  UNITS25 NOTES MAX.  0.6 1.1 0.6 tCK(avg) tCK(avg) tCK(avg) tCK(avg) pS pS pS pS tCK(avg) pS 15,35 12 14,36 14,37 16,27,29, 41,42,44 17,27,29, 41,42,44 16,27,29, 41,42,44 17,27,29, 41,42,44 tDS(base) DQ and DM input setup time tDH(base) DQ and DM input hold time tDS(ref) tDH(ref) tDIPW tHZ DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width for each input Data-out high-impedance time from CLK/ CLK DQS/ DQS -low-impedance time from CLK/ CLK tLZ(DQ) tHP tQHS tQH tXSNR tXSRD tXP tXARD tXARDS tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tMRD tMOD tOIT tDELAY DQ low-impedance time from CLK/ CLK Clock half pulse width Data hold skew factor DQ/DQS output hold time from DQS Exit Self Refresh to a non-Read command Exit Self Refresh to a Read command Exit precharge power down to any command Exit active power down to Read command Exit active power down to Read command (slow exit, lower power) ODT turn-on delay ODT turn-on ODT turn-on (Power Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power Down mode) ODT to power down Entry Latency ODT Power Down Exit Latency Mode Register Set command cycle time MRS command to ODT update delay OCD Drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW      tAC,max tLZ(DQS) tAC,min 2 x tAC,min Min. (tCH(abs), tCL(abs))  tHP - tQHS tRFC + 10 200 2 2 8 - AL 2 tAC,min tAC,max tAC,max tAC,min 2 x tAC,min Min. (tCH(abs), tCL(abs)) tAC,max tAC,max pS pS pS 15,35 15,35 32 33 34 23 300       2  tHP - tQHS tRFC + 10 200 2 2 7 - AL 2 340       2 pS pS nS nCK nCK nCK nCK nCK nS nS nCK nS nS nCK nCK nCK nS nS nS 18 18,19 20 20,35 tAC,max + 0.7 tAC,min tAC,max + 0.7 2 x tCK(avg) + 2 x tCK(avg) + tAC,min + 2 tAC,min + 2 tAC,max + 1 tAC,max + 1 2.5 tAC,min tAC,min + 2 3 8 2 0 0 tIS+tCK(avg)+ tIH  12 12  2.5 tAC,max + 0.6 2.5 tAC,min 2.5 tAC,max + 0.6 21,39 21,38,39 2.5 x tCK(avg) 2.5 x tCK(avg) tAC,min + 2 + tAC,max + 1 + tAC,max + 1  3 8 2 0 0 tIS+tCK(avg)+ tIH  12 12   23 23 22 - 46 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB Notes: 1. All voltages are referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ODT is disabled for all measurements that are not ODT-specific. 3. AC timing reference load: VDDQ DQ Output DUT DQS DQS Timing reference point 25Ω VTT = VDDQ/2 Figure 16 – AC timing reference load 4. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the t RTP and tRAS(min) have been satisfied. 5. If refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 6. This is an optional feature. For detailed information, please refer to “operating temperature condition” section 9.2 in this data sheet. 7. tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 8. A minimum of two clocks (2 *nCK) is required irrespective of operating frequency. 9. tWTR is at least two clocks (2 * nCK) independent of operation frequency. 10. There are two sets of values listed for Command/Address input setup time: tIS(base) and tIS(ref). The tIS(ref) value (for reference only) is equivalent to the baseline value of tIS(base) at VREF when the slew rate is 1.0 V/nS. The baseline value tIS(base) is the JEDEC defined value, referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to 1.0 V/nS, then the baseline values must be derated by adding the values from table of tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 (page 55). CLK CLK tIS(base) tIH(base) Logic levels tIS(base) tIH(base) VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS VREF levels tIS(ref) tIH(ref) tIS(ref) tIH(ref) Figure 17 – Differential input waveform timing – tIS and tIH - 47 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 11. There are two sets of values listed for Command/Address input hold time: tIH(base) and tIH(ref). The tIH(ref) value (for reference only) is equivalent to the baseline value of tIH(base) at VREF when the slew rate is 1.0 V/nS. The baseline value tIH(base) is the JEDEC defined value, referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to 1.0 V/nS, then the baseline values must be derated by adding the values from table tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 (page 55). 12. The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrades accordingly. 13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mismatch between DQS / DQS and associated DQ in any given cycle. 14. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 18 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 15. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (t HZ), or begins driving (tLZ). Figure 18 shows a method to calculate the point when device is no longer driving (t HZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. tLZ(DQ) refers to tLZ of the DQ‟s and tLZ(DQS) refers to tLZ of the (DQS, DQS , RDQS, RDQS ) each treated as single-ended signal. VOH - x mV VOH - 2x mV tHZ tRPST end point VOL + 2x mV VOL + x mV T1 T2 VTT + 2x mV VTT + x mV tLZ tRPRE begin point VTT - x mV VTT - 2x mV T1 T2 tHZ,tRPST end point = 2 x T1 - T2 tLZ,tRPRE begin point = 2 x T1 - T2 Figure 18 – Method for calculating transitions and endpoints 16. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0. There are two sets of values listed for DQ and DM input setup time: tDS(base) and tDS(ref). The tDS(ref) value (for reference only) is equivalent to the baseline value tDS(base) at VREF when the slew rate is 2.0 V/nS, differentially. The baseline value tDS(base) is the JEDEC defined value, referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. See Figure 19. If the differential DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from table of DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe (page 60). 17. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0. There are two sets of values listed for DQ and DM input hold time: tDH(base) and tDH(ref). The tDH(ref) value (for reference only) is equivalent to the baseline value tDH(base) at VREF when the slew rate is 2.0 V/nS, differentially. The baseline value tDH(base) is the JEDEC defined value, referenced from the differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. See Figure 19. If the differential DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from table of DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe (page 60). - 48 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB DQS DQS tDS(base) tDH(base) Logic levels tDS(base) tDH(base) VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS VREF levels tDS(ref) Figure 19 tDH(ref) tDS(ref) tDH(ref) – Differential input waveform timing – tDS and tDH 18. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing . 19. AL = Additive Latency. 20. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND, which is interpreted differently per speed bin. For DDR2-667/800/1066, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 21. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted as 0.5 x tCK(avg) [nS] after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges . For DDR2-667/800: If tCK(avg) = 3 nS is assumed, tAOFD is 1.5 nS (= 0.5 x 3 nS) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges . For DDR2-1066: tAOFD is 0.9375 [nS] (= 0.5 x 1.875 [nS]) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges . 22. The clock frequency is allowed to change during Self Refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required as described in section 7.10. 23. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. Examples: The device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15nS, the device will support tnRP = RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15nS due to input clock jitter. For DDR2-1066 7-7-7, of which tRP = 13.125 nS, the device will support tnRP = RU{tRP / tCK(avg)} = 7, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm+7 is valid even if (Tm+7 - Tm) is less than 13.125 nS due to input clock jitter. 24. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [pS] / tCK(avg) [pS] }, where WR is the value programmed in the mode register set and RU stands for round up. Example: For DDR2-1066 7-7-7 at tCK(avg) = 1.875 nS with WR programmed to 8 nCK, tDAL = 8 + RU{13.125 nS / 1.875 nS} [nCK] = 8 + 7 [nCK] = 15 [nCK]. - 49 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 25. New units, „tCK(avg)‟ and „nCK‟, are introduced in DDR2-667, DDR2-800 and DDR2-1066. Unit „tCK(avg)‟ represents the actual tCK(avg) of the input clock under operation. Unit „nCK‟ represents one clock cycle of the input clock, counting the actual clock edges. Examples: For DDR2-667/800: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min. For DDR2-1066: tXP = 3 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+3, even if (Tm+3 - Tm) is 3 x tCK(avg) + tERR(3per),min. 26. These parameters are measured from a command/address signal (CKE, CS , R AS , C AS , WE , ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CLK/ CLK ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 27. If tDS or tDH is violated, data corruption m ay occur and the data must be re-written with valid data before a valid READ can be executed. 28. These parameters are measured from a data strobe signal (DQS, DQS , RDQS, RDQS ) crossing to its respective clock signal (CLK/ CLK ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 29. These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal (DQS, DQS , RDQS, RDQS ) crossing. - 50 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 30. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters'. The jitter specified is a random jitter meeting a Gaussian distribution. Input clock-Jitter specifications parameters for DDR2-667, DDR2-800 and DDR2-1066 PARAMETER Clock period jitter Clock period jitter during DLL locking period Cycle to cycle clock period Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n cycles, n = 6 ... 10, inclusive Cumulative error across n cycles, n = 11 ... 50, inclusive Duty cycle jitter SYMBOL tJIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6-10per) tERR(11-50per) tJIT(duty) DDR2-667 MIN. -125 -100 -250 -200 -175 -225 -250 -250 -350 -450 -125 DDR2-800 MIN. -100 -80 -200 -160 -150 -175 -200 -200 -300 -450 -100 DDR2-1066 MIN. -90 -80 -180 -160 -132 -157 -175 -188 -250 -425 -75 MAX. 125 100 250 200 175 225 250 250 350 450 125 MAX. 100 80 200 160 150 175 200 200 300 450 100 MAX. 90 80 180 160 132 157 175 188 250 425 75 UNIT pS pS pS pS pS pS pS pS pS pS pS Definitions: - tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window. N  tCK(avg) =  tCK j  / N  j 1  where N = 200 - tCH(avg) and tCL(avg) tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses. N  tCH(avg) =  tCH j  / (N × tCK(avg))  j 1  where N = 200 tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses. N  tCL(avg) =  tCL j  / (N × tCK(avg))  j 1  where N = 200 - 51 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB - tJIT(duty) tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single t CH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg). tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} where, tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200} tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200} - tJIT(per), tJIT(per,lck) tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing. - tJIT(cc), tJIT(cc,lck) tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of |tCKi+1 – tCKi| tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing. - tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per) tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg) . i  n1  tERR(nper) =   tCK j  –n × tCK(avg)  j 1   n=2  n=3   n=4 Where   n=5  6  n  10  11  n  50  for for for for for for tER (2per) R tER (3per) R tER (4per) R tER (5per) R tER – 10per) R(6 tER R(11 – 50per) - 52 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 31. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.) PARAMETER Absolute clock period Absolute clock HIGH pulse width SYMBOL tCK(abs) tCH(abs) MIN tCK(avg),min + tJIT(per),min tCH(avg),min x tCK(avg),min + tJIT(duty),min tCL(avg),min x tCK(avg),min + tJIT(duty),min MAX tCK(avg),max + tJIT(per),max tCH(avg),max x tCK(avg),max + tJIT(duty),max tCL(avg),max x tCK(avg),max + tJIT(duty),max UNIT pS pS Absolute clock LOW pulse width tCL(abs) pS Examples: 1) For DDR2-667, tCH(abs),min = ( 0.48 x 3000 pS ) - 125 pS = 1315 pS 2) For DDR2-1066, tCH(abs),min = ( 0.48 x 1875 pS ) - 75 pS = 825 pS 32. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = Min ( tCH(abs), tCL(abs) ), where, tCH(abs) is the minimum of the actual instantaneous clock HIGH time; tCL(abs) is the minimum of the actual instantaneous clock LOW time; 33. tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p -channel to nchannel variation of the output drivers 34. tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 pS into a DDR2-667 SDRAM, the DRAM provides tQH of 975 pS minimum. 2) If the system provides tHP of 1420 pS into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 pS minimum. 3) If the system provides tHP of 825 pS into a DDR2-1066 SDRAM, the DRAM provides tQH of 575 pS minimum. 4) If the system provides tHP of 900 pS into a DDR2-1066 SDRAM, the DRAM provides tQH of 650 pS minimum. 35. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) Examples: 1) If the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 pS and tERR(6-10per),max = + 293 pS, then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 400 pS - 293 pS = - 693 pS and tDQSCK,max(derated) = tDQSCK,max - tERR(6-10per),min = 400 pS + 272 pS = + 672 pS. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ),min(derated) = - 900 pS - 293 pS = - 1193 pS and tLZ(DQ),max(derated) = 450 pS + 272 pS = + 722 pS. (Caution on the min/max usage!) 2) If the measured jitter into a DDR2-1066 SDRAM has tERR(6-10per),min = - 202 pS and tERR(6-10per),max = + 223 pS, then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 300 pS - 223 pS = - 523 pS and tDQSCK,max(derated) = tDQSCK,max - tERR(6-10per),min = 300 pS + 202 pS = + 502 pS. Similarly, tLZ(DQ) for DDR2-1066 derates to tLZ(DQ),min(derated) = - 700 pS - 223 pS = - 923 pS and tLZ(DQ),max(derated) = 350 pS + 202 pS = + 552 pS. (Caution on the min/max usage!) - 53 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 36. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock .) Examples: 1) If the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 pS and tJIT(per),max = + 93 pS, then tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 pS = + 2178 pS and tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 93 pS = + 2843 pS. (Caution on the min/max usage!) 2) If the measured jitter into a DDR2-1066 SDRAM has tJIT(per),min = - 72 pS and tJIT(per),max = + 63 pS, then tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 pS = + 1615.5 pS and tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 63 pS = + 2125.5 pS. (Caution on the min/max usage!) 37. When the device is operated with input clock jitter, this parameter needs t o be derated by the actual tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.) Examples: 1) If the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 pS and tJIT(duty),max = + 93 pS, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 pS = + 928 pS and tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 93 pS = + 1592 pS. (Caution on the min/max usage!) 2) If the measured jitter into a DDR2-1066 SDRAM has tJIT(duty),min = - 72 pS and tJIT(duty),max = + 63 pS, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 pS = + 678 pS and tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 63 pS = + 1188 pS. (Caution on the min/max usage! ) 38. When the device is operated with input clock jitter, this parameter needs to be derated by { -tJIT(duty),max - tERR(610per),max } and { - tJIT(duty),min - tERR(6-10per),min } of the actual input clock. (output deratings are relative to the SDRAM input clock.) Examples: 1) If the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 pS, tERR(6-10per),max = + 293 pS, tJIT(duty),min = - 106 pS and tJIT(duty),max = + 94 pS, then tAOF,min(derated) = tAOF,min + { - tJIT(duty),max - tERR(6-10per),max } = - 450 pS + { - 94 pS - 293 pS} = - 837 pS and tAOF,max(derated) = tAOF,max + { tJIT(duty),min - tERR(6-10per),min } = 1050 pS + { 106 pS + 272 pS } = + 1428 pS. (Caution on the min/max usage!) 2) If the measured jitter into a DDR2-1066 SDRAM has tERR(6-10per),min = - 202 pS, tERR(6-10per),max = + 223 pS, tJIT(duty),min = - 66 pS and tJIT(duty),max = + 74 pS, then tAOF,min(derated) = tAOF,min + { - tJIT(duty),max tERR(6-10per),max } = - 350 pS + { - 74 pS - 223 pS} = - 647 pS and tAOF,max(derated) = tAOF,max + { tJIT(duty),min - tERR(6-10per),min } = 950 pS + { 66 pS + 202 pS } = + 1218 pS. (Caution on the min/max usage!) 39. For tAOFD of DDR2-667/800/1066, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg), average input clock HIGH pulse width of 0.5 relative to tCK(avg). tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5. Example: If an input clock has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtracting 0.02 x tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the tAOF,max should be derated by adding 0.02 x tCK(avg) to it. Therefore, we have; tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH(avg),min)] x tCK(avg) tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH(avg),max) - 0.5] x tCK(avg) or tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH(avg),min] x tCK(avg)) tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH(avg),max - 0.5] x tCK(avg)) where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at the DRAM input balls. Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6 -10per). However tAC values used in the equations shown above are from the timing parameter table and are not der ated. Thus the final derated values for tAOF are; tAOF,min(derated_final) = tAOF,min(derated) + { - tJIT(duty),max - tERR(6-10per),max } tAOF,max(derated_final) = tAOF,max(derated) + { - tJIT(duty),min - tERR(6-10per),min } 40. Timings are specified with command/address input slew rate of 1.0 V/nS. 41. Timings are specified with DQs and DM input slew rate of 1.0V/nS. 42. Timings are specified with CLK/ CLK differential slew rate of 2.0 V/nS. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/nS in differential strobe mode. - 54 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 43. tIS and tIH (input setup and hold) derating. tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 ΔtIS and ΔtIH Derating Values for DDR2-667, DDR2-800 and DDR2-1066 Command/ Address Slew Rate (V/nS) ΔtIS 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 +150 +143 +133 +120 +100 +67 0 -5 -13 -22 -34 -60 -100 -168 -200 -325 -517 -1000 CLK/ CLK Differential Slew Rate 2.0 V/nS ΔtIH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 ΔtIS +180 +173 +163 +150 +130 +97 +30 +25 +17 +8 -4 -30 -70 -138 -170 -295 -487 -970 1.5 V/nS ΔtIH +124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095 ΔtIS +210 +203 +193 +180 +160 +127 +60 +55 +47 +38 +26 0 -40 -108 -140 -265 -457 -940 1.0 V/nS ΔtIH +154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065 Unit pS pS pS pS pS pS pS pS pS pS pS pS pS pS pS pS pS pS For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the ΔtIS and ΔtIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded „VREF(dc) to AC region‟, use nominal slew rate for derating value. See Figure 20 Illustration of nominal slew rate for tIS. If the actual signal is later than the nominal slew rate line anywhere between shaded „VREF(dc) to AC region‟, the slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 21 Illustration of tangent line for tIS. Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V IL(dc)max and the first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded „DC to VREF(dc) region‟, use nominal slew rate for derating value. See Figure 22 Illustration of nominal slew rate for tIH. If the actual signal is earlier than the nominal slew rate line anywhere between shaded „ DC to VREF(dc) region‟, the slew rate of a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 23 Illustration of tangent line for tIH. Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the tra nsition and reach VIH/IL(ac). For slew rates in between the values listed in above tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 table, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. - 55 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB CLK CLK tIS VDDQ tIH tIS tIH VIH(ac)min VREF to AC region VIH(dc)min nominal slew rate VREF(dc) nominal slew rate VIL(dc)max VREF to AC region VIL(ac)max VSS ΔTF ΔTR Setup Slew Rate = Falling Signal VREF(dc) - VIL(ac)max ΔTF Setup Slew Rate Rising Signal = VIH(ac)min - VREF(dc) ΔTR Figure 20 – Illustration of nominal slew rate for tIS - 56 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB CLK CLK tIS VDDQ tIH tIS tIH VIH(ac)min VREF to AC region VIH(dc)min nominal line tangent line VREF(dc) tangent line VIL(dc)max VREF to AC region VIL(ac)max nominal line ΔTR VSS ΔTF Setup Slew Rate Rising Signal = tangent line[VIH(ac)min - VREF(dc)] ΔTR Setup Slew Rate tangent line[VREF(dc) - VIL(ac)max] Falling Signal = ΔTF Figure 21 – Illustration of tangent line for tIS - 57 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB CLK CLK tIS VDDQ tIH tIS tIH VIH(ac)min VIH(dc)min DC to VREF region VREF(dc) nominal slew rate VIL(dc)max DC to VREF region nominal slew rate VIL(ac)max VSS ΔTR ΔTF VREF(dc) - VIL(dc)max Hold Slew Rate Rising Signal = ΔTR Hold Slew Rate VIH(dc)min - VREF(dc) Falling Signal = ΔTF Figure 22 – Illustration of nominal slew rate for tIH - 58 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB CLK CLK tIS VDDQ tIH tIS tIH VIH(ac)min nominal line VIH(dc)min DC to VREF region VREF(dc) tangent line VIL(dc)max nominal DC to VREF region line tangent line VIL(ac)max VSS ΔTR ΔTF tangent line[VREF(dc) - VIL(ac)max] Hold Slew Rate = Rising Signal ΔTR tangent line[VIH(dc)min - VREF(dc)] Hold Slew Rate = Falling Signal ΔTF Figure 23 – Illustration of tangent line for tIH - 59 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 44. Data setup and hold time derating. DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe DQ Slew Rate (V/nS) ΔtDS, ΔtDH derating values for DDR2-667, DDR2-800 and DDR2-1066 (All units in „pS‟; the note applies to the entire table) DQS/ DQS Differential Slew Rate 4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/nS 1.6 V/nS 1.4 V/nS 1.2 V/nS 1.0 V/nS 0.8 V/nS ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 100 67 0 45 21 0 100 67 0 -5 45 21 0 -14 100 67 0 -5 -13 45 21 0 -14 -31 79 12 7 -1 -10 33 12 -2 -19 -42 24 19 11 2 -10 24 10 -7 -30 -59 31 23 14 2 -24 22 5 -18 -47 -89 35 26 14 -12 -52 17 -6 -35 -77 -140 38 26 0 -40 6 -23 -65 -128 38 12 -28 -11 -53 -116 For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base ) and tDH(base) value to the ΔtDS and ΔtDH derating value respectively. Example: tDS (total setup time) = tDS(base) + ΔtDS. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the f irst crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rat e between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rat e line between shaded „VREF(dc) to AC region‟, use nominal slew rate for derating value. See Figure 24 Illustration of nominal slew rate for tDS (differential DQS, DQS ). If the actual signal is later than the nominal slew rate line anywhere between shaded „VREF(dc) to AC region‟, the slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 25 Illustration of tangent line for tDS (differential DQS, DQS ). Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V IL(dc)max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded „DC level to VREF(dc) region‟, use nominal slew rate for derating value. See Figure 26 Illustration of nominal slew rate for tDH (differential DQS, DQS ). If the actual signal is earlier than the nominal slew rate line anywhere between shaded „DC to VREF(dc) region‟, the slew rate of a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 27 Illustration of tangent line for tDH (differential DQS, DQS ). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(a c) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in above DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe table, the derating values may be obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. - 60 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB DQS DQS tDS VDDQ tDH tDS tDH VIH(ac)min VREF to AC region VIH(dc)min nominal slew rate VREF(dc) nominal slew rate VIL(dc)max VIL(ac)max VREF to AC region VSS ΔTF ΔTR VREF(dc) - VIL(ac)max Setup Slew Rate = Falling Signal ΔTF VIH(ac)min - VREF(dc) Setup Slew Rate = Rising Signal ΔTR Figure 24 – Illustration of nominal slew rate for tDS (differential DQS, DQS ) - 61 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB DQS DQS tDS VDDQ tDH tDS tDH nominal line VIH(ac)min VREF to AC region VIH(dc)min tangent line VREF(dc) tangent line VIL(dc)max VREF to AC region VIL(ac)max nominal line VSS Setup Slew Rate tangent line[VIH(ac)min - VREF(dc)] Rising Signal = ΔTR ΔTF ΔTR Setup Slew Rate tangent line[VREF(dc) - VIL(ac)max] Falling Signal = ΔTF Figure 25 – Illustration of tangent line for tDS (differential DQS, DQS ) - 62 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB DQS DQS tDS VDDQ tDH tDS tDH VIH(ac)min VIH(dc)min DC to VREF region VREF(dc) nominal slew rate VIL(dc)max DC to VREF region nominal slew rate VIL(ac)max VSS ΔTR ΔTF Hold Slew Rate VREF(dc) - VIL(dc)max Rising Signal = ΔTR VIH(dc)min - VREF(dc) Hold Slew Rate Falling Signal = ΔTF Figure 26 – Illustration of nominal slew rate for tDH (differential DQS, DQS ) - 63 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB DQS DQS tDS VDDQ tDH tDS tDH VIH(ac)min nominal line VIH(dc)min DC to VREF region tangent line VREF(dc) tangent line VIL(dc)max DC to VREF region nominal line VIL(ac)max VSS ΔTR ΔTF Hold Slew Rate tangent line[VREF(dc) - VIL(ac)max] Rising Signal = ΔTR Hold Slew Rate tangent line [VIH(dc)min - VREF(dc)] = Falling Signal ΔTF Figure 27 – Illustration tangent line for tDH (differential DQS, DQS ) - 64 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 9.12 AC Input Test Conditions Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(ac) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. VREF VSWING(MAX) SLEW 0.5 x VDDQ 1.0 1.0 V V V/nS 1 1 2, 3 9.13 Differential Input/Output AC Logic Levels PARAMETER AC differential input voltage AC differential cross point input voltage AC differential cross point output voltage Notes: 1. VID (ac) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CLK, DQS) and VCP is the complementary input signal (such as C LK , DQS ). The minimum value is equal to VIH (ac) VIL (ac). 2. The typical value of VIX (ac) is expected to be about 0.5 x VDDQ of the transmitting device and VIX (ac) is expected to track variations in VDDQ. VIX (ac) indicates the voltage at which differential input signals must cross. 3. The typical value of VOX (ac) is expected to be about 0.5 x VDDQ of the transmitting device and VOX (ac) is expected to track variations in VDDQ. VOX (ac) indicates the voltage at which differential output signals must cross . SYM. VID (ac) VIX (ac) VOX (ac) MIN. 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125 MAX. VDDQ + 0.6 0.5 x VDDQ + 0.175 0.5 x VDDQ + 0.125 UNIT V V V NOTES 1 2 3 VDDQ VIH(ac) min VIH(dc) min VSWING(MAX) VREF VIL(dc) max VIL(ac) max VSS ΔTF VREF - VIL(ac) max ΔTF ΔTR Rising Slew = VIH(ac) min - VREF ΔTR VCP VSSQ VTR VID Crossing point VIX or VOX VDDQ Falling Slew = Figure 28 – AC input test signal and Differential signal levels waveform - 65 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 9.14 AC Overshoot / Undershoot Specification 9.14.1 AC Overshoot / Undershoot Specification for Address and Control Pins: A0-A14, BA0-BA2, /CS, /RAS, /CAS, /WE, CKE, ODT PARAMETER Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDD Maximum undershoot area below VSS DDR2-1066 0.9 0.9 0.5 0.5 DDR2-800 0.9 0.9 0.66 0.66 DDR2-667 0.9 0.9 0.8 0.8 UNIT V V V-nS V-nS 9.14.2 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins: DQ, DQS, /DQS, RDQS, /RDQS, DM, CLK, /CLK PARAMETER Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDDQ Maximum undershoot area below VSSQ DDR2-1066 0.9 0.9 0.19 0.19 DDR2-800 0.9 0.9 0.23 0.23 DDR2-667 0.9 0.9 0.23 0.23 UNIT V V V-nS V-nS Maximum Amplitude Overshoot Area VDD/VDDQ Volts (V) VSS/VSSQ Maximum Amplitude Time (nS) Undershoot Area Figure 29 – AC overshoot and undershoot definition - 66 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10. TIMING WAVEFORMS 10.1 Command Input Timing tCK tCK CLK CLK tIS CS tIH tCH tCL tIS RAS tIH tIS CAS tIH tIS WE tIH tIS A 0 ~ A 14 BA0,1,2 tIH Refer to the Command Truth Table 10.2 Timing of the CLK Signals tCH CLK CLK tCK CLK CLK VX VX VX VIH VIL tT tT tCL VIH VIH(AC) VIL(AC) VIL - 67 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.3 ODT Timing for Active/Standby Mode T0 CLK CLK tIS CKE tIS VIH(ac) T1 T2 T3 T4 T5 T6 T7 T8 tIS VIL(ac) ODT tAOND tAOFD Internal Term Res. tAON(min) RTT tAOF(min) tAON(max) tAOF(max) 10.4 ODT Timing for Power Down Mode T0 CLK CLK CKE tIS VIH(ac) T1 T2 T3 T4 T5 T6 T7 T8 tIS VIL(ac) ODT tAOFPD(max) tAOFPD(min) Internal Term Res. RTT tAONPD(min) tAONPD(max) - 68 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.5 ODT Timing mode switch at entering power down mode T-5 CLK CLK CKE tIS Entering Slow Exit Active Power Down Mode or Precharge Power Down Mode tIS ODT VIL(ac) T-4 T-3 T- 2 T-1 T0 T1 T2 tANPD Internal Term Res. RTT tAOFD Active & Standby mode timings to be applied ODT VIL(ac) tIS Internal Term Res. RTT tAOFPD(max) Power Down mode timings to be applied tIS VIH(ac) ODT Internal Term Res. tAOND RTT Active & Standby mode timings to be applied tIS VIH(ac) ODT Internal Term Res. tAONPD(max) RTT Power Down mode timings to be applied - 69 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.6 ODT Timing mode switch at exiting power down mode T0 CLK CLK T1 T5 T6 T7 T8 T9 T10 tIS VIH(ac) tAXPD CKE Exiting from Slow Active Power Down Mode or Precharge Power Down Mode tIS ODT Active & Standby mode timings to be applied Internal Term Res. VIL(ac) RTT tIS tAOFD ODT Power Down mode timings to be applied Internal Term Res. VIL(ac) RTT tAOFPD(max) tIS VIH(ac) Active & Standby mode timings to be applied ODT Internal Term Res. RTT RTT tIS VIH(ac) tAOND Power Down mode timings to be applied ODT Internal Term Res. RTT tAONPD(max) - 70 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.7 Data output (read) timing tCH CLK CLK tCL DQS DQS DQS DQS tRPRE tRPST DQ tDQSmax Q Q Q tDQSmax Q tQH tQH 10.8 Burst read operation: RL=5 (AL=2, CL=3, BL=4) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD Posted CAS READ A NOP NOP NOP NOP NOP NOP ≤ tDQSCK NOP NOP NOP NOP DQS, DQS AL = 2 RL = 5 DQ's Dout A0 Dout A1 Dout A2 Dout A3 CL = 3 - 71 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.9 Data input (write) timing tDQSH tDQSL DQS DQS DQS DQS tWPRE VIH(ac) D VIL(ac) tWPST VIH(dc) D VIL(dc) DQ D D tDS DM DMin tDS VIH(ac) DMin VIL(ac) tDH DMin tDH VIH(dc) DMin VIL(dc) 10.10 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4) T0 CLK CLK T1 T2 T3 T4 T5 T6 T7 Tn CMD Posted CAS WRITE A NOP NOP NOP NOP tDQSS NOP tDQSS tDSS tDSS NOP NOP Completion of The Burst Write Precharge Case 1: with tDQSS(max) DQS DQS WL = RL – 1= 4 DIN A0 tDQSS tDSH DIN A1 DIN A2 tDQSS tDSH DIN A3 ≥ tWR DQs Case 2: with tDQSS(min) DQS DQS WL = RL – 1= 4 DIN A0 DIN A1 DIN A2 DIN A3 ≥ tWR DQs - 72 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.11 Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) T0 CLK CLK Post CAS READ A Post CAS READ B T1 T2 T3 T4 T5 T6 T7 T8 CMD NOP NOP NOP NOP NOP NOP NOP DQS DQS AL = 2 RL = 5 DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 CL = 3 Note: The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated. 10.12 Seamless burst write operation: RL = 5 ( WL = 4, BL = 4) T0 CLK CLK CMD Post CAS Write A NOP Post CAS Write B NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 DQS DQS WL = RL - 1 = 4 DQ's DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 Note: The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated. - 73 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.13 Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD READ A NOP READ B NOP NOP NOP NOP NOP NOP DQS, DQS DQ's Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6 Dout B7 10.14 Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD NOP Write A NOP Write B NOP NOP NOP NOP NOP DQS, DQS DQ's Din A0 Din A1 Din A2 Din A3 Din B0 Din B1 Din B2 Din B3 Din B4 Din B5 Din B6 Din B7 - 74 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.15 Write operation with Data Mask: WL=3, AL=0, BL=4) Data Mask Timing DQS/ DQS DQ VIH(ac) VIH(dc) VIH(ac) VIH(dc) DM VIL(ac) VIL(dc) VIL(ac) VIL(dc) tDS tDH tDS tDH CLK CLK CMDMAND Write WL + tDQSS (min) tWR Case 1: min tDQSS DQS/DQS DQ DM Case 2: max tDQSS DQS/DQS WL + tDQSS (max) DQ DM - 75 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.16 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≤ 2clks) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD Post CAS READ A NOP NOP AL+BL/2 clks Precharge NOP NOP ≥ tRP NOP Bank A Activate NOP DQS, DQS AL = 1 RL = 4 DQ's ≥ tRAS ≥ tRTP Dout A0 Dout A1 Dout A2 Dout A3 CL = 3 10.17 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD Post CAS READ A NOP NOP AL + BL/2 clks NOP NOP Precharge NOP NOP NOP DQS, DQS AL = 1 RL = 4 DQ's CL = 3 Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 ≥ tRTP first 4-bit prefetch second 4-bit prefetch - 76 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.18 Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≤ 2clks) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD Post CAS READ A NOP NOP AL + BL/2 clks NOP Precharge NOP ≥ tRP NOP Bank A Activate NOP DQS, DQS AL = 2 RL = 5 DQ's ≥ tRAS ≥ tRTP CL = 3 Dout A3 Dout A0 Dout A1 Dout A2 CL = 3 10.19 Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≤ 2clks) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD Post CAS READA NOP NOP AL + BL/2 clks NOP Precharge NOP ≥ tRP NOP Bank A Activate NOP DQS, DQS AL = 2 RL = 6 DQ's ≥ tRAS ≥ tRTP CL = 4 CL = 4 Dout A0 Dout A1 Dout A2 Dout A3 - 77 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.20 Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD Post CAS READ A NOP NOP NOP NOP Precharge NOP NOP Bank A Activate AL + BL/2 + max(RTP, 2) - 2 clks DQS, DQS AL = 0 CL = 4 RL = 4 ≥ tRP Dout A0 ≥ tRAS ≥ tRTP Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 DQ's first 4-bit prefetch second 4-bit prefetch 10.21 Burst write operation followed by precharge: WL = (RL-1) = 3 T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD Post CAS WRITE A NOP NOP NOP NOP NOP NOP NOP Precharge Completion of the Burst Write ≥ tWR DQS, DQS WL = 3 DQ's DIN A0 DIN A1 DIN A2 DIN A3 - 78 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.22 Burst write operation followed by precharge: WL = (RL-1) = 4 T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T9 CMD Posted CAS WRITE A NOP NOP NOP NOP NOP NOP NOP Precharge A Completion of the Burst Write ≥ tWR DQS, DQS WL = 4 DQ's DIN A0 DIN A1 DIN A2 DIN A3 10.23 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD Post CAS READA A10 = 1 NOP NOP AL + BL/2 clks NOP NOP NOP NOP ≥ tRP NOP Bank A Activate DQS, DQS AL = 1 RL = 4 DQ's Dout A0 ≥ tRTP first 4-bit prefetch second 4-bit prefetch tRTP Precharge begins here Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 CL = 3 - 79 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.24 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD Post CAS READA A10 = 1 NOP NOP ≥ AL + tRTP + tRP NOP NOP NOP NOP Bank A Activate NOP DQS, DQS AL = 1 RL = 4 DQ's Dout A0 Dout A1 Dout A2 Dout A3 CL = 3 4-bit prefetch tRTP Precharge begins here tRP 10.25 Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD Post CAS READA A10 = 1 NOP NOP NOP NOP NOP NOP NOP Bank A Activate ≥ tRAS min. (AL + BL/2) DQS, DQS AL = 2 RL = 5 DQ's Auto-precharge begins ≥ tRP CL = 3 Dout A0 tRC min. Dout A1 Dout A2 Dout A3 - 80 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.26 Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 T8 CMD Post CAS READA A10 = 1 NOP NOP NOP NOP NOP NOP Bank A Activate NOP ≥ tRAS min. DQS, DQS AL = 2 RL = 5 DQ's Auto-precharge begins tRP min. CL = 3 Dout A0 ≥ tRC Dout A1 Dout A2 Dout A3 10.27 Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3 T0 CLK/CLK T1 T2 T3 T4 T5 T6 T7 Tm CMD Post CAS WRA Bank A NOP NOP NOP NOP NOP NOP NOP Bank A Activate A10 = 1 DQS, DQS WL= RL- 1 = 2 DQ's DIN A0 DIN A1 Completion of the Burst Write Auto-precharge Begins ≥ WR ≥ tRP DIN A2 DIN A3 tRC min. - 81 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.28 Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 T0 CLK/CLK T3 T4 T5 T6 T7 T8 T9 T11 CMD Post CAS WRA Bank A NOP NOP NOP NOP NOP NOP NOP Bank A Activate A10 = 1 Completion of the Burst Write Auto-precharge Begins DQS, DQS WL = RL - 1 = 4 DIN A0 DIN A1 DIN A2 DIN A3 ≥ tRC ≥ WR tRP min. DQ's 10.29 Self Refresh Timing T0 tCK tCH CLK CLK tRP CKE VIL(ac) VIH(ac) T1 T2 T3 T4 T5 T6 Tm Tn tCL ≥ tXSNR ≥ tXSRD tAOFD ODT VIL(ac) tIS tIH tIS tIH tIS tIH tIS tIH CMD VIH(ac) VIL(ac) Self Refresh VIH(dc) VIL(dc) NOP Non-Read Command NOP Read Command - 82 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.30 Active Power Down Mode Entry and Exit Timing T0 CLK CLK T1 T2 Tn Tn+1 Tn+2 CMD Activate NOP NOP NOP NOP Valid Command CKE tIS tIS tXARD or tXARDS Active Power Down Entry Active Power Down Exit 10.31 Precharged Power Down Mode Entry and Exit Timing T0 CLK CLK T1 T2 T3 Tn Tn+1 Tn+2 CMD Precharge NOP NOP NOP NOP NOP Valid Command NOP CKE tIS tIS tRP tXP Precharge Power Down Entry Precharge Power Down Exit - 83 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 10.32 Clock frequency change in precharge Power Down mode T0 CLK CLK DLL RESET T1 T2 T4 TX TX+1 TY TY+1 TY+2 TY+3 TY+4 Tz CMD CKE NOP NOP NOP NOP NOP Valid 200 Clocks tIS ODT tRP tXP tAOFD tIH ODT is off during DLL RESET Frequency change Occurs here tIS Minimum 2 clocks required before changing frequency Stable new clock before power down exit - 84 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 11. PACKAGE SPECIFICATION Package Outline WBGA60 (11x11.5 mm2) A E1 9 (1.75) bbb C Pin A1 index E 1 2 34 5 67 89 aaa A1 21 Pin A1 index 8 76 5 43 A B C D B E F G H eD A B C D E F G H J K L D A D1 J K L eE 60xΦb The window-side encapsulant ccc C B C Seating plane Solder ball diameter refers. To post reflow condition. ddd M eee M C C A B Symbol A A1 b D E D1 E1 eE eD aaa bbb ccc ddd eee Dimension (mm) Min. --0.25 0.40 11.40 10.90 Nom. ----0.45 11.50 Max. 1.20 0.40 0.50 11.60 Ball Land 11.00 11.10 8.00 BSC. 6.40 BSC. 0.80 BSC. 0.80 BSC. --0.15 --0.20 ------0.10 0.15 0.08 Ball Opening Note: 1. Ball land : 0.5mm 2. Ball opening : 0.4mm 3. PCB Ball land suggested ≤ 0.4mm ----------- - 85 - Publication Release Date: Feb. 18, 2011 Revision A02 W972GG8JB 12. REVISION HISTORY VERSION A01 A02 DATE Nov. 05, 2010 Feb. 18, 2011 PAGE All 4, 5, 37, 38, 40~42, 45, 46, 65 DESCRIPTION Initial formally data sheet Added DDR2-800 (5-5-5/6-6-6), industrial parts: 25I Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 86 - Publication Release Date: Feb. 18, 2011 Revision A02