W9751G6KB-18

W9751G6KB 8M  4 BANKS  16 BIT DDR2 SDRAM Table of Contents1. GENERAL DESCRIPTION................................................................................................................................... 4 2. FEATURES .......................................................................................................................................................... 4 3. ORDER INFORMATION ...................................................................................................................................... 5 4. KEY PARAMETERS ............................................................................................................................................ 5 5. BALL CONFIGURATION ..................................................................................................................................... 6 6. BALL DESCRIPTION ........................................................................................................................................... 7 7. BLOCK DIAGRAM ............................................................................................................................................... 8 8. FUNCTIONAL DESCRIPTION ............................................................................................................................. 9 8.1 Power-up and Initialization Sequence ......................................................................................................... 9 8.2 Mode Register and Extended Mode Registers Operation ......................................................................... 10 8.2.1 Mode Register Set Command (MRS) ............................................................................................ 10 8.2.2 Extend Mode Register Set Commands (EMRS) ............................................................................ 11 8.2.2.1 Extend Mode Register Set Command (1), EMR (1)............................................................ 11 8.2.2.2 DLL Enable/Disable ............................................................................................................ 12 8.2.2.3 Extend Mode Register Set Command (2), EMR (2)............................................................ 13 8.2.2.4 Extend Mode Register Set Command (3), EMR (3)............................................................ 14 8.2.3 Off-Chip Driver (OCD) Impedance Adjustment.............................................................................. 15 8.2.3.1 Extended Mode Register for OCD Impedance Adjustment ................................................ 16 8.2.3.2 OCD Impedance Adjust ...................................................................................................... 16 8.2.3.3 Drive Mode ......................................................................................................................... 17 8.2.4 On-Die Termination (ODT) ............................................................................................................ 18 8.2.5 ODT related timings ...................................................................................................................... 18 8.2.5.1 MRS command to ODT update delay ................................................................................. 18 8.3 Command Function ................................................................................................................................... 20 8.3.1 Bank Activate Command ............................................................................................................... 20 8.3.2 Read Command ............................................................................................................................ 20 8.3.3 Write Command ............................................................................................................................ 21 8.3.4 Burst Read with Auto-precharge Command .................................................................................. 21 8.3.5 Burst Write with Auto-precharge Command .................................................................................. 21 8.3.6 Precharge All Command ............................................................................................................... 21 8.3.7 Self Refresh Entry Command ........................................................................................................ 21 8.3.8 Self Refresh Exit Command .......................................................................................................... 22 8.3.9 Refresh Command ........................................................................................................................ 22 8.3.10 No-Operation Command ............................................................................................................. 23 8.3.11 Device Deselect Command ......................................................................................................... 23 8.4 Read and Write access modes .................................................................................................................. 23 8.4.1 Posted CAS ................................................................................................................................. 23 8.4.1.1 Examples of posted CAS operation ................................................................................. 23 8.4.2 Burst mode operation .................................................................................................................... 24 8.4.3 Burst read mode operation ............................................................................................................ 25 8.4.4 Burst write mode operation............................................................................................................ 25 8.4.5 Write data mask ............................................................................................................................ 26 8.5 Burst Interrupt ............................................................................................................................................ 26 8.6 Precharge operation .................................................................................................................................. 27 Publication Release Date: Aug. 15, 2014 Revision: A07 -1- W9751G6KB 8.6.1 Burst read operation followed by precharge .................................................................................. 27 8.6.2 Burst write operation followed by precharge.................................................................................. 27 8.7 Auto-precharge operation .......................................................................................................................... 27 8.7.1 Burst read with Auto-precharge ..................................................................................................... 28 8.7.2 Burst write with Auto-precharge .................................................................................................... 28 8.8 Refresh Operation ..................................................................................................................................... 29 8.9 Power Down Mode .................................................................................................................................... 29 8.9.1 Power Down Entry ......................................................................................................................... 30 8.9.2 Power Down Exit ........................................................................................................................... 30 8.10 Input clock frequency change during precharge power down .................................................................. 30 9. OPERATION MODE .......................................................................................................................................... 31 9.1 Command Truth Table............................................................................................................................... 31 9.2 Clock Enable (CKE) Truth Table for Synchronous Transitions .................................................................. 32 9.3 Data Mask (DM) Truth Table ..................................................................................................................... 32 9.4 Function Truth Table ................................................................................................................................. 33 9.5 Simplified Stated Diagram ......................................................................................................................... 36 10. ELECTRICAL CHARACTERISTICS ................................................................................................................ 37 10.1 Absolute Maximum Ratings ..................................................................................................................... 37 10.2 Operating Temperature Condition ........................................................................................................... 37 10.3 Recommended DC Operating Conditions ............................................................................................... 37 10.4 ODT DC Electrical Characteristics........................................................................................................... 38 10.5 Input DC Logic Level ............................................................................................................................... 38 10.6 Input AC Logic Level ............................................................................................................................... 38 10.7 Capacitance ............................................................................................................................................ 39 10.8 Leakage and Output Buffer Characteristics ............................................................................................. 39 10.9 DC Characteristics................................................................................................................................... 40 10.10 IDD Measurement Test Parameters ...................................................................................................... 42 10.11 AC Characteristics ................................................................................................................................. 43 10.11.1 AC Characteristics and Operating Condition for -18/18I speed grade ....................................... 43 10.11.2 AC Characteristics and Operating Condition for -25/25L/25I/-3 speed grade ............................ 45 10.12 AC Input Test Conditions ....................................................................................................................... 66 10.13 Differential Input/Output AC Logic Levels .............................................................................................. 66 10.14 AC Overshoot / Undershoot Specification ............................................................................................. 67 10.14.1 AC Overshoot / Undershoot Specification for Address and Control Pins: ................................. 67 10.14.2 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins: ................... 67 11. TIMING WAVEFORMS .................................................................................................................................... 68 11.1 Command Input Timing ........................................................................................................................... 68 11.2 ODT Timing for Active/Standby Mode ..................................................................................................... 69 11.3 ODT Timing for Power Down Mode ......................................................................................................... 69 11.4 ODT Timing mode switch at entering power down mode ........................................................................ 70 11.5 ODT Timing mode switch at exiting power down mode ........................................................................... 71 11.6 Data output (read) timing ......................................................................................................................... 72 11.7 Burst read operation: RL=5 (AL=2, CL=3, BL=4) .................................................................................... 72 11.8 Data input (write) timing ........................................................................................................................... 73 11.9 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4) ......................................................................... 73 11.10 Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) .................................................. 74 11.11 Seamless burst write operation: RL = 5 ( WL = 4, BL = 4)..................................................................... 74 11.12 Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) ......................................................................... 75 11.13 Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) .............................................................. 75 11.14 Write operation with Data Mask: WL=3, AL=0, BL=4) ........................................................................... 76 Publication Release Date: Aug. 15, 2014 Revision: A07 -2- W9751G6KB 11.15 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≤ 2clks) ........................ 77 11.16 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ........................ 77 11.17 Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≤ 2clks) ........................ 78 11.18 Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≤ 2clks) ........................ 78 11.19 Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) ........................ 79 11.20 Burst write operation followed by precharge: WL = (RL-1) = 3 .............................................................. 79 11.21 Burst write operation followed by precharge: WL = (RL-1) = 4 .............................................................. 80 11.22 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ........................... 80 11.23 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) ........................... 81 11.24 Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) .................................................................................................. 81 11.25 Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) .................................................................................................. 82 11.26 Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3 ............................................. 82 11.27 Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 ................................... 83 11.28 Self Refresh Timing ............................................................................................................................... 83 11.29 Basic Power Down Entry and Exit Timing ............................................................................................. 84 11.30 Precharged Power Down Entry and Exit Timing .................................................................................... 84 11.31 Clock frequency change in precharge Power Down mode .................................................................... 85 12. PACKAGE SPECIFICATION ........................................................................................................................... 86 13. REVISION HISTORY ....................................................................................................................................... 87 Publication Release Date: Aug. 15, 2014 Revision: A07 -3- W9751G6KB 1. GENERAL DESCRIPTION The W9751G6KB is a 512M bits DDR2 SDRAM, organized as 8,388,608 words  4 banks  16 bits. This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general applications. W9751G6KB is sorted into the following speed grades: -18, 18I, -25, 25L, 25I and -3. The -18/18I grade parts are compliant to the DDR2-1066 (7-7-7) specification (the 18I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -25/25L/25I grade parts are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -3 grade parts is compliant to the DDR2-667 (5-5-5) specification. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source synchronous fashion. 2. FEATURES  Power Supply: VDD, VDDQ = 1.8 V ± 0.1V  Double Data Rate architecture: two data transfers per clock cycle  CAS Latency: 3, 4, 5, 6 and 7  Burst Length: 4 and 8  Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data  Edge-aligned with Read data and center-aligned with Write data  DLL aligns DQ and DQS transitions with clock  Differential clock inputs (CLK and CLK )  Data masks (DM) for write data  Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS  Posted CAS programmable additive latency supported to make command and data bus efficiency  Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)  Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality  Auto-precharge operation for read and write bursts  Auto Refresh and Self Refresh modes  Precharged Power Down and Active Power Down  Write Data Mask  Write Latency = Read Latency - 1 (WL = RL - 1)  Interface: SSTL_18  Packaged in WBGA 84 Ball (8X12.5 mm2), using Lead free materials with RoHS compliant Publication Release Date: Aug. 15, 2014 Revision: A07 -4- W9751G6KB 3. ORDER INFORMATION PART NUMBER W9751G6KB-18 W9751G6KB18I W9751G6KB-25 W9751G6KB25L W9751G6KB25I W9751G6KB-3 SPEED GRADE OPERATING TEMPERATURE 0°C ≤ TCASE ≤ 85°C -40°C ≤ TCASE ≤ 95°C 0°C ≤ TCASE ≤ 85°C 0°C ≤ TCASE ≤ 85°C -40°C ≤ TCASE ≤ 95°C 0°C ≤ TCASE ≤ 85°C DDR2-1066 (7-7-7) DDR2-1066 (7-7-7) DDR2-800 (5-5-5) or DDR2-800 (6-6-6) DDR2-800 (5-5-5) or DDR2-800 (6-6-6) DDR2-800 (5-5-5) or DDR2-800 (6-6-6) DDR2-667 (5-5-5) 4. KEY PARAMETERS SPEED GRADE DDR2-1066 DDR2-800 DDR2-800 DDR2-667 Bin(CL-tRCD-tRP) 7-7-7 5-5-5/6-6-6 5-5-5/6-6-6 5-5-5 Part Number Extension -18/18I -25/25I 25L -3     SYM. @CL = 7 @CL = 6 tCK(avg) Average clock period @CL = 5 @CL = 4 @CL = 3 tRCD Active to Read/Write Command Delay Time tREFI Average periodic refresh Interval 1.875 nS Max. 7.5 nS  Min. 2.5 nS 2.5 nS 2.5 nS  Max. 7.5 nS 8 nS 8 nS  Min. 3 nS 2.5 nS 2.5 nS Max. 7.5 nS 8 nS 8 nS 8 nS Min. 3.75 nS 3.75 nS 3.75 nS 3.75 nS Max. 7.5 nS 8 nS 8 nS 8 nS Min.  5 nS 5 nS 5 nS Max.  8 nS 8 nS 8 nS Min. 13.125 nS 12.5 nS 12.5 nS 15 nS -40°C ≤ TCASE ≤ 85°C 0°C ≤ TCASE ≤ 85°C  Min. 7.8 μS* Max. 85°C < TCASE ≤ 95°C 2, 3 7.8 μS* 1 3.9 μS* 4 7.8 μS* 2, 3 7.8 μS* 1 3.9 μS* 4 * 3 nS * 2 2 7.8 μS* 1 7.8 μS* 1 3.9 μS* 4 3.9 μS* 4 tRP Precharge to Active Command Period Min. 13.125 nS 12.5 nS 12.5 nS 15 nS tRC Active to Ref/Active Command Period Min. 58.125 nS 57.5 nS 57.5 nS 60 nS tRAS Active to Precharge Command Period Min. 45 nS 45 nS 45 nS 45 nS IDD0 Operating current Max. 105 mA 90 mA 90 mA 80 mA 90 mA IDD1 Operation current (Single bank) Max. 115mA 100 mA 100 mA IDD2P Precharge power-down current Max. 8 mA 8 mA 6 mA 8 mA IDD4R Operating burst read current Max. 165 mA 140 mA 140 mA 125 mA IDD4W Operating burst write current Max. 200 mA 165 mA 165 mA 150 mA IDD5B Burst refresh current Max. 105 mA 95 mA 95 mA 90 mA IDD6 Self refresh current (TCASE ≤ 85C) Max. 6 mA 6 mA 3 mA 6 mA IDD7 Operating bank interleave read current Max. 245 mA 200 mA 200 mA 180 mA Notes: 1. All speed grades support 0°C ≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications. 2. For -18, -25, 25L and -3 speed grades, -40°C ≤ TCASE < 0°C is not available. 3. 18I and 25I speed grades support -40°C ≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications. 4. For all speed grade parts, TCASE is able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS period ( tREFI = 3.9 µS) and to enter to Self Refresh mode at this high temperature range via A7 “1” on EMR (2). Publication Release Date: Aug. 15, 2014 Revision: A07 -5- W9751G6KB 5. BALL CONFIGURATION 1 2 3 VDD NC VSS A VSSQ UDQS VDDQ DQ14 VSSQ UDM B UDQS VSSQ DQ15 VDDQ DQ9 VDDQ C VDDQ DQ8 VDDQ DQ12 VSSQ DQ11 D DQ10 VSSQ DQ13 VDD VSS E VSSQ LDQS VDDQ VSSQ LDM F LDQS VSSQ DQ7 G VDDQ DQ0 VDDQ DQ6 NC VDDQ DQ1 VDDQ DQ4 VSSQ DQ3 VDDL VREF NC VSS VDD 4 5 H 6 7 DQ2 8 9 VSSQ DQ5 VSS J VSSDL CLK CKE WE K RAS CLK BA0 BA1 L CAS CS A10/AP A1 M A2 A0 A3 A5 N A6 A4 A7 A9 P A11 A8 A12 NC R NC NC VDD ODT VDD VSS Publication Release Date: Aug. 15, 2014 Revision: A07 -6- W9751G6KB 6. BALL DESCRIPTION BALL NUMBER SYMBOL FUNCTION DESCRIPTION M8,M3,M7,N2,N8,N3 ,N7,P2,P8,P3,M2,P7 ,R2 A0−A12 Address Provide the row address for active commands, and the column address and Auto-precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. Row address: A0−A12. Column address: A0−A9. (A10 is used for Auto-precharge) L2,L3 BA0−BA1 Bank Select BA0−BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. G8,G2,H7,H3,H1,H9 ,F1,F9,C8,C2,D7,D3, D1,D9,B1,B9 DQ0−DQ15 Data Input / Output K9 ODT On Die Termination Control F7,E8 LDQS, LDQS LOW Data Strobe Bi-directional data bus. ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. Data Strobe for Lower Byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, centeraligned with write data. LDQS corresponds to the data on DQ0−DQ7. LDQS is only used when differential data strobe mode is enabled via the control bit at EMR (1)[A10 EMRS command]. B7,A8 UDQS, UDQS UP Data Strobe Data Strobe for Upper Byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, centeraligned with write data. UDQS corresponds to the data on DQ8−DQ15. UDQS is only used when differential data strobe mode is enabled via the control bit at EMR (1)[A10 EMRS command]. L8 CS Chip Select All commands are masked when CS is registered HIGH. CS provides for external rank selection on systems with multiple ranks. CS is considered part of the command code. K7,L7,K3 RAS , CAS , Command Inputs RAS , CAS and WE (along with CS ) define the command being entered. UDM, LDM Input Data Mask DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. CLK, CLK Differential Clock Inputs WE B3,F3 J8,K8 CLK and CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of CLK . Output (read) data is referenced to the crossings of CLK and CLK (both directions of crossing). K2 CKE Clock Enable J2 VREF A1,E1,J9,M9,R1 VDD Power Supply A3,E3,J3,N1,P9 VSS Ground A9,C1,C3,C7,C9,E9, G1,G3,G7,G9 VDDQ A7,B2,B8,D2,D8,E7, F2,F8,H2,H8 VSSQ DQ Ground A2,E2,L1,R3,R7,R8 NC No Connection J7 VSSDL DLL Ground J1 VDDL CKE (registered HIGH) activates and CKE (registered deactivates clocking circuitry on the DDR2 SDRAM. LOW) Reference Voltage VREF is reference voltage for inputs. Power Supply: 1.8V ± 0.1V. Ground. DQ Power Supply DQ Power Supply: 1.8V ± 0.1V. DQ Ground. Isolated on the device for improved noise immunity. No connection. DLL Ground. DLL Power Supply DLL Power Supply: 1.8V ± 0.1V. Publication Release Date: Aug. 15, 2014 Revision: A07 -7- W9751G6KB 7. BLOCK DIAGRAM CLK CLK DLL CLOCK BUFFER CKE CONTROL CS SIGNAL RAS GENERATOR COMMAND CAS DECODER COLUMN DECODER A10 COLUMN DECODER ROW DECODER ROW DECODER WE CELL ARRAY BANK #0 MODE REGISTER A0 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER ODT PREFETCH REGISTER DQ DATA CONTROL BUFFER CIRCUIT COLUMN COUNTER COUNTER ODT CONTROL DQ0 | DQ15 LDQS LDQS UDQS UDQS LDM UDM COLUMN DECODER COLUMN DECODER ROW DECODER REFRESH ROW DECODER A9 A11 A12 BA0 BA1 CELL ARRAY BANK #1 CELL ARRAY BANK #2 SENSE AMPLIFIER CELL ARRAY BANK #3 SENSE AMPLIFIER NOTE: The cell array configuration is 8192 * 1024 * 16 Publication Release Date: Aug. 15, 2014 Revision: A07 -8- W9751G6KB 8. FUNCTIONAL DESCRIPTION 8.1 Power-up and Initialization Sequence DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for Power-up and Initialization. 1. Apply power and attempt to maintain CKE below 0.2 × VDDQ and ODT*1 at a LOW state (all other inputs may be undefined.) Either one of the following sequence is required for Power-up. A. The VDD voltage ramp time must be no greater than 200 mS from when VDD ramps from 300 mV to VDD min; and during the VDD voltage ramp, |VDD -VDDQ| ≤ 0.3 volts.  VDD, VDDL and VDDQ are driven from a single power converter output  VTT is limited to 0.95V max  VREF*2 tracks VDDQ/2  VDDQ ≥ VREF must be met at all times B. Voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be maintained and is applicable to both AC and DC levels until the ramping of the supply voltages is complete.  Apply VDD/VDDL*3 before or at the same time as VDDQ  Apply VDDQ*4 before or at the same time as VTT  VREF*2 tracks VDDQ/2  VDDQ ≥ VREF must be met at all times  Apply VTT  The VTT voltage ramp time from when VDDQ min is achieved on VDDQ to when VTT min is achieved on VTT must be no greater than 500 mS 2. Start Clock and maintain stable condition for 200 µS (min.). 3. After stable power and clock (CLK, CLK ), apply NOP or Deselect and take CKE HIGH. 4. Wait minimum of 400 nS then issue precharge all command. NOP or Deselect applied during 400 nS period. 5. Issue an EMRS command to EMR (2). (To issue EMRS command to EMR (2), provide LOW to BA0, HIGH to BA1.) 6. Issue an EMRS command to EMR (3). (To issue EMRS command to EMR (3), provide HIGH to BA0 and BA1.) 7. Issue EMRS to enable DLL. (To issue DLL Enable command, provide LOW to A0, HIGH to BA0 and LOW to BA1. And A9=A8=A7=LOW must be used when issuing this command.) 8. Issue a Mode Register Set command for DLL reset. (To issue DLL Reset command, provide HIGH to A8 and LOW to BA0 and BA1.) 9. Issue a precharge all command. 10. Issue 2 or more Auto Refresh commands. 11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating parameters without resetting the DLL.) 12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRS to EMR (1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1). 13. The DDR2 SDRAM is now ready for normal operation. Publication Release Date: Aug. 15, 2014 Revision: A07 -9- W9751G6KB Notes: 1. To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin. 2. VREF must be within ± 300 mV with respect to VDDQ/2 during supply ramp time. 3. VDD/VDDL voltage ramp time must be no greater than 200 mS from when VDD ramps from 300 mV to VDD min. 4. The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be no greater than 500 mS tCH tCL CLK CLK tIS tIS CKE ODT Command PRE ALL NOP 400nS EMRS tRP PRE ALL MRS tMRD tMRD REF REF tRP tRFC MRS tRFC tMRD ANY CMD EMRS EMRS Follow OCD tOIT Flow chart DLL Enable DLL Reset min 200 Cycle OCD Default OCD CAL. Mode Exit Figure 1 – Initialization sequence after power-up 8.2 Mode Register and Extended Mode Registers Operation For application flexibility, burst length, burst type, CAS Latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS Latency, ODT (On Die Termination), single-ended strobe and OCD (off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MR) or Extended Mode Registers EMR (1), EMR (2) and EMR (3) can be altered by re-executing the MRS or EMRS Commands. Even if the user chooses to modify only a subset of the MR or EMR (1), EMR (2) and EMR (3) variables, all variables within the addressed register must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which mean re-initialization including those can be executed at any time after power-up without affecting array contents. 8.2.1 Mode Register Set Command (MRS) ( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "L", A0 to A12 = Register Data) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS Latency, burst length, burst sequence, test mode, DLL reset, Write Recovery (WR) and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value in the Mode Register after power-up is not defined, therefore the Mode Register must be programmed during initialization for proper operation. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. Publication Release Date: Aug. 15, 2014 Revision: A07 - 10 - W9751G6KB The mode register is divided into various fields depending on functionality. Burst length is defined by A[2:0] with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2 does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the table for specific codes. A8 BA1 BA0 A12 0 0 PD 0 DLL Reset No 1 Yes A11 A10 A9 WR A8 A7 DLL TM A7 A6 A5 A4 A3 CAS Latency Mode A2 A1 A0 BT Burst Length A3 Burst Type Sequential 0 Normal 0 1 Test 1 Address Field Mode Register Burst Length A2 A1 A0 BL 0 1 0 4 0 1 1 8 Interleave BA1 BA0 MRS mode 0 0 MR 0 1 EMR (1) A11 A10 A9 WR * A6 A5 A4 Latency 1 0 EMR (2) 0 0 0 Reserved 0 0 0 Reserved 1 1 EMR (3) 0 0 1 2 0 0 1 Reserved 0 1 0 3 0 1 0 Reserved 0 1 1 3 1 0 0 4 1 0 1 5 Write recovery for Auto-precharge 0 1 1 4 0 Fast exit (use tXARD) 1 0 0 5 1 Slow exit (use tXARDS) 1 0 1 6 1 1 0 7 1 1 0 6 1 1 1 8 1 1 1 7 DDR2-1066 Active power down exit time DDR2-667 A12 DDR2-800 DDR2-1066 DDR2-667 DDR2-800 CAS Latency Note: 1. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min. WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this value. This is also used with tRP to determine tDAL. Figure 2 – Mode Register Set (MRS) 8.2.2 8.2.2.1 Extend Mode Register Set Commands (EMRS) Extend Mode Register Set Command (1), EMR (1) ( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L", A0 to A12 = Register data) The extended mode register (1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended mode register (1) is not defined, therefore the extended mode register (1) must be programmed during initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register (1). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1). Extended mode register (1) contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the additive latency, A[9:7] are used for OCD control, A10 is used for DQS disable. A2 and A6 are used for ODT setting. Publication Release Date: Aug. 15, 2014 Revision: A07 - 11 - W9751G6KB 8.2.2.2 DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self Refresh operation and is automatically re-enabled and reset upon exit of Self Refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. A12 1 Qoff 0 BA1 0 0 1 1 BA0 0 1 0 1 A11 A10 MRS mode MR EMR (1) EMR (2) EMR (3) 0*1 DQS A9 A8 A7 A6 A5 OCD program Rtt Additive WR Latency BT A6 0 0 1 1 A2 0 1 0 1 A4 Rtt (nominal) ODT Disabled 75 ohm 150 ohm A10 0 1 A2 Rtt A1 A0 D.I.C DLL A0 0 1 Address Field Extended Mode Register (1) DLL Enable Enable Disable 50 ohm*2 Driver impedance adjustment A9 A8 A7 OCD Calibration Program 0 0 0 OCD calibration mode exit; matain setting 0 0 1 Drive (1) 0 1 0 Drive (0) 1 0 0 Adjust mode*3 1 1 1 OCD Calibration default*4 A12 0 1 A3 Additive Latency A5 0 0 0 0 1 1 1 1 Qoff (Optional)*5 Output buffer enabled Output buffer disabled DQS Enable Disable A4 0 0 1 1 0 0 1 1 A3 0 1 0 1 0 1 0 1 Latency 0 1 2 3 4 5 6 Reserved DDR2-/667/800 BA0 DDR2-1066 BA1 Output Driver Impedance Control Strobe Function Matrix A10 (DQS Enable) DQS DQS 0 (Enable) DQS DQS 1 (Disable) DQS Hi-z A1 Output driver impedance control Driver size 0 1 Normal Reduced 100% 60% Notes: 1. A11 default is “0” RDQS disabled. 2. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066. 3. When Adjust mode is issued, AL from previously set value must be applied. 4. After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. Refer to the section 8.2.3 for detailed information. 5. Output disabled - DQs, LDQS, LDQS , UDQS, UDQS . This feature is used in conjunction with DIMM IDD measurements when IDDQ is not desired to be included. Figure 3 – EMR (1) Publication Release Date: Aug. 15, 2014 Revision: A07 - 12 - W9751G6KB 8.2.2.3 Extend Mode Register Set Command (2), EMR (2) ( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "H", A0 to A12 = Register data) The extended mode register (2) controls refresh related features. The default value of the extended mode register (2) is not defined, therefore the extended mode register (2) must be programmed during initialization for proper operation. The DDR2 SDRAM should be in all bank precharge state with CKE already high prior to writing into the extended mode register (2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. BA1 BA0 1 0 A12 A11 A10 0*1 A9 A8 A7 A6 A5 A4 A3 A2 A1 0*1 SELF BA1 BA0 MRS mode A7 0 0 0 1 MRS EMR (1) 0 Disable 1 0 EMR (2) 1 Enable*2 1 1 EMR (3) A0 Address Field Extended Mode Register (2) High Temperature Self Refresh Rate Enable Notes: 1. The rest bits in EMR (2) is reserved for future use and all bits in EMR (2) except A7, BA0 and BA1 must be programmed to “0” when setting the extended mode register (2) during initialization. 2. When DRAM is operated at 85°C < TCASE ≤ 95°C the extended Self Refresh rate must be enabled by setting bit A7 to “1” before the Self Refresh mode can be entered. Figure 4 – EMR (2) Publication Release Date: Aug. 15, 2014 Revision: A07 - 13 - W9751G6KB 8.2.2.4 Extend Mode Register Set Command (3), EMR (3) ( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "H", A0 to A12 = Register data) No function is defined in extended mode register (3). The default value of the EMR (3) is not defined, therefore the EMR (3) must be programmed during initialization for proper operation. BA1 BA0 A12 A11 A10 A9 1 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field Extended Mode Register (3) 0*1 Note: 1. All bits in EMR (3) except BA0 and BA1 are reserved for future use and must be set to “0” when programming the EMR (3). Figure 5 – EMR (3) Publication Release Date: Aug. 15, 2014 Revision: A07 - 14 - W9751G6KB 8.2.3 Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart in Figure 6 is an example of the sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before any other command being issued. MRS should be set before entering OCD impedance adjustment and On Die Termination (ODT) should be carefully controlled depending on system environment. All MR shoud be programmed before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS: OCD calibration mode exit EMRS: Drive(1) DQ &DQS High; DQS Low Test EMRS: Drive(0) DQ &DQS Low; DQS High ALL OK ALL OK Test Need Calibration Need Calibration EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: Enter Adjust Mode EMRS: Enter Adjust Mode BL=4 code input to all DQs Inc, Dec or NOP BL=4 code input to all DQs Inc, Dec or NOP EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End Figure 6 – OCD Impedance Adjustment Flow Chart Publication Release Date: Aug. 15, 2014 Revision: A07 - 15 - W9751G6KB 8.2.3.1 Extended Mode Register for OCD Impedance Adjustment OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by DDR2 SDRAM. In Drive (1) mode, all DQ, DQS signals are driven HIGH and all DQS signals are driven LOW. In Drive (0) mode, all DQ, DQS signals are driven LOW and all DQS signals are driven HIGH. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 Ohms during nominal temperature and voltage conditions. OCD applies only to normal full strength output drive setting defined by EMR (1) and if reduced strength is set, OCD default driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS commands not intended to adjust OCD characteristics must specify A[9:7] as ’000’ in order to maintain the default or calibrated value. Table 1 – OCD Drive Mode Program A9 0 A8 0 A7 0 Operation OCD calibration mode exit 0 0 1 Drive (1) DQ, DQS HIGH and DQS LOW 0 1 0 Drive (0) DQ, DQS LOW and DQS HIGH 1 1 0 1 0 1 Adjust mode OCD calibration default 8.2.3.2 OCD Impedance Adjust To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4 bit burst code to DDR2 SDRAM as in table 2. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 in table 2 means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs and DQS’s of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the 16 step range. When Adjust mode command is issued, AL from previously set value must be applied. Table 2 – OCD Adjust Mode Program 4 bit burst code inputs to all DQs Operation DT0 DT1 DT2 DT3 0 0 0 0 NOP (No operation) NOP (No operation) 0 0 0 1 Increase by 1 step NOP 0 0 1 0 Decrease by 1 step NOP 0 1 0 0 NOP Increase by 1 step 1 0 0 0 NOP Decrease by 1 step 0 1 0 1 Increase by 1 step Increase by 1 step 0 1 1 0 Decrease by 1 step Increase by 1 step 1 0 0 1 Increase by 1 step Decrease by 1 step 1 0 1 0 Decrease by 1 step Decrease by 1 step Pull-up driver strength Other Combinations Pull-down driver strength Reserved Publication Release Date: Aug. 15, 2014 Revision: A07 - 16 - W9751G6KB For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as shown in Figure 7. For input data pattern for adjustment, DT0 - DT3 is a fixed order and is not affected by burst type (i.e., sequential or interleave). CLK CLK CMD EMRS NOP NOP WL NOP NOP NOP NOP DQS EMRS NOP WR DQS_in tDS tDH DQ_in DT0 DT1 DT2 DT3 DM OCD adjust mode OCD calibration mode exit Figure 7 – OCD Adjust Mode 8.2.3.3 Drive Mode Drive mode, both Drive (1) and Drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers are turned-off tOIT after “OCD calibration mode exit” command as shown in Figure 8. CLK CLK CMD EMRS NOP NOP NOP NOP tOIT DQS DQS EMRS NOP NOP NOP tOIT DQS high & DQS low for Drive (1), DQS low & DQS high for Drive (0) HI-Z DQs high for Drive (1) DQ DQs low for Drive (0) Enter Drive mode OCD calibration mode exit Figure 8 – OCD Drive Mode Publication Release Date: Aug. 15, 2014 Revision: A07 - 17 - W9751G6KB 8.2.4 On-Die Termination (ODT) On-Die Termination (ODT) is a new feature on DDR2 components that allows a DRAM to turn on/off termination resistance for each DQ, UDQS/ UDQS , LDQS/ LDQS , UDM and LDM signal via the ODT control pin. UDQS and LDQS are terminated only when enabled in the EMR (1) by address bit A10 = 0. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self Refresh mode. (Example timing waveforms refer to 11.2, 11.3 ODT Timing for Active/Standby/Power Down Mode and 11.4, 11.5 ODT timing mode switch at entering/exiting power down mode diagram in Chapter 11) VDDQ VDDQ VDDQ sw1 sw2 sw3 Rval1 Rval2 Rval3 DRAM Input Buffer Input Pin Rval1 Rval2 Rval3 sw1 sw2 sw3 VSSQ VSSQ VSSQ Switch (sw1, sw2, sw3) is enabled by ODT pin. Selection among sw1, sw2, and sw3 is determined by “Rtt (nominal)” in EMR (1). Termination included on all DQs, DM, DQS, DQS pins. Figure 9 – Functional Representation of ODT 8.2.5 ODT related timings 8.2.5.1 MRS command to ODT update delay During normal operation the value of the effective termination resistance can be changed with an EMRS command. The update of the Rtt setting is done between tMOD,min and tMOD,max, and CKE must remain HIGH for the entire duration of tMOD window for proper operation. The timings are shown in the following timing diagram. Publication Release Date: Aug. 15, 2014 Revision: A07 - 18 - W9751G6KB CMD EMRS NOP NOP NOP NOP NOP CLK CLK ODT tIS tMOD,max tAOFD tMOD,min Rtt Old setting Updating New setting 1) EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal). 2) "setting" in this diagram is the Register and I/O setting, not what is measured from outside. Figure 10 – ODT update delay timing - tMOD However, to prevent any impedance glitch on the channel, the following conditions must be met.  tAOFD must be met before issuing the EMRS command.  ODT must remain LOW for the entire duration of tMOD window, until tMOD,max is met. Now the ODT is ready for normal operation with the new setting, and the ODT signal may be raised again to turned on the ODT. Following timing diagram shows the proper Rtt update procedure. CLK CLK EMRS CMD NOP NOP NOP NOP NOP ODT tIS tAOFD Rtt tMOD,max tAOND Old setting New setting 1) EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal). 2) "setting" in this diagram is what is measured from outside. Figure 11 – ODT update delay timing - tMOD, as measured from outside Publication Release Date: Aug. 15, 2014 Revision: A07 - 19 - W9751G6KB 8.3 Command Function 8.3.1 Bank Activate Command ( CS = "L", RAS = "L", CAS = "H", WE = "H", BA0, BA1 = Bank, A0 to A12 be row address) The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a Read/Write command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay when the Read/Write command is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 and 6 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between Bank Activate commands is tRRD. T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 CLK CLK Internal RAS - RAS delay (≥ tRCDmin) Address Bank A Row Addr. Bank A Col. Addr. Bank B Row Addr. Bank B Col. Addr. Bank A Addr. Bank B Addr. Bank A Row Addr. Bank A Precharge Bank B Precharge Bank A Activate CAS - CAS delay time(tCCD) Additive Latency delay(AL) tRCD = 1 Read Begins RAS - RAS delay time(≥ tRRD) Command Bank A Activate Bank A Post CAS Read Bank B Activate Bank B Post CAS Read Bank Active (≥ tRAS) Bank Precharge time (≥ tRP) RAS Cycle time (≥ tRC) Figure 12 – Bank activate command cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2 8.3.2 Read Command ( CS = "L", RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A10 = "L", A0 to A9 = Column Address) The READ command is used to initiate a burst read access to an active row. The value on BA0, BA1 inputs selects the bank, and the A0 to A9 address inputs determine the starting column address. The address input A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected, the row being accessed will be precharged at the end of the READ burst; if Auto-precharge is not selected, the row will remain open for subsequent accesses. Publication Release Date: Aug. 15, 2014 Revision: A07 - 20 - W9751G6KB 8.3.3 Write Command ( CS = "L", RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "L", A0 to A9 = Column Address) The WRITE command is used to initiate a burst write access to an active row. The value on BA0, BA1 inputs selects the bank, and the A0 to A9 address inputs determine the starting column address. The address input A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if Auto-precharge is not selected, the row will remain open for subsequent accesses. 8.3.4 Burst Read with Auto-precharge Command ( CS = "L", RAS = "H", CAS ="L", WE = "H", BA0, BA1 = Bank, A10 = "H", A0 to A9 = Column Address) If A10 is HIGH when a Read Command is issued, the Read with Auto-precharge function is engaged. The DDR2 SDRAM starts an Auto-precharge operation on the rising edge which is (AL + BL/2) cycles later than the read with AP command if tRAS(min) and tRTP(min) are satisfied. 8.3.5 Burst Write with Auto-precharge Command ( CS = "L", RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "H", A0 to A9 = Column Address) If A10 is HIGH when a Write Command is issued, the Write with Auto-precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (WR) programmed in the mode register. 8.3.6 Precharge All Command ( CS = "L", RAS = "L", CAS = "H", WE = "L", BA0, BA1 = Don’t Care, A10 = "H", A0 to A9 and A11 to A12 = Don’t Care) The Precharge All command precharge all banks simultaneously. Then all banks are switched to the idle state. 8.3.7 Self Refresh Entry Command ( CS = "L", RAS = "L", CAS = "L", WE = "H", CKE = "L", BA0, BA1, A0 to A12 = Don’t Care) The Self Refresh command can be used to retain data, even if the rest of the system is powered down. When in the Self Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin LOW or using an EMRS command. Once the command is registered, CKE must be held LOW to keep the device in Self Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self Refresh. When the DDR2 SDRAM has entered Self Refresh mode, all of the external signals except CKE, are “Don’t Care”. The clock is internally disabled during self refresh operation to save power. The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered; however, the clock must be restarted and stable before the device can exit self refresh operation. Publication Release Date: Aug. 15, 2014 Revision: A07 - 21 - W9751G6KB 8.3.8 Self Refresh Exit Command (CKE = "H", CS = "H" or CKE = "H", CS = "L", RAS = "H", CAS = "H", WE = "H", BA0, BA1, A0 to A12 = Don’t Care) The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least tXSNR must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period tXSRD for proper operation except for self refresh re-entry. Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after waiting at least tXSNR period and issuing one refresh command (refresh period of tRFC). NOP or Deselect commands must be registered on each positive clock edge during the Self Refresh exit interval tXSNR. ODT should be turned off during tXSRD. The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh mode. 8.3.9 Refresh Command ( CS = "L", RAS = "L", CAS = "L", WE = "H", CKE = "H", BA0, BA1, A0 to A12 = Don’t Care) Refresh is used during normal operation of the DDR2 SDRAM. This command is non persistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an Auto Refresh command. The DDR2 SDRAM requires Auto Refresh cycles at an average periodic interval of tREFI (max.). When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A delay between the auto refresh command (REF) and the next activate command or subsequent auto refresh command must be greater than or equal to the auto refresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 9 x tREFI. T0 T1 T2 T3 Tm Tn Tn + 1 CLK/CLK "HIGH" CKE ≥ tRFC ≥ tRP CMD Precharge NOP NOP REF ≥ tRFC REF NOP ANY Figure 13 – Refresh command Publication Release Date: Aug. 15, 2014 Revision: A07 - 22 - W9751G6KB 8.3.10 No-Operation Command ( CS = "L", RAS = "H", CAS = "H", WE = "H", CKE, BA0, BA1, A0 to A12 = Don’t Care) The No-Operation command simply performs no operation (same command as Device Deselect). 8.3.11 Device Deselect Command ( CS = "H", RAS , CAS , WE , CKE, BA0, BA1, A0 to A12 = Don’t Care) The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 8.4 Read and Write access modes The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. The 8 Mbit x 16 I/O x 4 Bank chip has a page length of 1024 bits (defined by CA0 to CA9)*. The page length of 1024 is divided into 256 or 128 uniquely addressable boundary segments depending on burst length, 256 for 4 bit burst, 128 for 8 bit burst respectively. A 4-bit or 8-bit burst operation will occur entirely within one of the 256 or 128 groups beginning with the column address supplied to the device during the Read or Write Command (CA0 to CA9). The second, third and fourth access will also occur within this group segment. However, the burst order is a function of the starting address, and the burst sequence. A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundary respectively. The minimum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles. Note: Page length is a function of I/O organization and column addressing 8M bits × 16 organization (CA0 to CA9); Page Length = 1024 bits 8.4.1 Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command (or any time during the RAS - CAS -delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS Latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL (greater than 0) must be written into the EMR (1). The Write Latency (WL) is always defined as RL -1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS Latency (RL = AL + CL). Read or Write operations using AL allow seamless bursts. (Example timing waveforms refer to 11.10 and 11.11 seamless burst read/write operation diagram in Chapter 11) 8.4.1.1 Examples of posted CAS operation Examples of a read followed by a write to the same bank where AL = 2 and where AL = 0 are shown in Figures 14 and 15, respectively. Publication Release Date: Aug. 15, 2014 Revision: A07 - 23 - W9751G6KB -1 0 1 Active A-Bank Read A-Bank 2 3 4 5 6 7 8 9 10 11 12 11 12 CLK /CLK CMD Write A-Bank WL=RL-1=4 CL=3 AL=2 DQS/DQS ≥ tRCD RL=AL+CL=5 DQ Dout0 Dout1 Din0 Dout2 Dout3 Din1 Din2 Din3 [AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4] Figure 14 – Example 1: Read followed by a write to the same bank, where AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4 -1 0 1 2 3 4 5 6 7 8 9 10 CLK/CLK AL=0 CMD Active A-Bank Read A-Bank Write A-Bank WL=RL-1=2 CL=3 DQS/DQS ≥ tRCD RL=AL+CL=3 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4] Figure 15 – Example 2: Read followed by a write to the same bank, where AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4 8.4.2 Burst mode operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by MR A[2:0]. The burst type, either sequential or interleaved, is programmable and defined by MR [A3]. Seamless burst read or write operations are supported. Publication Release Date: Aug. 15, 2014 Revision: A07 - 24 - W9751G6KB Unlike DDR1 devices, interruption of a burst read or writes cycle during BL = 4 mode operation is prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write. (Example timing waveforms refer to 11.12 and 11.13 Burst read and write interrupt timing diagram in Chapter 11) Therefore the Burst Stop command is not supported on DDR2 SDRAM devices. Table 3 – Burst Length and Sequence Burst Length 4 8 Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal) x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 8.4.3 Burst read mode operation Burst Read is initiated with a READ command. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven LOW one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS Latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register EMR (1). (Example timing waveforms refer to 11.6 and 11.7 Data output (read) timing and Burst read operation diagram in Chapter 11) 8.4.4 Burst write mode operation Burst Write is initiated with a WRITE command. The address inputs determine the starting column address for the burst. Write Latency (WL) is defined by a Read Latency (RL) minus one and is equal to (AL + CL -1); and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first DQS strobe. A data strobe signal (DQS) should be driven LOW (preamble) nominally half clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (WR). (Example timing waveforms refer to 11.8 and 11.9 Data input (write) timing and Burst write operation diagram in Chapter 11) Publication Release Date: Aug. 15, 2014 Revision: A07 - 25 - W9751G6KB 8.4.5 Write data mask One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAM, consistent with the implementation on DDR1 SDRAM. It has identical timings on write operations as the data bits, and though used in a unidirectional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles. (Example timing waveform refer to 11.14 Write operation with Data Mask diagram in Chapter 11) 8.5 Burst Interrupt Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write or Precharge Command is prohibited. 2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read or Precharge Command is prohibited. 3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings are prohibited. 4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other Write burst interrupt timings are prohibited. 5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM. 6. Read or Write burst with Auto-precharge enabled is not allowed to interrupt. 7. Read burst interruption is allowed by a Read with Auto-precharge command. 8. Write burst interruption is allowed by a Write with Auto-precharge command. 9. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For example below:  Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt).  Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not from the end of the actual burst end. (Example timing waveforms refer to 11.12 and 11.13 Burst read and write interrupt timing diagram in Chapter 11) Publication Release Date: Aug. 15, 2014 Revision: A07 - 26 - W9751G6KB 8.6 Precharge operation The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 are used to define which bank to precharge when the command is issued. Table 4 – Bank selection for precharge by address bits 8.6.1 A10 BA1 BA0 Precharge Bank(s) LOW LOW LOW Bank 0 only LOW LOW HIGH Bank 1 only LOW HIGH LOW Bank 2 only LOW HIGH HIGH Bank 3 only HIGH Don’t Care Don’t Care All Banks Burst read operation followed by precharge Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max(RTP, 2) - 2 clks For the earliest possible precharge, the precharge command may be issued on the rising edge which is “Additive Latency (AL) + BL/2 + max(RTP, 2) - 2 clocks” after a Read command. A new bank active (command) may be issued to the same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied. The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command. (Example timing waveforms refer to 11.15 to 11.19 Burst read operation followed by precharge diagram in Chapter 11) 8.6.2 Burst write operation followed by precharge Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay. (Example timing waveforms refer to 11.20 to 11.21 Burst write operation followed by precharge diagram in Chapter 11) 8.7 Auto-precharge operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command or the Auto-precharge function. When a Read or a Write command is given to the DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is LOW when the READ or WRITE command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is HIGH when the Read or Write command is issued, then the Auto-precharge function is engaged. During Auto-precharge, a Read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is CAS Latency (CL) clock cycles before the end of the read burst. Publication Release Date: Aug. 15, 2014 Revision: A07 - 27 - W9751G6KB Auto-precharge is also implemented during Write commands. The precharge operation engaged by the Auto-precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS Latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed (tRAS satisfied) so that the Auto-precharge command may be issued with any read or write command. 8.7.1 Burst read with Auto-precharge If A10 is HIGH when a Read Command is issued, the Read with Auto-precharge function is engaged. The DDR2 SDRAM starts an Auto-precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if tRAS(min) and tRTP(min) are satisfied. (Example timing waveform refer to 11.22 Burst read operation with Auto-precharge diagram in Chapter 11) If tRAS(min) is not satisfied at the edge, the start point of Auto-precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the start point of Auto-precharge operation will be delayed until tRTP(min) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where tRTP ends (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Autoprecharge to the next Activate command becomes AL + RU{ (tRTP + tRP) / tCK(avg) } (Example timing waveform refer to 11.23 Burst read operation with Auto-precharge diagram in Chapter 11.), for BL = 8 the time from Read with Auto-precharge to the next Activate command is AL + 2 + RU{ (tRTP + tRP) / tCK(avg) }, where RU stands for “rounded up to the next integer”. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. A new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously.  The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-precharge begins.  The RAS cycle time (tRC) from the previous bank activation has been satisfied. (Example timing waveforms refer to 11.24 to 11.25 Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit) and (tRP Limit) diagram in Chapter 11) 8.7.2 Burst write with Auto-precharge If A10 is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (WR) programmed in the mode register. The bank undergoing Autoprecharge from the completion of the write burst may be reactivated if the following two conditions are satisfied.  The data-in to bank activate delay time (WR + tRP) has been satisfied.  The RAS cycle time (tRC) from the previous bank activation has been satisfied. (Example timing waveforms refer to 11.26 to 11.27 Burst write with Auto-precharge (tRC Limit) and (WR + tRP Limit) diagram in Chapter 11) Publication Release Date: Aug. 15, 2014 Revision: A07 - 28 - W9751G6KB Table 5 – Precharge & Auto-precharge clarifications From Command To Command Minimum Delay between “From Command” to “To Command” Unit Notes Read Precharge (to same Bank as Read) AL + BL/2 + max(RTP, 2) - 2 clks 1, 2 Precharge All AL + BL/2 + max(RTP, 2) - 2 clks 1, 2 Precharge (to same Bank as Read w/AP) AL + BL/2 + max(RTP, 2) - 2 clks 1, 2 Precharge All AL + BL/2 + max(RTP, 2) - 2 clks 1, 2 Precharge (to same Bank as Write) WL + BL/2 + tWR clks 2 Precharge All WL + BL/2 + tWR clks 2 Precharge (to same Bank as Write w/AP) WL + BL/2 + WR clks 2 Precharge All WL + BL/2 + WR clks 2 Precharge (to same Bank as Precharge) 1 clks 2 Precharge All 1 clks 2 Precharge 1 clks 2 Precharge All 1 clks 2 Read w/AP Write Write w/AP Precharge Precharge All Notes: 1. RTP[cycles] = RU{ tRTP[nS] / tCK(avg)[nS] }, where RU stands for round up. 2. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command issued to that bank. 8.8 Refresh Operation DDR2 SDRAM requires a refresh of all rows in any rolling 64 mS interval. The necessary refresh can be generated in one of two ways: by explicit Auto Refresh commands or by an internally timed Self Refresh mode. Dividing the number of device rows into the rolling 64 mS interval defines the average refresh interval, tREFI, which is a guideline to controllers for distributed refresh timing. When CS , RAS and CAS are held LOW and WE HIGH at the rising edge of the clock, the chip enters the Refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Refresh command (REF) can be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started. (Example timing waveform refer to 11.28 Self Refresh diagram in Chapter 11) 8.9 Power Down Mode Power-down is synchronously entered when CKE is registered LOW, along with NOP or Deselect command. CKE is not allowed to go LOW while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go LOW while any other operation such as row activation, Precharge or Auto-precharge or Auto Refresh is in progress, but power down IDD specification will not be applied until finishing those operations. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. Publication Release Date: Aug. 15, 2014 Revision: A07 - 29 - W9751G6KB 8.9.1 Power Down Entry Two types of Power Down Mode can be performed on the device: Precharge Power Down Mode and Active Power Down Mode. If power down occurs when all banks are idle, this mode is referred to as Precharge Power Down; if power down occurs when there is a row active in any bank, this mode is referred to as Active Power Down. Entering power down deactivates the input and output buffers, excluding CLK, CLK , ODT and CKE. Also the DLL is disabled upon entering Precharge Power Down or slow exit Active Power Down, but the DLL is kept enabled during fast exit Active Power Down. In power down mode, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and ODT should be in a valid state but all other input signals are “Don’t Care”. CKE LOW must be maintained until tCKE has been satisfied. Maximum power down duration is limited by the refresh requirements of the device, which allows a maximum of 9 x tREFI if maximum posting of REF is utilized immediately before entering power down. (Example timing waveforms refer to 11.29 Basic Power Down Entry and Exit diagram and 11.30 Precharged Power Down Entry and Exit diagram in Chapter 11) 8.9.2 Power Down Exit The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes HIGH. Power-down exit latency is defined at AC Characteristics table of this data sheet. 8.10 Input clock frequency change during precharge power down DDR2 SDRAM input clock frequency can be changed under following condition: DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL must be RESET via MRS command after precharge power down exit. Depending on new clock frequency an additional MRS or EMRS command may need to be issued to appropriately set the WR, CL etc… During DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency. (Example timing waveform refer to 11.31 Clock frequency change in precharge Power Down mode diagram in Chapter 11) Publication Release Date: Aug. 15, 2014 Revision: A07 - 30 - W9751G6KB 9. OPERATION MODE 9.1 Command Truth Table COMMAND CKE Previous Current Cycle Cycle BA1 BA0 A12 A11 A10 A9-A0 Row Address CS RAS CAS WE NOTES L L H H 1, 2 Bank Activate H H BA Single Bank Precharge H H BA X L X L L H L 1, 2 Precharge All Banks H H X X H X L L H L 1 Write H H BA Column L Column L H L L 1, 2, 3 Write with Auto-precharge H H BA Column H Column L H L L 1, 2, 3 Read H H BA Column L Column L H L H 1, 2, 3 Read with Auto-precharge H H BA Column H Column L H L H 1, 2, 3 (Extended) Mode Register Set H H BA L L L L 1, 2 No Operation H X X X X X L H H H 1 Device Deselect H X X X X X H X X X 1 Refresh H H X X X X L L L H 1 Self Refresh Entry H L X X X X L L L H 1, 4 Self Refresh Exit L H X X X X H X X X L H H H Power Down Mode Entry H L X X X X H X X X L H H H Power Down Mode Exit H X X X L H X X X X L H H H OP Code 1, 4, 5 1, 6 1, 6 Notes: 1. All DDR2 SDRAM commands are defined by states of CS , RAS , CAS , WE and CKE at the rising edge of the clock. 2. Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. 3. Burst reads or writes at BL = 4 can not be terminated or interrupted. See “Burst Interrupt” in section 8.5 for details. 4. VREF must be maintained during Self Refresh operation. 5. Self Refresh Exit is asynchronous. 6. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in section 8.9. Publication Release Date: Aug. 15, 2014 Revision: A07 - 31 - W9751G6KB 9.2 Clock Enable (CKE) Truth Table for Synchronous Transitions CKE CURRENT 2 STATE Previous Cycle (N-1) 1 COMMAND (N) Current Cycle (N) 3 ACTION (N) 1 RAS , CAS , W E , CS 3 NOTES L L X Maintain Power Down 11, 13, 15 L H DESELECT or NOP Power Down Exit 4, 8, 11, 13 L L X Maintain Power Down 11, 15, 16 L H DESELECT or NOP Self Refresh Exit 4, 5, 9, 16 H L DESELECT or NOP Active Power Down Entry 4, 8, 10, 11, 13 H L DESELECT or NOP Precharge Power Down Entry 4, 8, 10, 11, 13 H L REFRESH Self Refresh Entry 6, 9, 11, 13 H H Power Down Self Refresh Bank(s) Active All Banks Idle Refer to the Command Truth Table 7 Notes: 1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. 3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N). 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t XSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 6. Self Refresh mode can only be entered from the All Banks Idle state. 7. Must be a legal command as defined in the Command Truth Table. 8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only. 9. Valid commands for Self Refresh Exit are NOP and DESELECT only. 10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge operations are in progress. See section 8.9 “Power Down Mode” and section 8.3.7/8.3.8 “Self Refresh Entry Command/Self Refresh Exit Command” for a detailed list of restrictions. 11. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See section 8.2.4. 13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in section 8.9. 14. CKE must be maintained HIGH while the SDRAM is in OCD calibration mode. 15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMR (1)). 16. VREF must be maintained during Self Refresh operation. 9.3 Data Mask (DM) Truth Table FUNCTION DM DQS NOTE Write enable L Valid 1 Write inhibit H X 1 Note: 1. Used to mask write data, provided coincident with the corresponding data. Publication Release Date: Aug. 15, 2014 Revision: A07 - 32 - W9751G6KB 9.4 Function Truth Table CURRENT STATE Idle Banks Active Read CS RAS CAS WE ADDRESS H X X X X DSL NOP or Power down L H H H X NOP NOP or Power down L H L H BA, CA, A10 READ/READA ILLEGAL 1 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 1 L L H H BA, RA ACT L L H L BA, A10 PRE/PREA Precharge/ Precharge all banks L L L H REF/SELF Auto Refresh or Self Refresh 2 L L L L Mode/Extended register accessing 2 X Op-Code COMMAND MRS/EMRS ACTION Row activating H X X X X DSL NOP L H H H X NOP NOP L H L H BA, CA, A10 READ/READA Begin read L H L L BA, CA, A10 WRIT/WRITA Begin write L L H H BA, RA ACT L L H L BA, A10 PRE/PREA Precharge/ Precharge all banks L L L H REF/SELF ILLEGAL L L L L MRS/EMRS ILLEGAL X Op-Code NOTES ILLEGAL 1 H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H L H BA, CA, A10 READ/READA Burst interrupt 1, 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 1 L L H H BA, RA ACT ILLEGAL 1 L L H L BA, A10 PRE/PREA ILLEGAL 1 L L L H REF/SELF ILLEGAL L L L L MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H L H BA, CA, A10 READ/READA ILLEGAL 1 L H L L BA, CA, A10 WRIT/WRITA Burst interrupt 1, 3 L L H H BA, RA ACT ILLEGAL 1 L L H L BA, A10 PRE/PREA ILLEGAL 1 L L L H REF/SELF ILLEGAL L L L L MRS/EMRS ILLEGAL X Op-Code Write X Op-Code Publication Release Date: Aug. 15, 2014 Revision: A07 - 33 - W9751G6KB Function Truth Table, continued CURRENT STATE Read with Autoprecharge Write with Autoprecharge Precharge Row Activating CS RAS CAS WE ADDRESS COMMAND ACTION X DSL Continue burst to end NOP Continue burst to end NOTES H X X X L H H H X L H L H BA, CA, A10 READ/READA ILLEGAL 1 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 1 L L H H BA, RA ACT ILLEGAL 1 L L H L BA, A10 PRE/PREA ILLEGAL 1 L L L H REF/SELF ILLEGAL L L L L H X X X L H H X Op-Code MRS/EMRS ILLEGAL X DSL Continue burst to end H X NOP Continue burst to end READ/READA L H L H BA, CA, A10 ILLEGAL 1 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 1 L L H H BA, RA ACT ILLEGAL 1 L L H L BA, A10 PRE/PREA ILLEGAL 1 L L L H REF/SELF ILLEGAL X Op-Code MRS/EMRS L L L L H X X X X DSL NOP-> Idle after tRP L H H H X NOP NOP-> Idle after tRP L H L H BA, CA, A10 READ/READA ILLEGAL 1 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 1 L L H H BA, RA ACT ILLEGAL 1 L L H L BA, A10 PRE/PREA NOP-> Idle after tRP 1 L L L H REF/SELF ILLEGAL X Op-Code MRS/EMRS ILLEGAL L L L L H X X X X DSL NOP-> Row active after tRCD L H H H X NOP NOP-> Row active after tRCD L H L H BA, CA, A10 READ/READA ILLEGAL 1 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 1 L L H H BA, RA ACT ILLEGAL 1 L L H L BA, A10 PRE/PREA ILLEGAL 1 L L L H REF/SELF ILLEGAL L L L L MRS/EMRS ILLEGAL X Op-Code ILLEGAL Publication Release Date: Aug. 15, 2014 Revision: A07 - 34 - W9751G6KB Function Truth Table, continued CURRENT STATE Write Recovering Write Recovering with Autoprecharge Refreshing Mode Register Accessing CS RAS CAS WE ADDRESS COMMAND ACTION H X X X X DSL NOP-> Bank active after tWR L H H H X NOP NOP-> Bank active after tWR L H L H BA, CA, A10 READ/READA ILLEGAL NOTES 1 L H L L BA, CA, A10 WRIT/WRITA New write L L H H BA, RA ACT ILLEGAL 1 L L H L BA, A10 PRE/PREA ILLEGAL 1 L L L H REF/SELF ILLEGAL L L L L MRS/EMRS ILLEGAL X Op-Code H X X X X DSL NOP-> Precharge after tWR L H H H X NOP NOP-> Precharge after tWR L H L H BA, CA, A10 READ/READA ILLEGAL 1 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 1 L L H H BA, RA ACT ILLEGAL 1 L L H L BA, A10 PRE/PREA ILLEGAL 1 L L L H REF/SELF ILLEGAL L L L L MRS/EMRS ILLEGAL H X X X L H H L H L X Op-Code X DSL NOP-> Idle after tRC H X NOP NOP-> Idle after tRC H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PREA ILLEGAL L L L H REF/SELF ILLEGAL L L L L MRS/EMRS ILLEGAL H X X X X DSL NOP-> Idle after tMRD L H H H X NOP NOP-> Idle after tMRD L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PREA ILLEGAL L L L H REF/SELF ILLEGAL L L L L MRS/EMRS ILLEGAL X Op-Code X Op-Code Notes: 1. This command may be issued for other banks, depending on the state of the banks. 2. All banks must be in “IDLE”. 3. Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8. Burst read/write can only be interrupted by another read/write with 4 bit burst boundary. Any other case of read/write interrupt is not allowed. Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data. Publication Release Date: Aug. 15, 2014 Revision: A07 - 35 - W9751G6KB 9.5 Simplified Stated Diagram Initialization Sequence OCD calibration CKEL Self Refreshing SELF PRE Setting MR,EMR (1) EMR (2) EMR (3) CKEH Idle All banks Precharged (E)MRS REF Refreshing CKEL ACT CKEL CKEH Precharge Power Down CKEL Autoomatic Sequence Activating Command Sequence CKEL CKEL Active Power Down CKEH CKEL Bank Active Read Write Write WRITA Read Writing Read READA Reading Write WRITA READA CKEL = CKE LOW, enter Power Down CKEH = CKE HIGH, exit Power Down CKEH = CKE HIGH, exit Self Refresh ACT = Activate WRITA = Write with Auto-precharge READA = Read with Auto-precharge PRE = Precharge PREA = Precharge All (E)MRS = (Extended) Mode Register Set SELF = Enter Self Refresh REF = Refresh READA WRITA Writing with Auto-precharge Reading with Auto-precharge PRE, PREA PRE, PREA PRE, PREA Precharging Publication Release Date: Aug. 15, 2014 Revision: A07 - 36 - W9751G6KB 10. ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT NOTES Voltage on VDD pin relative to VSS VDD -1.0 ~ 2.3 V 1, 2 Voltage on VDDQ pin relative to VSS VDDQ -0.5 ~ 2.3 V 1, 2 Voltage on VDDL pin relative to VSS VDDL -0.5 ~ 2.3 V 1, 2 VIN, VOUT -0.5 ~ 2.3 V 1, 2 TSTG -55 ~ 100 °C 1, 3 Voltage on any pin relative to VSS Storage Temperature Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. When VDD and VDDQ and VDDL are less than 500mV; VREF may be equal to or less than 300mV. 3. Storage temperature is the case surface temperature on the center/top side of the DRAM. 10.2 Operating Temperature Condition PARAMETER SYMBOL RATING UNIT NOTES Operating Temperature (for -18/-25/25L/-3) TOPR 0 ~ 85 °C 1, 2, 3 Operating Temperature (for 18I/25I) TOPR -40 ~ 95 °C 1, 2, 3, 4 Notes: 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. 2. Supporting 0 ~ 85°C with full JEDEC AC and DC specifications. 3. Supporting 0 ~ 85°C and being able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS period ( tREFI = 3.9 µS) and to enter to Self Refresh mode at this high temperature range via A7 “1” on EMR (2). 4. During operation, the DRAM case temperature must be maintained between -40 to 95°C for Industrial parts under all specification parameters. 10.3 Recommended DC Operating Conditions SYM. PARAMETER MIN. TYP. MAX. UNIT NOTES VDD Supply Voltage 1.7 1.8 1.9 V 1 VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 5 VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 1, 5 VREF Input Reference Voltage 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V 2, 3 Termination Voltage (System) VREF - 0.04 VREF VREF + 0.04 V 4 VTT Notes: 1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions VDDQ must than or equal to VDD. 2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of V REF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 3. Peak to peak AC noise on VREF may not exceed ± 2 % VREF(dc). 4. VTT of transmitting device must track VREF of receiving device. 5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. Publication Release Date: Aug. 15, 2014 Revision: A07 - 37 - W9751G6KB 10.4 ODT DC Electrical Characteristics PARAMETER/CONDITION SYM. MIN. NOM. MAX. UNIT NOTES Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 Ω Rtt1(eff) 60 75 90 Ω 1 Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 Ω Rtt2(eff) 120 150 180 Ω 1 Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 Ω Rtt3(eff) 40 50 60 Ω 1, 2 ΔVM -6 +6 % 1 Deviation of VM with respect to VDDQ/2 Notes: 1. Test condition for Rtt measurements. 2. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066. Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18. (ac)) and I(VIL (ac)) Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)) Measurement Definition for ΔVM: Measure voltage (VM) at test pin (midpoint) with no load. ΔVM = ((2 x Vm / VDDQ) – 1) x 100% 10.5 Input DC Logic Level PARAMETER SYM. MIN. MAX. UNIT DC input logic HIGH VIH(dc) VREF + 0.125 VDDQ + 0.3 V DC input logic LOW VIL(dc) -0.3 VREF - 0.125 V 10.6 Input AC Logic Level PARAMETER SYM. AC input logic HIGH AC input logic LOW -18/18I -25/25L/25I/-3 UNIT MIN. MAX. MIN. MAX. VIH (ac) VREF + 0.200  VREF + 0.200 VDDQ + VPEAK1 V VIL (ac)  VREF - 0.200 V VREF - 0.200 VSSQ - VPEAK 1 Note: 1. Refer to the page 67 sections 10.14.1 and 10.14.2 AC Overshoot/Undershoot specification table for VPEAK value: maximum peak amplitude allowed for Overshoot/Undershoot. Publication Release Date: Aug. 15, 2014 Revision: A07 - 38 - W9751G6KB 10.7 Capacitance SYM. CCK CDCK CI PARAMETER Input Capacitance , CLK and CLK Input Capacitance delta , CLK and CLK input Capacitance, all other input-only pins CDI Input Capacitance delta, all other input-only pins CIO Input/output Capacitance, DQ, LDM, UDM, LDQS, LDQS , UDQS, UDQS CDIO Input/output Capacitance delta, DQ, LDM, UDM, LDQS, LDQS , UDQS, UDQS MIN. MAX. UNIT 1.0 2.0 pF  0.25 pF 1.0 1.75 pF  0.25 pF 2.5 3.5 pF  0.5 pF 10.8 Leakage and Output Buffer Characteristics SYM. IIL IOL PARAMETER Input Leakage Current (0V ≤ VIN ≤ VDD) Output Leakage Current (Output disabled, 0V ≤ VOUT ≤ VDDQ) VOH Minimum Required Output Pull-up VOL Maximum Required Output Pull-down VOTR Output Timing Measurement Reference Level MIN. MAX. UNIT NOTES -2 2 µA 1 -5 5 µA 2 VTT + 0.603  V  VTT - 0.603 V 0.5 x VDDQ  V 3 IOH(dc) Output Minimum Source DC Current -13.4  mA 4, 6 IOL(dc) Output Minimum Sink DC Current 13.4  mA 5, 6 Notes: 1. All other pins not under test = 0 V. 2. DQ, LDQS, LDQS , UDQS, UDQS are disabled and ODT is turned off. 3. The VDDQ of the device under test is referenced. 4. VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT - VDDQ)/IOH must be less than 21 Ω for values of VOUT between VDDQ and VDDQ 0.28V. 5. VDDQ = 1.7 V; VOUT = 0.28V. VOUT/IOL must be less than 21 Ω for values of VOUT between 0 V and 0.28V. 6. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 3 and 4. They are used to test drive current capability to ensure VIHmin plus a noise margin and VILmax minus a noise margin are delivered to an SSTL_18 receiver. Publication Release Date: Aug. 15, 2014 Revision: A07 - 39 - W9751G6KB 10.9 DC Characteristics SYM. -18/18I -25/25I 25L -3 MAX. MAX. MAX. MAX. 105 90 90 115 100 8 CONDITIONS UNIT NOTES 80 mA 1,2,3,4,5, 6 100 90 mA 1,2,3,4,5, 6 8 6 8 mA 1,2,3,4,5, 6,7 50 45 45 40 mA 1,2,3,4,5, 6 40 35 35 35 mA 1,2,3,4,5, 6 Fast PDN Exit MRS(12) = 0 15 15 15 15 mA 1,2,3,4,5, 6 Slow PDN Exit MRS(12) = 1 12 12 12 12 mA 1,2,3,4,5, 6,7 75 65 65 60 mA 1,2,3,4,5, 6 Operating Current - One Bank Active-Precharge tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); IDD0 IDD1 CKE is HIGH, CS is HIGH between valid commands; Address and control inputs are SWITCHING; Databus inputs are SWITCHING. Operating Current - One Bank Active-ReadPrecharge IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address and control inputs are SWITCHING; Data bus inputs are SWITCHING. IDD2P IDD2N IDD2Q IDD3PF IDD3PS IDD3N Precharge Power-Down Current All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address inputs are STABLE; Data Bus inputs are FLOATING. (TCASE ≤ 85°C) Precharge Standby Current All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING. Precharge Quiet Standby Current All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address inputs are STABLE; Data bus inputs are FLOATING. Active Power-Down Current All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address inputs are STABLE; Data bus inputs are FLOATING. (TCASE ≤ 85°C) Active Standby Current All banks open; tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING. Publication Release Date: Aug. 15, 2014 Revision: A07 - 40 - W9751G6KB IDD4R Operating Burst Read Current All banks open, Continuous burst reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD); 165 140 140 125 mA 1,2,3,4,5, 6 200 165 165 150 mA 1,2,3,4,5, 6 105 95 95 90 mA 1,2,3,4,5, 6 6 6 3 6 mA 1,2,3,4,5, 6,7 245 200 200 180 mA 1,2,3,4,5, 6 CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data Bus inputs are SWITCHING. IDD4W Operating Burst Write Current All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data Bus inputs are SWITCHING. IDD5B Burst Refresh Current tCK = tCK(IDD); Refresh command every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING. Self Refresh Current IDD6 IDD7 CKE≤ 0.2 V, external clock off, CLK and CLK at 0 V; Other control and address inputs are FLOATING; Data bus inputs are FLOATING. (TCASE ≤ 85°C) Operating Bank Interleave Read Current All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during deselects; Data Bus inputs are SWITCHING. Notes: 1. VDD = 1.8 V ± 0.1V; VDDQ = 1.8 V ± 0.1V. 2. IDD specifications are tested after the device is properly initialized. 3. Input slew rate is specified by AC Parametric Test Condition. 4. IDD parameters are specified with ODT disabled. 5. Data Bus consists of DQ, LDM, UDM, LDQS, LDQS , UDQS and UDQS . 6. Definitions for IDD LOW = Vin ≤ VIL (ac) (max) HIGH = Vin ≥ VIH (ac) (min) STABLE = inputs stable at a HIGH or LOW level FLOATING = inputs at VREF = VDDQ/2 SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. 7. The following IDD values must be derated (IDD limits increase), when TCASE ≥ 85°C IDD2P must be derated by 20%; IDD3P(slow) must be derated by 30% and IDD6 must be derated by 80%. (IDD6 will increase by this amount if TCASE < 85°C and the 2X refresh option is still enabled) Publication Release Date: Aug. 15, 2014 Revision: A07 - 41 - W9751G6KB 10.10 IDD Measurement Test Parameters SPEED GRADE DDR2-1066 (-18/18I) DDR2-800 (-25/25L/25I) DDR2-667 (-3) Bin(CL-tRCD-tRP) 7-7-7 5-5-5/6-6-6 5-5-5 CL(IDD) 7 5/6 5 tCK tCK(IDD) 1.875 2.5 3 nS tRCD(IDD) 13.125 12.5 15 nS tRP(IDD) 13.125 12.5 15 nS tRC(IDD) 58.125 57.5 60 nS tRASmin(IDD) 45 45 45 nS tRASmax(IDD) 70000 70000 70000 nS tRRD(IDD)-2KB 10 10 10 nS tFAW(IDD)-2KB 45 45 50 nS tRFC(IDD) 105 105 105 nS UNIT Publication Release Date: Aug. 15, 2014 Revision: A07 - 42 - W9751G6KB 10.11 AC Characteristics 10.11.1 AC Characteristics and Operating Condition for -18/18I speed grade Notes: 1-3 and 45-47 apply to the entire table SYM. SPEED GRADE DDR2-1066 (-18/18I) Bin(CL-tRCD-tRP) 7-7-7 PARAMETER MIN. UNIT25 NOTES MAX. Active to Read/Write Command Delay Time 13.125  nS 23 tRP Precharge to Active Command Period 13.125  nS 23 tRC Active to Ref/Active Command Period 58.125  nS 23 tRAS Active to Precharge Command Period 45 70000 nS 4,23 tRFC Auto Refresh to Active/Auto Refresh command period 105  nS 5 5 tREFI Average periodic refresh Interval tRCD -40°C ≤ TCASE ≤ 85°C* tCCD tCK(avg) 7.8 μS 0°C ≤ TCASE ≤ 85°C  7.8 μS 5 85°C < TCASE ≤ 95°C  3.9 μS 5,6 2  nCK CAS to CAS command delay Average clock period tCK(avg) @ CL=4 3.75 7.5 nS 30,31 tCK(avg) @ CL=5 3 7.5 nS 30,31 tCK(avg) @ CL=6 2.5 7.5 nS 30,31 tCK(avg) @ CL=7 1.875 7.5 nS 30,31 tCH(avg) Average clock high pulse width 0.48 0.52 tCK(avg) 30,31 tCL(avg) Average clock low pulse width 0.48 0.52 tCK(avg) 30,31 DQ output access time from CLK/ CLK -350 350 pS 35 tDQSCK DQS output access time from CLK / CLK -325 325 pS 35 tDQSQ DQS-DQ skew for DQS & associated DQ signals  13 tAC 175 pS tCKE CKE minimum high and low pulse width 3  nCK 7 tRRD Active to active command period for 2KB page size 10  nS 8,23 tFAW Four Activate Window for 2KB page size 45 nS 23 tWR Write recovery time 15  nS 23 tDAL Auto-precharge write recovery + precharge time WR + tnRP  nCK 24 tWTR Internal Write to Read command delay 7.5  nS 9,23 tRTP Internal Read to Precharge command delay 7.5  nS 4,23 tIS (base) Address and control input setup time 125  pS 10,26, 40,42,43 tIH (base) Address and control input hold time 200  pS 11,26, 40,42,43 tIS (ref) Address and control input setup time 325  pS 10,26, 40,42,43 tIH (ref) Address and control input hold time 325  pS 11,26, 40,42,43 tIPW tDQSS Address and control input pulse width for each input DQS latching rising transitions to associated clock edges  0.6 -0.25 0.25 tCK(avg) tCK(avg) 28 tDSS DQS falling edge to CLK setup time 0.2  tCK(avg) 28 tDSH DQS falling edge hold time from CLK 0.2  tCK(avg) 28 tDQSH DQS input high pulse width 0.35  tCK(avg) tDQSL DQS input low pulse width 0.35  tCK(avg) * -40°C ≤ TCASE ≤ 85°C is for 18I grade only. Publication Release Date: Aug. 15, 2014 Revision: A07 - 43 - W9751G6KB AC Characteristics and Operating Condition for -18/18I speed grade, continued Notes: 1-3 and 45-47 apply to the entire table SYM. SPEED GRADE DDR2-1066 (-18/18I) Bin(CL-tRCD-tRP) 7-7-7 PARAMETER UNITS25 NOTES MIN. MAX. tWPRE Write preamble 0.35  tCK(avg) tWPST Write postamble 0.4 0.6 tCK(avg) 12 tRPRE Read preamble 0.9 1.1 tCK(avg) 14,36 tRPST Read postamble 0.4 0.6 tCK(avg) 14,37 tDS(base) DQ and DM input setup time 0  pS 16,27,29, 41,42,44 tDH(base) DQ and DM input hold time 75  pS 17,27,29, 41,42,44 tDS(ref) DQ and DM input setup time 200  pS 16,27,29, 41,42,44 tDH(ref) DQ and DM input hold time 200  pS 17,27,29, 41,42,44 tDIPW DQ and DM input pulse width for each input 0.35  tCK(avg)  tAC,max pS 15,35 tAC,min tAC,max pS 15,35 tHZ Data-out high-impedance time from CLK/ CLK tLZ(DQS) DQS/ DQS -low-impedance time from CLK/ CLK tLZ(DQ) DQ low-impedance time from CLK/ CLK 2 x tAC,min tAC,max pS 15,35  pS 32 tHP Clock half pulse width Min. (tCH(abs), tCL(abs)) tQHS Data hold skew factor  250 pS 33 tQH DQ/DQS output hold time from DQS tHP - tQHS  pS 34 tXSNR Exit Self Refresh to a non-Read command tRFC + 10  nS 23 tXSRD Exit Self Refresh to a Read command 200  nCK Exit precharge power down to any command 3  nCK tXARD Exit active power down to Read command 3  nCK 18 tXARDS Exit active power down to Read command (slow exit, lower power) 10 - AL  nCK 18,19 tAOND ODT turn-on delay tXP tAON tAONPD tAOFD tAOF ODT turn-on ODT turn-on (Power Down mode) ODT turn-off delay ODT turn-off 2 2 nCK 20 tAC,min tAC,max + 2.575 nS 20,35 tAC,min + 2 3 x tCK(avg) + tAC,max+1 nS 2.5 2.5 nCK 21,39 tAC,min tAC,max + 0.6 nS 21,38,39 tAC,min + 2 2.5 x tCK(avg) + tAC,max + 1 nS  nCK tAOFPD ODT turn-off (Power Down mode) tANPD ODT to power down Entry Latency 4 tAXPD ODT Power Down Exit Latency 11 tMRD Mode Register Set command cycle time 2  nCK tMOD MRS command to ODT update delay 0 12 nS 23 tOIT OCD Drive mode output delay 0 12 nS 23 tIS+tCK(avg)+tIH  nS 22 tDELAY Minimum time clocks remain ON after CKE asynchronously drops LOW nCK Publication Release Date: Aug. 15, 2014 Revision: A07 - 44 - W9751G6KB 10.11.2 AC Characteristics and Operating Condition for -25/25L/25I/-3 speed grade Notes: 1-3 and 45-47 apply to the entire table SYM. SPEED GRADE DDR2-800 (-25/25L/25I) DDR2-667 (-3) Bin(CL-tRCD-tRP) 5-5-5/6-6-6 5-5-5 PARAMETER tRCD UNITS25 NOTES MIN. MAX. MIN. MAX. Active to Read/Write Command Delay Time 12.5  15  nS 23 23 tRP Precharge to Active Command Period 12.5  15  nS tRC Active to Ref/Active Command Period 57.5  60  nS 23 tRAS Active to Precharge Command Period 45 70000 45 70000 nS 4,23 tRFC Auto Refresh to Active/Auto Refresh command period 105  105  nS 5  7.8   μS 5 tREFI Average periodic refresh Interval 7.8  7.8 μS 5  3.9  3.9 μS 5,6 -40°C ≤ TCASE ≤ 85°C* 0°C < TCASE ≤ 85°C 85°C < TCASE ≤ 95°C 2  2  nCK tCK(avg) @ CL=3 5 8 5 8 nS 30,31 tCK(avg) @ CL=4 3.75 8 3.75 8 nS 30,31 tCK(avg) @ CL=5 2.5 8 3 8 nS 30,31 tCK(avg) @ CL=6 2.5 8   nS 30,31 tCH(avg) Average clock high pulse width 0.48 0.52 0.48 0.52 tCK(avg) 30,31 tCL(avg) Average clock low pulse width 0.48 0.52 0.48 0.52 tCK(avg) 30,31 -400 400 -450 450 pS 35 -350 350 -400 400 pS 35  200  13 tCCD CAS to CAS command delay tCK(avg) Average clock period tAC DQ output access time from CLK/ CLK tDQSCK DQS output access time from CLK / CLK tDQSQ 240 pS tCKE DQS-DQ skew for DQS & associated DQ signals CKE minimum high and low pulse width 3  3  nCK 7 tRRD Active to active command period for 2KB page size 10  10  nS 8,23 tFAW Four Activate Window for 2KB page size 45  50  nS 23 tWR Write recovery time 15  15  nS 23 tDAL Auto-precharge write recovery + precharge time WR + tnRP  WR + tnRP  nCK 24 tWTR Internal Write to Read command delay 7.5  7.5  nS 9,23 tRTP Internal Read to Precharge command delay 7.5  7.5  nS 4,23 tIS (base) Address and control input setup time 175  200  pS 10,26, 40,42,43 tIH (base) Address and control input hold time 250  275  pS 11,26, 40,42,43 tIS (ref) Address and control input setup time 375  400  pS 10,26, 40,42,43 tIH (ref) Address and control input hold time 375  400  pS 11,26, 40,42,43 Address and control input pulse width for each input 0.6  0.6  tCK(avg) -0.25 0.25 -0.25 0.25 tCK(avg) 28 tIPW tDQSS DQS latching rising transitions to associated clock edges tDSS DQS falling edge to CLK setup time 0.2  0.2  tCK(avg) 28 tDSH DQS falling edge hold time from CLK 0.2  0.2  tCK(avg) 28 tDQSH DQS input high pulse width 0.35  0.35  tCK(avg) tDQSL DQS input low pulse width 0.35  0.35  tCK(avg) * -40°C ≤ TCASE ≤ 85°C is for 25I grade only. Publication Release Date: Aug. 15, 2014 Revision: A07 - 45 - W9751G6KB AC Characteristics and Operating Condition for -25/25L/25I/-3 speed grades, continued Notes: 1-3 and 45-47 apply to the entire table SYM. SPEED GRADE DDR2-800 (-25/25L/25I) DDR2-667 (-3) Bin(CL-tRCD-tRP) PARAMETER 5-5-5/6-6-6 MIN. MAX. 5-5-5 UNITS25 NOTES MIN. MAX. 0.35 0.4 0.9 0.4  0.6 1.1 0.6 tCK(avg) 0.4 0.9 0.4  0.6 1.1 0.6 tDS(base) DQ and DM input setup time 50  100  pS tDH(base) DQ and DM input hold time 125  175  pS tWPRE Write preamble 0.35 tWPST tRPRE tRPST Write postamble Read preamble Read postamble tCK(avg) tCK(avg) tCK(avg) 12 14,36 14,37 16,27,29, 41,42,44 17,27,29, 41,42,44 16,27,29, 41,42,44 17,27,29, 41,42,44 tDS(ref) DQ and DM input setup time 250  300  pS tDH(ref) DQ and DM input hold time 250  300  pS 0.35  0.35  tCK(avg)  tAC,max  tAC,max pS 15,35 tAC,min tAC,max tAC,min tAC,max pS 15,35 2 x tAC,min tAC,max 2 x tAC,min tAC,max pS 15,35 pS 32 tDIPW tHZ tLZ(DQS) DQ and DM input pulse width for each input Data-out high-impedance time from CLK/ CLK DQS/ DQS -low-impedance time from CLK/ CLK tLZ(DQ) DQ low-impedance time from CLK/ CLK Min. (tCH(abs), tCL(abs)) Min. (tCH(abs), tCL(abs)) tHP Clock half pulse width tQHS Data hold skew factor pS 33   tHP - tQHS 340 DQ/DQS output hold time from DQS  tHP - tQHS 300 tQH  pS 34 tXSNR Exit Self Refresh to a non-Read command tRFC + 10  tRFC + 10  nS 23 tXSRD Exit Self Refresh to a Read command 200  200  nCK Exit precharge power down to any command 2  2  nCK Exit active power down to Read command 2  2  nCK 18 8 - AL  7 - AL  nCK 18,19 2 2 tAC,max + 0.7 tAC,min 2 x tCK(avg) + tAC,min + 2 tAC,min + 2 tAC,max + 1 2.5 2.5 2.5 tAC,min tAC,max + 0.6 tAC,min 2.5 x tCK(avg) tAC,min + 2 tAC,min + 2 + tAC,max + 1 2 tAC,max + 0.7 2 x tCK(avg) + tAC,max + 1 2.5 tAC,max + 0.6 2.5 x tCK(avg) + tAC,max + 1 nCK nS 20 20,35   nCK tXP tXARD tAOND tAON Exit active power down to Read command (slow exit, lower power) ODT turn-on delay ODT turn-on tAONPD ODT turn-on (Power Down mode) tXARDS 2 tAC,min tAOFD tAOF ODT turn-off delay ODT turn-off tAOFPD ODT turn-off (Power Down mode) tANPD ODT to power down Entry Latency 3 tAXPD ODT Power Down Exit Latency 8 tMRD Mode Register Set command cycle time 2 tMOD tOIT MRS command to ODT update delay OCD Drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW 0 0 tDELAY tIS+tCK(avg)+ tIH 3 8  12 12 2  tIS+tCK(avg)+ tIH 0 0 nS nCK nS 21,39 21,38,39 nS nCK  12 12 nCK nS nS 23 23  nS 22 Publication Release Date: Aug. 15, 2014 Revision: A07 - 46 - W9751G6KB Notes: 1. All voltages are referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ODT is disabled for all measurements that are not ODT-specific. 3. AC timing reference load: VDDQ DQ Output DUT VTT = VDDQ/2 DQS, DQS Timing reference point Figure 16 25Ω – AC timing reference load 4. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min) have been satisfied. 5. If refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 6. This is an optional feature. For detailed information, please refer to “Operating Temperature Condition” section 10.2 in this data sheet. 7. tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 8. A minimum of two clocks (2 * nCK) is required irrespective of operating frequency. 9. tWTR is at least two clocks (2 * nCK) independent of operation frequency. 10. There are two sets of values listed for Command/Address input setup time: tIS(base) and tIS(ref). The tIS(ref) value (for reference only) is equivalent to the baseline value of tIS(base) at VREF when the slew rate is 1.0 V/nS. The baseline value tIS(base) is the JEDEC defined value, referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to 1.0 V/nS, then the baseline values must be derated by adding the values from table of tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 (page 55). CLK CLK tIS(base) tIH(base) tIS(base) tIH(base) Logic levels VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS VREF levels Figure 17 tIS(ref) tIH(ref) tIS(ref) tIH(ref) – Differential input waveform timing – tIS and tIH Publication Release Date: Aug. 15, 2014 Revision: A07 - 47 - W9751G6KB 11. There are two sets of values listed for Command/Address input hold time: tIH(base) and tIH(ref). The tIH(ref) value (for reference only) is equivalent to the baseline value of tIH(base) at VREF when the slew rate is 1.0 V/nS. The baseline value tIH(base) is the JEDEC defined value, referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to 1.0 V/nS, then the baseline values must be derated by adding the values from table tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 (page 55). 12. The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrades accordingly. 13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mismatch between DQS / DQS and associated DQ in any given cycle. 14. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 18 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 15. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ). Figure 18 shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. tLZ(DQ) refers to tLZ of the DQ’s and tLZ(DQS) refers to tLZ of the (UDQS, LDQS, UDQS and LDQS ) each treated as single-ended signal. VOH - x mV VTT + 2x mV VOH - 2x mV VTT + x mV tHZ tLZ tRPST end point tRPRE begin point VOL + 2x mV VTT - x mV VOL + x mV VTT - 2x mV T1 T2 tHZ,tRPST end point = 2 x T1 - T2 T1 T2 tLZ,tRPRE begin point = 2 x T1 - T2 Figure 18 – Method for calculating transitions and endpoints 16. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0. There are two sets of values listed for DQ and DM input setup time: tDS(base) and tDS(ref). The tDS(ref) value (for reference only) is equivalent to the baseline value tDS(base) at VREF when the slew rate is 2.0 V/nS, differentially. The baseline value tDS(base) is the JEDEC defined value, referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. See Figure 19. If the differential DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from table of DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe (page 60). 17. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0. There are two sets of values listed for DQ and DM input hold time: tDH(base) and tDH(ref). The tDH(ref) value (for reference only) is equivalent to the baseline value tDH(base) at VREF when the slew rate is 2.0 V/nS, differentially. The baseline value tDH(base) is the JEDEC defined value, referenced from the differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. See Figure 19. If the differential DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from table of DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe (page 60). Publication Release Date: Aug. 15, 2014 Revision: A07 - 48 - W9751G6KB DQS DQS tDS(base) tDH(base) tDS(base) tDH(base) Logic levels VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS VREF levels tDS(ref) Figure 19 tDH(ref) tDS(ref) tDH(ref) – Differential input waveform timing – tDS and tDH 18. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. 19. AL = Additive Latency. 20. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND, which is interpreted differently per speed bin. For DDR2-667/800/1066, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 21. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted as 0.5 x tCK(avg) [nS] after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges. For DDR2-667/800: If tCK(avg) = 3 nS is assumed, tAOFD is 1.5 nS (= 0.5 x 3 nS) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges. For DDR2-1066: tAOFD is 0.9375 [nS] (= 0.5 x 1.875 [nS]) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges. 22. The clock frequency is allowed to change during Self Refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required as described in section 8.10. 23. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. Examples: The device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15nS, the device will support tnRP = RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15nS due to input clock jitter. For DDR2-1066 7-7-7, of which tRP = 13.125 nS, the device will support tnRP = RU{tRP / tCK(avg)} = 7, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm+7 is valid even if (Tm+7 - Tm) is less than 13.125 nS due to input clock jitter. 24. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [pS] / tCK(avg) [pS] }, where WR is the value programmed in the mode register set and RU stands for round up. Example: For DDR2-1066 7-7-7 at tCK(avg) = 1.875 nS with WR programmed to 8 nCK, tDAL = 8 + RU{13.125 nS / 1.875 nS} [nCK] = 8 + 7 [nCK] = 15 [nCK]. Publication Release Date: Aug. 15, 2014 Revision: A07 - 49 - W9751G6KB 25. New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667, DDR2-800 and DDR2-1066. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges. Examples: For DDR2-667/800: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min. For DDR2-1066: tXP = 3 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+3, even if (Tm+3 - Tm) is 3 x tCK(avg) + tERR(3per),min. 26. These parameters are measured from a command/address signal (CKE, CS , RAS , CAS , WE , ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CLK/ CLK ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 27. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 28. These parameters are measured from a data strobe signal ((L/U)DQS/ DQS ) crossing to its respective clock signal (CLK/ CLK ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 29. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U)DQS/ DQS ) crossing. Publication Release Date: Aug. 15, 2014 Revision: A07 - 50 - W9751G6KB 30. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters'. The jitter specified is a random jitter meeting a Gaussian distribution. Input clock-Jitter specifications parameters for DDR2-667, DDR2-800 and DDR2-1066 PARAMETER SYMBOL DDR2-667 DDR2-800 DDR2-1066 UNIT MIN. MAX. MIN. MAX. MIN. MAX. tJIT(per) -125 125 -100 100 -90 90 pS tJIT(per,lck) -100 100 -80 80 -80 80 pS tJIT(cc) -250 250 -200 200 -180 180 pS Cycle to cycle clock period jitter during DLL locking period tJIT(cc,lck) -200 200 -160 160 -160 160 pS Cumulative error across 2 cycles tERR(2per) -175 175 -150 150 -132 132 pS Cumulative error across 3 cycles tERR(3per) -225 225 -175 175 -157 157 pS Cumulative error across 4 cycles tERR(4per) -250 250 -200 200 -175 175 pS Cumulative error across 5 cycles tERR(5per) -250 250 -200 200 -188 188 pS Cumulative error across n cycles, n = 6 ... 10, inclusive tERR(6-10per) -350 350 -300 300 -250 250 pS Cumulative error across n cycles, n = 11 ... 50, inclusive tERR(11-50per) -450 450 -450 450 -425 425 pS tJIT(duty) -125 125 -100 100 -75 75 pS Clock period jitter Clock period jitter during DLL locking period Cycle to cycle clock period Duty cycle jitter Definitions: - tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window. N  tCK(avg) =  tCK j  / N  j 1  where N = 200 - tCH(avg) and tCL(avg) tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses. N  tCH(avg) =  tCH j  / (N × tCK(avg))  j 1  where N = 200 tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses. N  tCL(avg) =  tCL j  / (N × tCK(avg))  j 1  where N = 200 Publication Release Date: Aug. 15, 2014 Revision: A07 - 51 - W9751G6KB - tJIT(duty) tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg). tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} where, tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200} tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200} - tJIT(per), tJIT(per,lck) tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing. - tJIT(cc), tJIT(cc,lck) tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of |tCKi+1 – tCKi| tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing. - tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per) tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg). i  n 1  tERR(nper) =   tCK j  –n × tCK(avg)  j 1   n=2  n=3   n=4 Where   n=5  6  n  10  11  n  50 for tERR(2per) for tERR(3per) for tERR(4per) for tERR(5per) for tERR(6 – 10per) for tERR(11 – 50per) Publication Release Date: Aug. 15, 2014 Revision: A07 - 52 - W9751G6KB 31. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.) PARAMETER SYMBOL MIN MAX UNIT Absolute clock period tCK(abs) tCK(avg),min + tJIT(per),min tCK(avg),max + tJIT(per),max pS Absolute clock HIGH pulse width tCH(abs) tCH(avg),min x tCK(avg),min + tJIT(duty),min tCH(avg),max x tCK(avg),max + tJIT(duty),max pS Absolute clock LOW pulse width tCL(abs) tCL(avg),min x tCK(avg),min + tJIT(duty),min tCL(avg),max x tCK(avg),max + tJIT(duty),max pS Examples: 1) For DDR2-667, tCH(abs),min = ( 0.48 x 3000 pS ) - 125 pS = 1315 pS 2) For DDR2-1066, tCH(abs),min = ( 0.48 x 1875 pS ) - 75 pS = 825 pS 32. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = Min ( tCH(abs), tCL(abs) ), where, tCH(abs) is the minimum of the actual instantaneous clock HIGH time; tCL(abs) is the minimum of the actual instantaneous clock LOW time; 33. tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to nchannel variation of the output drivers 34. tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 pS into a DDR2-667 SDRAM, the DRAM provides tQH of 975 pS minimum. 2) If the system provides tHP of 1420 pS into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 pS minimum. 3) If the system provides tHP of 825 pS into a DDR2-1066 SDRAM, the DRAM provides tQH of 575 pS minimum. 4) If the system provides tHP of 900 pS into a DDR2-1066 SDRAM, the DRAM provides tQH of 650 pS minimum. 35. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) Examples: 1) If the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 pS and tERR(6-10per),max = + 293 pS, then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 400 pS - 293 pS = - 693 pS and tDQSCK,max(derated) = tDQSCK,max - tERR(6-10per),min = 400 pS + 272 pS = + 672 pS. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ),min(derated) = - 900 pS - 293 pS = - 1193 pS and tLZ(DQ),max(derated) = 450 pS + 272 pS = + 722 pS. (Caution on the min/max usage!) 2) If the measured jitter into a DDR2-1066 SDRAM has tERR(6-10per),min = - 202 pS and tERR(6-10per),max = + 223 pS, then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 300 pS - 223 pS = - 523 pS and tDQSCK,max(derated) = tDQSCK,max - tERR(6-10per),min = 300 pS + 202 pS = + 502 pS. Similarly, tLZ(DQ) for DDR2-1066 derates to tLZ(DQ),min(derated) = - 700 pS - 223 pS = - 923 pS and tLZ(DQ),max(derated) = 350 pS + 202 pS = + 552 pS. (Caution on the min/max usage!) Publication Release Date: Aug. 15, 2014 Revision: A07 - 53 - W9751G6KB 36. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.) Examples: 1) If the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 pS and tJIT(per),max = + 93 pS, then tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 pS = + 2178 pS and tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 93 pS = + 2843 pS. (Caution on the min/max usage!) 2) If the measured jitter into a DDR2-1066 SDRAM has tJIT(per),min = - 72 pS and tJIT(per),max = + 63 pS, then tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 pS = + 1615.5 pS and tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 63 pS = + 2125.5 pS. (Caution on the min/max usage!) 37. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.) Examples: 1) If the measured jitter into a DDR2-800 SDRAM has tJIT(duty),min = - 72 pS and tJIT(duty),max = + 93 pS, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 pS = + 928 pS and tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 93 pS = + 1593 pS. (Caution on the min/max usage!) 2) If the measured jitter into a DDR2-1066 SDRAM has tJIT(duty),min = - 72 pS and tJIT(duty),max = + 63 pS, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 pS = + 678 pS and tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 63 pS = + 1188 pS. (Caution on the min/max usage!) 38. When the device is operated with input clock jitter, this parameter needs to be derated by { -tJIT(duty),max - tERR(610per),max } and { - tJIT(duty),min - tERR(6-10per),min } of the actual input clock. (output deratings are relative to the SDRAM input clock.) Examples: 1) If the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 pS, tERR(6-10per),max = + 293 pS, tJIT(duty),min = - 106 pS and tJIT(duty),max = + 94 pS, then tAOF,min(derated) = tAOF,min + { - tJIT(duty),max - tERR(6-10per),max } = - 450 pS + { - 94 pS - 293 pS} = - 837 pS and tAOF,max(derated) = tAOF,max + { tJIT(duty),min - tERR(6-10per),min } = 1050 pS + { 106 pS + 272 pS } = + 1428 pS. (Caution on the min/max usage!) 2) If the measured jitter into a DDR2-1066 SDRAM has tERR(6-10per),min = - 202 pS, tERR(6-10per),max = + 223 pS, tJIT(duty),min = - 66 pS and tJIT(duty),max = + 74 pS, then tAOF,min(derated) = tAOF,min + { - tJIT(duty),max tERR(6-10per),max } = - 350 pS + { - 74 pS - 223 pS} = - 647 pS and tAOF,max(derated) = tAOF,max + { tJIT(duty),min - tERR(6-10per),min } = 950 pS + { 66 pS + 202 pS } = + 1218 pS. (Caution on the min/max usage!) 39. For tAOFD of DDR2-667/800/1066, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg), average input clock HIGH pulse width of 0.5 relative to tCK(avg). tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5. Example: If an input clock has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtracting 0.02 x tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the tAOF,max should be derated by adding 0.02 x tCK(avg) to it. Therefore, we have; tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH(avg),min)] x tCK(avg) tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH(avg),max) - 0.5] x tCK(avg) or tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH(avg),min] x tCK(avg)) tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH(avg),max - 0.5] x tCK(avg)) where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at the DRAM input balls. Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6-10per). However tAC values used in the equations shown above are from the timing parameter table and are not derated. Thus the final derated values for tAOF are; tAOF,min(derated_final) = tAOF,min(derated) + { - tJIT(duty),max - tERR(6-10per),max } tAOF,max(derated_final) = tAOF,max(derated) + { - tJIT(duty),min - tERR(6-10per),min } 40. Timings are specified with command/address input slew rate of 1.0 V/nS. 41. Timings are specified with DQs and DM input slew rate of 1.0V/nS. 42. Timings are specified with CLK/ CLK differential slew rate of 2.0 V/nS. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/nS in differential strobe mode. Publication Release Date: Aug. 15, 2014 Revision: A07 - 54 - W9751G6KB 43. tIS and tIH (input setup and hold) derating. tIS/tIH Derating values for DDR2-667, DDR2-800 and DDR2-1066 ΔtIS and ΔtIH Derating Values for DDR2-667, DDR2-800 and DDR2-1066 Command/ Address Slew Rate (V/nS) CLK/ CLK Differential Slew Rate 2.0 V/nS 1.5 V/nS 1.0 V/nS Unit ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH 4.0 +150 +94 +180 +124 +210 +154 pS 3.5 +143 +89 +173 +119 +203 +149 pS 3.0 +133 +83 +163 +113 +193 +143 pS 2.5 +120 +75 +150 +105 +180 +135 pS 2.0 +100 +45 +130 +75 +160 +105 pS 1.5 +67 +21 +97 +51 +127 +81 pS 1.0 0 0 +30 +30 +60 +60 pS 0.9 -5 -14 +25 +16 +55 +46 pS 0.8 -13 -31 +17 -1 +47 +29 pS 0.7 -22 -54 +8 -24 +38 +6 pS 0.6 -34 -83 -4 -53 +26 -23 pS 0.5 -60 -125 -30 -95 0 -65 pS 0.4 -100 -188 -70 -158 -40 -128 pS 0.3 -168 -292 -138 -262 -108 -232 pS 0.25 -200 -375 -170 -345 -140 -315 pS 0.2 -325 -500 -295 -470 -265 -440 pS 0.15 -517 -708 -487 -678 -457 -648 pS 0.1 -1000 -1125 -970 -1095 -940 -1065 pS For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the ΔtIS and ΔtIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF(dc) to AC region’, use nominal slew rate for derating value. See Figure 20 Illustration of nominal slew rate for tIS. If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to AC region’, the slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 21 Illustration of tangent line for tIS. Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded ‘DC to VREF(dc) region’, use nominal slew rate for derating value. See Figure 22 Illustration of nominal slew rate for tIH. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 23 Illustration of tangent line for tIH. Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in above tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 table, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. Publication Release Date: Aug. 15, 2014 Revision: A07 - 55 - W9751G6KB CLK CLK tIS tIH tIS tIH VDDQ VIH(ac)min VREF to AC region VIH(dc)min nominal slew rate VREF(dc) nominal slew rate VIL(dc)max VREF to AC region VIL(ac)max VSS ΔTF Setup Slew Rate = Falling Signal ΔTR VREF(dc) - VIL(ac)max ΔTF Setup Slew Rate Rising Signal = VIH(ac)min - VREF(dc) ΔTR Figure 20 – Illustration of nominal slew rate for tIS Publication Release Date: Aug. 15, 2014 Revision: A07 - 56 - W9751G6KB CLK CLK tIS tIH tIS tIH VDDQ nominal line VIH(ac)min VREF to AC region VIH(dc)min tangent line VREF(dc) tangent line VIL(dc)max VREF to AC region VIL(ac)max nominal line ΔTR VSS ΔTF Setup Slew Rate Rising Signal = tangent line[VIH(ac)min - VREF(dc)] ΔTR Setup Slew Rate tangent line[VREF(dc) - VIL(ac)max] Falling Signal = ΔTF Figure 21 – Illustration of tangent line for tIS Publication Release Date: Aug. 15, 2014 Revision: A07 - 57 - W9751G6KB CLK CLK tIH tIS tIS tIH VDDQ VIH(ac)min VIH(dc)min DC to VREF region nominal slew rate VREF(dc) nominal slew rate DC to VREF region VIL(dc)max VIL(ac)max VSS ΔTR VREF(dc) - VIL(dc)max Hold Slew Rate = Rising Signal ΔTR ΔTF Hold Slew Rate VIH(dc)min - VREF(dc) Falling Signal = ΔTF Figure 22 – Illustration of nominal slew rate for tIH Publication Release Date: Aug. 15, 2014 Revision: A07 - 58 - W9751G6KB CLK CLK tIS tIH tIS tIH VDDQ VIH(ac)min nominal line VIH(dc)min DC to VREF region tangent line VREF(dc) tangent line nominal DC to VREF region line VIL(dc)max VIL(ac)max VSS ΔTR ΔTF tangent line[VREF(dc) - VIL(dc)max] Hold Slew Rate = Rising Signal ΔTR tangent line[VIH(dc)min - VREF(dc)] Hold Slew Rate Falling Signal = ΔTF Figure 23 – Illustration of tangent line for tIH Publication Release Date: Aug. 15, 2014 Revision: A07 - 59 - W9751G6KB 44. Data setup and hold time derating. DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe DQ Slew Rate (V/nS) ΔtDS, ΔtDH Derating Values for DDR2-667, DDR2-800 and DDR2-1066 (All units in ‘pS’; the note applies to the entire table) DQS/ DQS Differential Slew Rate 4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/nS 1.6 V/nS 1.4 V/nS 1.2 V/nS 1.0 V/nS 0.8 V/nS ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH 2.0 100 45 100 45 100 45 - - - - - - - - - - - - 1.5 67 21 67 21 67 21 79 33 - - - - - - - - - - 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - 0.9 - - -5 -14 -5 -14 7 -2 19 10 31 22 - - - - - - 0.8 - - - - -13 -31 -1 -19 11 -7 23 5 35 17 - - - - 0.7 - - - - - - -10 -42 2 -30 14 -18 26 -6 38 6 - - 0.6 - - - - - - - - -10 -59 2 -47 14 -35 26 -23 38 -11 0.5 - - - - - - - - - - -24 -89 -12 -77 0 -65 12 -53 0.4 - - - - - - - - - - - - -52 -140 -40 -128 -28 -116 For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the ΔtDS and ΔtDH derating value respectively. Example: tDS (total setup time) = tDS(base) + ΔtDS. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF(dc) to AC region’, use nominal slew rate for derating value. See Figure 24 Illustration of nominal slew rate for tDS (differential DQS, DQS ). If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to AC region’, the slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 25 Illustration of tangent line for tDS (differential DQS, DQS ). Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded ‘DC level to VREF(dc) region’, use nominal slew rate for derating value. See Figure 26 Illustration of nominal slew rate for tDH (differential DQS, DQS ). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 27 Illustration of tangent line for tDH (differential DQS, DQS ). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in above DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe table, the derating values may be obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. Publication Release Date: Aug. 15, 2014 Revision: A07 - 60 - W9751G6KB 45. Slew Rate Measurement Levels: a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS ) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b) Input slew rate for single ended signals is measured from VREF(dc) to VIH(ac),min for rising edges and from VREF(dc) to VIL(ac),max for falling edges. For differential signals (e.g. CLK - CLK ) slew rate for rising edges is measured from CLK - CLK = - 250 mV to CLK - CLK = + 500 mV (+ 250 mV to - 500 mV for falling edges). c) VID is the magnitude of the difference between the input voltage on CLK and the input voltage on CLK , or between DQS and DQS for differential strobe. 46. DDR2 SDRAM output slew rate test load: Output slew rate is characterized under the test conditions as shown in below figure. VDDQ DQ DUT Output VTT = VDDQ/2 DQS, DQS Test point 25Ω Output slew rate test load 47. Differential data strobe: DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the cross point of DQS and its complement, DQS . This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS , must be tied externally to VSS through a 20 Ω to 10 kΩ resistor to insure proper operation. Publication Release Date: Aug. 15, 2014 Revision: A07 - 61 - W9751G6KB DQS DQS tDS tDH tDS tDH VDDQ VIH(ac)min VREF to AC region VIH(dc)min nominal slew rate VREF(dc) nominal slew rate VIL(dc)max VREF to AC region VIL(ac)max VSS ΔTF ΔTR VIH(ac)min - VREF(dc) Setup Slew Rate = Rising Signal ΔTR VREF(dc) - VIL(ac)max Setup Slew Rate = Falling Signal ΔTF Figure 24 – Illustration of nominal slew rate for tDS (differential DQS, DQS ) Publication Release Date: Aug. 15, 2014 Revision: A07 - 62 - W9751G6KB DQS DQS tDS tDH tDS tDH VDDQ nominal line VIH(ac)min VREF to AC region VIH(dc)min tangent line VREF(dc) tangent line VIL(dc)max VREF to AC region VIL(ac)max nominal line ΔTR VSS Setup Slew Rate tangent line[VIH(ac)min - VREF(dc)] Rising Signal = ΔTR ΔTF Setup Slew Rate tangent line[VREF(dc) - VIL(ac)max] Falling Signal = ΔTF Figure 25 – Illustration of tangent line for tDS (differential DQS, DQS ) Publication Release Date: Aug. 15, 2014 Revision: A07 - 63 - W9751G6KB DQS DQS tDS tDS tDH tDH VDDQ VIH(ac)min VIH(dc)min DC to VREF region nominal slew rate VREF(dc) nominal slew rate DC to VREF region VIL(dc)max VIL(ac)max VSS ΔTR Hold Slew Rate VREF(dc) - VIL(dc)max Rising Signal = ΔTR ΔTF VIH(dc)min - VREF(dc) Hold Slew Rate Falling Signal = ΔTF Figure 26 – Illustration of nominal slew rate for tDH (differential DQS, DQS ) Publication Release Date: Aug. 15, 2014 Revision: A07 - 64 - W9751G6KB DQS DQS tDS tDS tDH tDH VDDQ VIH(ac)min nominal line VIH(dc)min DC to VREF region tangent line VREF(dc) tangent line nominal line VIL(dc)max DC to VREF region VIL(ac)max VSS ΔTR ΔTF Hold Slew Rate tangent line[VREF(dc) - VIL(dc)max] Rising Signal = ΔTR Hold Slew Rate tangent line [VIH(dc)min - VREF(dc)] = Falling Signal ΔTF Figure 27 – Illustration tangent line for tDH (differential DQS, DQS ) Publication Release Date: Aug. 15, 2014 Revision: A07 - 65 - W9751G6KB 10.12 AC Input Test Conditions CONDITION SYMBOL VALUE UNIT NOTES 0.5 x VDDQ V 1 VSWING(MAX) 1.0 V 1 SLEW 1.0 V/nS 2, 3 Input reference voltage VREF Input signal maximum peak to peak swing Input signal minimum slew rate Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(ac) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. 10.13 Differential Input/Output AC Logic Levels PARAMETER SYM. MIN. MAX. UNIT NOTES AC differential input voltage VID (ac) 0.5 VDDQ + 0.6 V 1 AC differential cross point input voltage VIX (ac) 0.5 x VDDQ - 0.175 0.5 x VDDQ + 0.175 V 2 AC differential cross point output voltage VOX (ac) 0.5 x VDDQ - 0.125 0.5 x VDDQ + 0.125 V 3 Notes: 1. VID (ac) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CLK, LDQS or UDQS) and VCP is the complementary input signal (such as CLK , LDQS or UDQS ). The minimum value is equal to VIH (ac) - VIL (ac). 2. The typical value of VIX (ac) is expected to be about 0.5 x VDDQ of the transmitting device and VIX (ac) is expected to track variations in VDDQ. VIX (ac) indicates the voltage at which differential input signals must cross. 3. The typical value of VOX (ac) is expected to be about 0.5 x VDDQ of the transmitting device and VOX (ac) is expected to track variations in VDDQ. VOX (ac) indicates the voltage at which differential output signals must cross. VDDQ VIH(ac) min VIH(dc) min VSWING(MAX) VREF VIL(dc) max VDDQ VTR VID VIL(ac) max VCP VSS ΔTF VREF - VIL(ac) max Falling Slew = ΔTF ΔTR Rising Slew = Crossing point VIX or VOX VSSQ VIH(ac) min - VREF ΔTR Figure 28 – AC input test signal and Differential signal levels waveform Publication Release Date: Aug. 15, 2014 Revision: A07 - 66 - W9751G6KB 10.14 AC Overshoot / Undershoot Specification 10.14.1 AC Overshoot / Undershoot Specification for Address and Control Pins: Applies to A0-A12, BA0-BA1, CS , RAS , CAS , WE , CKE, ODT DDR2-1066 DDR2-800 DDR2-667 UNIT Maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 V Maximum peak amplitude allowed for undershoot area 0.5 0.5 0.5 V Maximum overshoot area above VDD 0.5 0.66 0.8 V-nS Maximum undershoot area below VSS 0.5 0.66 0.8 V-nS PARAMETER 10.14.2 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins: Applies to DQ, LDQS, LDQS , UDQS, UDQS , LDM, UDM, CLK, CLK DDR2-1066 DDR2-800 DDR2-667 UNIT Maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 V Maximum peak amplitude allowed for undershoot area 0.5 0.5 0.5 V Maximum overshoot area above VDDQ 0.19 0.23 0.23 V-nS Maximum undershoot area below VSSQ 0.19 0.23 0.23 V-nS PARAMETER Maximum Amplitude Overshoot Area VDD/VDDQ Volts (V) VSS/VSSQ Maximum Amplitude Undershoot Area Time (nS) Figure 29 – AC overshoot and undershoot definition Publication Release Date: Aug. 15, 2014 Revision: A07 - 67 - W9751G6KB 11. TIMING WAVEFORMS 11.1 Command Input Timing tCK tCK tCH tCL CLK CLK tIS tIH CS tIS tIH tIS tIH tIS tIH tIS tIH RAS CAS WE A0~A12 BA0,1 Refer to the Command Truth Table Publication Release Date: Aug. 15, 2014 Revision: A07 - 68 - W9751G6KB 11.2 ODT Timing for Active/Standby Mode T0 T1 T2 T4 T3 T5 T6 T7 T8 T7 T8 CLK CLK tIS CKE tIS tIS VIH(ac) ODT VIL(ac) tAOFD tAOND Internal Term Res. RTT tAON(min) tAOF(min) tAOF(max) tAON(max) 11.3 ODT Timing for Power Down Mode T0 T1 CLK T2 T3 T4 T5 T6 CLK CKE tIS tIS VIH(ac) ODT VIL(ac) tAOFPD(max) tAOFPD(min) Internal Term Res. RTT tAONPD(min) tAONPD(max) Publication Release Date: Aug. 15, 2014 Revision: A07 - 69 - W9751G6KB 11.4 ODT Timing mode switch at entering power down mode T-5 T-2 T-3 T-4 T0 T-1 T1 T2 CLK CLK tANPD CKE tIS Entering Slow Exit Active Power Down Mode or Precharge Power Down Mode tIS ODT Active & Standby mode timings to be applied VIL(ac) Internal RTT Term Res. tAOFD tIS ODT VIL(ac) Internal Power Down mode timings to be applied RTT Term Res. tAOFPD(max) tIS Active & Standby mode timings to be applied VIH(ac) tAOND ODT Internal RTT Term Res. tIS VIH(ac) Power Down mode timings to be applied tAONPD(max) ODT Internal RTT Term Res. Publication Release Date: Aug. 15, 2014 Revision: A07 - 70 - W9751G6KB 11.5 ODT Timing mode switch at exiting power down mode T0 T1 T5 T7 T6 T9 T8 T10 CLK CLK tIS tAXPD VIH(ac) CKE Exiting from Slow Active Power Down Mode or Precharge Power Down Mode tIS ODT Active & Standby mode timings to be applied VIL(ac) Internal RTT Term Res. tAOFD tIS ODT Power Down mode timings to be applied VIL(ac) Internal RTT Term Res. tAOFPD(max) tIS VIH(ac) Active & Standby mode timings to be applied ODT Internal RTT R TT Term Res. tAOND tIS VIH(ac) Power Down mode timings to be applied ODT Internal RTT Term Res. tAONPD(max) Publication Release Date: Aug. 15, 2014 Revision: A07 - 71 - W9751G6KB 11.6 Data output (read) timing tCH tCL CLK CLK DQS DQS DQS DQS tRPST tRPRE Q DQ Q Q tDQSQmax Q tDQSQmax tQH tQH 11.7 Burst read operation: RL=5 (AL=2, CL=3, BL=4) T0 T1 T2 T4 T3 T5 T6 T7 T8 CLK/CLK CMD Posted CAS READ A NOP NOP NOP NOP NOP NOP NOP NOP NOP ≤ tDQSCK DQS, DQS CL = 3 AL = 2 RL = 5 Dout A0 DQ's Dout A1 Dout A2 Dout A3 Publication Release Date: Aug. 15, 2014 Revision: A07 - 72 - W9751G6KB 11.8 Data input (write) timing tDQSH DQS DQS DQS tDQSL DQS tWPRE tWPST VIH(ac) D DQ VIH(dc) D VIL(dc) D VIL(ac) DM VIH(ac) DMin VIL(ac) DMin tDH tDH tDS tDS D VIH(dc) DMin VIL(dc) DMin 11.9 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4) T0 T1 T2 T3 T4 T5 T6 T7 Tn CLK CLK CMD Posted CAS WRITE A NOP NOP NOP NOP NOP tDQSS Case 1: with tDQSS(max) DQS DQS NOP tDQSS tDSS tDSS WL = RL – 1= 4 Precharge Completion of The Burst Write ≥ tWR DIN A0 DQs Case 2: with tDQSS(min) NOP DIN A1 tDQSS DIN A2 DIN A3 tDQSS tDSH tDSH DQS DQS WL = RL – 1= 4 DQs ≥ tWR DIN A0 DIN A1 DIN A2 DIN A3 Publication Release Date: Aug. 15, 2014 Revision: A07 - 73 - W9751G6KB 11.10 Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK CLK CMD Post CAS READ A Post CAS READ B NOP NOP NOP NOP NOP NOP NOP DQS DQS CL = 3 AL = 2 RL = 5 DOUT A1 DOUT A0 DQ's DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 Note: The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated. 11.11 Seamless burst write operation: RL = 5 ( WL = 4, BL = 4) T0 T1 T2 T3 T4 T5 T8 T7 T6 CLK CLK CMD Post CAS Write A NOP Post CAS Write B NOP NOP NOP NOP NOP NOP DQS DQS WL = RL - 1 = 4 DQ's DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 Note: The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated. Publication Release Date: Aug. 15, 2014 Revision: A07 - 74 - W9751G6KB 11.12 Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) T0 T1 T2 T3 T5 T4 T6 T7 T8 CLK/CLK CMD READ A NOP READ B NOP NOP NOP NOP NOP NOP DQS, DQS Dout A0 DQ's Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6 Dout B7 11.13 Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) T0 T1 T2 T3 T5 T4 T6 T7 T8 CLK/CLK CMD NOP Write A NOP Write B NOP NOP NOP NOP NOP DQS, DQS DQ's Din A0 Din A1 Din A2 Din A3 Din B0 Din B1 Din B2 Din B3 Din B4 Din B5 Din B6 Din B7 Publication Release Date: Aug. 15, 2014 Revision: A07 - 75 - W9751G6KB 11.14 Write operation with Data Mask: WL=3, AL=0, BL=4) Data Mask Timing DQS/ DQS DQ VIH(ac) VIH(dc) VIH(ac) VIH(dc) VIL(ac) VIL(dc) VIL(ac) VIL(dc) tDS tDH tDS DM tDH CLK CLK CMDMAND Write tWR WL + tDQSS (min) Case 1: min tDQSS DQS/DQS DQ DM Case 2: max tDQSS WL + tDQSS (max) DQS/DQS DQ DM Publication Release Date: Aug. 15, 2014 Revision: A07 - 76 - W9751G6KB 11.15 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≤ 2clks) T0 T1 T2 T3 T5 T4 T6 T7 T8 CLK/CLK CMD Post CAS READ A NOP NOP Precharge NOP Bank A Activate NOP NOP NOP ≥ tRP AL+BL/2 clks DQS, DQS CL = 3 AL = 1 RL = 4 Dout A0 DQ's Dout A1 Dout A2 Dout A3 ≥ tRAS ≥ tRTP 11.16 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) T0 T1 T2 T3 T5 T4 T6 T7 T8 CLK/CLK CMD Post CAS READ A NOP NOP NOP NOP Precharge NOP NOP NOP AL + BL/2 clks DQS, DQS AL = 1 CL = 3 RL = 4 Dout A0 DQ's Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 ≥ tRTP first 4-bit prefetch second 4-bit prefetch Publication Release Date: Aug. 15, 2014 Revision: A07 - 77 - W9751G6KB 11.17 Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≤ 2clks) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK/CLK CMD Post CAS READ A NOP Precharge NOP NOP Bank A Activate NOP NOP NOP ≥ tRP AL + BL/2 clks DQS, DQS AL = 2 CL = 3 RL = 5 Dout A0 DQ's ≥ tRAS Dout A1 Dout A2 Dout A3 CL = 3 ≥ tRTP 11.18 Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≤ 2clks) T0 T1 T2 T4 T3 T5 T6 T8 T7 CLK/CLK CMD Post CAS READA NOP NOP NOP Precharge NOP Bank A Activate NOP NOP ≥ tRP AL + BL/2 clks DQS, DQS AL = 2 CL = 4 RL = 6 Dout A0 DQ's ≥ tRAS Dout A1 Dout A2 Dout A3 CL = 4 ≥ tRTP Publication Release Date: Aug. 15, 2014 Revision: A07 - 78 - W9751G6KB 11.19 Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK/CLK CMD Post CAS READ A NOP NOP NOP Precharge NOP NOP Bank A Activate NOP AL + BL/2 + max(RTP, 2) - 2 clks DQS, DQS AL = 0 CL = 4 ≥ tRP RL = 4 Dout A0 DQ's Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 ≥ tRAS ≥ tRTP second 4-bit prefetch first 4-bit prefetch 11.20 Burst write operation followed by precharge: WL = (RL-1) = 3 T0 T1 T2 T3 T5 T4 T6 T7 T8 CLK/CLK CMD Post CAS WRITE A NOP NOP NOP NOP NOP NOP NOP Precharge Completion of the Burst Write ≥ tWR DQS, DQS WL = 3 DQ's DIN A0 DIN A1 DIN A2 DIN A3 Publication Release Date: Aug. 15, 2014 Revision: A07 - 79 - W9751G6KB 11.21 Burst write operation followed by precharge: WL = (RL-1) = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 CLK/CLK CMD Posted CAS WRITE A NOP NOP NOP NOP NOP NOP NOP Precharge A Completion of the Burst Write ≥ tWR DQS, DQS WL = 4 DIN A0 DIN A1 DIN A2 DIN A3 DQ's 11.22 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK/CLK CMD Post CAS READA A10 = 1 NOP NOP NOP NOP NOP NOP Bank A Activate NOP ≥ tRP AL + BL/2 clks DQS, DQS AL = 1 CL = 3 RL = 4 Dout A0 DQ's Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 ≥ tRTP first 4-bit prefetch second 4-bit prefetch tRTP Precharge begins here Publication Release Date: Aug. 15, 2014 Revision: A07 - 80 - W9751G6KB 11.23 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) T0 T1 T2 T4 T3 T5 T6 T7 T8 CLK/CLK CMD Post CAS READA NOP A10 = 1 NOP NOP NOP NOP Bank A Activate NOP NOP ≥ AL + tRTP + tRP DQS, DQS AL = 1 CL = 3 RL = 4 Dout A0 DQ's 4-bit prefetch Dout A1 tRTP Dout A2 Dout A3 tRP Precharge begins here 11.24 Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK/CLK CMD Post CAS READA NOP NOP NOP NOP NOP NOP NOP Bank A Activate A10 = 1 ≥ tRAS min. (AL + BL/2) Auto-precharge begins DQS, DQS ≥ tRP AL = 2 CL = 3 RL = 5 Dout A0 DQ's Dout A1 Dout A2 Dout A3 tRC min. Publication Release Date: Aug. 15, 2014 Revision: A07 - 81 - W9751G6KB 11.25 Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK/CLK CMD Post CAS READA NOP NOP NOP NOP NOP Bank A Activate NOP NOP A10 = 1 Auto-precharge begins ≥ tRAS min. DQS, DQS tRP min. AL = 2 CL = 3 RL = 5 Dout A0 DQ's Dout A1 Dout A2 Dout A3 ≥ tRC 11.26 Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3 T0 T1 T2 T3 T4 T5 T6 T7 Tm CLK/CLK CMD Post CAS WRA Bank A NOP NOP NOP A10 = 1 NOP NOP NOP NOP Bank A Activate Completion of the Burst Write Auto-precharge Begins DQS, DQS ≥ WR ≥ tRP WL= RL- 1 = 2 DQ's DIN A0 DIN A1 DIN A2 DIN A3 tRC min. Publication Release Date: Aug. 15, 2014 Revision: A07 - 82 - W9751G6KB 11.27 Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 T0 T3 T4 T6 T5 T7 T8 T11 T9 CLK/CLK CMD Post CAS WRA Bank A NOP NOP NOP NOP NOP Bank A Activate NOP NOP A10 = 1 Completion of the Burst Write Auto-precharge Begins DQS, DQS ≥ WR tRP min. WL = RL - 1 = 4 DIN A0 DQ's DIN A1 DIN A2 DIN A3 ≥ tRC 11.28 Self Refresh Timing T0 T1 T2 T3 T4 T5 Tm T6 Tn tCK tCH tCL CLK CLK ≥ tXSNR tRP ≥ tXSRD CKE VIH(ac) VIL(ac) tAOFD ODT tIS tIH VIL(ac) tIH tIS tIS tIH tIS tIH CMD VIH(ac) VIL(ac) Self Refresh VIH(dc) VIL(dc) NOP Non-Read Command NOP Read Command Notes: 1. Device must be in the “All banks idle” state prior to entering Self Refresh mode. 2. ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again when tXSRD timing is satisfied. 3. tXSRD is applied for a Read or a Read with Auto-precharge command. tXSNR is applied for any command except a Read or a Read with Auto-precharge command. Publication Release Date: Aug. 15, 2014 Revision: A07 - 83 - W9751G6KB 11.29 Basic Power Down Entry and Exit Timing CLK CLK tIH tIS tIH tIS tIH tIS tIH CKE CMD VALID NOP NOP tCKEmin NOP VALID VALID or NOP tXP, tXARD tXARDS tCKEmin Power-Down Mode Exit Power-Down Mode Entry Don't Care 11.30 Precharged Power Down Entry and Exit Timing CLK CLK tIH tIS tIH tIS CKE CMD NOP Precharge 1 x tCK NOP VALID tXP tCKEmin Precharge Power-Down Entry NOP Precharge Power-Down Exit Don't Care Publication Release Date: Aug. 15, 2014 Revision: A07 - 84 - W9751G6KB 11.31 Clock frequency change in precharge Power Down mode T0 T1 T2 NOP NOP T4 TX TX+1 TY TY+1 TY+2 TY+3 TY+4 NOP NOP DLL RESET Tz CLK CLK CMD NOP Valid CKE 200 Clocks tIS tIS Frequency change Occurs here ODT tRP tIH tXP tAOFD Minimum 2 clocks required before changing frequency ODT is off during DLL RESET Stable new clock before power down exit Publication Release Date: Aug. 15, 2014 Revision: A07 - 85 - W9751G6KB 12. PACKAGE SPECIFICATION Package Outline WBGA-84 (8x12.5 mm2, ball pitch: 0.8mm, Ø =0.45mm) Note: 1. Ball land:0.5mm, Ball opening:0.4mm, PCB Ball land suggested ≦0.4mm Publication Release Date: Aug. 15, 2014 Revision: A07 - 86 - W9751G6KB 13. REVISION HISTORY VERSION DATE PAGE A01 Dec. 09, 2011 All Initial formal datasheet 5 Added section 3 order information table A02 Jul. 20, 2012 A03 Aug. 10, 2012 A04 Sep. 03, 2012 DESCRIPTION 4, 5, 13, 37, 38, Added 25A and 25K automotive grade parts 40~42, 45, 46 1 Header title typo corrected 9 Added VTT voltage ramp time required condition in section 8.1 power-up and initialization sequence 83 Added notes for 11.28 self refresh timing diagram Added “ddd” and “eee” symbols in WBGA84 package outline drawing diagram 4, 5, 13, 37, 38, Removed 25A and 25K automotive grade parts and 40~42, 45, 46 Added 25L grade part 86 A05 Apr. 01, 2014 A06 May 23, 2014 4, 5, 37, 38, 40~44 A07 Aug. 15, 2014 5 Added 18I industrial grade parts Revise tRAS value typo in Key parameters table Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Publication Release Date: Aug. 15, 2014 Revision: A07 - 87 -