W979H6KBVX2I

W979H6KB / W979H2KB LPDDR2-S4B 512Mb Table of Contents1. GENERAL DESCRIPTION ............................................................................................................................................ 6 2. FEATURES .................................................................................................................................................................... 6 3. ORDER INFORMATION ................................................................................................................................................ 7 4. 4.1 4.2 PIN CONFIGURATION .................................................................................................................................................. 8 134 Ball VFBGA ............................................................................................................................................................. 8 168 Ball WFBGA ............................................................................................................................................................ 9 5.1 5.2 PIN DESCRIPTION ..................................................................................................................................................... 10 Basic Functionality ....................................................................................................................................................... 10 Addressing Table ......................................................................................................................................................... 11 5. 6. BLOCK DIAGRAM ....................................................................................................................................................... 12 7. FUNCTIONAL DESCRIPTION..................................................................................................................................... 13 Simplified LPDDR2 State Diagram .............................................................................................................................. 13 7.1 7.1.1 7.2 Simplified LPDDR2 Bus Interface State Diagram ............................................................................................................ 14 Power-up, Initialization, and Power-Off ........................................................................................................................ 15 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.3 Power Ramp and Device Initialization ............................................................................................................................. 15 Timing Parameters for Initialization ................................................................................................................................. 17 Power Ramp and Initialization Sequence ........................................................................................................................ 17 Initialization after Reset (without Power ramp) ................................................................................................................ 18 Power-off Sequence ........................................................................................................................................................ 18 Timing Parameters Power-Off ......................................................................................................................................... 18 Uncontrolled Power-Off Sequence .................................................................................................................................. 18 Mode Register Definition .............................................................................................................................................. 19 7.3.1 7.3.1.1 7.3.2 7.3.3 7.3.3.1 7.3.3.2 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 7.3.14 7.3.15 7.3.16 7.4 Mode Register Assignment and Definition ....................................................................................................................... 19 Mode Register Assignment ................................................................................................................................... 19 MR0_Device Information (MA[7:0] = 00H) ....................................................................................................................... 20 MR1_Device Feature 1 (MA[7:0] = 01H) ......................................................................................................................... 20 Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC) ............................................... 21 Non Wrap Restrictions .......................................................................................................................................... 21 MR2_Device Feature 2 (MA[7:0] = 02H) ......................................................................................................................... 22 MR3_I/O Configuration 1 (MA[7:0] = 03H)....................................................................................................................... 22 MR4_Device Temperature (MA[7:0] = 04H) .................................................................................................................... 22 MR5_Basic Configuration 1 (MA[7:0] = 05H)................................................................................................................... 23 MR6_Basic Configuration 2 (MA[7:0] = 06H)................................................................................................................... 23 MR7_Basic Configuration 3 (MA[7:0] = 07H)................................................................................................................... 23 MR8_Basic Configuration 4 (MA[7:0] = 08H)................................................................................................................... 23 MR9_Test Mode (MA[7:0] = 09H) .................................................................................................................................... 23 MR10_Calibration (MA[7:0] = 0AH) ................................................................................................................................. 24 MR16_PASR_Bank Mask (MA[7:0] = 10H) ..................................................................................................................... 24 MR32_DQ Calibration Pattern A (MA[7:0] = 20H) ........................................................................................................... 25 MR40_DQ Calibration Pattern B (MA[7:0] = 28H) ........................................................................................................... 25 MR63_Reset (MA[7:0] = 3FH): MRW only....................................................................................................................... 25 Command Definitions and Timing Diagrams ................................................................................................................ 25 7.4.1 7.4.1.1 7.4.1.2 7.4.1.3 7.4.2 7.4.3 7.4.3.1 7.4.3.2 7.4.3.3 7.4.3.4 Activate Command .......................................................................................................................................................... 25 Activate Command Cycle: tRCD = 3, tRP = 3, tRRD = 2 ...................................................................................... 25 Command Input Setup and Hold Timing ............................................................................................................... 26 CKE Input Setup and Hold Timing ........................................................................................................................ 26 Read and Write Access Modes ....................................................................................................................................... 27 Burst Read Command ..................................................................................................................................................... 27 Data Output (Read) Timing (tDQSCKmax) ........................................................................................................... 27 Data Output (Read) Timing (tDQSCKmin) ............................................................................................................ 28 Burst Read: RL = 5, BL = 4, tDQSCK > tCK ......................................................................................................... 28 Burst Read: RL = 3, BL = 8, tDQSCK < tCK ......................................................................................................... 29 Publication Release Date: Jan. 19, 2015 Revision: A01-002 -1- W979H6KB / W979H2KB 7.4.3.5 7.4.3.6 7.4.3.7 7.4.3.8 7.4.3.9 7.4.4 7.4.4.1 7.4.5 7.4.5.1 7.4.5.2 7.4.5.3 7.4.5.4 7.4.6 7.4.6.1 7.4.7 7.4.7.1 7.4.7.2 7.4.8 7.4.8.1 7.4.9 7.4.9.1 7.4.10 7.4.10.1 7.4.10.2 7.4.11 7.4.11.1 7.4.12 7.4.13 7.4.13.1 7.4.14 7.4.14.1 7.4.14.2 7.4.15 7.4.15.1 7.4.16 7.4.16.1 7.4.16.2 7.4.16.3 7.4.16.4 7.4.16.5 7.4.16.6 7.4.17 7.4.18 7.4.19 7.4.19.1 7.4.19.2 7.4.19.3 7.4.20 7.4.20.1 7.4.20.2 7.4.20.3 7.4.21 7.4.21.1 7.4.21.2 7.4.22 7.4.23 LPDDR2: tDQSCKDL Timing ................................................................................................................................ 29 LPDDR2: tDQSCKDM Timing ............................................................................................................................... 30 LPDDR2: tDQSCKDS Timing ............................................................................................................................... 30 Burst Read Followed by Burst Write: RL = 3, WL = 1, BL = 4 .............................................................................. 31 Seamless Burst Read: RL = 3, BL= 4, tCCD = 2 .................................................................................................. 31 Reads Interrupted by a Read ........................................................................................................................................... 32 Read Burst Interrupt Example: RL = 3, BL= 8, tCCD = 2 ..................................................................................... 32 Burst Write Operation ...................................................................................................................................................... 32 Data Input (Write) Timing ...................................................................................................................................... 33 Burst Write: WL = 1, BL= 4 ................................................................................................................................... 33 Burst Wirte Followed by Burst Read: RL = 3, WL= 1, BL= 4 ................................................................................ 34 Seamless Burst Write: WL= 1, BL = 4, tCCD = 2.................................................................................................. 34 Writes Interrupted by a Write ........................................................................................................................................... 35 Write Burst Interrupt Timing: WL = 1, BL = 8, tCCD = 2 ....................................................................................... 35 Burst Terminate ............................................................................................................................................................... 35 Burst Write Truncated by BST: WL = 1, BL = 16 .................................................................................................. 36 Burst Read Truncated by BST: RL = 3, BL = 16 ................................................................................................... 36 Write Data Mask .............................................................................................................................................................. 37 Write Data Mask Timing ........................................................................................................................................ 37 Precharge Operation ....................................................................................................................................................... 38 Bank Selection for Precharge by Address Bits ..................................................................................................... 38 Burst Read Operation Followed by Precharge ................................................................................................................ 38 Burst Read Followed by Precharge: RL = 3, BL = 8, RU(tRTP(min)/tCK) = 2 ...................................................... 39 Burst Read Followed by Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 3 ...................................................... 39 Burst Write Followed by Precharge ................................................................................................................................. 40 Burst Write Follwed by Precharge: WL = 1, BL = 4 .............................................................................................. 40 Auto Precharge Operation ............................................................................................................................................... 41 Burst Read with Auto-Precharge ..................................................................................................................................... 41 Burst Read with Auto-Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 2 .......................................................... 41 Burst Write with Auto-Precharge ..................................................................................................................................... 42 Burst Write with Auto-Precharge: WL = 1, BL = 4 ................................................................................................. 42 Precharge & Auto Precharge Clarification ............................................................................................................ 43 Refresh Command ........................................................................................................................................................... 44 Command Scheduling Separations Related to Refresh ....................................................................................... 44 LPDDR2 SDRAM Refresh Requirements ........................................................................................................................ 45 Definition of tSRF .................................................................................................................................................. 45 Regular, Distributed Refresh Pattern .................................................................................................................... 46 Allowable Transition from Repetitive Burst Refresh .............................................................................................. 47 NOT-Allowable Transition from Repetitive Burst Refresh ..................................................................................... 47 Recommended Self-Refresh Entry and Exit ......................................................................................................... 48 All Bank Refresh Operation .................................................................................................................................. 48 Self Refresh Operation .................................................................................................................................................... 49 Partial Array Self-Refresh: Bank Masking ....................................................................................................................... 50 Mode Register Read Command ...................................................................................................................................... 51 Mode Register Read Timing Example: RL = 3, tMRR = 2 .................................................................................... 51 Read to MRR Timing Example: RL = 3, tMRR = 2 ............................................................................................... 52 Burst Write Followed by MRR: RL = 3, WL = 1, BL = 4 ........................................................................................ 52 Temperature Sensor ........................................................................................................................................................ 53 Temperature Sensor Timing ................................................................................................................................. 54 DQ Calibration ...................................................................................................................................................... 54 MR32 and MR40 DQ Calibration Timing Example: RL = 3, tMRR = 2 ................................................................. 55 Mode Register Write Command ...................................................................................................................................... 56 Mode Register Write Timing Example: RL = 3, tMRW = 5 .................................................................................... 56 Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW) .................................................... 56 Mode Register Write Reset (MRW Reset) ....................................................................................................................... 57 Mode Register Write ZQ Calibration Command .............................................................................................................. 57 Publication Release Date: Jan. 19, 2015 Revision: A01-002 -2- W979H6KB / W979H2KB 7.4.23.1 7.4.23.2 7.4.23.3 7.4.23.4 7.4.23.5 7.4.24 7.4.24.1 7.4.24.2 7.4.24.3 7.4.24.4 7.4.24.5 7.4.24.6 7.4.24.7 7.4.24.8 7.4.24.9 7.4.24.10 7.4.24.11 7.4.24.12 7.4.25 7.4.25.1 7.4.26 7.4.27 7.5 Truth Tables ................................................................................................................................................................. 67 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 8. 8.1 8.2 ZQ Calibration Initialization Timing Example ........................................................................................................ 58 ZQ Calibration Short Timing Example .................................................................................................................. 58 ZQ Calibration Long Timing Example ................................................................................................................... 59 ZQ Calibration Reset Timing Example .................................................................................................................. 59 ZQ External Resistor Value, Tolerance, and Capacitive Loading ......................................................................... 60 Power-Down .................................................................................................................................................................... 60 Basic Power Down Entry and Exit Timing ............................................................................................................. 60 CKE Intensive Environment .................................................................................................................................. 61 Refresh to Refresh Timing with CKE Intensive Environment ................................................................................ 61 Read to Power-Down Entry .................................................................................................................................. 62 Read with Auto Precharge to Power-Down Entry ................................................................................................. 62 Write to Power-Down Entry ................................................................................................................................... 63 Write with Auto Precharge to Power-Down Entry ................................................................................................. 63 Refresh Command to Power-Down Entry ............................................................................................................. 64 Activate Command to Power-Down Entry ............................................................................................................. 64 Precharge/Precharge-All Command to Power-Down Entry .................................................................................. 64 Mode Register Read to Power-Down Entry .......................................................................................................... 65 MRW Command to Power-Down Entry ................................................................................................................ 65 Deep Power-Down ........................................................................................................................................................... 65 Deep Power Down Entry and Exit Timing ............................................................................................................. 66 Input Clock Stop and Frequency Change ........................................................................................................................ 66 No Operation Command .................................................................................................................................................. 67 Command Truth Table ..................................................................................................................................................... 68 CKE Truth Table .............................................................................................................................................................. 69 Current State Bank n - Command to Bank n Truth Table ................................................................................................ 70 Current State Bank n - Command to Bank m Truth Table ............................................................................................... 72 Data Mask Truth Table .................................................................................................................................................... 73 ELECTRICAL CHARACTERISTIC .............................................................................................................................. 74 Absolute Maximum DC Ratings ................................................................................................................................... 74 AC & DC Operating Conditions .................................................................................................................................... 74 8.2.1 8.2.1.1 8.2.2 8.2.3 8.2.4 8.2.4.1 8.2.4.1.1 8.2.4.1.2 8.2.4.1.3 8.2.4.2 8.2.4.2.1 8.2.4.3 8.2.4.3.1 8.2.4.4 8.2.4.4.1 8.2.4.4.2 8.2.4.5 8.2.4.6 8.2.4.7 8.2.4.8 8.2.5 8.2.5.1 8.2.5.2 8.2.5.3 Recommended DC Operating Conditions ....................................................................................................................... 74 Recommended DC Operating Conditions ............................................................................................................. 74 Input Leakage Current ..................................................................................................................................................... 75 Operating Temperature Conditions ................................................................................................................................. 75 AC and DC Input Measurement Levels ........................................................................................................................... 75 AC and DC Logic Input Levels for Single-Ended Signals ..................................................................................... 75 Single-Ended AC and DC Input Levels for CA and CS_n Inputs .......................................................................... 75 Single-Ended AC and DC Input Levels for CKE ................................................................................................... 76 Single-Ended AC and DC Input Levels for DQ and DM ........................................................................................ 76 Vref Tolerances ..................................................................................................................................................... 76 VRef(DC) Tolerance and VRef AC-Noise Limits................................................................................................... 77 Input Signal ........................................................................................................................................................... 78 LPDDR2-800/1066 Input Signal ............................................................................................................................ 78 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 79 Differential Signal Definition .................................................................................................................................. 79 Differential swing requirements for clock (CK_t - CK_c) and strobe (DQS_t - DQS_c) ........................................ 79 Single-Ended Requirements for Differential Signals ............................................................................................. 80 Differential Input Cross Point Voltage ................................................................................................................... 81 Slew Rate Definitions for Single-Ended Input Signals .......................................................................................... 82 Slew Rate Definitions for Differential Input Signals............................................................................................... 82 AC and DC Output Measurement Levels ........................................................................................................................ 83 Single Ended AC and DC Output Levels .............................................................................................................. 83 Differential AC and DC Output Levels .................................................................................................................. 83 Single Ended Output Slew Rate ........................................................................................................................... 83 Publication Release Date: Jan. 19, 2015 Revision: A01-002 -3- W979H6KB / W979H2KB 8.2.5.4 8.2.5.5 8.2.6 8.2.6.1 8.2.6.2 8.2.6.3 8.2.6.4 8.2.6.5 8.2.6.6 8.2.6.7 8.3 IDD Specification Parameters and Test Conditions ..................................................................................................... 93 8.3.1 8.3.2.1 IDD Measurement Conditions .......................................................................................................................................... 93 Definition of Switching for CA Input Signals .......................................................................................................... 93 Definition of Switching for IDD4R .......................................................................................................................... 94 Definition of Switching for IDD4W ......................................................................................................................... 94 IDD Specifications ........................................................................................................................................................... 95 LPDDR2 IDD Specification Parameters and Operating Conditions, 85°C (x16, x32) ........................................... 95 8.3.2.2 IDD6 Partial Array Self-Refresh Current, 85°C (x16, x32)..................................................................................... 97 8.3.1.1 8.3.1.2 8.3.1.3 8.3.2 8.4 Clock Specification ....................................................................................................................................................... 97 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.5 Definition for tCK(avg) and nCK ...................................................................................................................................... 97 Definition for tCK(abs) ..................................................................................................................................................... 97 Definition for tCH(avg) and tCL(avg) ............................................................................................................................... 98 Definition for tJIT(per) ...................................................................................................................................................... 98 Definition for tJIT(cc) ........................................................................................................................................................ 98 Definition for tERR(nper) ................................................................................................................................................. 98 Definition for Duty Cycle Jitter tJIT(duty) ......................................................................................................................... 99 Definition for tCK(abs), tCH(abs) and tCL(abs) ............................................................................................................... 99 Period Clock Jitter ........................................................................................................................................................ 99 8.5.1 8.5.1.1 8.5.1.2 8.5.2 8.5.3 8.5.3.1 8.5.3.2 8.5.3.3 8.5.3.4 8.5.4 8.5.4.1 8.5.4.2 8.5.4.3 8.6 Clock Period Jitter Effects on Core Timing Parameters .................................................................................................. 99 Cycle Time De-rating for Core Timing Parameters ............................................................................................... 99 Clock Cycle De-rating for Core Timing Parameters ............................................................................................ 100 Clock Jitter Effects on Command/Address Timing Parameters ..................................................................................... 100 Clock Jitter Effects on Read Timing Parameters ........................................................................................................... 100 tRPRE ................................................................................................................................................................. 100 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) ............................................................................................ 100 tQSH, tQSL ......................................................................................................................................................... 100 tRPST ................................................................................................................................................................. 101 Clock Jitter Effects on Write Timing Parameters ........................................................................................................... 101 tDS, tDH .............................................................................................................................................................. 101 tDSS, tDSH ......................................................................................................................................................... 101 tDQSS ................................................................................................................................................................. 101 Refresh Requirements ............................................................................................................................................... 102 8.6.1 8.7 Differential Output Slew Rate ................................................................................................................................ 85 Overshoot and Undershoot Specifications ............................................................................................................ 86 Output buffer Characteristics ........................................................................................................................................... 87 HSUL_12 Driver Output Timing Reference Load .................................................................................................. 87 RONPU and RONPD Resistor Definition.................................................................................................................. 87 RONPU and RONPD Characteristics with ZQ Calibration ....................................................................................... 88 Output Driver Temperature and Voltage Sensitivity .............................................................................................. 88 RONPU and RONPD Characteristics without ZQ Calibration .................................................................................. 89 RZQ I-V Curve ...................................................................................................................................................... 90 Input/Output Capacitance ..................................................................................................................................... 92 Refresh Requirement Parameters ................................................................................................................................. 102 AC Timings ................................................................................................................................................................ 103 8.7.1 8.7.2 8.7.2.1 8.7.2.2 8.7.2.3 8.7.2.4 8.7.2.5 8.7.2.6 8.7.2.7 8.7.3 8.7.3.1 LPDDR2 AC Timing ....................................................................................................................................................... 103 CA and CS_n Setup, Hold and Derating ....................................................................................................................... 108 CA and CS_n Setup and Hold Base-Values for 1V/nS ....................................................................................... 108 Derating Values LPDDR2 tIS/tIH - AC/DC Based AC220................................................................................... 109 Required Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition........................................................... 109 Nominal Slew Rate and tVAC for Setup Time tIS for CA and CS_n with Respect to Clock ............................... 110 Nominal Slew Rate for Hold Time tIH for CA and CS_n with Respect to Clock ................................................. 111 Tangent Line for Setup Time tIS for CA and CS_n with Respect to Clock ......................................................... 112 Tangent Line for Hold Time tIH for CA and CS_n with Respect to Clock ........................................................... 113 Data Setup, Hold and Slew Rate Derating .................................................................................................................... 114 Data Setup and Hold Base-Values ..................................................................................................................... 114 Publication Release Date: Jan. 19, 2015 Revision: A01-002 -4- W979H6KB / W979H2KB 8.7.3.2 8.7.3.3 8.7.3.4 8.7.3.5 8.7.3.6 8.7.3.7 Derating Values LPDDR2 tDS/tDH - AC/DC Based AC220 ............................................................................... 115 Required Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition........................................................... 115 Nominal Slew Rate and tVAC for Setup Time tDS for DQ with Respect to Strobe............................................. 116 Nominal Slew Rate for Hold time tDH for DQ with Respect to Strobe ................................................................ 117 Tangent Line for Setup Time tDS for DQ with Respect to Strobe ....................................................................... 118 Tangent Line for Hold Time tDH for DQ with Respect to Strobe ........................................................................ 119 9. PACKAGE DIMENSIONS .......................................................................................................................................... 120 10. REVISION HISTORY ................................................................................................................................................. 122 Publication Release Date: Jan. 19, 2015 Revision: A01-002 -5- W979H6KB / W979H2KB 1. GENERAL DESCRIPTION LPDDR2 is a high-speed SDRAM device internally configured as a 4-Bank memory. These devices contains 512Mb has 536,870,912 bits. All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock. For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access. 2. FEATURES  VDD1 = 1.7~1.95V  Deep Power Down Mode (DPD Mode)  VDD2/VDDCA/VDDQ = 1.14V~1.30V  Programmable output buffer driver strength  Data width: x16 / x32  Data mask (DM) for write data  Clock rate: up to 533 MHz  Clock Stop capability during idle periods  Data rate: up to 1066 Mb/s/pin  Double data rate for data output  Four-bit prefetch DDR architecture  Differential clock inputs  Four internal banks  Bidirectional differential data strobe  Programmable READ and WRITE latencies (RL/WL)  Interface: HSUL_12  Programmable burst lengths: 4, 8, or 16  JEDEC LPDDR2-S4B compliance  Auto refresh: All bank refresh mode only  Support package: Single channel: 134 VFBGA (10mm x11.5mm)  Partial Array Self-Refresh (PASR): Single channel: 168 WFBGA (12mm x12mm) All bank or per bank, bank mask is supported but segment mask is not supported  Operating Temperature Range:  Precharge command: All bank or per bank -25°C ≤ TCASE ≤ 85°C  Read with auto-prechage -40°C ≤ TCASE ≤ 85°C  Write with auto-prechage Publication Release Date: Jan. 19, 2015 Revision: A01-002 -6- W979H6KB / W979H2KB 3. ORDER INFORMATION Part Number VDD1/VDD2/VDDQ I/O Width Package Others W979H6KBQX2I 1.8V/1.2V/1.2V 16 168WFBGA 400MHz, -40°C~85°C W979H2KBQX2I 1.8V/1.2V/1.2V 32 168WFBGA 400MHz, -40°C~85°C W979H6KBQX1I 1.8V/1.2V/1.2V 16 168WFBGA 533MHz, -40°C~85°C W979H2KBQX1I 1.8V/1.2V/1.2V 32 168WFBGA 533MHz, -40°C~85°C W979H6KBQX2E 1.8V/1.2V/1.2V 16 168WFBGA 400MHz, -25°C~85°C W979H2KBQX2E 1.8V/1.2V/1.2V 32 168WFBGA 400MHz, -25°C~85°C W979H6KBQX1E 1.8V/1.2V/1.2V 16 168WFBGA 533MHz, -25°C~85°C W979H2KBQX1E 1.8V/1.2V/1.2V 32 168WFBGA 533MHz, -25°C~85°C W979H6KBVX2I 1.8V/1.2V/1.2V 16 134VFBGA 400MHz, -40°C~85°C W979H2KBVX2I 1.8V/1.2V/1.2V 32 134VFBGA 400MHz, -40°C~85°C W979H6KBVX1I 1.8V/1.2V/1.2V 16 134VFBGA 533MHz, -40°C~85°C W979H2KBVX1I 1.8V/1.2V/1.2V 32 134VFBGA 533MHz, -40°C~85°C W979H6KBVX2E 1.8V/1.2V/1.2V 16 134VFBGA 400MHz, -25°C~85°C W979H2KBVX2E 1.8V/1.2V/1.2V 32 134VFBGA 400MHz, -25°C~85°C W979H6KBVX1E 1.8V/1.2V/1.2V 16 134VFBGA 533MHz, -25°C~85°C W979H2KBVX1E 1.8V/1.2V/1.2V 32 134VFBGA 533MHz, -25°C~85°C Publication Release Date: Jan. 19, 2015 Revision: A01-002 -7- W979H6KB / W979H2KB 4. PIN CONFIGURATION 4.1 134 Ball VFBGA 1 2 3 9 10 A DNU DNU DNU DNU A B DNU NC NC VDD2 VDD1 DQ31 NC DQ29 NC DQ26 NC DNU B C VDD1 VSS NC VSS VSSQ VDDQ DQ25 NC VSSQ VDDQ C D VSS VDD2 ZQ0 VDDQ DQ30 NC DQ27 NC DQS3_t NC DQS3_c NC VSSQ D E VSSCA CA9 CA8 DQ28 NC DQ24 NC DM3 NC DQ15 VDDQ VSSQ E F VDDCA CA6 CA7 VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ F G VDD2 CA5 Vref (CA) DQS1_c DQS1_t DQ10 DQ9 DQ8 VSSQ G H VDDCA VSS CK_c DM1 VDDQ J VSSCA NC CK_t VSSQ VDDQ K CKE0 NC NC DM0 VDDQ L CS0_n NC NC DQS0_c DQS0_t DQ5 DQ6 DQ7 VSSQ L LPDDR2 DQ M CA4 CA3 CA2 VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ M LPDDR2 CA N VSSCA VDDCA CA1 DQ19 NC DQ23 NC DM2 NC DQ0 VDDQ VSSQ N Power P VSS VDD2 CA0 VDDQ DQ17 NC DQ20 NC DQS2_t NC DQS2_c NC VSSQ P Ground R VDD1 VSS NC VSS VSSQ VDDQ DQ22 NC VSSQ VDDQ R Do Not Use /NC T DNU NC NC VDD2 VDD1 DQ16 NC DQ18 NC DQ21 NC DNU T ZQ U DNU DNU DNU DNU U Clock 1 2 9 10 3 4 4 5 5 6 6 7 8 Ball Definition where 2 labe's are present 1st Row 2nd Row x32 device x16 device H VDD2 VSS J Vref (DQ) K 7 8 [Top View] Publication Release Date: Jan. 19, 2015 Revision: A01-002 -8- W979H6KB / W979H2KB 4.2 168 Ball WFBGA 168Ball WFBGA 1 2 3 4 A NC B NC C VSS D E 5 6 7 NC NC NC VDD1 8 9 NC NC NC NC VSS NC 10 11 12 NC NC NC VSS 13 14 15 NC NC VDD1 NC VSS VDD2 16 17 VSSQ DQ30 DQ29 DQ31 VDDQ DQ28 VSSQ DQ26 DQ25 DQ27 VDDQ DQ24 18 19 20 21 22 23 VSSQ DQS3_c VDD1 VSS NC NC DQS3_t VDDQ VDD2 NC NC VDD2 DQ15 VSSQ NC NC VDDQ DQ14 NC NC DQ12 DQ13 F NC VSS DQ11 VSSQ G NC NC VDDQ DQ10 H NC NC DQ8 DQ9 J NC VSS DQS1_t VSSQ K NC NC VDDQ DQS1_c DM3 L NC NC VDD2 DM1 M NC VSS Vref(DQ) VSS N NC VDD1 VDD1 DM0 P ZQ Vref(CA) R VSS VDD2 DQS0_c VSSQ VDDQ DQS0_t T CA9 CA8 DQ6 DQ7 U CA7 VDDCA DQ5 VSSQ V VSSCA CA6 VDDQ DQ4 W CA5 VDDCA DQ2 DQ3 Y CK_c CK_t DQ1 VSSQ AA VSS VDD2 VDDQ DQ0 AB NC NC CS_n NC VDD1 CA1 VSSCA CA3 CA4 VDD2 VSS DQ16 VDDQ DQ18 DQ20 VDDQ DQ22 DQS2_t VDDQ DM2 VDD2 NC NC AC NC NC CKE NC VSS CA0 CA2 VDDCA VSS NC NC VSSQ DQ17 DQ19 VSSQ DQ21 DQ23 VSSQ DQS2_c VDD1 VSS NC NC [Top View] Note: x16: DQ16~DQ31,DM2,DM3,DQS2_t,DQS2_c, DQS3_t & DQS3_c is NC. Publication Release Date: Jan. 19, 2015 Revision: A01-002 -9- W979H6KB / W979H2KB 5. PIN DESCRIPTION 5.1 Basic Functionality Name CK_t, CK_c Type Description Input Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK_t. Single Data Rate (SDR) inputs, CS_n and CKE, are sampled at the positive Clock edge. Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is defined by the crosspoint of a rising CK_t and a falling CK_c. The negative Clock edge is defined by the crosspoint of a falling CK_t and a rising CK_c. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input CKE Input CS_n Input CA[n:0] Input DQ[n:0] I/O buffers and output drivers. Power savings modes are entered and exited through CKE transitions. CKE is considered part of the command code. See 7.5.1 “Command Truth Table” for command code descriptions. CKE is sampled at the positive Clock edge. Chip Select: CS_n is considered part of the command code. See 7.5.1 “Command Truth Table” for command code descriptions. CS_n is sampled at the positive Clock edge. DDR Command/Address Inputs: Uni-directional command/address bus inputs. CA is considered part of the command code. See 7.5.1 “Command Truth Table” for command code descriptions. Data Inputs/Output: Bi-directional data bus. n=15 for 16 bits DQ; n=31 for 32 bits DQ. Data Strobe (Bi-directional, Differential): DQSn_t, DQSn_c I/O The data strobe is bi-directional (used for read and write data) and differential (DQS_t and DQS_c). It is output with read data and input with write data. DQS_t is edge-aligned to read data and centered with write data. For x16, DQS0_t and DQS0_c correspond to the data on DQ0-7; DQS1_t and DQS1_c to the data on DQ8-15. For x32 DQS0_t and DQS0_c correspond to the data on DQ0-7; DQS1_t and DQS1_c to the data on DQ8-15; DQS2_t and DQS2_c to the data on DQ16-23; DQS3_t and DQS3_c to the data on DQ24-31. Input Data Mask: DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS_t. Although DM is for input only, the DM loading shall match the DQ and DQS (or DQS_c). DM0 is the input data mask signal for the data on DQ0-7. For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15. For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data mask signal for the data on DQ24-31. DMn Input VDD1 Supply Core Power Supply 1: Power supply for core. VDD2 Supply Core Power Supply 2: Power supply for core. VDDCA Supply Input Receiver Power Supply: Power supply for CA[n:0], CKE, CS_n, CK_t, and CK_c input buffers. VDDQ Supply I/O Power Supply: Power supply for Data input/output buffers. VREF(CA) Supply Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all VREF(DQ) Supply Reference Voltage for DQ Input Receiver: Reference voltage for all Data input buffers. VSS Supply Ground VSSCA Supply Ground for CA Input Receivers VSSQ Supply I/O Ground ZQ I/O CA[n:0], CKE, CS_n, CK_t, and CK_c input buffers. Reference Pin for Output Drive Strength Calibration Note: Data includes DQ and DM. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 10 - W979H6KB / W979H2KB 5.2 Addressing Table Density 512Mb Number of Banks 4 Bank Addresses BA0-BA1 Row Addresses R0-R12 Column Addresses*1 C0-C9 Row Addresses R0-R12 Column Addresses*1 C0-C8 x16 x32 Notes: 1. The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero. 2. Row and Column Address values on the CA bus that are not used are “don’t care”. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 11 - W979H6KB / W979H2KB 6. BLOCK DIAGRAM CK_c CK_t CLOCK BUFFER CKE CONTROL SIGNAL COMMAND COLUMN DECODER GENERATOR R O W DECODER CA0 MODE REGISTER CA9 ADDRESS D E C O R D E R CELL ARRAY BANK #3 BANK #0 BUFFER SENSE AMPLIFIER Power GND ZQ REFRESH COUNTER COLUMN COUNTER DATA CONTROL CIRCUIT DQ BUFFER DQ , DQS_t , DQS_c DM Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 12 - W979H6KB / W979H2KB 7. FUNCTIONAL DESCRIPTION LPDDR2-S4 devices use a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR2-S4 effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal SDRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Prior to normal operation, the LPDDR2 device must be initialized. The following section provides detailed information covering device initialization, register definition, command description and device operation. 7.1 Simplified LPDDR2 State Diagram LPDDR2-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related commands to control them. For a complete definition of the device behavior, the information provided by the state diagram should be integrated with the truth tables and timing specification. The truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of all the banks. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 13 - W979H6KB / W979H2KB 7.1.1 Simplified LPDDR2 Bus Interface State Diagram Power Applied Resetting MR Reading DPDX Power On Reset Deep Power Down Automatic Sequence Command Sequence MRR Resetting DPD PD PDX Resetting Power Down Self Refreshing SREF SREFX Reset Idle MR Reading MRR REF Idle MRW PDX MR Writing Active Power Down ACT PD Idle Power Down MRR PDX Refreshing Active MR Reading PR,PRA PD Active*1 BST RD WR WR Writing RDA WRA PR(A)=Precharge (All) ACT=Activate WR(A)=Write(with Autoprecharge) RD(A)=Read (with Autoprecharge) BST=Burst Terminate Reset=Reset is achieved through MRW command MRW=Mode Register Write MRR=Mode Register Read PD=Enter Power Down PDX=Exit Power Down SREF=Enter Self Refresh SREFX=Exit Self Refresh DPD=Enter Deep Power Down DPDX=Exit Deep Power Down REF=Refresh RD Reading WRA Writing With Autoprecharge BST RDA PR,PRA Reading With Autoprecharge Precharging Note: For LPDDR2-SDRAM in the Idle state, all banks are precharged. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 14 - W979H6KB / W979H2KB 7.2 Power-up, Initialization, and Power-Off The LPDDR2 Devices must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. 7.2.1 Power Ramp and Device Initialization The following sequence shall be used to power up an LPDDR2 device. Unless specified otherwise, these steps are mandatory. 1. Power Ramp While applying power (after Ta), CKE shall be held at a logic low level (≤ 0.2 x VDDCA), all other inputs shall be between VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE is held low. On or before the completion of the power ramp (Tb) CKE must be held low. DQ, DM, DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latchup. CK_t, CK_c, CS_n, and CA input levels must be between VSSCA and VDDCA during voltage ramp to avoid latch-up. The following conditions apply: Ta is the point where any power supply first reaches 300mV. After Ta is reached, VDD1 must be greater than VDD2 - 200mV. After Ta is reached, VDD1 and VDD2 must be greater than VDDCA - 200mV. After Ta is reached, VDD1 and VDD2 must be greater than VDDQ - 200mV. After Ta is reached, VREF must always be less than all other supply voltages. The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100mV. The above conditions apply between Ta and power-off (controlled or uncontrolled). Tb is the point when all supply voltages are within their respective min/max operating conditions. Reference voltages shall be within their respective min/max operating conditions a minimum of 5 clocks before CKE goes high. For supply and reference voltage operating conditions, see 8.2.1.1 “Recommended DC Operating Conditions” table. Power ramp duration tINIT0 (Tb - Ta) must be no greater than 20 mS. 2. CKE and clock Beginning at Tb, CKE must remain low for at least tINIT1 = 100 nS, after which it may be asserted high. Clock must be stable at least tINIT2 = 5 x tCK prior to the first low to high transition of CKE (Tc). CKE, CS_n and CA inputs must observe setup and hold time (tIS, tIH) requirements with respect to the first rising clock edge (as well as to the subsequent falling and rising edges). The clock period shall be within the range defined for tCKb (18 nS to 100 nS), if any Mode Register Reads are performed. Mode Register Writes can be sent at normal clock operating frequencies so long as all AC Timings are met. Furthermore, some AC parameters (e.g. tDQSCK) may have relaxed timings (e.g. tDQSCKb) before the system is appropriately configured. While keeping CKE high, issue NOP commands for at least tINIT3 = 200 µS. (Td). Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 15 - W979H6KB / W979H2KB 3. Reset command After tINIT3 is satisfied, a MRW(Reset) command shall be issued (Td). The memory controller may optionally issue a Precharge-All command prior to the MRW Reset command. Wait for at least tINIT4 = 1 µS while keeping CKE asserted and issuing NOP commands. 4. Mode Registers Reads and Device Auto-Initialization (DAI) polling: After tINIT4 is satisfied (Te) only MRR commands and power-down entry/exit commands are allowed. Therefore, after Te, CKE may go low in accordance to Power-Down entry and exit specification (see section 7.4.24 “Power-Down”). The MRR command may be used to poll the DAI-bit to acknowledge when Device Auto-Initialization is complete or the memory controller shall wait a minimum of tINIT5 before proceeding. As the memory output buffers are not properly configured yet, some AC parameters may have relaxed timings before the system is appropriately configured. After the DAI-bit (MR#0, “DAI”) is set to zero “DAI complete” by the memory device, the device is in idle state (Tf). The state of the DAI status bit can be determined by an MRR command to MR#0. The LPDDR2 SDRAM device will set the DAI-bit no later than tINIT5 (10 µS) after the Reset command. The memory controller shall wait a minimum of tINIT5 or until the DAI-bit is set before proceeding. After the DAI-Bit is set, it is recommended to determine the device type and other device characteristics by issuing MRR commands (MR0 “Device Information” etc.). 5. ZQ Calibration: After tINIT5 (Tf), an MRW ZQ Initialization Calibration command may be issued to the memory (MR10). This command is used to calibrate the LPDDR2 output drivers (RON) over process, voltage, and temperature. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. In systems in which more than one LPDDR2 device exists on the same bus, the controller must not overlap ZQ Calibration commands. The device is ready for normal operation after tZQINIT. 6. Normal Operation: After tZQINIT (Tg), MRW commands may be used to properly configure the memory, for example the output buffer driver strength, latencies etc. Specifically, MR1, MR2, and MR3 shall be set to configure the memory for the target frequency and memory configuration. The LPDDR2 device will now be in IDLE state and ready for any valid command. After Tg, the clock frequency may be changed according to the clock frequency change procedure described in section 7.4.26 “Input Clock Stop and Frequency Change”. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 16 - W979H6KB / W979H2KB 7.2.2 Timing Parameters for Initialization Symbol Value min max tINIT0 20 Unit Comment mS Maximum Power Ramp Time tINIT1 100 nS Minimum CKE low time after completion of power ramp tINIT2 5 tCK Minimum stable clock before first CKE high tINIT3 200 µS Minimum Idle time after first CKE assertion tINIT4 1 µS Minimum Idle time after Reset command µS Maximum duration of Device Auto-Initialization µS ZQ Initial Calibration for LPDDR2-S4 nS Clock cycle time during boot tINIT5 10 tZQINIT 1 tCKb 18 7.2.3 100 Power Ramp and Initialization Sequence Ta Tb Td Tc Te Tf Tg tINIT2 = 5 tCK (min) CK_t / CK_c tINIT0 = 20 ms (max) Supplies tINIT3 = 200 μs (min) tINIT1 = 100 ns (min) CKE PD tINIT5 tISCKE tZQINIT tINIT4 = 1 μs (min) CA* RESET MRR ZQC Valid DQ *Midlevel on CA bus means : valid NOP Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 17 - W979H6KB / W979H2KB 7.2.4 Initialization after Reset (without Power ramp) If the RESET command is issued outside the power up initialization sequence, the reinitialization procedure shall begin with step 3 (Td). 7.2.5 Power-off Sequence The following sequence shall be used to power off the LPDDR2 device. While removing power, CKE shall be held at a logic low level (≤ 0.2 x VDDCA), all other inputs shall be between VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE is held low. DQ, DM, DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ during power off sequence to avoid latch-up. CK_t, CK_c, CS_n and CA input levels must be between VSSCA and VDDCA during power off sequence to avoid latch-up. Tx is the point where any power supply decreases under its minimum value specified in 8.2.1.1 “Recommended DC Operating Conditions” table. Tz is the point where all power supplies are below 300 mV. After Tz, the device is powered off. The time between Tx and Tz (tPOFF) shall be less than 2s. The following conditions apply: Between Tx and Tz, VDD1 must be greater than VDD2 - 200 mV. Between Tx and Tz, VDD1 and VDD2 must be greater than VDDCA - 200 mV. Between Tx and Tz, VDD1 and VDD2 must be greater than VDDQ - 200 mV. Between Tx and Tz, VREF must always be less than all other supply voltages. The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100 mV. For supply and reference voltage operating conditions, see 8.2.1.1 “Recommended DC Operating Conditions” table. 7.2.6 Timing Parameters Power-Off Symbol tPOFF Value min max - 2 Unit s Comment Maximum Power-Off Ramp Time 7.2.7 Uncontrolled Power-Off Sequence The following sequence shall be used to power off the LPDDR2 device under uncontrolled condition. Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition table. After turning off all power supplies, any power supply current capacity must be zero, except for any static charge remaining in the system. Tz is the point where all power supply first reaches 300 mV. After Tz, the device is powered off. The time between Tx and Tz (tPOFF) shall be less than 2s. The relative levels between supply voltages are uncontrolled during this period. VDD1 and VDD2 shall decrease with a slope lower than 0.5 V/µS between Tx and Tz. Uncontrolled power off sequence can be applied only up to 400 times in the life of the device. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 18 - W979H6KB / W979H2KB 7.3 Mode Register Definition 7.3.1 Mode Register Assignment and Definition Each register is denoted as “R” if it can be read but not written, “W” if it can be written but not read, and “R/W” if it can be read and written. Mode Register Read command shall be used to read a register. Mode Register Write command shall be used to write a register. 7.3.1.1 Mode Register Assignment MR# MA[7:0] Function Access 0 00H 01H Device Info. R (RFU) Device Feature 1 W nWR (for AP) Device Feature 2 W (RFU) RL & WL I/O Config-1 W (RFU) DS 1 2 3 4 5 6 7 8 9 10 11-15 16 17 18-19 20-31 32 33-39 40 41-47 48-62 63 64-126 02H 03H 04H 05H OP6 OP5 OP4 OP3 RZQI TUF WC OP2 OP1 OP0 DNVI DI DAI BT (RFU) BL Refresh Rate R Basic Config-1 R LPDDR2 Manufacturer ID 06H 07H Basic Config-2 R Revision ID1 Basic Config-3 R Revision ID2 08H 09H Basic Config-4 R Test Mode W Vendor-Specific Test Mode 0AH 0BH~0FH I/O Calibration W Calibration Code (reserved) - (RFU) 10H 11H PASR_Bank W Bank Mask (Reserved) W (RFU) 12H~13H 14h–1Fh (Reserved) - (RFU) 20H 21H~27H DQ Calibration Pattern A R 28H 29H~2FH DQ Calibration Pattern B R (Do Not Use) - 30H~3EH 3FH 40H~7EH (Reserved) - I/O width Refresh Rate Density Type Reserved for NVM (Do Not Use) See 7.4.20.2 “DQ Calibration” See 7.4.20.2 “DQ Calibration” (RFU) Reset W X (Reserved) - (RFU) 127 7FH (Do Not Use) - 128-190 (Reserved for Vendor Use) - (Do Not Use) - 192-254 80H~BEH BFH C0H~FEH (Reserved for Vendor Use) - 255 FFH (Do Not Use) - 191 OP7 (RFU) (RFU) Notes: 1. RFU bits shall be set to ‘0’ during Mode Register writes. 2. RFU bits shall be read as ‘0’ during Mode Register reads. 3. All Mode Registers that are specified as RFU or write-only shall return undefined data when read and DQS shall be toggled. 4. All Mode Registers that are specified as RFU shall not be written. 5. Writes to read-only registers shall have no impact on the functionality of the device. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 19 - W979H6KB / W979H2KB 7.3.2 MR0_Device Information (MA[7:0] = 00H) OP7 OP6 OP5 OP4 (RFU) OP3 OP2 RZQI DNVI OP1 OP0 DI DAI DAI (Device Auto-Initialization Status) Read-only OP0 0b: DAI complete 1b: DAI still in progress DI (Device Information) Read-only OP1 0b: S4 SDRAM DNVI (Data Not Valid Information) Read-only OP2 0b: LPDDR2 SDRAM will not implement DNV functionalit OP[4:3] 00b: RZQ self test not executed. 01b: ZQ-pin may connect to VDDCA or float 10b: ZQ-pin may short to GND 11b: ZQ-pin self test completed, no error condition detected (ZQ-pin may not connect to VDDCA or float nor short to GND) RZQI (Built in Self Test for RZQ Information) Read-only Notes: 1. RZQI will be set upon completion of the MRW ZQ Initialization Calibration command. 2. If ZQ is connected to VDDCA to set default calibration by user, OP[4:3] shall be read as 01. If user does not want to connect ZQ pin to VDDCA, but OP[4:3] is read as 01 or 10, it might indicate a ZQ-pin assembly error. It is recommended that the assembly error being corrected first. 3. In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 as defined above), the LPDDR2 device will default to factory trim settings for RON, and will ignore ZQ calibration commands. In either case, the system may not function as intended. 4. In the case of the ZQ self-test returning a value of 11b, this result indicates that the device has detected a resistor connection to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits (i.e., 240 Ohm ± 1%). 7.3.3 MR1_Device Feature 1 (MA[7:0] = 01H) OP7 OP6 OP5 nWR (for AP) BL Write-only OP[2:0] BT Write-only OP3 WC Write-only OP4 OP4 OP3 WC BT OP2 OP1 OP0 BL 010b: BL4 (default) 011b: BL8 100b: BL16 All others: reserved 0b: Sequential (default) 1b: Interleaved 0b: Wrap (default) 1 b: No wrap (allowed for SDRAM BL4 only) 001b: nWR=3 (default) 010b: nWR=4 nWR Write-only OP[7:5] 011b: nWR=5 100b: nWR=6 1 101b: nWR=7 110b: nWR=8 All others: reserved Note: 1. Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge operation for a write burst with AP enabled. It is determined by RU(tWR/tCK). Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 20 - W979H6KB / W979H2KB 7.3.3.1 Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC) Burst Cycle Number and Burst Address Sequence C3 C2 C1 C0 WC BT BL 1 2 3 4 0 1 2 3 3 0 1 5 6 7 8 9 10 11 12 13 14 15 16 X 0b 0b X X 1b 0b X X X 0b X 0b 0b 0b X 0b 1b 0b X 1b 0b 0b X 1b 1b 0b X 0b 0b 0b X 0b 1b 0b X 1b 0b 0b X 1b 1b 0b X X X 0b 0b 0b 0b 0b 0 1 2 3 4 5 6 7 8 9 A B C D E F 0b 0b 1b 0b 2 3 4 5 6 7 8 9 A B C D E F 0 1 0b 1b 0b 0b 4 5 6 7 8 9 A B C D E F 0 1 2 3 0b 1b 1b 0b 6 7 8 9 A B C D E F 0 1 2 3 4 5 1b 0b 0b 0b 1b 0b 1b 0b 1b 1b 0b 1b 1b X X X wrap any nw any 4 2 y y+1 y+2 y+3 0 1 2 3 4 5 6 7 2 3 4 5 6 7 0 1 4 5 6 7 0 1 2 3 6 7 0 1 2 3 4 5 0 1 2 3 4 5 6 7 2 3 0 1 6 7 4 5 4 5 6 7 0 1 2 3 6 7 4 5 2 3 0 1 seq wrap 8 int nw any illegal (not allowed) seq wrap 8 9 A B C D E F 0 1 2 3 4 5 6 7 A B C D E F 0 1 2 3 4 5 6 7 8 9 0b C D E F 0 1 2 3 4 5 6 7 8 9 A B 1b 0b E F 0 1 2 3 4 5 6 7 8 9 A B C D X X 0b X X 0b 16 nw int illegal (not allowed) any illegal (not allowed) Notes: 1. C0 input is not present on CA bus. It is implied zero. 2. For BL=4, the burst address represents C[1: 0]. 3. For BL=8, the burst address represents C[2:0]. 4. For BL=16, the burst address represents C[3:0]. 5. For no-wrap (nw), BL4, the burst shall not cross the page boundary and shall not cross sub-page boundary. The variable y may start at any address with C0 equal to 0 and may not start at any address shown in table below. 7.3.3.2 Non Wrap Restrictions Bus Width 512Mb Not across full page boundary x16 3FE, 3FF, 000, 001 x32 1FE, 1FF, 000, 001 Not across sub page boundary x16 1FE, 1FF, 200, 201 x32 None Note: Non-wrap BL=4 data-orders shown above are prohibited. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 21 - W979H6KB / W979H2KB 7.3.4 MR2_Device Feature 2 (MA[7:0] = 02H) OP7 OP6 OP5 OP4 OP3 OP2 (RFU) RL & WL 7.3.5 OP0 RL & WL Write-only 0001b: RL = 3 / WL = 1 (default) 0010b: RL = 4 / WL = 2 0011b: RL = 5 / WL = 2 0100b: RL = 6 / WL = 3 0101b: RL = 7 / WL = 4 0110b: RL = 8 / WL = 4 All others: reserved OP[3:0] MR3_I/O Configuration 1 (MA[7:0] = 03H) OP7 OP6 OP5 OP4 OP3 OP2 (RFU) DS 7.3.6 OP1 OP1 OP0 DS Write-only 0000b: reserved 0001b: 34.3-ohm typical 0010b: 40-ohm typical (default) 0011b: 48-ohm typical 0100b: 60-ohm typical 0101b: reserved 0110b: 80-ohm typical 0111b: 120-ohm typical All others: reserved OP[3:0] MR4_Device Temperature (MA[7:0] = 04H) OP7 OP6 OP5 TUF OP4 OP3 (RFU) SDRAM Refresh Rate Read-only OP[2:0] Temperature Update Flag (TUF) Read-only OP7 OP2 OP1 OP0 SDRAM Refresh Rate 000b: SDRAM Low temperature operating limit exceeded 001b: 4x tREFI, 4x tREFW 010b: 2x tREFI, 2x tREFW 011b: 1x tREFI, 1x tREFW (≤ 85°C) 100b: Reserved 101b: 0.25x tREFI, 0.25x tREFW, do not de-rate SDRAM AC timing 110b: 0.25x tREFI, 0.25x tREFW, de-rate SDRAM AC timing 111b: SDRAM High temperature operating limit exceeded 0b: OP[2:0] value has not changed since last read of MR4. 1b: OP[2:0] value has changed since last read of MR4. Notes: 1. A Mode Register Read from MR4 will reset OP7 to ‘0’. 2. OP7 is reset to ‘0’ at power-up. 3. If OP2 equals ‘1’, the device temperature is greater than 85°C. 4. OP7 is set to ‘1’ if OP2:OP0 has changed at any time since the last read of MR4. 5. LPDDR2 might not operate properly when OP[2:0] = 000b or 111b. 6. For specified operating temperature range and maximum operating temperature, refer to “Operating Temperature Conditions” table. 7. LPDDR2 devices must be derated by adding 1.875 nS to the following core timing parameters: tRCD, tRC, tRAS, tRP, and tRRD. tDQSCK shall be de-rated according to the tDQSCK de-rating value in “LPDDR2 AC Timing” table. Prevailing clock frequency spec and related setup and hold timings shall remain unchanged. 8. The recommended frequency for reading MR4 is provided in “Temperature Sensor” section. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 22 - W979H6KB / W979H2KB 7.3.7 MR5_Basic Configuration 1 (MA[7:0] = 05H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 LPDDR2 Manufacturer ID LPDDR2 Manufacturer ID 7.3.8 Read-only OP[7:0] 0000 1000b: Winbond MR6_Basic Configuration 2 (MA[7:0] = 06H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Revision ID1 Revision ID1 Read-only OP[7:0] 00000000b: A-version Note: MR6 is Vendor Specific. 7.3.9 MR7_Basic Configuration 3 (MA[7:0] = 07H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Revision ID2 Revision ID2 Read-only OP[7:0] 00000000b: A-version Note: MR7 is Vendor Specific. 7.3.10 MR8_Basic Configuration 4 (MA[7:0] = 08H) OP7 OP6 OP5 OP4 I/O width OP3 OP2 OP1 Density OP0 Type Type Read-only OP[1:0] 00b: S4 SDRAM Density Read-only OP[5:2] 0011b: 512Mb I/O width Read-only OP[7:6] 00b: x32 01b: x16 7.3.11 MR9_Test Mode (MA[7:0] = 09H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Vendor-specific Test Mode Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 23 - W979H6KB / W979H2KB 7.3.12 MR10_Calibration (MA[7:0] = 0AH) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Calibration Code Write-only Calibration Code OP[7:0] 0xFF: Calibration command after initialization 0xAB: Long calibration 0x56: Short calibration 0xC3: ZQ Reset others: Reserved Notes: 1. Host processor shall not write MR10 with “Reserved” values. 2. LPDDR2 devices shall ignore calibration command when a “Reserved” value is written into MR10. 3. See AC timing table for the calibration latency. 4. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see section 7.4.23 “Mode Register Write ZQ Calibration Command”) or default calibration (through the ZQreset command) is supported. If ZQ is connected to VDDCA, the device operates with default calibration, and ZQ calibration commands are ignored. In both cases, the ZQ connection shall not change after power is applied to the device. 5. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. 7.3.13 MR16_PASR_Bank Mask (MA[7:0] = 10H) OP7 S4 SDRAM OP6 OP5 OP4 Reserved OP3 OP2 OP1 OP0 Bank Mask Bank [3:0] Mask Write-only OP[3:0] 0b: self-refresh enable to the bank (=unmasked, default) 1b: self-refresh blocked (=masked) OP0: bank 0 OP1: bank 1 OP2: bank 2 OP3: bank 3 Reserved Write-only OP[7:4] Reserved. Any value written to OP[7:4] are ignored by LPDDR2. Note: The MR16 is used to control which bank or banks are to be masked or unmasked in self-refresh mode. It has no effect in autorefresh mode because LPDDR2 512Mb device does not support per-bank refresh in auto-refresh mode. OP Bank Mask 4-Bank S4 SDRAM 0 XXXXXXX1 Bank 0 1 XXXXXX1X Bank 1 2 XXXXX1XX Bank 2 3 XXXX1XXX Bank 3 4 - - 5 - - 6 - - 7 - - Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 24 - W979H6KB / W979H2KB 7.3.14 MR32_DQ Calibration Pattern A (MA[7:0] = 20H) Reads to MR32 return DQ Calibration Pattern “A”. See section 7.4.20.2 “DQ Calibration”. 7.3.15 MR40_DQ Calibration Pattern B (MA[7:0] = 28H) Reads to MR40 return DQ Calibration Pattern “B”. See section 7.4.20.2 “DQ Calibration”. 7.3.16 MR63_Reset (MA[7:0] = 3FH): MRW only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 X For additonal information on MRW RESET see section 7.4.21 “Mode Register Write Command”. 7.4 Command Definitions and Timing Diagrams 7.4.1 Activate Command The SDRAM Activate command is issued by holding CS_n LOW, CA0 LOW, and CA1 HIGH at the rising edge of the clock. The bank addresses are used to select the desired bank. The row addresses are used to determine which row to activate in the selected bank. The Activate command must be applied before any Read or Write operation can be executed. The LPDDR2 SDRAM can accept a read or write command at time tRCD after the activate command is sent. Once a bank has been activated it must be precharged before another Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between Activate commands to different banks is tRRD. 7.4.1.1 Activate Command Cycle: tRCD = 3, tRP = 3, tRRD = 2 T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 CK_t / CK_c CA0-9 Bank A Row Addr Row Addr Bank B Bank A Row Addr Row Addr Col Addr Col Addr RAS-CAS delay=tRCD Bank A Read Begins RAS-RAS delay time=tRRD [Cmd] Activate Nop Activate Bank A Row Addr Row Addr Bank Precharge time=tRP Read Precharge Nop Nop Activate Bank Active=tRAS Row Cycle time=tRC Note: A Precharge-All command uses tRPab timing, while a Single Bank Precharge command uses tRPpb timing. In this figure, tRP is used to denote either an All-bank Precharge or a Single Bank Precharge Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 25 - W979H6KB / W979H2KB 7.4.1.2 Command Input Setup and Hold Timing T0 T1 T2 T3 CK_t / CK_c tIS CS_n tIH tIH VIH(AC) VIL(DC) VIL(AC) tIS CA0-9 tIS VIH(DC) tIH tIS tIH CA CA CA CA CA CA CA CA Rise Fall Rise Fall Rise Fall Rise Fall Nop [Cmd] Nop Command Command HIGH or LOW (but a defined logic level) Note: Setup and hold conditions also apply to the CKE pin. See section related to power down for timing diagrams related to the CKE pin. 7.4.1.3 CKE Input Setup and Hold Timing T0 T1 Tx Tx+1 CK_t / CK_c tIHCKE tIHCKE CKE VIHCKE VILCKE VIHCKE VILCKE tISCKE tISCKE HIGH or LOW (but a defined logic level) Notes: 1. After CKE is registered LOW, CKE signal level shall be maintained below VILCKE for tCKE specification (LOW pulse width). 2. After CKE is registered HIGH, CKE signal level shall be maintained above VIHCKE for tCKE specification (HIGH pulse width). Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 26 - W979H6KB / W979H2KB 7.4.2 Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting CS_n LOW, CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine whether the access cycle is a READ operation (CA2 HIGH) or a WRITE operation (CA2 LOW). The LPDDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a burst read or write operation on successive clock cycles. A new burst access must not interrupt the previous 4-bit burst operation in case of BL = 4 setting. In case of BL = 8 and BL = 16 settings, Reads may be interrupted by Reads and Writes may be interrupted by Writes provided that this occurs on even clock cycles after the Read or Write command and tCCD is met. 7.4.3 Burst Read Command The Burst Read command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 HIGH at the rising edge of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for the burst. The Read Latency (RL) is defined from the rising edge of the clock on which the Read Command is issued to the rising edge of the clock from which the tDQSCK delay is measured. The first valid datum is available RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Read Command is issued. The data strobe output is driven LOW tRPRE before the first rising valid strobe edge. The first bit of the burst is synchronized with the first rising edge of the data strobe. Each subsequent data-out appears on each DQ pin edge aligned with the data strobe. The RL is programmed in the mode registers. Timings for the data strobe are measured relative to the crosspoint of DQS_t and its complement, DQS_c. 7.4.3.1 Data Output (Read) Timing (tDQSCKmax) RL-1 RL tCH RL+BL/2 tCL CK_c CK_t tLZ(DQS) tDQSCKmax tQSH DQS_c DQS_c DQS_t tQSL tHZ(DQs) DQS_t tRPRE tRPST DQ Q tDQSQmax Q Q Q tDQSQmax tQH tLZ(DQ) tQH tHZ(DQ) Notes: 1. tDQSCK may span multiple clock periods. 2. An effective Burst Length of 4 is shown. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 27 - W979H6KB / W979H2KB 7.4.3.2 Data Output (Read) Timing (tDQSCKmin) RL-1 RL tCH RL+BL/2 tCL CK_c CK_t tHZ(DQs) tLZ(DQS) tDQSCKmin tQSH DQS_c DQS_c DQS_t tQSL DQS_t tRPST tRPRE DQ Q tDQSQmax tLZ(DQ) Q Q Q tDQSQmax tQH tQH tHZ(DQ) Note: An effective Burst Length of 4 is shown. 7.4.3.3 Burst Read: RL = 5, BL = 4, tDQSCK > tCK T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank A Col Addr Col Addr [Cmd] Read Nop Nop Nop Nop Nop Nop Nop Nop tDQSCK DQS_c DQS_t RL = 5 DQS DOUT A0 DOUT A1 DOUT A2 DOUT A3 Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 28 - W979H6KB / W979H2KB 7.4.3.4 Burst Read: RL = 3, BL = 8, tDQSCK < tCK T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Col Addr Read Nop Nop Nop Nop Nop Nop Nop Nop tDQSCK DQS_c DQS_t RL = 3 DQS 7.4.3.5 DOUT A0 DOUT A2 DOUT A1 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 LPDDR2: tDQSCKDL Timing Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 CA0-9 Col Col Addr Addr Col Col Addr Addr [Cmd] Read Nop CK_t / CK_c Nop Nop Nop Nop Nop Nop Nop Read Nop Nop tDQSCKn DQS_c DQS_t DQS Nop Nop Nop Nop Nop Nop tDQSCKm RL = 5 RL = 5 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 32mS maximum tDQSCKDL = l tDQSCKn – tDQSCKm l Note: tDQSCKDLmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn ,tDQSCKm} pair within any 32mS rolling window. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 29 - W979H6KB / W979H2KB 7.4.3.6 LPDDR2: tDQSCKDM Timing Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 CA0-9 Col Col Addr Addr Col Col Addr Addr [Cmd] Read Nop Nop Nop Nop Nop Nop Nop Nop Read Nop Nop Nop Nop Nop Nop Nop Nop tDQSCKn tDQSCKm CK_t / CK_c DQS_c DQS_t RL = 5 RL = 5 DQS DOUT DOUT DOUT DOUT A0 A1 A2 A3 DOUT DOUT DOUT DOUT A1 A2 A3 A0 1.6µS maximum tDQSCKDM = l tDQSCKn – tDQSCKm l Note: tDQSCKDMmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn,tDQSCKm} pair within any 1.6µS rolling window. 7.4.3.7 LPDDR2: tDQSCKDS Timing Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 CK_t / CK_c CA0-9 [Cmd] Col Col Addr Addr Col Col Addr Addr Read Nop Nop Nop Nop Nop Nop Nop Nop Read Nop Nop tDQSCKn DQS_c DQS_t DQS Nop Nop Nop Nop Nop Nop tDQSCKm RL = 5 RL = 5 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 160nS maximum tDQSCKDS = l tDQSCKn – tDQSCKm l Note: tDQSCKDSmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn ,tDQSCKm} pair for reads within a consecutive burst within any 160nS rolling window Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 30 - W979H6KB / W979H2KB 7.4.3.8 Burst Read Followed by Burst Write: RL = 3, WL = 1, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank A Col Addr [Cmd] Bank A Col Addr Col Addr Read Nop Nop Nop Nop Nop tDQSCK Col Addr Write Nop Nop tDQSSmin BL / 2 DQS_c DQS_t RL = 3 DQS WL=1 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DIN A0 DIN A1 DIN A2 The minimum time from the burst read command to the burst write command is defined by the Read Latency (RL) and the Burst Length (BL). Minimum read to write latency is RL + RU(tDQSCKmax/tCK) + BL/2 + 1 - WL clock cycles. Note that if a read burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated read burst should be used as “BL” to calculate the minimum read to write delay. 7.4.3.9 Seamless Burst Read: RL = 3, BL= 4, tCCD = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank N Col Addr A Col Addr A Read Bank N Col Addr B Col Addr B Nop Read Nop Nop Nop Nop Nop Nop tCCD = 2 DQS_c DQS_t RL = 3 DQS DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, every 4 clocks for BL = 8 operation, and every 8 clocks for BL=16 operation. For LPDDR2-SDRAM, this operation is allowed regardless of whether the accesses read the same or different banks as long as the banks are activated. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 31 - W979H6KB / W979H2KB 7.4.4 Reads Interrupted by a Read For LPDDR2-S4 device, burst read can be interrupted by another read on even clock cycles after the Read command, provided that tCCD is met. 7.4.4.1 Read Burst Interrupt Example: RL = 3, BL= 8, tCCD = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank N Col Addr A Col Addr A [Cmd] Read Bank N Col Addr B Col Addr B Nop Read Nop Nop Nop Nop Nop Nop tCCD=2 DQS_c DQS_t RL = 3 DQS DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B4 DOUT B5 Notes: 1. For LPDDR2-S4 devices, read burst interrupt function is only allowed on burst of 8 and burst of 16. 2. For LPDDR2-S4 devices, read burst interrupt may occur on any clock cycle after the intial read command, provided that tCCD is met. 3. Reads can only be interrupted by other reads or the BST command. 4. Read burst interruption is allowed to any bank inside DRAM. 5. Read burst with Auto-Precharge is not allowed to be interrupted. 6. The effective burst length of the first read equals two times the number of clock cycles between the first read and the interrupting read. 7.4.5 Burst Write Operation The Burst Write command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 LOW at the rising edge of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for the burst. The Write Latency (WL) is defined from the rising edge of the clock on which the Write Command is issued to the rising edge of the clock from which the tDQSS delay is measured. The first valid data must be driven WL * tCK + tDQSS from the rising edge of the clock from which the Write command is issued. The data strobe signal (DQS) should be driven LOW tWPRE prior to the data input. The data bits of the burst cycle must be applied to the DQ pins tDS prior to the respective edge of the DQS_t, DQS_c and held valid until tDH after that edge. The burst data are sampled on successive edges of the DQS_t, DQS_c until the burst length is completed, which is 4, 8, or 16 bit burst. For LPDDR2-SDRAM devices, tWR must be satisfied before a precharge command to the same bank may be issued after a burst write operation. Input timings are measured relative to the crosspoint of DQS_t and its complement, DQS_c. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 32 - W979H6KB / W979H2KB 7.4.5.1 Data Input (Write) Timing tDQSH tDQSL DQS_c DQS_c DQS_t DQS_t tWPST tWPRE VIH(ac) DQ VIH(dc) D D D D VIL(ac) VIL(dc) tDS tDH tDH tDS VIH(ac) DM VIH(dc) DMin DMin DMin DMin VIL(dc) VIL(ac) 7.4.5.2 Burst Write: WL = 1, BL= 4 T0 T1 T3 T2 T4 Tx Tx+1 Ty Ty+1 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Write Case 1:with tDQSS(max) DQS_c DQS_t Bank A Row Addr Row Addr Bank A Col Addr Nop Nop Nop tDSS tDSS tDQSSmax Precharge Nop Nop Activate Nop Completion of Burst Write WL = 1 tWR DQS DIN A0 DIN A1 DIN A2 DIN A3 tRP Case 2:with tDQSS(min) tDQSSmin DQS_c DQS_t DQS tDSH tDSH WL = 1 tWR DIN A0 DIN A1 DIN A2 DIN A3 Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 33 - W979H6KB / W979H2KB 7.4.5.3 Burst Wirte Followed by Burst Read: RL = 3, WL= 1, BL= 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Write Bank N Col Addr B Col Addr B Nop Nop Nop Nop Nop Read Nop Nop RL = 3 WL = 1 DQS_c DQS_t tWTR DQS DIN A0 DIN A1 DIN A2 DIN A3 Notes: 1. The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 + BL/2 + RU( tWTR/tCK)]. 2. tWTR starts at the rising edge of the clock after the last valid input datum. 3. If a write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated write burst should be used as “BL” to calculate the minimum write to read delay. 7.4.5.4 Seamless Burst Write: WL= 1, BL = 4, tCCD = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Write Bank N Col Addr B Col Addr B Nop Nop Nop Write Nop Nop Nop Nop tCCD = 2 DQS_c DQS_t WL=1 DQS DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 Note: The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four clocks for BL = 8 operation, or every eight clocks for BL = 16 operation. This operation is allowed regardless of same or different banks as long as the banks are activated Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 34 - W979H6KB / W979H2KB 7.4.6 Writes Interrupted by a Write For LPDDR2-S4 devices, burst writes can only be interrupted by another write on even clock cycles after the write command, provided that tCCD(min) is met. 7.4.6.1 Write Burst Interrupt Timing: WL = 1, BL = 8, tCCD = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Write Bank N Col Addr B Col Addr B Nop Nop Nop Write Nop Nop Nop Nop tCCD = 2 DQS_c DQS_t WL=1 DQS DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN B6 DIN B7 Notes: 1. For LPDDR2-S4 devices, write burst interrupt function is only allowed on burst of 8 and burst of 16. 2. For LPDDR2-S4 devices, write burst interrupt may only occur on even clock cycles after the previous write commands, provided that tCCD(min) is met. 3. Writes can only be interrupted by other writes or the BST command. 4. Write burst interruption is allowed to any bank inside DRAM. 5. Write burst with Auto-Precharge is not allowed to be interrupted. 6. The effective burst length of the first write equals two times the number of clock cycles between the first write and the interrupting write. 7.4.7 Burst Terminate The Burst Terminate (BST) command is initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 LOW at the rising edge of clock. A Burst Teminate command may only be issued to terminate an active Read or Write burst. Therefore, a Burst Terminate command may only be issued up to and including BL/2 - 1 clock cycles after a Read or Write command. The effective burst length of a Read or Write command truncated by a BST command is as follows: Effective burst length = 2 x {Number of clock cycles from the Read or Write Command to the BST command} Note that if a read or write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated burst should be used as “BL” to calculate the minimum read to write or write to read delay. The BST command only affects the most recent read or write command. The BST command truncates an ongoing read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Burst Terminate command is issued. The BST command truncates an on going write burst WL * tCK + tDQSS after the rising edge of the clock where the Burst Terminate command is issued. For LPDDR2-S4 devices, the 4-bit prefetch architecture allows the BST command to be issued on an even number of clock cycles after a Write or Read command. Therefore, the effective burst length of a Read or Write command truncated by a BST command is an integer multiple of 4. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 35 - W979H6KB / W979H2KB 7.4.7.1 Burst Write Truncated by BST: WL = 1, BL = 16 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Write Nop Nop Nop Nop BST Nop Nop WL*tCK+tDQSS Nop BST not allowed WL=1 DQS_c DQS_t DQS DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A7 DIN A6 Notes: 1. The BST command truncates an ongoing write burst WL * tCK + tDQSS after the rising edge of the clock where the Burst Terminate command is issued. 2. For LPDDR2-S4 devices, BST can only be issued at even number of clock cycles after the Write command. 3. Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command. 7.4.7.2 Burst Read Truncated by BST: RL = 3, BL = 16 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank N Col Addr A Col Addr A [Cmd] Read Nop Nop Nop BST Nop Nop Nop Nop RL*tCK+tDQSCK+tDQSQ BST not allowed DQS_c DQS_t RL = 3 DQS DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 Notes: 1. The BST command truncates an ongoing read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Burst Terminate command is issued. 2. For LPDDR2-S4 devices, BST can only be issued at even number of clock cycles after the Read command. 3. Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 36 - W979H6KB / W979H2KB 7.4.8 Write Data Mask One write data mask (DM) pin for each data byte (DQ) will be supported on LPDDR2 devices, consistent with the implementation on LPDDR SDRAMs. Each data mask (DM) may mask its respective data byte (DQ) for any given cycle of the burst. Data mask has identical timings on write operations as the data bits, though used as input only, is internally loaded identically to data bits to insure matched system timing. See 7.4.14.2 “Precharge & Auto Precharge Clarification” table for Write to Precharge timings. 7.4.8.1 Write Data Mask Timing Data Mask Timing DQS_c DQS_t DQ VIH(ac) VIH(dc) VIL(ac) VIL(dc) DM tDS VIH(ac) VIH(dc) VIL(ac) VIL(dc) tDH tDS tDH Data Mask Function,WL= 2, BL=4 shown,second DQ masked CK_c CK_t [Cmd] Case 1: min tDQSS DQS_c DQS_t DQ Wirte WL = 2 tWR tWTR tDQSSmin 0 1 2 3 0 1 2 DM Case 2: max tDQSS tDQSSmax DQS_c DQS_t DQ 3 DM Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 37 - W979H6KB / W979H2KB 7.4.9 Precharge Operation The Precharge command is used to precharge or close a bank that has been activated. The Precharge command is initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. For 4bank devices, the AB flag, and the bank address bits, BA0 and BA1 are used to determine which bank(s) to precharge. The bank(s) will be available for a subsequent row access tRPab after an All-Bank Precharge command is issued and tRPpb after a Single-Bank Precharge command is issued. For 4-bank devices, the Row Precharge time (tRP) for an All-Bank Precharge (tRPab) is equal to the Row Precharge time for a Single-Bank Precharge (tRPpb). 7.4.9.1 Bank Selection for Precharge by Address Bits AB (CA4r) BA1 (CA8r) BA0 (CA7r) Precharged Bank(s) 4-bank device 0 0 0 Bank 0 only 0 0 1 Bank 1 only 0 1 0 Bank 2 only 0 1 1 Bank 3 only 1 DON’T CARE DON’T CARE All Banks 7.4.10 Burst Read Operation Followed by Precharge For the earliest possible precharge, the precharge command may be issued BL/2 clock cycles after a Read command. For an untruncated burst, BL is the value from the Mode Register. For a truncated burst, BL is the effective burst length. A new bank active (command) may be issued to the same bank after the Row Precharge time (tRP). A precharge command cannot be issued until after tRAS is satisfied. For LPDDR2-S4 devices, the minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a Read command. This time is called tRTP (Read to Precharge). For LPDDR2-S4 devices, tRTP begins BL/2 - 2 clock cycles after the Read command. If the burst is truncated by a BST command or a Read command to a different bank, the effective “BL” shall be used to calculate when tRTP begins. See 7.4.14.2 “Precharge & Auto Precharge Clarification” table for Read to Precharge timings. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 38 - W979H6KB / W979H2KB 7.4.10.1 Burst Read Followed by Precharge: RL = 3, BL = 8, RU(tRTP(min)/tCK) = 2 T0 T2 T1 T3 T4 T5 T7 T6 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Read Bank M Nop Nop Nop Bank M Row Addr Row Addr Nop Precharge Nop Activate Nop BL / 2 tRTP DQS_c DQS_t RL = 3 DQS DOUT A0 DOUT A1 DOUT A3 DOUT A2 DOUT A4 DOUT A5 DOUT A6 DOUT A7 tRP 7.4.10.2 Burst Read Followed by Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 3 T0 T2 T1 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Read Bank M Nop Nop Bank M Row Addr Row Addr Precharge Nop Nop Activate Nop Nop BL / 2 DQS_c DQS_t DQS RL = 3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 tRTP=3 tRP Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 39 - W979H6KB / W979H2KB 7.4.11 Burst Write Followed by Precharge For write cycles, a delay must be satisfied from the time of the last valid burst input data until the Precharge command may be issued. This delay is known as the write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command to the same bank should be issued prior to the tWR delay. LPDDR2-S4 devices write data to the array in prefetch quadruples (prefetch = 4). The beginning of an internal write operation may only begin after a prefetch group has been latched completely. Therefore, the write recovery time (tWR) starts at different boundaries. The minimum Write to Precharge command spacing to the same bank is WL + BL/2 + 1 + RU(tWR/tCK) clock cycles. For an untruncated burst, BL is the value from the Mode Register. For a truncated burst, BL is the effective burst length. See 7.4.14.2 “Precharge & Auto Precharge Clarification” table for Write to Precharge timings. 7.4.11.1 Burst Write Follwed by Precharge: WL = 1, BL = 4 T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Bank A Write Case 1:with tDQSS(max) DQS_c DQS_t Nop Nop Nop Nop tDQSSmax Nop Activate Nop tWR DIN A0 DIN A1 DIN A2 DIN A3 Case 2:with tDQSS(min) WL = 1 Precharge Completion of Burst Write WL = 1 DQS >=tRP tDQSSmin DQS_c DQS_t DQS Bank A Row Addr Row Addr Col Addr tWR DIN A0 DIN A1 DIN A2 DIN A3 Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 40 - W979H6KB / W979H2KB 7.4.12 Auto Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command or the auto-precharge function. When a Read or a Write command is given to the LPDDR2 SDRAM, the AP bit (CA0f) may be set to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If AP is LOW when the Read or Write command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst. If AP is HIGH when the Read or Write command is issued, then the auto-precharge function is engaged. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon Read or Write latency) thus improving system performance for random data access. 7.4.13 Burst Read with Auto-Precharge If AP (CA0f) is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged. LPDDR2-S4 devices start an Auto-Precharge operation on the rising edge of the clock BL/2 or BL/2 - 2 + RU(tRTP/tCK) clock cycles later than the Read with AP command, whichever is greater. Refer to section 7.4.14.2 “Precharge & Auto Precharge Clarification” table for equations related to Auto-Precharge for LPDDR2-S4. A new bank Activate command may be issued to the same bank if both of the following two conditions are satisfied simultaneously. ■ The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. ■ The RAS cycle time (tRC) from the previous bank activation has been satisfied. 7.4.13.1 Burst Read with Auto-Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Row Addr Row Addr Bank M Col Addr A Col Addr A Read Nop Nop Nop Nop Activate Nop Nop Nop BL / 2 DQS_c DQS_t RL = 3 DQS DOUT A0 tRTP DOUT A1 DOUT A2 DOUT A3 >=tRPpb Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 41 - W979H6KB / W979H2KB 7.4.14 Burst Write with Auto-Precharge If AP (CA0f) is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The LPDDR2 SDRAM starts an Auto Precharge operation on the rising edge which is tWR cycles after the completion of the burst write. A new bank activate (command) may be issued to the same bank if both of the following two conditions are satisfied. ■ The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. ■ The RAS cycle time (tRC) from the previous bank activation has been satisfied. 7.4.14.1 Burst Write with Auto-Precharge: WL = 1, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Col Addr Write Bank A Row Addr Row Addr Nop Nop Nop Nop Nop Activate Nop tWR WL = 1 DQS_c DQS_t DQS Nop tRPpb DIN A0 DIN A1 DIN A2 DIN A3 Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 42 - W979H6KB / W979H2KB 7.4.14.2 Precharge & Auto Precharge Clarification From Command Read BST (for Reads) Read w/AP Write BST (for Writes) Write w/AP Precharge Precharge All To Command Minimum Delay between “From Command” to “To Command” Unit Notes Precharge (to same Bank as Read) BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1 Precharge All BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1 Precharge (to same Bank as Read) 1 CLK 1 Precharge All 1 CLK 1 Precharge (to same Bank as Read w/AP) BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1, 2 Precharge All BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1 Activate (to same Bank as Read w/AP) BL/2 + max(2, RU(tRTP/tCK)) - 2 + RU(tRPpb/tCK) CLK 1 Write or Write w/AP (same bank) lllegal CLK 3 Write or Write w/AP (different bank) RL + BL/2 + RU(tDQSCKmax/tCK) - WL + 1 CLK 3 Read or Read w/AP (same bank) lllegal CLK 3 Read or Read w/AP (different bank) BL/2 CLK 3 Precharge (to same Bank as Write) WL + BL/2 + RU(tWR/tCK) + 1 CLK 1 Precharge All WL + BL/2 + RU(tWR/tCK) + 1 CLK 1 Precharge (to same Bank as Write) WL + RU(tWR/tCK) + 1 CLK 1 Precharge All WL + RU(tWR/tCK) + 1 CLK 1 Precharge (to same Bank as Write w/AP) WL + BL/2+ RU(tWR/tCK) + 1 CLK 1 Precharge All WL + BL/2 + RU(tWR/tCK) + 1 CLK 1 Activate (to same Bank as Write w/AP) WL + BL/2 + RU(tWR/tCK) + 1 + RU(tRPpb/tCK) CLK 1 Write or Write w/AP (same bank) lllegal CLK 3 Write or Write w/AP (different bank) BL/2 CLK 3 Read or Read w/AP (same bank) lllegal CLK 3 Read or Read w/AP (different bank) WL + BL/2 + RU(tWTR/tCK) + 1 CLK 3 Precharge (to same Bank as Precharge) 1 CLK 1 Precharge All 1 CLK 1 Precharge 1 CLK 1 Precharge All 1 CLK 1 Notes: 1. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command issued to that bank. 2. Any command issued during the specified minimum delay time is illegal. 3. After Read with AP, seamless read operations to different banks are supported. After Write with AP, seamless write operations to different banks are supported. Read w/AP and Write w/AP may not be interrupted or truncated. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 43 - W979H6KB / W979H2KB 7.4.15 Refresh Command The Refresh command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of clock. Per Bank Refresh is initiated by having CA3 LOW at the rising edge of clock. An All Bank Refresh command, REFab performs a refresh operation to all banks. All banks have to be in Idle state when REFab is issued (for instance, by Precharge all-bank command). REFab also synchronizes the bank count between the controller and the SDRAM to zero. As shown in 7.4.15.1 “Command Scheduling Separations Related to Refresh” table, the REFab command may not be issued to the memory until the following conditions have been met: a) The tRFCab has been satisified after the prior REFab command b) The tRP has been satisified after prior Precharge commands When the All Bank refresh cycle has completed, all banks will be in the Idle state. As shown in 7.4.15.1 “Command Scheduling Separations Related to Refresh” table, after issuing REFab: a) The tRFCab latency must be satisfied before issuing an ACTIVATE command b) The tRFCab latency must be satisfied before issuing a REFab command 7.4.15.1 Command Scheduling Separations Related to Refresh Symbol minimum delay from tRFCab REFab tRRD Activate to REFab Activate cmd to any bank Activate cmd to different bank than prior Activate Note: A bank must be in the Idle state before it is refreshed. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 44 - W979H6KB / W979H2KB 7.4.16 LPDDR2 SDRAM Refresh Requirements (1) Minimum number of Refresh commands: The LPDDR2 SDRAM requires a minimum number of R Refresh (REFab) commands within any rolling Refresh Window (tREFW = 32 mS @ MR4[2:0] = “011” or TCASE ≤ 85°C). The required minimum number of Refresh commands and resulting average refresh interval (tREFI) are given in 8.6.1 “Refresh Requirement Parameters” table. See Mode Register 4 for tREFW and tREFI refresh multipliers at different MR4 settings. (2) Burst Refresh limitation: To limit maximum current consumption, a maximum of 8 REFab commands may be issued in any rolling tREFBW (tREFBW = 4 x 8 x tRFCab). (3) Refresh Requirements and Self-Refresh: If any time within a refresh window is spent in Self-Refresh Mode, the number of required Refresh commands in this particular window is reduced to: R* = R - RU{tSRF / tREFI} = R - RU{R * tSRF / tREFW}; where RU stands for the round-up function. 7.4.16.1 Definition of tSRF A) tREFW tSRF CKE Enter Self-Refresh Exit Self-Refresh tREFW B) tSRF CKE C) CKE tREFW tSRF Exit Self-Refresh D) Enter Self-Refresh tREFW tSRF1 tSRF2 CKE Exit Self-Refresh Enter Self-Refresh tSRF=tSRF1+tSRF2 Exit Self-Refresh Several examples on how tSRF is caclulated: A: with the time spent in Self-Refresh Mode fully enclosed in the Refresh Window (tREFW). B: at Self-Refresh entry. C: at Self-Refresh exit. D: with several different invervals spent in Self Refresh during one tREFW interval. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 45 - W979H6KB / W979H2KB In contrast to JESD79 and JESD79-2 and JESD79-3 compliant SDRAM devices, LPDDR2-S4 devices allow significant flexibiliy in scheduling REFRESH commands, as long as the boundary conditions above are met. In the most straight forward case a REFRESH command should be scheduled every tREFI. In this case Self-Refresh may be entered at any time. The users may choose to deviate from this regular refresh pattern e.g., to enable a period where no refreshes are required. As an example, using a 1Gb LPDDR2-S4 device, the user can choose to issue a refresh burst of 4096 REFRESH commands with the maximum allowable rate (limited by tREFBW) followed by a long time without any REFRESH commands, until the refresh window is complete, then repeating this sequence. The achieveable time without REFRESH commands is given by tREFW - (R / 8) * tREFBW = tREFW - R * 4 * tRFCab.@ TCASE ≤ 85°C this can be up to 32 mS - 4096 * 4 * 130 nS ≈ 30 mS. While both - the regular and the burst/pause - patterns can satisfy the refresh requirements per rolling refresh interval, if they are repeated in every subsequent 32 mS window, extreme care must be taken when transitioning from one pattern to another to satisfy the refresh requirement in every rolling refresh window during the transition. Figure of 7.4.16.3 shows an example of an allowable transition from a burst pattern to a regular, distributed pattern. If this transition happens directly after the burst refresh phase, all rolling tREFW interval will have at least the required number of refreshes. Figure of 7.4.16.4 shows an example of a non-allowable transition. In this case the regular refresh pattern starts after the completion of the pause-phase of the burst/pause refresh pattern. For several rolling tREFW intervals the minimmun number of REFRESH commands is not satisfied. The understanding of the pattern transition is extremly relevant (even if in normal operation only one pattern is employed), as in Self-Refresh-Mode a regular, distributed refresh pattern has to be assumed, which is reflected in the equation for R* above. Therefore it is recommended to enter Self-Refresh-Mode ONLY directly after the burstphase of a burst/pause refresh pattern as indicated in figure of 7.4.16.5 and begin with the burst phase upon exit from Self-Refresh. 7.4.16.2 Regular, Distributed Refresh Pattern tREFBW 16,384 12,288 96 mS 12,289 8,192 64 mS 8,193 32 mS 8,192 4,096 4,097 4,096 0 mS tREFI 12,288 tREFI tREFBW Notes: 1. Compared to repetitive burst Refresh with subsequent Refresh pause. 2. For an example, in a 1Gb LPDDR2 device at TCASE ≤ 85°C, the distributed refresh pattern would have one REFRESH command per 7.8 µS; the burst refresh pattern would have an average of one refresh command per 0.52 µS followed by ≈30 mS without any REFRESH command. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 46 - W979H6KB / W979H2KB 7.4.16.3 Allowable Transition from Repetitive Burst Refresh tREFI 64 mS 16,384 96 mS 12,288 10,240 4,097 4,096 tREFBW 8,192 32 mS 0 mS tREFI tREFBW Notes: 1. Shown with subsequent Refresh pause to regular distributed Refresh pattern. 2. For an example, in a 1Gb LPDDR2 device at TCASE ≤ 85°C, the distributed refresh pattern would have one REFRESH command per 7.8 µS; the burst refresh pattern would have an average of one refresh command per 0.52 µS followed by ≈30 mS without any REFRESH command. 7.4.16.4 NOT-Allowable Transition from Repetitive Burst Refresh tREFI 64 mS 12,288 96 mS 10,240 8,193 4,097 4,096 8,192 32 mS 0 mS tREFI tREFW=32mS tREFBW tREFBW Not enough Refresh commands In this refresh window!! Notes: 1. Shown with subsequent Refresh pause to regular distributed Refresh pattern. 2. Only ≈2048 REFRESH commands (< R which is 4096) in the indicated tREFW window. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 47 - W979H6KB / W979H2KB 7.4.16.5 Recommended Self-Refresh Entry and Exit 4,097 4,096 8,192 32 mS 0 mS Self-Refresh tREFBW tREFBW Note: 1. In conjunction with a Burst/Pause Refresh patterns. 7.4.16.6 All Bank Refresh Operation T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1 CK_t / CK_c AB CA0-9 [Cmd] Precharge Nop >=tRPab Nop Nop REFab >=tRFCab REFab Nop ANY >=tRFCab Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 48 - W979H6KB / W979H2KB 7.4.17 Self Refresh Operation The Self Refresh command can be used to retain data in the LPDDR2 SDRAM, even if the rest of the system is powered down. When in the Self Refresh mode, the LPDDR2 SDRAM retains data without external clocking. The LPDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CKE LOW, CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. CKE must be HIGH during the previous clock cycle. A NOP command must be driven in the clock cycle following the power-down command. Once the command is registered, CKE must be held LOW to keep the device in Self Refresh mode. LPDDR2-S4 devices can operate in Self Refresh in both the Standard or Extended Temperature Ranges. LPDDR2S4 devices will also manage Self Refresh power consumption when the operating temperature changes, lower at low temperatures and higher temperatures. Once the LPDDR2 SDRAM has entered Self Refresh mode, all of the external signals except CKE, are “don’t care”. For proper self refresh operation, power supply pins (VDD1, VDD2, and VDDCA) must be at valid levels. VDDQ may be turned off during Self-Refresh. Prior to exiting Self-Refresh, VDDQ must be within specified limits. VrefDQ and VrefCA may be at any level within minimum and maximum levels (see section 8.1 “Absolute Maximum DC Ratings” table). However prior to exit Self-Refresh, VrefDQ and VrefCA must be within specified limits (see section 8.2.1.1 “Recommended DC Operating Conditions” table). The SDRAM initiates a minimum of one all-bank refresh command internally within tCKESR period once it enters Self Refresh mode. The clock is internally disabled during Self Refresh Operation to save power. The minimum time that the LPDDR2 SDRAM must remain in Self Refresh mode is tCKESR. The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered; however, the clock must be restarted and stable before the device can exit Self Refresh operation. The procedure for exiting Self Refresh requires a sequence of commands. First, the clock shall be stable and within specified limits for a minmum of 2 clock cycles prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least tXSR must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period tXSR for proper operation except for self refresh re-entry. NOP commands must be registered on each positive clock edge during the Self Refresh exit interval tXSR. The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, it is required that at least one Refresh command (one all-bank) is issued before entry into a subsequent Self Refresh. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 49 - W979H6KB / W979H2KB For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements outlined in section 7.4.16 “LPDDR2 SDRAM Refresh Requirements”, since no refresh operations are performed in power-down mode. 2 tCK(min) CK_c CK_t tIHCKE Input clock frequency may be changed or stopped during Self-Refresh tIHCKE CKE tISCKE tISCKE CS_n [Cmd] Valid Enter SR NOP Exit SR NOP Valid tXSR(min) tCKESR(min) Enter Self-Refresh NOP Exit Self-Refresh Figure of Self Refresh Operation Notes: 1. Input clock frequency may be changed or stopped during self-refresh, provided that upon exiting self-refresh, a minimum of 2 clocks of stable clock are provided and the clock frequency is between the minimum and maximum frequency for the particular speed grad 2. Device must be in the “All banks idle” state prior to entering Self Refresh mode. 3. tXSR begins at the rising edge of the clock after CKE is driven HIGH. 4. A valid command may be issued only after tXSR is satisfied. NOPs shall be issued during tXSR. 7.4.18 Partial Array Self-Refresh: Bank Masking Each bank of LPDDR2 SDRAM can be independently configured whether a self refresh operation is taking place. One mode register unit of 4 bits accessible via MRW command is assigned to program the bank masking status of each bank up to 4 banks. For bank masking bit assignments, see section 7.3.13 Mode Register 16 “MR16_PASR_Bank Mask (MA[7:0] = 10H)”. The mask bit to the bank controls a refresh operation of entire memory within the bank. If a bank is masked via MRW, a refresh operation to the entire bank is blocked and data retention by a bank is not guaranteed in self refresh mode. To enable a refresh operation to a bank, a coupled mask bit has to be programmed, “unmasked”. When a bank mask bit is unmasked, a refresh to a bank is determined by the programmed status of segment mask bits. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 50 - W979H6KB / W979H2KB 7.4.19 Mode Register Read Command The Mode Register Read command is used to read configuration and status data from mode registers. The Mode Register Read (MRR) command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r- CA4r}. The mode register contents are available on the first data beat of DQ[0:7], RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Mode Register Read Command is issued. Subsequent data beats contain valid, but undefined content, except in the case of the DQ Calibration function DQC, where subsequent data beats contain valid content as described in section 7.4.20.2 “DQ Calibration”. All DQS_t, DQS_c shall be toggled for the duration of the Mode Register Read burst. The MRR command has a burst length of four. The Mode Register Read operation (consisting of the MRR command and the corresponding data traffic) shall not be interrupted. The MRR command period (tMRR) is 2 clock cycles. Mode Register Reads to reserved and write-only registers shall return valid, but undefined content on all data beats and DQS_t, DQS_c shall be toggled. 7.4.19.1 Mode Register Read Timing Example: RL = 3, tMRR = 2 T0 T2 T1 T3 T4 T5 T7 T6 T8 CK_t / CK_c CA0-9 [Cmd] DQS_t DQS_c Reg A Reg A Reg B MRR Reg B MRR tMRR = 2 tMRR = 2 RL = 3 DQ[0-7] DQ[8-max] DOUT A UNDEF UNDEF UNDEF DOUT B UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF CMD not allowed Notes: 1. Mode Register Read has a burst length of four. 2. Mode Register Read operation shall not be interrupted. 3. Mode Register data is valid only on DQ[0-7] on the first beat. Subsequent beats contain valid, but undefined data. DQ[8-max] contain valid, but undefined data for the duration of the MRR burst. 4. The Mode Register Command period is tMRR. No command (other than Nop) is allowed during this period. 5. Mode Register Reads to DQ Calibration registers MR32 and MR40 are described in the section on DQ Calibration. 6. Minimum Mode Register Read to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 - WL clock cycles. 7. Minimum Mode Register Read to Mode Register Write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 clock cycles. The MRR command shall not be issued earlier than BL/2 clock cycles after a prior Read command and WL + 1 + BL/2 + RU( tWTR/tCK) clock cycles after a prior Write command, because read-bursts and write-bursts shall not be truncated by MRR. Note that if a read or write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated burst should be used as “BL”. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 51 - W979H6KB / W979H2KB 7.4.19.2 Read to MRR Timing Example: RL = 3, tMRR = 2 T0 T2 T1 T3 T4 T5 T7 T6 T8 CK_t / CK_c CA0-9 BA M Col Addr A [Cmd] Col Addr A Reg B Read Reg B MRR tMRR = 2 BL / 2 DQS_c DQS_t RL = 3 DQ[0-7] DQ[8-max] DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT B UNDEF UNDEF UNDEF DOUT A0 DOUT A1 DOUT A2 DOUT A3 UNDEF UNDEF UNDEF UNDEF CMD not allowed Notes: 1. The minimum number of clocks from the burst read command to the Mode Register Read command is BL/2. 2. The Mode Register Read Command period is tMRR. No command (other than Nop) is allowed during this period. 7.4.19.3 Burst Write Followed by MRR: RL = 3, WL = 1, BL = 4 T1 T0 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] BA N Col Addr A Reg B Col Addr A Write Reg B MRR RL = 3 DQS_c DQS_t tWTR WL = 1 DIN A0 DIN A1 DIN A2 tMRR = 2 DIN A3 CMD not allowed Notes: 1. The minimum number of clock cycles from the burst write command to the Mode Register Read command is [WL + 1 + BL/2 + RU( t WTR/tCK)]. 2. The Mode Register Read Command period is tMRR. No command (other than Nop) is allowed during this period. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 52 - W979H6KB / W979H2KB 7.4.20 Temperature Sensor LPDDR2 SDRAM features a temperature sensor whose status can be read from MR4. This sensor can be used to determine an appropriate refresh rate, determine whether AC timing derating is required in the Extended Temperature Range and/or monitor the operating temperature. Either the temperature sensor or the device operating temperature (See 8.2.3 “Operating Temperature Conditions” table) may be used to determine whether operating temperature requirements are being met. LPDDR2 devices shall monitor device temperature and update MR4 according to tTSI. Upon exiting self-refresh or power-down, the device temperature status bits shall be no older than tTSI. When using the temperature sensor, the actual device case temperature may be higher than the operating temperature specification (See 8.2.3 “Operating Temperature Conditions” table) that applies for the Standard or Extended Temperature Ranges. For example, TCASE may be above 85°C when MR4[2:0] equals 011b. To assure proper operation using the temperature sensor, applications should consider the following factors: TempGradient is the maximum temperature gradient experienced by the memory device at the temperature of interest over a range of 2°C. ReadInterval is the time period between MR4 reads from the system. TempSensorInterval (tTSI) is maximum delay between internal updates of MR4. SysRespDelay is the maximum time between a read of MR4 and the response by the system. LPDDR2 devices shall allow for a 2°C temperature margin between the point at which the device temperature enters the Extended Temperature Range and point at which the controller re-configures the system accordingly. In order to determine the required frequency of polling MR4, the system shall use the maximum TempGradient and the maximum response time of the system using the following equation: TempGradient x (ReadInterval + tTSI + SysRespDelay) ≤ 2°C Table of Temperature Sensor Symbol Parameter Max/Min Value Unit TempGradient System Temperature Gradient Max System Dependent °C/S ReadInterval MR4 Read Interval Max System Dependent mS tTSI Temperature Sensor Interval Max 32 mS SysRespDelay System Response Delay Max System Dependent mS TempMargin Device Temperature Margin Max 2 ºC For example, if TempGradient is 10°C/s and the SysRespDelay is 1 mS: 10°C/s x (ReadInterval + 32mS + 1mS) ≤ 2°C In this case, ReadInterval shall be no greater than 167 mS. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 53 - W979H6KB / W979H2KB 7.4.20.1 Temperature Sensor Timing Temp < (tTSI + Readlnterval + SysRespDelay) Device Temp Margin p Tem 2°C ien Grad t MR4 Trip Level tTSI MR4=0x03 MR4=0x86 MR4=0x86 MR4=0x86 MR4=0x86 Temperature Sensor Update MRR MR4=0x03 Time SysRespDelay Readlnterval Host MR4 Read MR4=0x06 MRR MR4=0x86 7.4.20.2 DQ Calibration LPDDR2 device features a DQ Calibration function that outputs one of two predefined system timing calibration patterns. A Mode Register Read to MR32 (Pattern “A”) or MR40 (Pattern “B”) will return the specified pattern on DQ[0] and DQ[8] for x16 devices, and DQ[0 ], DQ[8], DQ[16], and DQ[24] for x32 devices. For x16 devices, DQ[7:1] and DQ[15:9] may optionally drive the same information as DQ[0] or may drive 0b during the MRR burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0] or may drive 0b during the MRR burst. For LPDDR2-S4 devices, MRR DQ Calibration commands may only occur in the Idle state. Table of Data Calibration Pattern Description Pattern MR# Bit Time 0 Bit Time 1 Bit Time 2 Bit Time 3 Description Pattern A MR32 1 0 1 0 Read to MR32 return DQ calibration pattern A Pattern B MR40 0 0 1 1 Read to MR40 return DQ calibration pattern B Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 54 - W979H6KB / W979H2KB 7.4.20.3 MR32 and MR40 DQ Calibration Timing Example: RL = 3, tMRR = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] DQS_t DQS_c Reg 32 Reg 32 Reg 40 MRR32 Reg 40 MRR40 tMRR = 2 tMRR = 2 RL = 3 DQ[0] 1 0 1 0 0 0 1 1 DQ[7:1] 1 0 1 0 0 0 1 1 Pattern “B” Pattern “A” x16 DQ[8] 1 0 1 0 0 0 1 1 DQ[15:9] 1 0 1 0 0 0 1 1 x32 DQ[16] 1 0 1 0 0 0 1 1 DQ[23:17] 1 0 1 0 0 0 1 1 DQ[24] 1 0 1 0 0 0 1 1 DQ[31:25] 1 0 1 0 0 0 1 1 CMD not allowed Optionally driven the same as DQ0 or to 0b Notes: 1. Mode Register Read has a burst length of four. 2. Mode Register Read operation shall not be interrupted. 3. Mode Register Reads to MR32 and MR40 drive valid data on DQ[0] during the entire burst. For x16 devices, DQ[8] shall drive the same information as DQ[0] during the burst. For x32 devices, DQ[8], DQ[16], and DQ[24] shall drive the same information as DQ[0] during the burst. 4. For x16 devices, DQ[7:1] and DQ[15:9] may optionally drive the same information as DQ[0] or they may drive 0b during the burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0] or they may drive 0b during the burst. 5. The Mode Register Command period is tMRR. No command (other than Nop) is allowed during this period. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 55 - W979H6KB / W979H2KB 7.4.21 Mode Register Write Command The Mode Register Write command is used to write configuration data to mode registers. The Mode Register Write (MRW) command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 LOW at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r-CA4r}. The data to be written to the mode register is contained in CA9f-CA2f. The MRW command period is defined by tMRW. Mode Register Writes to readonly registers shall have no impact on the functionality of the device. For LPDDR2-S4 devices, the MRW may only be issued when all banks are in the idle precharge state. One method of ensuring that the banks are in the idle precharge state is to issue a Precharge-All command. 7.4.21.1 Mode Register Write Timing Example: RL = 3, tMRW = 5 T1 T0 T2 Tx + 1 Tx Tx + 2 Ty Ty + 1 Ty + 2 CK_t / CK_c CA0-9 MR Addr MR Data MR Addr MR Data [Cmd] MRW MRW ANY tMRW tMRW CMD not allowed Notes: 1. The Mode Register Write Command period is tMRW. No command (other than Nop) is allowed during this period. 2. At time Ty, the device is in the idle state. 7.4.21.2 Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW) Current State All Banks Idle Bank(s) Active Command Intermediate State Next State MRR Mode Register Reading (All Banks Idle) All Banks Idle MRW Mode Register Writing (All Banks Idle) All Banks Idle MRW (RESET) Resetting (Device Auto-Initialization) All Banks Idle MRR Mode Register Reading (Bank(s) Active) Bank(s) Active MRW Not Allowed Not Allowed MRW (RESET) Not Allowed Not Allowed Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 56 - W979H6KB / W979H2KB 7.4.22 Mode Register Write Reset (MRW Reset) Any MRW command issued to MRW63 initiates an MRW Reset. The MRW Reset command brings the device to the Device Auto-Initialization (Resetting) State in the Power-On Initialization sequence (see step 3 in sections 7.2.1 “Power Ramp and Device Initialization”). The MRW Reset command may be issued from the Idle state for LPDDR2-S4 devices. This command resets all Mode Registers to their default values. No commands other than NOP may be issued to the LPDDR2 device during the MRW Reset period (tINIT4). After MRW Reset, boot timings must be observed until the device initialization sequence is complete and the device is in the Idle state. Array data for LPDDR2-S4 devices are undefined after the MRW Reset command. For the timing diagram related to MRW Reset, refer to 7.2.3 “Power Ramp and Initialization Sequence” figure. 7.4.23 Mode Register Write ZQ Calibration Command The MRW command is also used to initiate the ZQ Calibration command. The ZQ Calibration command is used to calibrate the LPDDR2 ouput drivers (RON) over process, temperature, and voltage. LPDDR2-S4 devices support ZQ Calibration. There are four ZQ Calibration commands and related timings times, tZQINIT, tZQRESET, tZQCL, and tZQCS. tZQINIT corresponds to the initialization calibration, tZQRESET for resetting ZQ setting to default, tZQCL is for long calibration, and tZQCS is for short calibration. See Mode Register 10 (MR10) for description on the command codes for the different ZQ Calibration commands. The Initialization ZQ Calibration (ZQINIT) shall be performed for LPDDR2-S4 devices. This Initialization Calibration achieves a RON accuracy of ±15%. After initialization, the ZQ Long Calibration may be used to re-calibrate the system to a RON accuracy of ±15%. A ZQ Short Calibration may be used periodically to compensate for temperature and voltage drift in the system. The ZQReset Command resets the RON calibration to a default accuracy of ±30% across process, voltage, and temperature. This command is used to ensure RON accuracy to ±30% when ZQCS and ZQCL are not used. One ZQCS command can effectively correct a minimum of 1.5% (ZQCorrection) of RON impedance error within tZQCS for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and Temperature Sensitivity’. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the LPDDR2 is subject to in the application, is illustrated. The interval could be defined by the following formula: ZQCorrection (TSens × Tdriftrate ) + (VSens × Vdriftrate ) where TSens = max(dRONdT) and VSens = max(dRONdV) define the LPDDR2 temperature and voltage sensitivities. For example, if TSens = 0.75% / C, VSens = 0.20% / mV, Tdriftrate = 1C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as: 1.5 = 0.4s (0.75 × 1) + (0.20 × 15) For LPDDR2-S4 devices, a ZQ Calibration command may only be issued when the device is in Idle state with all banks precharged. No other activities can be performed on the LPDDR2 data bus during the calibration period (tZQINIT, tZQCL, tZQCS). The quiet time on the LPDDR2 data bus helps to accurately calibrate RON. There is no required quiet time after the ZQ Reset command. If multiple devices share a single ZQ Resistor, only one device may be calibrating at any given time. After calibration is achieved, the LPDDR2 device shall disable the ZQ pin’s current consumption path to reduce power. In systems that share the ZQ resistor between devices, the controller must not allow overlap of tZQINIT, tZQCS, or tZQCL between the devices. ZQ Reset overlap is allowed. If the ZQ resistor is absent from the system, ZQ shall be connected to VDDCA. In this case, the LPDDR2 device shall ignore ZQ calibration commands and the device will use the default calibration settings (See section 8.2.6.5 “RONPU and RONPD Characteristics without ZQ Calibration” Output Driver DC Electrical Characteristics without ZQ Calibration table). Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 57 - W979H6KB / W979H2KB 7.4.23.1 ZQ Calibration Initialization Timing Example T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2 Tx+1 Tx+2 CK_t / CK_c CA0-9 MR Addr MR Data [Cmd] MRW ANY tZQINIT CMD not allowed Notes: 1. The ZQ Calibration Initialization period is tZQINIT. No command (other than Nop) is allowed during this period. 2. CKE must be continuously registered HIGH during the calibration period. 3. All devices connected to the DQ bus should be high impedance during the calibration process. 7.4.23.2 ZQ Calibration Short Timing Example T0 T1 T2 T3 T4 T5 Tx CK_t / CK_c CA0-9 [Cmd] MR Addr MR Data MRW ANY tZQCS CMD not allowed Notes: 1. The ZQ Calibration Short period is tZQCS. No command (other than Nop) is allowed during this period. 2. CKE must be continuously registered HIGH during the calibration period. 3. All devices connected to the DQ bus should be high impedance during the calibration process. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 58 - W979H6KB / W979H2KB 7.4.23.3 ZQ Calibration Long Timing Example T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2 CK_t / CK_c CA0-9 MR Addr MR Data [Cmd] MRW ANY tZQCL CMD not allowed Notes: 1. The ZQ Calibration Long period is tZQCL. No command (other than Nop) is allowed during this period. 2. CKE must be continuously registered HIGH during the calibration period. 3. All devices connected to the DQ bus should be high impedance during the calibration process. 7.4.23.4 ZQ Calibration Reset Timing Example T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2 CK_t / CK_c CA0-9 [Cmd] MR Addr MR Data MRW ANY tZQRESET CMD not allowed Notes: 1. The ZQ Calibration Reset period is tZQRESET. No command (other than Nop) is allowed during this period. 2. CKE must be continuously registered HIGH during the calibration period. 3. All devices connected to the DQ bus should be high impedance during the calibration process. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 59 - W979H6KB / W979H2KB 7.4.23.5 ZQ External Resistor Value, Tolerance, and Capacitive Loading To use the ZQ Calibration function, a 240 Ohm ± 1% tolerance external resistor must be connected between the ZQ pin and ground. A single resistor can be used for each LPDDR2 device or one resistor can be shared between multiple LPDDR2 devices if the ZQ calibration timings for each LPDDR2 device do not overlap. The total capacitive loading on the ZQ pin must be limited (See section 8.2.6.7 “Input/Output Capacitance” table). 7.4.24 Power-Down For LPDDR2 SDRAM, power-down is synchronously entered when CKE is registered LOW and CS_n HIGH at the rising edge of clock. CKE must be registered HIGH in the previous clock cycle. A NOP command must be driven in the clock cycle following the power-down command. CKE is not allowed to go LOW while mode register, read, or write operations are in progress. CKE is allowed to go LOW while any of other operations such as row activation, precharge, autoprecharge, or refresh is in progress, but power-down IDD spec will not be applied until finishing those operations. Timing diagrams are shown in the following pages with details for entry into power down. For LPDDR2 SDRAM, if power-down occurs when all banks are idle, this mode is referred to as idle power- down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK_t, CK_c, and CKE. In power-down mode, CKE must be maintained LOW while all other input signals are “Don’t Care”. CKE LOW must be maintained until tCKE has been satisfied. VREF must be maintained at a valid level during power down. VDDQ may be turned off during power down. If VDDQ is turned off, then VREFDQ must also be turned off. Prior to exiting power down, both VDDQ and VREFDQ must be within their respective min/max operating ranges (See 8.2.1.1 “Recommended DC Operating Conditions” table). For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements outlined in section 7.4.16 “LPDDR2 SDRAM Refresh Requirements”, as no refresh operations are performed in power-down mode. The power-down state is exited when CKE is registered HIGH. The controller shall drive CS_n HIGH in conjunction with CKE HIGH when exiting the power-down state. CKE HIGH must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP after CKE goes HIGH. Power-down exit latency is defined in section 8.7.1 “LPDDR2 AC Timing” table. 7.4.24.1 Basic Power Down Entry and Exit Timing 2 tCK (min) CK_c CK_t tIHCKE Input clock frequency may be changed or the input clock stopped during Power-Down CKE tIHCKE tISCKE tISCKE CS_n [CMD] Valid Enter PD Exit PD NOP Valid Valid tXP(min) tCKE(min) Enter Power-Down mode NOP Exit Power-Down mode tcKE(min) Note: Input clock frequency may be changed or the input clock stopped during power-down, provided that upon exiting power-down, the clock is stable and within specified limits for a minmum of 2 clock cycles prior to power-down exit and the clock frequency is between the minimum and maximum frequency for the particular speed grade. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 60 - W979H6KB / W979H2KB 7.4.24.2 CKE Intensive Environment CK_c CK_t tCKE tCKE CKE tCKE tCKE 7.4.24.3 Refresh to Refresh Timing with CKE Intensive Environment CK_c CK_t CKE tCKE tCKE tXP [Cmd] tCKE REF tCKE tXP REF tREFI Note: The pattern shown above can repeat over a long period of time. With this pattern, LPDDR2 SDRAM guarantees all AC and DC timing & voltage specifications with temperature and voltage drift. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 61 - W979H6KB / W979H2KB 7.4.24.4 Read to Power-Down Entry T0 CK_c CK_t [Cmd] T1 T2 Tx+1 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 Read operation starts with a read command and CKE should be kept HIGH until the end of burst operation. RD CKE RL DQ Q Q Q tISCKE Q DQS_t DQS_c T0 [Cmd] T1 T2 Tx+1 Tx Tx+2 Tx+3 RD Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 CKE should be kept HIGH until the end of burst operation. CKE RL DQ DQS_t DQS_c Q Q Q Q Q tISCKE Q Q Q Note: CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Read command is registered. 7.4.24.5 Read with Auto Precharge to Power-Down Entry T0 T1 T2 Tx+1 Tx CK_c CK_t Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 Start internal precharge [Cmd] RDA PRE BL = 4 CKE should be kept HIGH until the end of burst operation. BL/2 With tRTP = 7.5ns & tRAS min satisfied CKE RL tISCKE DQ Q Q Q Q DQS_t DQS_c T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 Start internal precharge [Cmd] RDA BL = 8 CKE DQ PRE CKE should be kept HIGH until the end of burst operation. BL/2 With tRTP = 7.5ns & tRAS min satisfied RL tISCKE Q Q Q Q Q Q Q Q DQS_t DQS_c Note: CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Read command is registered. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 62 - W979H6KB / W979H2KB 7.4.24.6 Write to Power-Down Entry T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx+1 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+2 Tx+3 Tx+4 CK_c CK_t [Cmd] WR BL = 4 CKE WL DQ D D D tISCKE D tWR DQS_t DQS_c T0 T1 [Cmd] Tm Tm+1 Tm+2 Tm+3 Tm+4 D D Tm+5 Tx Tx+1 WR BL = 8 CKE WL DQ D D D D D tISCKE D tWR DQS_t DQS_c Note: CKE may be registered LOW WL + 1 + BL/2 + RU(tWR/tCK) clock cycles after the clock on which the Write command is registered. 7.4.24.7 Write with Auto Precharge to Power-Down Entry T0 CK_c CK_t [Cmd] T1 Tm Tm+1 Tm+2 Tm+3 Tx+1 Tx WRA Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Start Internal Precharge PRE BL = 4 CKE WL DQ D D D tISCKE D tWR DQS_t DQS_c T0 T1 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx Tx+1 Tx+2 Tx+3 Tx+4 CK_c CK_t [Cmd] PRE WRA Start Internal Precharge CKE DQ DQS_t DQS_c BL = 8 WL D D D D D D D tISCKE D tWR Note: CKE may be registered LOW WL + 1 + BL/2 + RU(tWR/tCK) + 1 clock cycles after the Write command is registered. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 63 - W979H6KB / W979H2KB 7.4.24.8 Refresh Command to Power-Down Entry T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK_c CK_t [Cmd] REF CKE tIHCKE tISCKE Note: CKE may go LOW tIHCKE after the clock on which the Refresh command is registered. 7.4.24.9 Activate Command to Power-Down Entry T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T7 T8 T9 T10 T11 CK_c CK_t [Cmd] ACT CKE tIHCKE tISCKE Note: CKE may go LOW tIHCKE after the clock on which the Activate command is registered. 7.4.24.10 Precharge/Precharge-All Command to Power-Down Entry T0 T1 T2 T3 T4 T5 T6 CK_c CK_t [Cmd] PRE CKE tIHCKE tISCKE Note: CKE may go LOW tIHCKE after the clock on which the Precharge/Precharge-All command is registered. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 64 - W979H6KB / W979H2KB 7.4.24.11 Mode Register Read to Power-Down Entry T0 T1 T2 Tx+1 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 CK_c CK_t Mode Register Read operation starts with a MRR command and [Cmd] MRR CKE CKE should be kept HIGH until the end of burst operation. RL tISCKE DQ Q Q Q Q DQS_t DQS_c Note: CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Mode Register Read command is registered. 7.4.24.12 MRW Command to Power-Down Entry T0 T1 T3 T2 T4 T5 T6 T7 T8 T9 T10 T11 CK_c CK_t [Cmd] MRW CKE can go to LOW tMRW after a Mode Register Write command CKE tISCKE tMRW Note: CKE may be registered LOW tMRW after the clock on which the Mode Register Write command is registered. 7.4.25 Deep Power-Down Deep Power-Down is entered when CKE is registered LOW with CS_n LOW, CA0 HIGH, CA1 HIGH, and CA2 LOW at the rising edge of clock. A NOP command must be driven in the clock cycle following the power-down command. CKE is not allowed to go LOW while mode register, read, or write operations are in progress. All banks must be in idle state with no activity on the data bus prior to entering the Deep Power Down mode. During Deep Power-Down, CKE must be held LOW. In Deep Power-Down mode, all input buffers except CKE, all output buffers, and the power supply to internal circuitry may be disabled within the SDRAM. All power supplies must be within specified limits prior to exiting Deep PowerDown. VrefDQ and VrefCA may be at any level within minimum and maximum levels (See 8.1 “Absolute Maximum DC Ratings”). However prior to exiting Deep Power-Down, Vref must be within specified limits (See 8.2.1.1 “Recommended DC Operating Conditions”). Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 65 - W979H6KB / W979H2KB The contents of the SDRAM may be lost upon entry into Deep Power-Down mode. The Deep Power-Down state is exited when CKE and CS_n are registered HIGH, while meeting tISCKE with a stable clock input. The SDRAM must be fully re-initialized by controller as described in the Power up initialization Sequence. The SDRAM is ready for normal operation after the initialization sequence. 7.4.25.1 Deep Power Down Entry and Exit Timing Tc 2 tCK (min) CK_c CK_t tIHCKE Input clock frequency may be changed or the input clock stopped during Deep Power-Down CKE tINIT3 = 200 μs (min) tISCKE tISCKE CS_n [Cmd] NOP Enter DPD Exit NOP NOP DPD NOP tRP Reset tDPD Exit Deep Power-Down mode Enter Deep Power-Down mode Notes: 1. Initialization sequence may start at any time after TC. 2. tINIT3 and TC refer to timings in the LPDDR2 initialization sequence. For more detail, see section 7.2 “Power-up, Initialization, and PowerOff”. 3. Input clock frequency may be changed or the input clock stopped during deep power-down, provided that upon exiting deep power-down, the clock is stable and within specified limits for a minmum of 2 clock cycles prior to deep power-down exit and the clock frequency is between the minimum and maximum frequency for the particular speed grade. 7.4.26 Input Clock Stop and Frequency Change LPDDR2 devices support input clock frequency change during CKE LOW under the following conditions: • tCK(abs)min is met for each clock cycle; • Refresh Requirements apply during clock frequency change; • During clock frequency change, only REFab or REFpb commands may be executing; • Any Activate, or Precharge commands have executed to completion prior to changing the frequency; • The related timing conditions (tRCD, tRP) have been met prior to changing the frequency; • The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW; • The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH. After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to set the WR, RL etc. These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 66 - W979H6KB / W979H2KB LPDDR2 devices support clock stop during CKE LOW under the following conditions: • CK_t is held LOW and CK_c is held HIGH during clock stop; • Refresh Requirements apply during clock stop; • During clock stop, only REFab commands may be executing; • Any Activate, or Precharge commands have executed to completion prior to stopping the clock; • The related timing conditions (tRCD, tRP) have been met prior to stopping the clock; • The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW; • The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH. LPDDR2 devices support input clock frequency change during CKE HIGH under the following conditions: • tCK(abs)min is met for each clock cycle; • Refresh Requirements apply during clock frequency change; • Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have executed to completion, including any associated data bursts prior to changing the frequency; • The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to changing the frequency; • CS_n shall be held HIGH during clock frequency change; • During clock frequency change, only REFab commands may be executing; • The LPDDR2 device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of 2tCK + tXP. After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL etc. These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency. LPDDR2 devices support clock stop during CKE HIGH under the following conditions: • CK_t is held LOW and CK_c is held HIGH during clock stop; • CS_n shall be held HIGH during clock clock stop; • Refresh Requirements apply during clock stop; • During clock stop, only REFab commands may be executing; • Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have executed to completion, including any associated data bursts prior to stopping the clock; • The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to stopping the clock; • The LPDDR2 device is ready for normal operation after the clock is restarted and satisfies tCH(abs) and tCL(abs) for a minimum of 2tCK + tXP. 7.4.27 No Operation Command The purpose of the No Operation command (NOP) is to prevent the LPDDR2 device from registering any unwanted command between operations. Only when the CKE level is constant for clock cycle N-1 and clock cycle N, a NOP command may be issued at clock cycle N. A NOP command has two possible encodings: 1. CS_n HIGH at the clock rising edge N. 2. CS_n LOW and CA0, CA1, CA2 HIGH at the clock rising edge N. The No Operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.5 Truth Tables The truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of all the Banks. Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the LPDDR2 device must be powered down and then restarted through the specified initialization sequence before normal operation can continue. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 67 - W979H6KB / W979H2KB 7.5.1 Command Truth Table Command Pins Command MRW MRR Refresh (all bank) Enter Self Refresh CKE CK_t(n-1) CK_t(n) H H H H DDR CA Pins (10) CS_N CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 L L L L L MA0 MA1 MA2 MA3 MA4 MA5 X MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 L L L L H MA0 MA1 MA2 MA3 MA4 MA5 X MA6 MA7 L L L H X H H H L X L L H X L X H Write (bank) H Read (bank) H Precharge (per bank, all bank) H BST H X X L L H R8 R9 R10 R11 R12 BA0 BA1 X X R0 R1 R2 R3 R4 R5 R6 R7 X X L H L L RFU RFU C1 C2 BA0 BA1 X C3 C4 C5 C6 C7 C8 C9 X X H H 3,4 X AP* L H L H RFU RFU C1 C2 BA0 BA1 X X AP*3,4 C3 C4 C5 C6 C7 C8 C9 X X L H H L H AB X X BA0 BA1 X H H X L X H H L H L X H H L X X H Maintain PD,SREF,DPD (NOP) L NOP H Exit PD, SREF,DPD X X H H H L L X H X Enter Power Down X L L Maintain PD,SREF,DPD (NOP) L H X NOP X H X Activate (bank) Enter Deep Power Down CK_t EDGE X H H H X L X X H X X X H X X X H X X X H X X X H L H L X L H X Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 68 - W979H6KB / W979H2KB Notes: 1. All LPDDR2 commands are defined by states of CS_n, CA0, CA1, CA2, CA3, and CKE at the rising edge of the clock. 2. For LPDDR2 SDRAM, Bank addresses BA0 and BA1 (BA) determine which bank is to be operated upon. 3. AP is significant only to SDRAM. 4. AP “high” during a READ or WRITE command indicates that an auto-precharge will occur to the bank associated with the READ or WRITE command. 5. “X” means “H or L (but a defined logic level)”. 6. Self refresh exit and Deep Power Down exit are asynchronous. 7. VREF must be between 0 and VDDQ during Self Refresh and Deep Power Down operation. 8. CAxr refers to command/address bit “x” on the rising edge of clock. 9. CAxf refers to command/address bit “x” on the falling edge of clock. 10. CS_n and CKE are sampled at the rising edge of clock. 11. The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero. 12. AB “high”during Precharge command indicates that all bank Precharge will occur. In this case, Bank Address is do-not-care. 7.5.2 CKE Truth Table Device Current State*3 CKEn-1*1 CKEn*1 CS_n*2 Active Power Down Idle Power Down Resetting Power Down Command n*4 Operation n*4 Device Next State Maintain Active Power Down Active Power Down L L X X L H H NOP Exit Active Power Down Active L L X X Maintain Idle Power Down Idle Power Down L H H NOP Exit Idle Power Down Idle Resetting Power Down L L X X Maintain Resetting Power Down L H H NOP Exit Resetting Power Down Idle or Resetting Deep Power Down L L X X Maintain Deep Power Down L H H NOP Exit Deep Power Down Power On L L X X Maintain Self Refresh Self Refresh L H H NOP Exit Self Refresh Idle H L H NOP Enter Active Power Down Active Power Down H L H NOP Enter Idle Power Down Idle Power Dow H L L Enter Self Refresh Enter Self Refresh Self Refresh H L L Deep Power Down Enter Deep Power Down Deep Power Down Resetting H L H NOP Enter Resetting Power Down Resetting Power Down Others states H H Deep Power Down Self Refresh Bank(s) Active All Banks Idle Notes 6, 9 6, 9 6, 9, 12 8 7, 10 Refer to the Command Truth Table Notes: 1. “CKEn” is the logic state of CKE at clock rising edge n; “CKEn-1” was the state of CKE at the previous clock edge. 2. “CS_n” is the logic state of CS_n at the clock rising edge n; 3. “Current state” is the state of the LPDDR2 device immediately prior to clock edge n. 4. “Command n” is the command registered at clock edge N, and “Operation n” is a result of “Command n”. 5. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 6. Power Down exit time (tXP) should elapse before a command other than NOP is issued. 7. Self-Refresh exit time (tXSR) should elapse before a command other than NOP is issued. 8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Func tional Description. 9. The clock must toggle at least once during the tXP period. 10. The clock must toggle at least once during the tXSR time. 11. X’ means ‘Don’t care’. 12. Upon exiting Resetting Power Down, the device will return to the Idle state if tINIT5 has expired. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 69 - W979H6KB / W979H2KB 7.5.3 Current State Bank n - Command to Bank n Truth Table Current State Any Command NOP ACTIVATE Refresh (All Bank) Idle Reading Writing Next State Continue previous operation Current State Select and activate row Begin to refresh Notes Active Refreshing(All Bank) 6 MR Writing 6 MRW Load value to Mode Register MRR Read value from Mode Register Idle MR Reading Reset Begin Device Auto-Initialization Resetting 6, 7 Precharging 8, 14 Precharge Row Active Operation Deactivate row in bank or banks Read Select column, and start read burst Reading Write Select column, and start write burst Writing MRR Read value from Mode Register Active MR Reading Precharge Deactivate row in bank or banks Precharging 8 Reading 9, 10 Read Select column, and start new read burst Write Select column, and start write burst Writing 9, 10, 11 BST Read burst terminate Active 12 Write Select column, and start new write burst Writing 9, 10 Read Select column, and start read burst Reading 9, 10, 13 BST Write burst terminate Active 12 6, 8 Power On Reset Begin Device Auto-Initialization Resetting Resetting MRR Read value from Mode Register Resetting MR Reading Notes: 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Power Down. 2. All states and sequences not shown are illegal or reserved. 3. Current State Definitions: Idle: The bank or banks have been precharged, and tRP has been met. Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accessesare in progress. Reading: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Writing: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other banks are determined by its current state and 7.5.3 “Current State Bank n - Command to Bank n Truth Table”, and according to 7.5.4 “Current State Bank n - Command to Bank m Truth Table”. Precharging: starts with the registration of a Precharge command and ends when t RP is met. Once tRP is met, the bank will be in the idle state. Row Activating: starts with registration of an Activate command and ends when tRCD is met. Once tRCD is met, the bank will be in the ‘Active’ state. Read with AP Enabled: starts with the registration of the Read command with Auto Precharge enabled and ends when t RP has been met. Once tRP has been met, the bank will be in the idle state. Write with AP Enabled: starts with registration of a Write command with Auto Precharge enabled and ends when t RP has been met. Once tRP is met, the bank will be in the idle state. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 70 - W979H6KB / W979H2KB 5. The following states must not be interrupted by any executable command; NOP commands must be applied to each positive clock edge during these states. Refreshing (All Bank): starts with registration of a Refresh (All Bank) command and ends when tRFCab is met. Once tRFCab is met, the device will be in an ‘all banks idle’ state. Idle MR Reading: starts with the registration of a MRR command and ends when t MRR has been met. Once tMRR has been met, the bank will be in the Idle state. Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Resetting state. Active MR Reading: starts with the registration of a MRR command and ends when t MRR has been met. Once tMRR has been met, the bank will be in the Active state. MR Writing: starts with the registration of a MRW command and ends when t MRW has been met. Once tMRW has been met, the bank will be in the Idle state. Precharging All: starts with the registration of a Precharge-All command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. 6. Not bank-specific; requires that all banks are idle and no bursts are in progress. 7. Not bank-specific reset command is achieved through Mode Register Write command. 8. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for pre- charging. 9. A command other than NOP should not be issued to the same bank while a Read or Write burst with Auto Precharge is enabled. 10. The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled. 11. A Write command may be applied after the completion of the Read burst; otherwise, a BST must be used to end the Read prior to asserting a Write command. 12. Not bank-specific. Burst Terminate (BST) command affects the most recent read/write burst started by the most recent Read/Write command, regardless of bank. 13. A Read command may be applied after the completion of the Write burst; otherwise, a BST must be used to end the Write prior to asserting a Read command. 14. If a Precharge command is issued to a bank in the Idle state, tRP shall still apply. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 71 - W979H6KB / W979H2KB 7.5.4 Current State Bank n - Command to Bank m Truth Table Current State of Bank n Command for Bank m Any NOP Continue previous operation Idle Any Any command allowed to Bank m - 18 Activate Select and activate row in Bank m Active 7 Reading 8 Writing 8 Row Activating, Active, or Precharging Reading (Autoprecharge disabled) Read Select column, and start read burst from Bank m Write Select column, and start write burst to Bank m Current State of Bank m Precharging 9 MRR Read value from Mode Register Idle MR Reading or Active MR Readin 10, 11, 13 BST Read or Write burst terminate an ongoing Read/Write from/to Bank m Active 18 Read Select column, and start read burst from Bank m Reading 8 Write Select column, and start write burst to Bank m Writing 8, 14 Activate Select and activate row in Bank m Deactivate row in bank or banks Active Precharging 9 Reading 8, 16 8 Read Select column, and start read burst from Bank m Write Select column, and start write burst to Bank m Writing Select and activate row in Bank m Active Activate Deactivate row in bank or banks Precharging 9 Reading 8, 15 8, 14, 15 Read Select column, and start read burst from Bank m Write Select column, and start write burst to Bank m Writing Select and activate row in Bank m Active Activate Precharge Writing with Autoprecharge Notes Deactivate row in bank or banks Precharge Reading with Autoprecharge Next State for Bank m Precharge Precharge Writing (Autoprecharge disabled) Operation Deactivate row in bank or banks Read Select column, and start read burst from Bank m Write Select column, and start write burst to Bank m Activate Select and activate row in Bank m Precharging 9 Reading 8, 15, 16 Writing 8, 15 Active Precharge Deactivate row in bank or banks Precharging 9 Power On Reset Begin Device Auto-Initialization Resetting 12, 17 Resetting MRR Read value from Mode Register Resetting MR Reading Notes: 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2. All states and sequences not shown are illegal or reserved. 3. Current State Definitions: Idle: the bank has been precharged, and tRP has been met. Active: a row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Reading: a Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Writing: a Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 72 - W979H6KB / W979H2KB 4. Refresh, Self-Refresh, and Mode Register Write commands may only be issued when all bank are idle. 5. A Burst Terminate (BST) command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. The following states must not be interrupted by any executable command; NOP commands must be applied during each clock cycle while in these states: Idle MR Reading: starts with the registration of a MRR command and ends when t MRR has been met. Once tMRR has been met, the bank will be in the Idle state. Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Resetting state. Active MR Reading: starts with the registration of a MRR command and ends when t MRR has been met. Once tMRR has been met, the bank will be in the Active state. MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will be in the Idle state. 7. tRRD must be met between Activate command to Bank n and a subsequent Activate command to Bank m. 8. Reads or Writes listed in the Command column include Reads and Writes with Auto Precharge enabled and Reads and Writes with Auto Precharge disabled. 9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for pre- charging. 10. MRR is allowed during the Row Activating state (Row Activating starts with registration of an Activate command and ends when tRCD is met). 11. MRR is allowed during the Precharging state. (Precharging starts with registration of a Precharge command and ends when tRP is met. 12. Not bank-specific; requires that all banks are idle and no bursts are in progress. 13. The next state for Bank m depends on the current state of Bank m (Idle, Row Activating, Precharging, or Active). The reader shall note that the state may be in transition when a MRR is issued. Therefore, if Bank m is in the Row Activating state and Precharging, the next state may be Active and Precharge dependent upon tRCD and tRP respectively. 14. A Write command may be applied after the completion of the Read burst; otherwise a BST must be issued to end the Read prior to asserting a Write command. 15. Read with auto precharge enabled or a Write with auto precharge enabled may be followed by any valid command to other banks provided that the timing restrictions in 7.4.14.2 “Precharge & Auto Precharge Clarification” table are followed. 16. A Read command may be applied after the completion of the Write burst; otherwise, a BST must be issued to end the Write prior to asserting a Read command. 17. Reset command is achieved through Mode Register Write command. 18. BST is allowed only if a Read or Write burst is ongoing. 7.5.5 Data Mask Truth Table Name (Functional) DM DQs Note Write enable L Valid 1 Write inhibit H X 1 Note: 1. Used to mask write data, provided coincident with the corresponding data. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 73 - W979H6KB / W979H2KB 8. ELECTRICAL CHARACTERISTIC 8.1 Absolute Maximum DC Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Symbol Min Max Units Notes VDD1 supply voltage relative to VSS VDD1 -0.4 +2.3 V 2 VDD2 supply voltage relative to VSS VDD2 -0.4 +1.6 V 2 VDDCA supply voltage relative to VSSCA VDDCA -0.4 +1.6 V 2, 4 VDDQ supply voltage relative to VSSQ VDDQ -0.4 +1.6 V 2, 3 VIN, VOUT -0.4 +1.6 V TSTG -55 +125 °C Voltage on any ball relative to VSS Storage Temperature 5 Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. See “Power Ramp” in section 7.2.1 “Power Ramp and Device Initialization” for relationships between power supplies. 3. VREFDQ ≤ 0.6 x VDDQ; however, VREFDQ may be ≥ VDDQ provided that VREFDQ ≤ 300mV. 4. VREFCA ≤ 0.6 x VDDCA; however, VREFCA may be ≥ VDDCA provided that VREFCA ≤ 300mV. 5. Storage Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement conditions, please refer to JESD51-2 standard. 8.2 AC & DC Operating Conditions Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the LPDDR2 Device must be powered down and then restarted through the specialized initialization sequence before normal operation can continue. 8.2.1 Recommended DC Operating Conditions 8.2.1.1 Recommended DC Operating Conditions Symbol LPDDR2-S4B DRAM Unit 1.95 Core Power1 V 1.20 1.30 Core Power2 V 1.14 1.20 1.30 Input Buffer Power V 1.14 1.20 1.30 I/O Buffer Power V Min Typ Max VDD1 1.70 1.80 VDD2 1.14 VDDCA VDDQ Note: VDD1 uses significantly less power than VDD2. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 74 - W979H6KB / W979H2KB 8.2.2 Input Leakage Current Parameter/Condition Symbol Min Max Unit Notes IL -2 2 µA 2 IVREF -1 1 µA 1 Input Leakage current For CA, CKE, CS_n, CK_t, CK_c Any input 0V ≤ VIN ≤ VDDCA (All other pins not under test = 0V) VREF supply leakage current VREFDQ = VDDQ/2 or VREFCA = VDDCA/2 (All other pins not under test = 0V) Notes: 1. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be minimal. 2. Although DM is for input only, the DM leakage shall match the DQ and DQS_t/DQS_c output leakage specification. 8.2.3 Operating Temperature Conditions Parameter/Condition Symbol Standard TOPER Extended Min Max Unit -40 85 °C 85 105 °C Notes: 1. Operating Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement conditions, please refer to JESD51-2 standard. 2. Some applications require operation of LPDDR2 in the maximum temperature conditons in the Extended Temperature Range between 85°C and 105°C case temperature. For LPDDR2 devices, some derating is neccessary to operate in this range. See the MR4 Device Temperature (MA[7:0] = 04h) table. 3. Either the device operating temperature or the temperature sensor (See section 7.4.20 “Temperature Sensor”) may be used to set an appropriate refresh rate, determine the need for AC timing derating and/or monitor the operating temperature. When using the temperature sensor, the actual device case temperature may be higher than the TOPER rating that applies for the Standard or Extended Temperature Ranges. For example, TCASE may be above 85ºC when the temperature sensor indicates a temperature of less than 85°C. 4. All parts list in section 3 ordering information table will not guarantee to meet AC specification in the range of extended temperature range. 8.2.4 AC and DC Input Measurement Levels 8.2.4.1 AC and DC Logic Input Levels for Single-Ended Signals 8.2.4.1.1 Single-Ended AC and DC Input Levels for CA and CS_n Inputs Symbol LPDDR2-800/1066 Parameter Min Max Unit Notes VIHCA(AC) AC input logic high Vref + 0.220 Note 2 V 1, 2 VILCA(AC) AC input logic low Note 2 Vref - 0.220 V 1, 2 VIHCA(DC) DC input logic high Vref + 0.130 VDDCA V 1 VILCA(DC) DC input logic low VSSCA Vref - 0.130 V 1 VRefCA(DC) Reference Voltage for CA and CS_n inputs 0.49 * VDDCA 0.51 * VDDCA V 3, 4 Notes: 1. For CA and CS_n input only pins. Vref = VrefCA(DC). 2. See section 8.2.5.5 “Overshoot and Undershoot Specifications”. 3. The ac peak noise on VRefCA may not allow VRefCA to deviate from VRefCA(DC) by more than ± 1% VDDCA (for reference: approx. ± 12 mV). 4. For reference: approx. VDDCA/2 ± 12 mV. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 75 - W979H6KB / W979H2KB 8.2.4.1.2 Single-Ended AC and DC Input Levels for CKE Symbol Parameter Min Max Unit Note VIHCKE CKE Input High Level 0.8 * VDDCA Note 1 V 1 VILCKE CKE Input Low Level Note 1 0.2 * VDDCA V 1 Note 1: See section 8.2.5.5 “Overshoot and Undershoot Specifications”. 8.2.4.1.3 Single-Ended AC and DC Input Levels for DQ and DM Symbol Parameter VIHDQ(AC) AC input logic high LPDDR2-1066/LPDDR2-800 Unit Notes Note 2 V 1, 2 Min Max Vref + 0.220 VILDQ(AC) AC input logic low Note 2 Vref - 0.220 V 1, 2 VIHDQ(DC) DC input logic high Vref + 0.130 VDDQ V 1 VILDQ(DC) DC input logic low VSSQ Vref - 0.130 V 1 VRefDQ(DC) Reference Voltage for DQ, DM inputs 0.49 * VDDQ 0.51 * VDDQ V 3, 4 Notes: 1. For DQ input only pins. Vref = VrefDQ(DC). 2. See section 8.2.5.5 “Overshoot and Undershoot Specifications”. 3. The ac peak noise on VRefDQ may not allow VRefDQ to deviate from VRefDQ(DC) by more than ± 1% VDDQ (for reference: approx. ±12 mV). 4. For reference: approx. VDDQ/2 ± 12 mV. 8.2.4.2 Vref Tolerances The DC tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in below “VRef(DC) Tolerance and VRef AC-Noise Limits” figure. It shows a valid reference voltage VRef(t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VDD stands for VDDCA for VRefCA and VDDQ for VRefDQ. VRef(DC) is the linear average of VRef(t) over a very long period of time (e.g. 1 sec) and is specified as a fraction of the linear average of VDDQ or VDDCA also over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in 8.2.4.1.1 “Single-Ended AC and DC Input Levels for CA and CS_n Inputs” table. Furthermore VRef(t) may temporarily deviate from VRef(DC) by no more than ± 1% VDD. Vref(t) cannot track noise on VDDQ or VDDCA if this would send Vref outside these specifications. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 76 - W979H6KB / W979H2KB 8.2.4.2.1 VRef(DC) Tolerance and VRef AC-Noise Limits voltage VDD VRef (t) VRef ac-noise VRef (DC)max VDD/2 VRef (DC)min VRef (DC) VSS time The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef. “VRef” shall be understood as VRef(DC), as defined in above “VRef(DC) Tolerance and VRef AC-Noise Limits” figure. This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. Devices will function correctly with appropriate timing deratings with VREF outside these specified levels so long as VREF is maintained between 0.44 x VDDQ (or VDDCA) and 0.56 x VDDQ (or VDDCA) and so long as the controller achieves the required single-ended AC and DC input levels from instantaneous VRef (see 8.2.4.1.1 “Single-Ended AC and DC Input Levels for CA and CS_n Inputs” table and 8.2.4.1.3 “Single-Ended AC and DC Input Levels for DQ and DM” table) Therefore, system timing and voltage budgets need to account for VREF deviations outside of this range. This also clarifies that the LPDDR2 setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (± 1% of VDD) are included in LPDDR2 timings and their associated deratings. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 77 - W979H6KB / W979H2KB 8.2.4.3 Input Signal 8.2.4.3.1 LPDDR2-800/1066 Input Signal VIL and VIH Levels With Ringback 1.550V VDD + 0.35V 1.200V VDD 0.820V VIH(AC) 0.730V VIH(DC) 0.624V 0.612V 0.600V 0.588V 0.576V VREF + AC noise VREF + DC error VREF – DC error VREF – AC noise 0.470V VIL(DC) 0.380V VIL(AC) 0.000V VSS Minimum VIL and VIH Levels 0.820V 0.730V VIH(AC) VIH(DC) 0.624V 0.612V 0.600V 0.588V 0.576V 0.470V 0.380V VIL(DC) VIL(AC) -0.350V VSS – 0.35V Notes: 1. Numbers reflect nominal values. 2. For CA0-9, CK_t, CK_c, and CS_n, VDD stands for VDDCA. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ. 3. For CA0-9, CK_t, CK_c, and CS_n, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 78 - W979H6KB / W979H2KB 8.2.4.4 AC and DC Logic Input Levels for Differential Signals 8.2.4.4.1 Differential Signal Definition Differntial voltage tDVAC VIHDIFF(AC)MIN VIHDIFF(DC)MIN CK_t-CK_c DQS_t-DQS_c 0.0 VILDIFF(DC)MAX VILDIFF(AC)MAX Half cycle tDVAC time Figure of Definition of Differential AC-Swing and “Time above AC-Level” tDVAC 8.2.4.4.2 Differential swing requirements for clock (CK_t - CK_c) and strobe (DQS_t - DQS_c) Table of Differential AC and DC Input Levels Symbol Parameter LPDDR2-800/1066 Unit Notes Note 3 V 1 Note 3 2 x (VIL(dc) - Vref) V 1 Min Max 2 x (VIH(dc) - Vref) VIHdiff(dc) Differential input high VILdiff(dc) Differential input logic low VIHdiff(ac) Differential input high ac 2 x (VIH(ac) - Vref) Note 3 V 2 VILdiff(ac) Differential input low ac Note 3 2 x (VIL(ac) - Vref) V 2 Notes: 1. Used to define a differential signal slew-rate. For CK_t - CK_c use VIH/VIL(dc) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(dc) of DQs and VREFDQ; if a reduced dc-high or dc-low level is used for a signal group, then the reduced level applies also here. 2. For CK_t - CK_c use VIH/VIL(ac) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however the single-ended signals CK_t, CK_c, DQS_t, and DQS_c need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to section 8.2.5.5 “Overshoot and Undershoot Specifications”. 4. For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref = VrefDQ(DC). Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 79 - W979H6KB / W979H2KB Table of Allowed Time before Ringback (tDVAC) for CK_t - CK_c and DQS_t - DQS_c Slew Rate [V/nS] tDVAC [pS] @ |VIHdiff(ac) or VILdiff(ac)| = 440mV > 4.0 175 4.0 170 3.0 167 2.0 163 1.8 162 1.6 161 1.4 159 1.2 155 1.0 150 < 1.0 150 8.2.4.5 Single-Ended Requirements for Differential Signals Each individual component of a differential signal (CK_t, DQS_t, CK_c, or DQS_c) has also to comply with certain requirements for single-ended signals. CK_t and CK_c shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle. DQS_t, DQS_c shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle preceeding and following a valid transition. Note that the applicable ac-levels for CA and DQ’s are different per speed-bin. VDDCA or VDDQ VSEH(ac) VSEH(ac)min VDDCA/2 or VDDQ/2 CK_t,CK_ DQS_t, or DQS_c VSEL(ac)max VSEL(ac) VSSCA or VSSQ time Figure of Single-Ended Requirement for Differential Signals Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 80 - W979H6KB / W979H2KB Note that while CA and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDDQ/2 for DQS_t, DQS_c and VDDCA/2 for CK_t, CK_c; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSEL(ac)max, VSEH(ac)min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. The signal ended requirements for CK_t, CK_c, DQS_t and DQS_c are found in 8.2.4.1.1 “Single-Ended AC and DC Input Levels for CA and CS_n Inputs” table and 8.2.4.1.3 “Single-Ended AC and DC Input Levels for DQ and DM” table, respectively. Table of Single-Ended Levels for CK_t, DQS_t, CK_c, DQS_c Symbol VSEH(AC) VSEL(AC) LPDDR2-800/1066 Parameter Unit Notes Note 3 V 1, 2 (VDDCA/2) + 0.220 Note 3 V 1, 2 Single-ended low-level for strobes Note 3 (VDDQ/2) - 0.220 V 1, 2 Single-ended low-level for CK_t, CK_c Note 3 (VDDCA/2) - 0.220 V 1, 2 Min Max Single-ended high-level for strobes (VDDQ/2) + 0.220 Single-ended high-level for CK_t, CK_c Notes: 1. For CK_t, CK_c use VSEH/VSEL(ac) of CA; for strobes (DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c) use VIH/VIL(ac) of DQs. 2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VSEH(ac)/VSEL(ac) for CA is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however the single-ended signals CK_t, CK_c, DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to section 8.2.5.5 “Overshoot and Undershoot Specifications”. 8.2.4.6 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK_t, CK_c and DQS_t, DQS_c) must meet the requirements of above Single-ended levels for CK_t, DQS_t, CK_c, DQS_c table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS. VDDCA or VDDQ CK_c, DQS_c VIX VDDCA/2 or VDDQ/2 VIX VIX CK_t, DQS_t VSSCA or VSSQ Figure of Vix Definition Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 81 - W979H6KB / W979H2KB Table of Cross Point Voltage for Differential Input Signals (CK, DQS) Symbol LPDDR2-800/1066 Parameter Min Max Unit Notes VIXCA Differential Input Cross Point Voltage relative to VDDCA/2 for CK_t, CK_c - 120 120 mV 1, 2 VIXDQ Differential Input Cross Point Voltage relative to VDDQ/2 for DQS_t, DQS_c - 120 120 mV 1, 2 Notes: 1. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross. 2. For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref = VrefDQ(DC). 8.2.4.7 Slew Rate Definitions for Single-Ended Input Signals See section 8.7.2 “CA and CS_n Setup, Hold and Derating” for single-ended slew rate definitions for address and command signals. See section 8.7.3 “Data Setup, Hold and Slew Rate Derating” for single-ended slew rate definitions for data signals. 8.2.4.8 Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK_t, CK_c and DQS_t, DQS_c) are defined and measured as shown in below table and figure. Table of Differential Input Slew Rate Definition Measured Description Defined by from to Differential input slew rate for rising edge (CK_t - CK_c and DQS_t - DQS_c). VILdiffmax VIHdiffmin [VIHdiffmin - VILdiffmax] / DeltaTRdiff Differential input slew rate for falling edge (CK_t - CK_c and DQS_t - DQS_c). VIHdiffmin VILdiffmax [VIHdiffmin - VILdiffmax] / DeltaTFdiff Differential Input Voltage (i.e.DQS_t-DQS_c;CK_t-CK_c) Note: The differential signal (i.e. CK_t - CK_c and DQS_t - DQS_c) must be linear between these thresholds. Delta TRdiff VIHdiffmin 0 VILdiffmax Delta TFdiff Figure of Differential Input Slew Rate Definition for DQS_t, DQS_c and CK_t, CK_c Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 82 - W979H6KB / W979H2KB 8.2.5 AC and DC Output Measurement Levels 8.2.5.1 Single Ended AC and DC Output Levels Table of Single-Ended AC and DC Output Levels Symbol Parameter LPDDR2-800/1066 Unit Notes VOH(DC) DC output high measurement level (for IV curve linearity) 0.9 x VDDQ V 1 VOL(DC) DC output low measurement level (for IV curve linearity) 0.1 x VDDQ V 2 VOH(AC) AC output high measurement level (for output slew rate) VREFDQ + 0.12 V VOL(AC) AC output low measurement level (for output slew rate) VREFDQ - 0.12 V IOZ Output Leakage current (DQ, DM, DQS_t, DQS_c) (DQ, DQS_t, DQS_c are disabled;0V ≤ Vout ≤ VDDQ) MMPUPD Delta RON between pull-up and pull-down for DQ/DM Min -5 Max +5 Miin -15 Max +15 µA % Notes: 1. IOH = -0.1mA. 2. IOL = +0.1mA. 8.2.5.2 Differential AC and DC Output Levels Table of Differential AC and DC Output Levels of (DQS_t, DQS_c) Symbol Parameter LPDDR2-800/1066 Unit VOHdiff(AC) AC differential output high measurement level (for output SR) + 0.20 x VDDQ V VOLdiff(AC) AC differential output low measurement level (for output SR) - 0.20 x VDDQ V Notes Notes: 1. IOH = -0.1mA. 2. IOL = +0.1mA. 8.2.5.3 Single Ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in below table and figure. Table of Single-Ended Output Slew Rate Definition Description Measured Defined by from to Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC) - VOL(AC)] / DeltaTRse Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC) - VOL(AC)] / DeltaTFse Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 83 - W979H6KB / W979H2KB Single Ended Output Vollage (i.e.DQ) Delta TRse VOH(AC) VREF VOL(AC) Delta TFse Figure of Single Ended Output Slew Rate Definiton Table of Output Slew Rate (Single-Ended) Symbol LPDDR2-800/1066 Parameter Min Max Units SRQse Single-ended Output Slew Rate (RON = 40Ω ± 30%) 1.5 3.5 V/nS SRQse Single-ended Output Slew Rate (RON = 60Ω ± 30%) 1.0 2.5 V/nS Output slew-rate matching Ratio (Pull-up to Pull-down) 0.7 1.4 Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals Notes: 1. Measured with output reference load. 2. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pulldown drivers due to process variation. 3. The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC). 4. Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic high and 1/2 of DQ signals per data byte driving logic low. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 84 - W979H6KB / W979H2KB 8.2.5.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in below table and figure. Table of Differential Output Slew Rate Definition Measured Description Defined by from to Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC) - VOLdiff(AC)] / DeltaTRdiff Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC) - VOLdiff(AC)] / DeltaTFdiff Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Differential Output VoltAge (i.e. DQS_t – DQS_c) Delta TRdiff VOHdiff(AC) 0 VOLdiff(AC) Delta TFdiff Figure of Differential Output Slew Rate Definition Table of Differential Output Slew Rate Symbol LPDDR2-800/1066 Parameter Min Max Units SRQdiff Differential Output Slew Rate (RON = 40Ω ± 30%) 3.0 7.0 V/nS SRQdiff Differential Output Slew Rate (RON = 60Ω ± 30%) 2.0 5.0 V/nS Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: differential Signals Notes: 1. Measured with output reference load. 2. The output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC). 3. Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of DQ signals per data byte driving logic-low. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 85 - W979H6KB / W979H2KB 8.2.5.5 Overshoot and Undershoot Specifications Table of AC Overshoot/Undershoot Specification Parameter 1066 933 800 LPDDR2 667 533 400 333 Unit Maximum peak amplitude allowed for overshoot area. (See figure below) Max 0.35 V Maximum peak amplitude allowed for undershoot area. (See figure below) Max 0.35 V Maximum area above VDD. (See figure below) Max 0.15 0.17 0.20 0.24 0.30 0.40 0.48 V-nS Maximum area below VSS. (See figure below) Max 0.15 0.17 0.20 0.24 0.30 0.40 0.48 V-nS (CA0-9, CS_n, CKE, CK_t, CK_c, DQ, DQS_t, DQS_c, DM) Notes: 1. For CA0-9, CK_t, CK_c, CS_n, and CKE, VDD stands for VDDCA. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ. 2. For CA0-9, CK_t, CK_c, CS_n, and CKE, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ. 3. Maximum peak amplitude values are referenced from actual VDD and VSS values. 4. Maximum area values are referenced from maximum operating VDD and VSS values. Maximum Amplitude Overshoot Area Volts (V) VDD VSS Undershoot Area Maximum Amplitude Time (ns) Figure of Overshoot and Undershoot Definition Notes: 1. For CA0-9, CK_t, CK_c, CS_n, and CKE, VDD stands for VDDCA. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ. 2. For CA0-9, CK_t, CK_c, CS_n, and CKE, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ. 3. Maximum peak amplitude values are referenced from actual VDD and VSS values. 4. Maximum area values are referenced from maximum operating VDD and VSS values. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 86 - W979H6KB / W979H2KB 8.2.6 Output buffer Characteristics 8.2.6.1 HSUL_12 Driver Output Timing Reference Load These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VREF 0.5 x VDDQ LPDDR2 SDRAM RTT = 50 Ω Output VTT = 0.5 x VDDQ Cload = 5pF Figure of HSUL_12 Driver Output Reference Load for Timing and Slew Rate Note: All output timing parameter values (like tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc.) are reported with respect to this reference load. This reference load is also used to report slew rate. 8.2.6.2 RONPU and RONPD Resistor Definition RONPU = (VDDQ – Vout ) ABS ( Iout ) Note: This is under the condition that RONPD is turned off RONPD = Vout ABS (Iout ) Note: This is under the condition that RONPU is turned off Chip in Drive Mode Output Driver VDDQ IPU To Other Circuityrt Like RCV, ... RONPU IOut RONPD DQ VOut IPD VSSQ Figure of Output Driver Definition of Voltages and Currents Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 87 - W979H6KB / W979H2KB 8.2.6.3 RONPU and RONPD Characteristics with ZQ Calibration Output driver impedance RON is defined by the value of the external reference resistor RZQ. Nominal RZQ is 240Ω. Table of Output Driver DC Electrical Characteristics with ZQ Calibration RONNOM 34.3Ω 40.0Ω 48.0Ω 60.0Ω 80.0Ω 120.0Ω Mismatch between pull-up and pull-down Resistor Vout Min Nom Max Unit Note RON34PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/7 1, 2, 3, 4 RON34PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/7 1, 2, 3, 4 RON40PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/6 1, 2, 3, 4 RON40PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/6 1, 2, 3, 4 RON48PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/5 1, 2, 3, 4 RON48PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/5 1, 2, 3, 4 RON60PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/4 1, 2, 3, 4 RON60PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/4 1, 2, 3, 4 RON80PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/3 1, 2, 3, 4 RON80PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/3 1, 2, 3, 4 RON120PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1, 2, 3, 4 RON120PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1, 2, 3, 4 +15.00 % 1, 2, 3, 4, 5 MMPUPD -15.00 Notes: 1. Across entire operating temperature range, after calibration. 2. RZQ = 240Ω. 3. The tolerance limits are specified after calibration with fixed voltage and temperature. For behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 4. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. 5. Mesaurement definition for mismatch between pull-up and pull-down: MMPUPD: Measure RONPU and RONPD, both at 0.5 x VDDQ: MMPUPD = RONPU – RONPD x 100 RONNOM For example, with MMPUPD(max) = 15% and RONPD = 0.85, RONPU must be less than 1.0. 8.2.6.4 Output Driver Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to the tables shown below. Table of Output Driver Sensitivity Definition Resistor RONPD RONPU Vout Min Max Unit Notes 0.5 x VDDQ 85 – (dR ONdT ×|ΔT| ) – (dRON d V × |ΔV| ) 115 + (dRONdT ×| ΔT| )+(dRONdV × |ΔV|) % 1, 2 Notes: 1. ΔT = T–T (@calibration), ΔV=V–V(@ calibration). 2. dRONdT and dRONdV are not subject to production test but are verified by design and characterization. Table of Output Driver Temperature and Voltage Sensitivity Symbol Parameter Min Max Unit dRONdT RON Temperature Sensitivity 0.00 0.75 % / °C dRONdV RON Voltage Sensitivity 0.00 0.20 % / mV Note Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 88 - W979H6KB / W979H2KB 8.2.6.5 RONPU and RONPD Characteristics without ZQ Calibration Output driver impedance RON is defined by design and characterization as default setting. Table of Output Driver DC Electrical Characteristics without ZQ Calibration RONNOM 34.3Ω 40.0Ω 48.0Ω 60.0Ω 80.0Ω 120.0Ω Resistor Vout Min Nom Max Unit Note RON34PD 0.5 x VDDQ 24 34.3 44.6 Ω 1 RON34PU 0.5 x VDDQ 24 34.3 44.6 Ω 1 RON40PD 0.5 x VDDQ 28 40 52 Ω 1 RON40PU 0.5 x VDDQ 28 40 52 Ω 1 RON48PD 0.5 x VDDQ 33.6 48 62.4 Ω 1 RON48PU 0.5 x VDDQ 33.6 48 62.4 Ω 1 RON60PD 0.5 x VDDQ 42 60 78 Ω 1 RON60PU 0.5 x VDDQ 42 60 78 Ω 1 RON80PD 0.5 x VDDQ 56 80 104 Ω 1 RON80PU 0.5 x VDDQ 56 80 104 Ω 1 RON120PD 0.5 x VDDQ 84 120 156 Ω 1 RON120PU 0.5 x VDDQ 84 120 156 Ω 1 Note: Across entire operating temperature range, without calibration. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 89 - W979H6KB / W979H2KB 8.2.6.6 RZQ I-V Curve Table of RZQ I-V Curve RON = 240Ω (RZQ) Voltage[V] Pull-Down Pull-Up Current [mA] / RON [Ohms] Current [mA] / RON [Ohms] default value after ZQReset default value after ZQReset With Calibration With Calibration Min Max Min Max Min Max Min Max [mA] [mA] [mA] [mA] [mA] [mA] [mA] [mA] 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.05 0.19 0.32 0.21 0.26 -0.19 -0.32 -0.21 -0.26 0.10 0.38 0.64 0.40 0.53 -0.38 -0.64 -0.40 -0.53 0.15 0.56 0.94 0.60 0.78 -0.56 -0.94 -0.60 -0.78 0.20 0.74 1.26 0.79 1.04 -0.74 -1.26 -0.79 -1.04 0.25 0.92 1.57 0.98 1.29 -0.92 -1.57 -0.98 -1.29 0.30 1.08 1.86 1.17 1.53 -1.08 -1.86 -1.17 -1.53 0.35 1.25 2.17 1.35 1.79 -1.25 -2.17 -1.35 -1.79 0.40 1.40 2.46 1.52 2.03 -1.40 -2.46 -1.52 -2.03 0.45 1.54 2.74 1.69 2.26 -1.54 -2.74 -1.69 -2.26 0.50 1.68 3.02 1.86 2.49 -1.68 -3.02 -1.86 -2.49 0.55 1.81 3.30 2.02 2.72 -1.81 -3.30 -2.02 -2.72 0.60 1.92 3.57 2.17 2.94 -1.92 -3.57 -2.17 -2.94 0.65 2.02 3.83 2.32 3.15 -2.02 -3.83 -2.32 -3.15 0.70 2.11 4.08 2.46 3.36 -2.11 -4.08 -2.46 -3.36 0.75 2.19 4.31 2.58 3.55 -2.19 -4.31 -2.58 -3.55 0.80 2.25 4.54 2.70 3.74 -2.25 -4.54 -2.70 -3.74 0.85 2.30 4.74 2.81 3.91 -2.30 -4.74 -2.81 -3.91 0.90 2.34 4.92 2.89 4.05 -2.34 -4.92 -2.89 -4.05 0.95 2.37 5.08 2.97 4.23 -2.37 -5.08 -2.97 -4.23 1.00 2.41 5.20 3.04 4.33 -2.41 -5.20 -3.04 -4.33 1.05 2.43 5.31 3.09 4.44 -2.43 -5.31 -3.09 -4.44 1.10 2.46 5.41 3.14 4.52 -2.46 -5.41 -3.14 -4.52 1.15 2.48 5.48 3.19 4.59 -2.48 -5.48 -3.19 -4.59 1.20 2.50 5.55 3.23 4.65 -2.50 -5.55 -3.23 -4.65 Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 90 - W979H6KB / W979H2KB 6 PD Max PD Min 4 PU Min PU Max mA 2 0 -2 -4 -6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Voltage Figure of RON = 240 Ohms IV Curve after ZQReset 6 PD Max PD Min 4 PU Min PU Max mA 2 0 -2 -4 -6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Voltage 0.8 0.9 1.0 1.1 1.2 Figure of RON = 240 Ohms IV Curve after Calibration Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 91 - W979H6KB / W979H2KB 8.2.6.7 Input/Output Capacitance Table of Input/Output Capacitance Parameter Symbol Min Max Units Note CPKGCK 1 3 pF 1, 2 CDPKGCK 0 0.2 pF 1, 2, 3 CPKGI 1 3 pF 1, 2, 4 Package Input capacitance delta, all other input-only pins CDPKGI -0.5 0.5 pF 1, 2, 5 Package Input/output capacitance, DQ, DM, DQS_t, DQS_c CPKGIO 1.25 3.5 pF 1, 2, 7 CDPKGDQS 0 0.25 pF 1, 2, 6 Package Input/output capacitance delta, DQ, DM CDPKGIO -0.5 0.5 pF 1, 2, 7 Package Input/output capacitance, ZQ Pin CPKGZQ 0 3.5 pF 1, 2 Package Input capacitance, CK_t and CK_c Package Input capacitance delta, CK_t and CK_c Package Input capacitance, all other input-only pins Package Input/output capacitance delta, DQS_t, DQS_c (TOPER; VDDQ = 1.14- 1.3V; VDDCA = 1.14-1.3V; VDD1 = 1.7-1.95V, LPDDR2-S4 VDD2 = 1.14-1.3V). Notes: 1. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147 (Procedure for measuring input capacitance using a vector network analyzer (VNA) with VDD1, VDD2, VDDQ, VSS, VSSCA, VSSQ applied and all other pins floating. 2. This parameter applies to package only (does not include die capacitance). This value is vendor specific. 3. Absolute value of CPKGCK_t - CPKGCK_c. 4. CPKGI applies to CS_n, CKE, CA0-CA9 5. CDPKGI = CPKGI - 0.5 * (CPKGDQS_t + CPKGDQS_c). 6. Absolute value of CPKGDQS_t and CPKGDQS_c. 7. CDPKGIO = CPKGIO - 0.5 * (CPKGDQS_t + CPKGDQS_c) in byte lane. 8. Maximum external load capacitance on ZQ pin, including packaging, board, pin, resistor, and other LPDDR2 devices: 5 pF. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 92 - W979H6KB / W979H2KB 8.3 IDD Specification Parameters and Test Conditions 8.3.1 IDD Measurement Conditions The following definitions are used within the IDD measurement tables: LOW: VIN ≤ VIL(DC) MAX HIGH: VIN ≥ VIH(DC) MIN STABLE: Inputs are stable at a HIGH or LOW level SWITCHING: See tables below. 8.3.1.1 Definition of Switching for CA Input Signals Switching for CA CK_t (RISING) / Ck_C (FALLING) CK_t (FALLING) / Ck_C (RISING) CK_t (RISING) / Ck_C (FALLING) CK_t (FALLING) / Ck_C (RISING) CK_t (RISING) / Ck_C (FALLING) CK_t (FALLING) / Ck_C (RISING) CK_t (RISING) / Ck_C (FALLING) CK_t (FALLING) / Ck_C (RISING) Cycle N N+1 N+2 N+3 CS_n HIGH HIGH HIGH HIGH CA0 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA1 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA2 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA3 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA4 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA5 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA6 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA7 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA8 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA9 HIGH HIGH HIGH LOW LOW LOW LOW HIGH Notes: 1. CS_n must always be driven HIGH. 2. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus. 3. The above pattern (N, N+1, N+2, N+3...) is used continuously during IDD measurement for IDD values that require SWITCHING on the CA bus. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 93 - W979H6KB / W979H2KB 8.3.1.2 Definition of Switching for IDD4R Clock CKE CS_n Clock Cycle Number Command CA0-CA2 CA3-CA9 All DQ Rising HIGH LOW N Read_Rising HLH LHLHLHL L Falling HIGH LOW N Read_Falling LLL LLLLLLL L Rising HIGH HIGH N+1 NOP LLL LLLLLLL H Falling HIGH HIGH N+1 NOP HLH HLHLLHL L Rising HIGH LOW N+2 Read_Rising HLH HLHLLHL H Falling HIGH LOW N+2 Read_Falling LLL HHHHHHH H Rising HIGH HIGH N+3 NOP LLL HHHHHHH H Falling HIGH HIGH N+3 NOP HLH LHLHLHL L Notes: 1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle. 2. The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4R. 8.3.1.3 Definition of Switching for IDD4W Clock CKE CS_n Clock Cycle Number Command CA0-CA2 CA3-CA9 All DQ Rising HIGH LOW N Write_Rising HLL LHLHLHL L Falling HIGH LOW N Write_Falling LLL LLLLLLL L Rising HIGH HIGH N+1 NOP LLL LLLLLLL H Falling HIGH HIGH N+1 NOP HLH HLHLLHL L Rising HIGH LOW N+2 Write_Rising HLL HLHLLHL H Falling HIGH LOW N+2 Write_Falling LLL HHHHHHH H Rising HIGH HIGH N+3 NOP LLL HHHHHHH H Falling HIGH HIGH N+3 NOP HLH LHLHLHL L Notes: 1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle. 2. Data masking (DM) must always be driven LOW. 3. The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4W. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 94 - W979H6KB / W979H2KB 8.3.2 IDD Specifications 8.3.2.1 LPDDR2 IDD Specification Parameters and Operating Conditions, 85°C (x16, x32) Parameter/Condition Symbol 533 MHz Unit Notes Operating one bank active-precharge current: tCK = tCK(avg)min; tRC = tRCmin; CKE is HIGH; CS_n is HIGH between valid commands; CA bus inputs are SWITCHING; Data bus inputs are STABLE Idle power-down standby current: tCK = tCK(avg)min; CKE is LOW; CS_n is HIGH; All banks/RBs idle; CA bus inputs are SWITCHING; Data bus inputs are STABLE Idle power-down standby current with clock stop: CK_t =LOW, CK_c =HIGH; CKE is LOW; CS_n is HIGH; All banks/RBs idle; CA bus inputs are STABLE; Data bus inputs are STABLE Idle non power-down standby current: tCK = tCK(avg)min; CKE is HIGH; CS_n is HIGH; All banks/RBs idle; CA bus inputs are SWITCHING; Data bus inputs are STABLE Idle non power-down standby current with clock stop: CK_t =LOW, CK_c =HIGH; CKE is HIGH; CS_n is HIGH; All banks/RBs idle; CA bus inputs are STABLE; Data bus inputs are STABLE Active power-down standby current: tCK = tCK(avg)min; CKE is LOW; CS_n is HIGH; One bank/RB active; CA bus inputs are SWITCHING; Data bus inputs are STABLE Active power-down standby current with clock stop: CK_t=LOW, CK_c=HIGH; CKE is LOW; CS_n is HIGH; One bank/RB active; CA bus inputs are STABLE; Data bus inputs are STABLE Active non power-down standby current: tCK = tCK(avg)min; CKE is HIGH; CS_n is HIGH; One bank/RB active; CA bus inputs are SWITCHING; Data bus inputs are STABLE Active non power-down standby current with clock stop: CK_t=LOW, CK_c=HIGH; CKE is HIGH; CS_n is HIGH; One bank/RB active; CA bus inputs are STABLE; Data bus inputs are STABLE IDD01 IDD02 Power Supply 400 MHz VDD1 VDD2 5 25 5 25 mA mA 1 1 IDD0IN VDDCA VDDQ 5.5 5.5 mA 1, 2 IDD2P1 IDD2P2 VDD1 VDD2 300 400 300 400 µA µA 1 1 IDD2PIN VDDCA VDDQ 35 35 µA 1, 2 IDD2PS1 IDD2PS2 VDD1 VDD2 300 400 300 400 µA µA 1 1 IDD2PSIN VDDCA VDDQ 35 35 µA 1, 2 IDD2N1 IDD2N2 VDD1 VDD2 0.3 13 0.3 15 mA mA 1 1 IDD2NIN VDDCA VDDQ 5 5 mA 1, 2 IDD2NS1 IDD2NS2 VDD1 VDD2 0.3 12 0.3 14 mA mA 1 1 IDD2NSIN VDDCA VDDQ 5 5 mA 1, 2 IDD3P1 IDD3P2 VDD1 VDD2 600 700 600 700 µA µA 1 1 IDD3PIN VDDCA VDDQ 35 35 µA 1, 2 IDD3PS1 IDD3PS2 VDD1 VDD2 600 700 600 700 µA µA 1 1 IDD3PSIN VDDCA VDDQ 35 35 µA 1, 2 IDD3N1 IDD3N2 VDD1 VDD2 0.6 16 0.6 18 mA mA 1 1 IDD3NIN VDDCA VDDQ 5 5 mA 1, 2 IDD3NS1 IDD3NS2 VDD1 VDD2 0.6 13 0.6 14 mA mA 1 1 IDD3NSIN VDDCA VDDQ 5 5 mA 1, 2 Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 95 - W979H6KB / W979H2KB Parameter/Condition Operating burst read current: tCK = tCK(avg)min; CS_n is HIGH between valid commands; One bank/RB active; BL = 4; RL = RLmin; CA bus inputs are SWITCHING; 50% data change each burst transfer Operating burst write current: tCK = tCK(avg)min; CS_n is HIGH between valid commands; One bank/RB active; BL = 4; WL = WLmin; CA bus inputs are SWITCHING; 50% data change each burst transfer All Bank Refresh Burst current: tCK = tCK(avg)min; CKE is HIGH between valid commands; tRC = tRFCabmin; Burst refresh; CA bus inputs are SWITCHING; Data bus inputs are STABLE; All Bank Refresh Average current: tCK = tCK(avg)min; CKE is HIGH between valid commands; tRC = tREFI; CA bus inputs are SWITCHING; Data bus inputs are STABLE; Deep Power-Down current: CK_t=LOW, CK_c=HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE; Symbol Power Supply 400 MHz 533 MHz Unit Notes IDD4R1 VDD1 1.3 1.3 mA 1 IDD4R2 VDD2 165 170 mA 1 IDD4RIN VDDCA 4.5 4.5 mA 1 IDD4W1 VDD1 1.3 1.3 mA 1 IDD4W2 VDD2 175 195 mA 1 IDD4WIN VDDCA VDDQ 19.1 19.1 mA 1, 2 IDD51 VDD1 15 15 mA 1 IDD52 VDD2 45 55 mA 1 IDD5IN VDDCA VDDQ 5 5 mA 1, 2 IDD5AB1 VDD1 1 1 mA 1 IDD5AB2 VDD2 13 14 mA 1 IDD5ABIN VDDCA VDDQ 5 5 mA 1, 2 IDD81 VDD1 10 10 µA 1 IDD82 VDD2 10 10 µA 1 IDD8IN VDDCA VDDQ 35 35 µA 1, 2 Notes: 1. IDD values published are the maximum of the distribution of the arithmetic mean. 2. Measured currents are the summation of VDDQ and VDDCA. 3. IDD current specifications are tested after the device is properly initialized. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 96 - W979H6KB / W979H2KB 8.3.2.2 IDD6 Partial Array Self-Refresh Current, 85°C (x16, x32) Parameter Full Array IDD6 Partial Array Self-Refresh Current 1/2 Array 1/4 Array Symbol Power Supply 400 MHz 533 MHz IDD61 VDD1 550 550 IDD62 VDD2 650 650 IDD6IN VDDCA VDDQ 35 35 IDD61 VDD1 500 500 IDD62 VDD2 550 550 IDD6IN VDDCA VDDQ 35 35 IDD61 VDD1 450 450 IDD62 VDD2 500 500 IDD6IN VDDCA VDDQ 35 35 Condition Unit µA Self refresh current CK_t=LOW, CK_c=HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE; µA µA Notes: 1. LPDDR2-S4 SDRAM uses the same PASR scheme & IDD6 current value categorization as LPDDR (JESD209). 2. IDD values published are the maximum of the distribution of the arithmetic mean. 3. Condition: temperature 85°C, self refresh window is 64 mS. 8.4 Clock Specification The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the LPDDR2 device. 8.4.1 Definition for tCK(avg) and nCK tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. tCK(avg) = where      tCK j  /  j 1  N  N N = 200 Unit ‘tCK(avg)’ represents the actual clock average tCK(avg) of the input clock under operation. Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges. tCK(avg) may change by up to ± 1% within a 100 clock cycle window, provided that all jitter and timing specs are met. 8.4.2 Definition for tCK(abs) tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 97 - W979H6KB / W979H2KB 8.4.3 Definition for tCH(avg) and tCL(avg) tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. N  tCH(avg) =  tCH j  / (N × tCK(avg))  j 1  where N = 200 tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. N  tCL(avg) =  tCL j  / (N × tCK(avg))  j 1  where N = 200 8.4.4 Definition for tJIT(per) tJIT(per) is the single period jitter defined as the largest deviation of any signal tCK from tCK(avg). tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}. tJIT(per),act is the actual clock jitter for a given system. tJIT(per),allowed is the specified allowed clock period jitter. tJIT(per) is not subject to production test. 8.4.5 Definition for tJIT(cc) tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles. tJIT(cc) = Max of |{tCKi +1 - tCKi}|. tJIT(cc) defines the cycle to cycle jitter. tJIT(cc) is not subject to production test. 8.4.6 Definition for tERR(nper) tERR(nper) is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR(nper),act is the actual clock jitter over n cycles for a given system. tERR(nper),allowed is the specified allowed clock period jitter over n cycles. tERR(nper) is not subject to production test. tERR(nper) = in1   tCK j  –    j i   n × tCK(avg) tERR(nper),min can be calculated by the formula shown below: tERR(nper), min = (1 + 0.68LN(n)) × tJIT(per), min tERR(nper),max can be calculated by the formula shown below: tERR(nper), max = (1 + 0.68LN(n)) × tJIT(per), max Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 98 - W979H6KB / W979H2KB 8.4.7 Definition for Duty Cycle Jitter tJIT(duty) tJIT(duty) is defined with absolute and average specification of tCH / tCL. tJIT(duty),min = MIN((tCH(abs),min – tCH(avg),min),(tCL(abs),min – tCL(avg),min)) x tCK(avg) tJIT(duty),max = MAX((tCH(abs),max – tCH(avg),max),(tCL(abs),max – tCL(avg),max)) x tCK(avg) 8.4.8 Definition for tCK(abs), tCH(abs) and tCL(abs) These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. Table of Definition for tCK(abs), tCH(abs), and tCL(abs) Parameter Symbol Min Unit Absolute Clock Period tCK(abs) tCK(avg),min + tJIT(per),min pS Absolute Clock HIGH Pulse Width tCH(abs) tCH(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg) Absolute Clock LOW Pulse Width tCL(abs) tCL(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg) Notes: 1. tCK(avg),min is expressed is pS for this table. 2. tJIT(duty),min is a negative value. 8.5 Period Clock Jitter LPDDR2 devices can tolerate some clock period jitter without core timing parameter de-rating. This section describes device timing requirements in the presence of clock period jitter (tJIT(per)) in excess of the values found in section 8.7.1 “LPDDR2 AC Timing” table and how to determine cycle time de-rating and clock cycle de-rating. 8.5.1 Clock Period Jitter Effects on Core Timing Parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) Core timing parameters extend across multiple clock cycles. Period clock jitter will impact these parameters when measured in numbers of clock cycles. When the device is operated with clock jitter within the specification limits, the LPDDR2 device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}. When the device is operated with clock jitter outside specification limits, the number of clocks or tCK(avg) may need to be increased based on the values for each core timing parameter. 8.5.1.1 Cycle Time De-rating for Core Timing Parameters For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error (tERR(tnPARAM),allowed), the equation below calculates the amount of cycle time de-rating (in nS) required if the equation results in a positive value for a core timing parameter (tCORE).   CycleTimeDerating = MAX  tPARAM  tERR(tnPARAM), act  tERR(tnPARAM), allowed  tCK (avg) , 0  tnPARAM   A cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time derating required is the maximum of the cycle time de-ratings determined for each individual core timing parameter. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 99 - W979H6KB / W979H2KB 8.5.1.2 Clock Cycle De-rating for Core Timing Parameters For a given number of clocks (tnPARAM) for each core timing parameter, clock cycle de-rating should be specified with amount of period jitter (tJIT(per)). For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error (tERR(tnPARAM),allowed), the equation below calculates the clock cycle derating (in clocks) required if the equation results in a positive value for a core timing parameter (tCORE).   ClockCycleDerating = RU tPARAM  tERR(tnPARAM), act  tERR(tnPARAM), allowed  tnPARAM   tCK (avg) A clock cycle de-rating analysis should be conducted for each core timing parameter. 8.5.2 Clock Jitter Effects on Command/Address Timing Parameters (tIS, tIH, tISCKE, tIHCKE, tISb, tIHb, tISCKEb, tIHCKEb) These parameters are measured from a command/address signal (CKE, CS, CA0 - CA9) transition edge to its respective clock signal (CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values shall be met. 8.5.3 Clock Jitter Effects on Read Timing Parameters 8.5.3.1 tRPRE When the device is operated with input clock jitter, tRPRE needs to be de-rated by the actual period jitter (tJIT(per),act,max) of the input clock in excess of the allowed period jitter (tJIT(per),allowed,max). Output de-ratings are relative to the input clock.  tJIT ( per ), act ,max  tJIT ( per ),allowed ,max    tCK (avg)   tRPRE(min, derated) = 0.9   For example, if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500 pS, tJIT(per),act,min = -172 pS and tJIT(per),act,max = + 193 pS, then tRPRE,min,derated = 0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500= .8628 tCK(avg) 8.5.3.2 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) These parameters are measured from a specific clock edge to a data signal (DMn, DQm.: n=0,1,2,3. m=0–31) transition and will be met with respect to that clock edge. Therefore, they are not affected by the amount of clock jitter applied (i.e. tJIT(per). 8.5.3.3 tQSH, tQSL These parameters are affected by duty cycle jitter which is represented by tCH(abs)min and tCL(abs)min. tQSH(abs)min = tCH(abs)min – 0.05 tQSL(abs)min = tCL(abs)min – 0.05 These parameters determine absolute Data-Valid window at the LPDDR2 device pin. Absolute min data-valid window @ LPDDR2 device pin = min { ( tQSH(abs)min * tCK(avg)min – tDQSQmax – tQHSmax ) , ( tQSL(abs)min * tCK(avg)min – tDQSQmax – tQHSmax ) } This minimum data-valid window shall be met at the target frequency regardless of clock jitter. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 100 - W979H6KB / W979H2KB 8.5.3.4 tRPST tRPST is affected by duty cycle jitter which is represented by tCL(abs). Therefore tRPST(abs)min can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min – 0.05 = tQSL(abs)min 8.5.4 Clock Jitter Effects on Write Timing Parameters 8.5.4.1 tDS, tDH These parameters are measured from a data signal (DMn, DQm.: n=0,1,2,3. m=0–31) transition edge to its respective data strobe signal (DQSn_t, DQSn_c: n=0,1,2,3) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values shall be met. 8.5.4.2 tDSS, tDSH These parameters are measured from a data strobe signal (DQSx_t, DQSx_c) crossing to its respective clock signal (CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values shall be met. 8.5.4.3 tDQSS This parameter is measured from a data strobe signal (DQSx_t, DQSx_c) crossing to the subsequent clock signal (CK_t/CK_c) crossing. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual period jitter tJIT(per),act of the input clock in excess of the allowed period jitter tJIT(per),allowed. tDQSS(min, derated) = 0.75  tJIT ( per ), act ,min  tJIT ( per ),allowed ,min tCK (avg) tDQSS(max, derated) = 1.25  tJIT ( per ), act ,max  tJIT ( per ),allowed ,max tCK (avg) For example, if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500 pS, tJIT(per),act,min = -172 pS and tJIT(per),act,max = + 193 pS, then tDQSS,(min,derated) = 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) = 0.75 - (-172 + 100)/2500 = .7788 tCK(avg) and tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 1.25 - (193 - 100)/2500 = 1.2128 tCK(avg) Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 101 - W979H6KB / W979H2KB 8.6 8.6.1 Refresh Requirements Refresh Requirement Parameters Parameter Symbol Number of Banks 512Mb Unit 4 Refresh Window TCASE ≤ 85°C tREFW 32 R 4,096 tREFI 7.8 µS Refresh Cycle time tRFCab 90 nS Burst Refresh Window = 4 x 8 x tRFCab tREFBW 2.88 µS Required number of REFRESH commands (min) Average time between REFRESH commands (for reference only) TCASE ≤ 85°C REFab mS Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 102 - W979H6KB / W979H2KB 8.7 AC Timings 8.7.1 LPDDR2 AC Timing (Note 6 apply to the entire table) Parameter Symbol Max. Frequency*4 min / max ~ min tCK Data Rate 1066 933 800 667 533 400 333 533 466 400 333 266 200 166 2.15 2.5 3 3.75 5 6 Unit MHz Clock Timing Average Clock Period tCK(avg) Average high pulse width tCH(avg) Average low pulse width tCL(avg) MIN 1.875 MAX 100 MIN 0.45 MAX 0.55 MIN 0.45 MAX 0.55 tCK(avg) tCK(avg) Absolute Clock Period tCK(abs) MIN tCK(avg)min + tJIT(per)min Absolute clock HIGH pulse width (with allowed jitter) tCH(abs), MIN 0.43 allowed MAX 0.57 Absolute clock LOW pulse width (with allowed jitter) tCL(abs), MIN 0.43 (allowed) MAX 0.57 Clock Period Jitter (with allowed jitter) tJIT(per), MIN -90 -95 -100 -110 -120 -140 -150 (allowed) MAX 90 95 100 110 120 140 150 MAX 180 190 200 220 240 280 300 Maximum Clock Jitter between two consecutive clock cycles (with allowed jitter) Duty cycle Jitter (with allowed jitter) Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles tJIT(cc), allowed tJIT(duty), allowed nS pS tCK(avg) tCK(avg) pS pS MIN MIN ((tCH(abs),min - tCH(avg),min), (tCL(abs),min - tCL(avg),min)) * tCK(avg) pS MAX MAX ((tCH(abs),max - tCH(avg),max), (tCL(abs),max - tCL(avg),max)) * tCK(avg) pS tERR(2per), MIN -132 -140 -147 -162 -177 -206 -221 (allowed) MAX 132 140 147 162 177 206 221 tERR(3per), MIN -157 -166 -175 -192 -210 -245 -262 (allowed) MAX 157 166 175 192 210 245 262 tERR(4per), MIN -175 -185 -194 -214 -233 -272 -291 (allowed) MAX 175 185 194 214 233 272 291 tERR(5per), MIN -188 -199 -209 -230 -251 -293 -314 (allowed) MAX 188 199 209 230 251 293 314 tERR(6per), MIN -200 -211 -222 -244 -266 -311 -333 (allowed) MAX 200 211 222 244 266 311 333 tERR(7per), MIN -209 -221 -232 -256 -279 -325 -348 (allowed) MAX 209 221 232 256 279 325 348 tERR(8per), MIN -217 -229 -241 -266 -290 -338 -362 (allowed) MAX 217 229 241 266 290 338 362 tERR(9per), MIN -224 -237 -249 -274 -299 -349 -374 (allowed) MAX 224 237 249 274 299 349 374 Cumulative error across 10 cycles tERR(10per), MIN -231 -244 -257 -282 -308 -359 -385 (allowed) MAX 231 244 257 282 308 359 385 Cumulative error across 11 cycles tERR(11per), MIN -237 -250 -263 -289 -316 -368 -395 (allowed) MAX 237 250 263 289 316 368 395 Cumulative error across 12 cycles tERR(12per), MIN -242 -256 -269 -296 -323 -377 -403 (allowed) MAX 242 256 269 296 323 377 403 Cumulative error across n = 13, 14 . . . 49, 50 cycles tERR(nper), MIN tERR(nper),allowed,min (allowed) MAX tERR(nper),allowed,max = (1 + 0.68ln(n)) * tJIT(per),allowed,max = (1 + 0.68ln(n)) * tJIT(per),allowed,min pS pS pS pS pS pS pS pS pS pS pS pS Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 103 - W979H6KB / W979H2KB Parameter Symbol min / max min tCK Data Rate 1066 933 800 667 533 400 333 Unit ZQ Calibration Parameters Initialization Calibration Time tZQINIT MIN 1 µS Full Calibration Time tZQCL MIN 6 360 nS Short Calibration Time tZQCS MIN 6 90 nS Calbration Reset Time tZQRESET MIN 3 50 nS Read Parameters *11 MIN 2500 MAX 5500 DQS output access time from CK_t/CK_c tDQSCK DQSCK Delta Short*15 tDQSCKDS MAX 330 DQSCK Delta Medium *16 380 pS 450 540 670 900 1080 pS tDQSCKDM MAX 680 780 900 1050 1350 1800 1900 pS DQSCK Delta Long*17 tDQSCKDL MAX 920 1050 1200 1400 1800 2400 - pS DQS - DQ skew tDQSQ MAX 200 220 240 280 340 400 500 pS Data hold skew factor tQHS MAX 230 260 280 340 400 480 600 pS DQS Output High Pulse Width tQSH MIN DQS Output Low Pulse Width tQSL Data Half Period tQHP DQ / DQS output hold time from DQS Read preamble *12,*13 Read postamble*12,*14 DQS low-Z from clock *12 DQ low-Z from clock*12 DQS high-Z from clock DQ high-Z from clock *12 *12 tCH(abs) - 0.05 tCK(avg) MIN tCL(abs) - 0.05 tCK(avg) MIN min(tQSH, tQSL) tCK(avg) tQH MIN tQHP - tQHS pS tRPRE MIN 0.9 tCK(avg) tRPST MIN tCL(abs) - 0.05 tCK(avg) tLZ(DQS) MIN tDQSCK(MIN) - 300 pS tLZ(DQ) MIN tDQSCK(MIN) - (1.4 * tQHS(MAX)) pS tHZ(DQS) MAX tDQSCK(MAX) - 100 pS MAX tDQSCK(MAX) + (1.4 * tDQSQ(MAX)) pS tHZ(DQ) Write Parameters*11 DQ and DM input hold time (Vref based) tDH MIN 210 235 270 350 430 480 600 DQ and DM input setup time (Vref based) tDS MIN 210 235 270 DQ and DM input pulse width tDIPW MIN 0.35 350 430 480 600 Write command to 1st DQS latching transition tDQSS DQS input high-level width pS pS tCK(avg) MIN 0.75 MAX 1.25 tDQSH MIN 0.4 tCK(avg) tCK(avg) DQS input low-level width tDQSL MIN 0.4 tCK(avg) DQS falling edge to CK setup time tDSS MIN 0.2 tCK(avg) DQS falling edge hold time from CK tDSH MIN 0.2 tCK(avg) Write postamble tWPST MIN 0.4 tCK(avg) Write preamble tWPRE MIN 0.35 tCK(avg) 3 tCK(avg) CKE Input Parameters CKE min. pulse width (high and low pulse width) tCKE CKE input setup time tISCKE*2 MIN 0.25 tCK(avg) *3 MIN 0.25 tCK(avg) CKE input hold time MIN tIHCKE 3 Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 104 - W979H6KB / W979H2KB Parameter Symbol min / max min tCK Data Rate 1066 933 800 667 533 400 333 Unit Command Address Input Parameters*11 Address and control input setup time (Vref based) tIS*1 MIN 220 250 290 370 460 600 740 pS Address and control input hold time (Vref based) tIH*1 MIN 220 250 290 370 460 600 740 pS tIPW MIN Address and control input pulse width 0.40 tCK(avg) Boot Parameters (10 MHz - 55 MHz)*5, 7, 8 Clock Cycle Time tCKb MAX 100 MIN 18 nS CKE Input Setup Time tISCKEb MIN 2.5 nS CKE Input Hold Time tIHCKEb MIN 2.5 nS Address & Control Input Setup Time tISb MIN 1150 pS Address & Control Input Hold Time tIHb MIN 1150 pS MIN 2.0 MAX 10.0 MAX 1.2 nS MAX 1.2 nS DQS Output Data Access Time from CK_t/CK_c tDQSCKb Data Strobe Edge to Ouput Data Edge tDQSQb - 1.2 tDQSQb Data Hold Skew Factor tQHSb nS Mode Register Parameters MODE REGISTER Write command period tMRW MIN 5 5 tCK(avg) Mode Register Read command period tMRR MIN 2 2 tCK(avg) LPDDR2 SDRAM Core Parameters *9 Read Latency RL MIN 3 8 7 6 5 4 3 3 tCK(avg) Write Latency WL MIN 1 4 4 3 2 2 1 1 tCK(avg) ACTIVE to ACTIVE command period tRC MIN CKE min. pulse width during Self-Refresh (low pulse width during Self-Refresh) tCKESR MIN Self refresh exit to next valid command delay tXSR Exit power down to next valid command delay tRAS + tRPab (with all-bank Precharge) tRAS + tRPpb (with per-bank Precharge) nS 3 15 nS MIN 2 tRFCab + 10 nS tXP MIN 2 7.5 nS CAS to CAS delay tCCD MIN 2 2 tCK(avg) Internal Read to Precharge command delay tRTP MIN 2 7.5 nS RAS to CAS Delay tRCD Fast 3 15 nS Row Precharge Time (single bank) tRPpb Fast 3 15 nS Row Precharge Time (all banks) tRPab 4-bank Fast 3 15 nS Row Active Time tRAS MIN 3 42 nS MAX - 70 µS Write Recovery Time tWR MIN 3 15 nS Internal Write to Read Command Delay tWTR MIN 2 Active bank A to Active bank B tRRD MIN 2 Four Bank Activate Window tFAW MIN 8 Minimum Deep Power Down Time tDPD MIN 7.5 10 nS 10 50 nS 60 500 nS µS Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 105 - W979H6KB / W979H2KB Parameter Symbol min / max min tCK Data Rate 1066 933 800 667 Unit 533 400 333 LPDDR2 Temperature De-Rating tDQSCK De-Rating Core Timings Temperature De-Rating tDQSCK (Derated) MAX tRCD (Derated) 5620 6000 pS MIN tRCD + 1.875 nS tRC (Derated) MIN tRC + 1.875 nS tRAS (Derated) MIN tRAS + 1.875 nS tRP (Derated) MIN tRP + 1.875 nS tRRD (Derated) MIN tRRD + 1.875 nS Notes: 1. Input set-up/hold time for signal (CA[0:n], CS_n). 2. CKE input setup time is measured from CKE reaching high/low voltage level to CK_t/CK_c crossing. 3. CKE input hold time is measured from CK_t/CK_c crossing to CKE reaching high/low voltage level. 4. Frequency values are for reference only. Clock cycle time (tCK) shall be used to determine device capabilities. 5. To guarantee device operation before the LPDDR2 device is configured a number of AC boot timing parameters are defined in this table. Boot parameter symbols have the letter b appended, e.g. tCK during boot is tCKb. 6. Frequency values are for reference only. Clock cycle time (tCK or tCKb) shall be used to determine device capabilities. 7. The SDRAM will set some Mode register default values upon receiving a RESET (MRW) command as specified in “Mode Register Definition”. 8. The output skew parameters are measured with Ron default settings into the reference load. 9. The min tCK column applies only when tCK is greater than 6nS for LPDDR2-S4 devices. 10. All AC timings assume an input slew rate of 1V/nS. 11. Read, Write, and Input Setup and Hold values are referenced to Vref. 12. For low-to-high and high-to-low transitions, the timing reference will be at the point when the signal crosses VTT. tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ) ), or begins driving (for tRPRE, tLZ(DQS), tLZ(DQ) ). Below “HSUL_12 Driver Output Reference Load for Timing and Slew Rate” figure shows a method to calculate the point when device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 106 - W979H6KB / W979H2KB VOH X VOH - X mV 2x X VTT + 2x Y mV VOH - 2x X mV VTT + Y mV tLZ(DQS), tLZ(DQ) VTT VTT Y Actual waveform 2x Y VTT - Y mV tHZ(DQS), tHZ(DQ) VOL + 2x X mV VTT - 2x Y mV VOL + X mV T1 T2 VOL T1T2 Stop driving point = 2 x T1 – T2 begin driving point = 2 x T1 – T2 Figure of HSUL_12 Driver Output Reference Load for Timing and Slew Rate The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and tRPST are determined from the differential signal DQS_t-DQS_c. 13. Measured from the start driving of DQS_t - DQS_c to the start driving the first rising strobe edge. 14. Measured from the from start driving the last falling strobe edge to the stop driving DQS_t , DQS_c. 15. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 160nS rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is < 10°C/s. Values do not include clock jitter. 16. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 1.6µS rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is < 10°C/s. Values do not include clock jitter. 17. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 32mS rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is < 10°C/s. Values do not include clock jitter. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 107 - W979H6KB / W979H2KB 8.7.2 CA and CS_n Setup, Hold and Derating For all input signals (CA and CS_n) the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see 8.7.2.1 “CA and CS_n Setup and Hold Base-Values for 1V/nS” table) to the ΔtIS and ΔtIH derating value (see 8.7.2.2 “Derating Values LPDDR2 tIS/tIH - AC/DC Based AC220” table). Example: tIS (total setup time) = tIS(base) + ΔtIS. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value (see 8.7.2.4 “Nominal Slew Rate and tVAC for Setup Time tIS for CA and CS_n with Respect to Clock” figure). If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see 8.7.2.6 “Tangent Line for Setup Time tIS for CA and CS_n with Respect to Clock” figure). Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value (see 8.7.2.5 “Nominal Slew Rate for Hold Time tIH for CA and CS_n with Respect to Clock” figure). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value (see 8.7.2.7 “Tangent Line for Hold Time tIH for CA and CS_n with Respect to Clock” figure). For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC (see 8.7.2.3 “Required Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition” table). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in 8.7.2.2 “Derating Values LPDDR2 tIS/tIH - AC/DC Based AC220” table, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. 8.7.2.1 CA and CS_n Setup and Hold Base-Values for 1V/nS Unit [pS] LPDDR2-1066 LPDDR2-800 reference tIS(base) 0 70 VIH/L(ac) = VREF(dc) ± 220mV tIH(base) 90 160 VIH/L(dc) = VREF(dc) ± 130mV Note: ac/dc referenced for 1V/nS CA and CS_n slew rate and 2V/nS differential CK_t-CK_c slew rate. Publication Release Date: Jan. 19, 2015 Revision: A01-002 - 108 - W979H6KB / W979H2KB 8.7.2.2 Derating Values LPDDR2 tIS/tIH - AC/DC Based AC220 ΔtIS, ΔtIH derating in [pS] AC/DC based AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV DC130 Threshold -> VIH(dc)=VREF(dc)+130mV, VIL(dc)=VREF(dc)-130mV CA, CS_n Slew Rate V/nS CK_t,CK_c Differential Slew Rate 4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/nS 1.6 V/nS 1.4 V/nS 1.2 V/nS 1.0 V/nS ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH 2.0 110 65 110 65 110 65 - - - - - - - - - - 1.5 74 43 73 43 73 43 89 59 - - - - - - - - 1.0 0 0 0 0 0 0 16 16 32 32 - - - - - - 0.9 - - -3 -5 -3 -5 13 11 29 27 45 43 - - - - 0.8 - - - - -8 -13 8 3 24 19 40 35 56 55 - - 0.7 - - - - - - 2 -6 18 10 34 26 50 46 66 78 0.6 - - - - - - - - 10 -3 26 13 42 33 58 65 0.5 - - - - - - - - - - 4 -4 20 16 36 48 0.4 - - - - - - - - - - - - -7 2 17 34 Note: Cell contents ‘-’ are defined as not supported. 8.7.2.3 Required Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition Slew Rate [V/nS] tVAC @ 220mV [pS] min max > 2.0 175 - 2.0 170 - 1.5 167 - 1.0 163 - 0.9 162 - 0.8 161 - 0.7 159 - 0.6 155 - 0.5 150 - VIH(ac) = VREF(dc) + 220mV, VIL(ac) = VREF(dc) - 220mV DC130 Threshold -> VIH(dc) = VREF(dc) + 130mV, VIL(dc) = VREF(dc) - 130mV DQS_t, DQS_c Differential Slew Rate DQ, DM Slew Rate V/nS 4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/nS 1.6 V/nS 1.4 V/nS 1.2 V/nS 1.0 V/nS ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH 2.0 110 65 110 65 110 65 - - - - - - - - - - 1.5 74 43 73 43 73 43 89 59 - - - - - - - - 1.0 0 0 0 0 0 0 16 16 32 32 - - - - - - 0.9 - - -3 -5 -3 -5 13 11 29 27 45 43 - - - - 0.8 - - - - -8 -13 8 3 24 19 40 35 56 55 - - 0.7 - - - - - - 2 -6 18 10 34 26 50 46 66 78 0.6 - - - - - - - - 10 -3 26 13 42 33 58 65 0.5 - - - - - - - - - - 4 -4 20 16 36 48 0.4 - - - - - - - - - - - - -7 2 17 34 Note: Cell contents ‘-’ are defined as not supported. 8.7.3.3 Required Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition Slew Rate [V/nS] tVAC @ 220mV [pS] min max > 2.0 175 - 2.0 170 - 1.5 167 - 1.0 163 - 0.9 162 - 0.8 161 - 0.7 159 - 0.6 155 - 0.5 150 -