W981216BH

W981216BH 2M × 4 BANKS × 16 BIT SDRAM GENERAL DESCRIPTION W 981216BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 2M words × 4 b anks × 1 6 bits. Using pipelined architecture and 0.175 µ m process technology, W981216BH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the personal computer industrial standard, W981216BH is sorted into three speed grades: -7, -75 and 8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W981216BH is ideal for main memory in high performance applications. FEATURES • 3.3V ±0.3V Power Supply • Up to 143 MHz Clock Frequency • 2,097,152 Words × 4 banks × 16 bits organization • Auto Refresh and Self Refresh • CAS Latency: 2 and 3 • Burst Length: 1, 2, 4, 8, and full page • Burst Read, Single Writes Mode • Byte Data Controlled by DQM • Power-Down Mode • Auto-precharge and Controlled Precharge • 4K Refresh cycles / 64 mS • Interface: LVTTL • Packaged in TSOP II 54 pin, 400 mil - 0.80 KEY PARAMETERS SYM. DESCRIPTION MIN. /MAX. -7 (PC133, CL2) -75 (PC133, CL3) -8H (PC100) tCK tAC tRP tRCD ICC1 ICC4 ICC6 Clock Cycle Time Access Time from CLK Precharge to Active Command Active to Read/Write Command Operation Current (Single bank) Burst Operation Current Self-Refresh Current Min. Max. Min. Min. Max. Max. Max. 7 nS 5.4 nS 15 nS 15 nS 80 mA 100 mA 2 mA 7.5 nS 5.4 nS 20 nS 20 nS 75 mA 95 mA 2 mA 8 nS 6 nS 20 nS 20 nS 70 mA 90 mA 2 mA -1- Publication Release Date: October 2000 Revision A1 W981216BH PIN CONFIGURATION V CC DQ0 V CC Q DQ1 DQ2 V SS Q DQ3 DQ4 V CC Q DQ5 DQ6 V SS Q DQ7 V CC LDQM WE CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 V CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS DQ15 V SS Q DQ14 DQ13 V CC Q DQ12 DQ11 V SS Q DQ10 DQ9 V CC Q DQ8 V SS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 V SS -2- W981216BH PIN DESCRIPTION PIN NUMBER PIN NAME FUNCTION DESCRIPTION 23 − 26, 22, 29 − 35 20, 21 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 19 A0 − A11 Address Multiplexed pins for row and column address. Row address: A0 − A11. Column address: A0 − A8. BS0, BS1 DQ0 − DQ15 Bank Select Data Input/ Output Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input. CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock, RAS , CAS and WE operation to be executed. Referred to RAS Referred to RAS The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode or Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Separated power from VCC, used for output buffers to improve noise. Separated ground from VSS, used for output buffers to improve noise. No connection define the 18 RAS Row Address Strobe 17 16 39, 15 CAS WE Column Address Strobe Write Enable Input/Output Mask UDQM/ LDQM 38 37 CLK CKE Clock Inputs Clock Enable 1, 14, 27 28, 41, 54 3, 9, 43, 49 6, 12, 46, 52 36, 40 VCC VSS VCCQ VSSQ NC Power (+3.3V) Ground Power (+3.3V) for I/O Buffer Ground for I/O Buffer No Connection -3- Publication Release Date: October 2000 Revision A1 W981216BH BLOCK DIAGRAM CLK CLOCK BUFFER CKE CS CONTROL SIGNAL GENERATOR RAS CAS COMMAND DECODER COLUMN DECODER COLUMN DECODER R O W WE R O W D E C O D E R A10 CELL ARRAY BANK #0 A0 ADDRESS BUFFER A9 A11 BS0 BS1 MODE REGISTER D E C O D E R CELL ARRAY BANK #1 SENSE AMPLIFIER SENSE AMPLIFIER DMn DQ0 DATA CONTROL CIRCUIT REFRESH COUNTER COLUMN COUNTER DQ BUFFER DQ15 UDQM LDQM COLUMN DECODER R O W D E C O D E R R O W COLUMN DECODER CELL ARRAY BANK #2 D C O D E R CELL ARRAY BANK #3 SENSE AMPLIFIER SENSE AMPLIFIER Note: The cell array configuration is 4096 * 512 * 16. -4- W981216BH ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Input/Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current of the device. VIN, VOUT VCC, VCCQ TOPR TSTG TSOLDER PD IOUT -0.3 − VCC +0.3 -0.3 − 4.6 0 − 70 -55 − 150 260 1 50 V V °C °C °C W mA Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability RECOMMENDED DC OPERATING CONDITIONS (TA = 0 to 70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input High Voltage Input Low Voltage Note: VIH(max) = VCC/ VCCQ+1.2V for pulse width < 5 nS VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 nS VCC VCCQ VIH VIL 3.0 3.0 2.0 -0.3 3.3 3.3 - 3.6 3.6 VCC +0.3 0.8 V V V V CAPACITANCE (VCC = 3.3V, f = 1 MHz, TA = 25°C) PARAMETER SYMBOL MIN. MAX. UNIT Input Capacitance (A0 to A11, BS0, BS1, CS , RAS , CAS , WE , DQM, CKE) Input Capacitance (CLK) Input/Output capacitance Note: These parameters are periodically sampled and not 100% tested. CI - 3.8 pf CCLK CIO - 3.5 6.5 pf pf -5- Publication Release Date: October 2000 Revision A1 W981216BH AC CHARACTERISTICS AND OPERATING CONDITION (Vcc = 3.3V ± 0.3V, TA = 0° to 70°C; Notes: 5, 6, 7, 8) PARAMETER SYM. MIN. -7 (PC133, CL2) MAX. MIN. -75 (PC133, CL3) MAX. MIN. -8H (PC100) MAX. UNIT Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b)Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time CL* = 2 CL* = 3 CLK Cycle Time CL* = 2 CL* = 3 tRC tRAS tRCD tCCD tRP tRRD tWR tCK tCH tCL 57 42 15 1 15 15 7.5 7 7.5 7 1000 1000 100000 65 45 20 1 20 15 10 7.5 10 7.5 1000 1000 100000 68 48 20 1 20 20 10 8 10 8 1000 1000 Cycle 100000 nS CLK High Level width CLK Low Level width Access Time from CLK CL* = 2 CL* = 3 Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK (Rise and Fall) Data-in Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode register Set Cycle Time *CL = CAS Latency 2.5 2.5 5.4 5.4 2.5 2.5 6 5.4 3 7 3 0 7 10 0 0.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 64 64 15 7.5 10 7.5 3 3 6 6 3 3 0 0 0.5 2 1 2 1 2 1 2 1 64 16 mS nS 8 10 8 nS tAC tOH tHZ tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC 14 3 3 0 0 0.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 -6- W981216BH DC CHARACTERISTICS (VCC = 3.3V ± 0.3V, TA = 0°− 70°C) PARAMETER SYM. -7 (PC133, CL2) MIN. Operating Current 1 bank operation ICC1 MAX. 80 -75 (PC133, CL3) MIN. MAX. 75 MIN. -8H (PC100) MAX. 70 3 UNIT NOTES tCK = min., tRC = min. Active precharge command cycling without burst operation Standby Current CKE = VIH = VIH CKE = VIL (Power Down mode) ICC2 40 35 30 3 tCK = min, CS VIH / L = VIH (min.)/ VIL (max.) Bank: Inactive state Standby Current CLK = VIL, CS = VIH VIH / L = VIH (min.)/ VIL (max.) BANK: Inactive state No Operating Current ICC2P 1 1 1 3 CKE = VIH ICC2S 10 10 10 CKE = VIL (Power down mode) ICC2PS 1 1 1 mA CKE = VIH ICC3 60 55 50 tCK = min., CS = VIH (min.) CKE = VIL (Power down mode) BANK: Active state (4 banks) Burst Operating Current ICC3P 10 10 10 ICC4 100 95 90 3, 4 tCK = min. Read/ Write command cycling Auto Refresh Current ICC5 170 160 150 3 tCK = min. Auto refresh command cycling Self Refresh Current Self Refresh Mode CKE = 0.2V ICC6 2 2 2 PARAMETER Input Leakage Current (0V ≤ VIN ≤ VCC, all other pins not under test = 0V) Output Leakage Current (Output disable , 0V ≤ VOUT ≤ VCCQ) LVTTL Output ″H″ Level Voltage (IOUT = -2 mA ) LVTTL Output ″L″ Level Voltage (IOUT = 2 mA ) SYMBOL II(L) MIN. -5 MAX. 5 UNIT µA NOTES IO(L) -5 5 µA VOH 2.4 - V VOL - 0.4 V -7- Publication Release Date: October 2000 Revision A1 W981216BH Notes: 1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices. 2. All voltages are referenced to VSS 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up sequence is further described in the "Functional Description" section. 6. AC Testing Conditions Output Reference Level Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signal Input Reference Level 1.4V/1.4V See diagram below 2.4V/0.4V 2 nS 1.4V 1.4 V 50 ohms Output Z = 50 ohms 50 pF AC TEST LOAD 7. Transition times are measured between VIH and VIL. 8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. -8- W981216BH OPERATION MODE F ully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (Note (1), (2)) COMMAND DEVICE STATE Idle Any Any Active (3) Active (3) Active (3) Active (3) Idle Any Active (4) Any Idle Idle idle (S.R.) Clock suspend Mode Entry Power Down Mode Entry Active Idle Active (5) Clock Suspend Mode Exit Power Down Mode Exit Active Any (power Data write/Output Enable Data Write/Output Disable Notes: (1) v = valid x = Don't care L = Low Level H = High Level Active Active CKEN-1 CKEN DQM BS0, 1 A10 A0−A9 A11 v x x v v v v v x x x x x x x x x x x x x x x CS L L L L L L L L L L H L L H L x H L x H L x x RAS L L L H H H H L H H x L L x H x x H x x H x x CAS H H H L L L L L H H x L L x H x x H x x H x x WE H L L L L H H L H L x H H x x x x x x x x x x Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set No - Operation Burst Stop Device Deselect Auto - Refresh Self - Refresh Entry Self Refresh Exit H H H H H H H H H H H H H L L H H H L L L H H x x x x x x x x x x x H L H H L L L H H H x x x x x x x x x x x x x x x x x x x x x x x L H v v x v v v v v x x x x x x x x x x x x x x x v L H L H L H v x x x x x x x x x x x x x x x (2) CKEn signal is input level when commands are provided. CKEn-1 signal is the input level one clock cycle before the command is issued. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. -9- Publication Release Date: October 2000 Revision A1 W981216BH FUNCTIONAL DESCRIPTION Power Up and Initialization T he default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed V C C + 0.3V on any of the input pins or Vcc supplies. After power up, an initial pause of 200 µ S is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation. Programming Mode Register A fter initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to t RSC h as elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table. Bank Activate Command T he Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to R A S a ctivate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (t RCD ). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t R C ). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t RRD ). The maximum time that each bank can be held active is specified as tRAS (max). Read and Write Access Modes A fter a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of t RCD d elay. WE pin voltage level defines whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. - 10 - W981216BH Burst Read Command T he Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode. Burst Write Command T he Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored. Read Interrupted by a Read A B urst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied. Read Interrupted by a Write T o interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed. Write Interrupted by a Write A b urst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Write Interrupted by a Read A R ead Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. Burst Stop Command A B urst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst - 11 - Publication Release Date: October 2000 Revision A1 W981216BH r ead cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. Addressing Sequence of Sequential Mode A c olumn access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table 2 Address Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 BL = 2 (disturb address is A0) No address carry from A0 to A1 BL = 4 (disturb addresses are A0 and A1) No address carry from A1 to A2 BL = 8 (disturb addresses are A0, A1 and A2) No address carry from A2 to A3 Addressing Sequence of Interleave Mode A c olumn access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode DATA ACCESS ADDRESS BUST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A 0 A8 A7 A6 A5 A4 A3 A2 A 1 A0 A8 A7 A6 A5 A4 A3 A2 A 1 A 0 A8 A7 A6 A5 A4 A3 A 2 A1 A0 A8 A7 A6 A5 A4 A3 A 2 A1 A 0 A8 A7 A6 A5 A4 A3 A 2 A8 A7 A6 A5 A4 A3 A 2 A 1 A0 A1 A0 BL = 2 BL = 4 BL = 8 - 12 - W981216BH Auto-Precharge Command I f A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency. A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (t RP ) has been satisfied. Issue of Auto-Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst write cycle. This delay is referred to as Write t W R . The bank undergoing auto-precharge can not be reactivated until tW R a nd t RP a re satisfied. This is referred to as t DAL, Data-in to Active delay (t DAL = t W R + t RP ). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS (min). Precharge Command T he Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). Self Refresh Command T he Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the t A C cycle time plus the Self Refresh exit time. If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. Power Down Mode T he Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (t REF) of the device. - 13 - Publication Release Date: October 2000 Revision A1 W981216BH T he Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on t CK . The input buffers need to be enabled with CKE held high for a period equal to tCKS (min) + tCK (min). No Operation Command T he No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command T he Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares. Clock Suspend Mode D uring normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. - 14 - W981216BH TIMING WAVEFORMS Command Input Timing t CK t CL tCH VIH CLK VIL tT t CMS t CMH t CMH tT t CMS CS t CMS t CMH RAS t CMS t CMH CAS t CMS t CMH WE t AS tAH A0-A11 BS0, 1 t CKS t CKH tCKS t CKH t CKS t CKH CKE - 15 - Publication Release Date: October 2000 Revision A1 W981216BH Timing Waveforms, continued Read Timing Read CAS Latency CLK CS RAS CAS WE A0-A11 BS0, 1 tAC t LZ tOH tAC tHZ tOH DQ Read Command Valid Data-Out Valid Data-Out Burst Length - 16 - W981216BH Timing Waveforms, continued Control Timing of Input / Output Data Control Timing of Input Data (Word Mask) CLK t CMH t CMS t CMH tCMS DQM t DS tDH Valid Data-in t DS t DH Valid Data-in t DS t DH Valid Data-in tDS t DH DQ0 -15 Valid Data-in (Clock Mask) CLK tCKH t CKS t CKH t CKS CKE tDS t DH Valid Data-in tDS tDH Valid Data-in t DS t DH Valid Data-in t DS tDH Valid Data-in DQ0 -15 Control Timing of Output Data (Output Enable) CLK t CMH t CMS tCMH tCMS DQM t AC t OH t OH Valid Data-Out t AC tOH Valid Data-Out t HZ t LZ t AC t OH Valid Data-Out t AC DQ0 -15 OPEN (Clock Mask) CLK t CKH t CKS tCKH t CKS CKE t AC t OH tOH Valid Data-Out Valid Data-Out tAC tOH t AC tOH Valid Data-Out tAC DQ0 -15 - 17 - Publication Release Date: October 2000 Revision A1 W981216BH Timing Waveforms, continued Mode Register Set Cycle t RSC CLK t CMS t CMH CS t CMS t CMH RAS t CMS t CMH CAS t CMS t CMH WE t AS t AH Register set data A0-A11 BS0,1 A0 A1 A2 A3 A4 A5 A6 A7 A0 A8 A9 A0 A10 A11 A0 BS0 BS1 "0" "0" "0" "0" A0 Reserved "0" "0" (Test Mode) Reserved A0 Write Mode CAS Latency Addressing Mode Burst Length A2 0 0 0 0 1 1 1 1 A0 A1 A0 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A0 A3 A0 0 A0 1 A0 0 1 0 1 0 1 0 1 next command BurstA0 Length Sequential A0 Interleave A0 1 A0 1 A0 2 A0 2 A0 4 A0 4 A0 8 A0 8 A0 Reserved FullA0 Page A0 Addressing Mode Sequential A0 Interleave A0 Reserved A0 A6 0 0 0 0 1 A5 A0 A0 0 A0 0 A0 1 A0 1 A0 0 A9 A0 A0 0 A0 1 A4 0 1 0 1 0 CAS Latency A0 Reserved A0 Reserved A0 2 A0 3 Reserved Single Write Mode Burst read and Burst write A0 Burst read and single write A0 - 18 - W981216BH OPERATING TIMING EXAMPLE Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD tRCD RBb RAc tRCD RBd tRCD RAe A10 RAa A0-A9, A11 DQM RAa CAw RBb CBx RAc CAy RBd CBz RAe CKE tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 tAC cy0 cy1 cy2 cy3 tAC DQ tRRD tRRD tRRD tRRD Bank #0 Active Bank #1 Bank #2 Idle Bank #3 Read Active Precharge Read Active Read Precharge Active Precharge Read Active - 19 - Publication Release Date: October 2000 Revision A1 W981216BH Operating Timing Example, contined Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRAS tRP tRP tRAS CAS WE BS0 BS1 tRCD tRCD tRCD RBd tRCD RAe A10 RAa RBb RAc A0-A9, A11 DQM RAa CAw RBb CBx RAc CAy RBd CBz RAe CKE tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 tAC cy0 cy1 cy2 cy3 tAC dz0 DQ tRRD tRRD tRRD tRRD Bank #0 Bank #1 Bank #2 Idle Bank #3 Active Read Active AP* Read Active Read AP* Active AP* Read Active * AP is the internal precharge start timing - 20 - W981216BH Operating Timing Example, contined Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC RAS tRAS tRP tRP tRAS tRAS tRP CAS WE BS0 BS1 tRCD tRCD RBb RAc tRCD A10 RAa A0-A9, A11 DQM RAa CAx RBb CBy RAc CAz CKE tAC tAC ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 tAC by7 CZ0 DQ tRRD tRRD Bank #0 Bank #1 Bank #2 Active Read Precharge Active Read Precharge Active Read Precharge Idle Bank #3 - 21 - Publication Release Date: October 2000 Revision A1 W981216BH Operating Timing Example, contined Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRC CS tRC RAS tRAS tRP tRAS tRAS tRP CAS WE BS0 BS1 tRCD tRCD tRCD A10 RAa RBb RAc A0-A9, A11 RAa CAx RBb CBy RAc CAz DQM CKE tCAC tCAC tCAC DQ ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 CZ0 tRRD tRRD Bank #0 Bank #1 Bank #2 Active Read Active AP* Read Active Read AP* Idle Bank #3 * AP is the internal precharge start timing - 22 - W981216BH Operating Timing Example, contined Interleaved Bank Write (Burst Length = 8) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRAS tRP CAS tRCD tRCD tRCD WE BS0 BS1 A10 RAa RBb RAc A0-A9, A11 DQM RAa CAx RBb CBy RAc CAz CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD tRRD Bank #0 Bank #1 Bank #2 Bank #3 Active Write Active Write Precharge Active Write Precharge Idle - 23 - Publication Release Date: October 2000 Revision A1 W981216BH Operating Timing Example, contined Interleaved Bank Write (Burst Length = 8, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRAS tRP CAS WE BS0 BS1 tRCD tRCD RBb RAb tRCD A10 RAa A0-A9, A11 RAa CAx RBb CBy RAc CAz DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD tRRD Bank #0 Active Bank #1 Bank #2 Idle Bank #3 Write Active AP* Write Active Write AP* * AP is the internal precharge start timing - 24 - W981216BH Operating Timing Example, contined Page Mode Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tCCD tCCD tCCD CS tRAS tRAS tRP tRP RAS CAS WE BS0 BS1 tRCD tRCD A10 A0-A9, A11 DQM RAa RBb RAa CAI RBb CBx CAy CAm CBz CKE tAC tAC tAC tAC tAC DQ a0 a1 a2 a3 bx0 bx1 Ay0 Ay1 Ay2 am0 am1 am2 bz0 bz1 bz2 bz3 tRRD Bank #0 Bank #1 Bank #2 Active Read Active Read Read Read Read Precharge AP* Idle Bank #3 * AP is the internal precharge start timing - 25 - Publication Release Date: October 2000 Revision A1 W981216BH Operating Timing Example, contined Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRAS tRP RAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa CAx CAy DQM CKE tAC tWR ax0 ax1 ax2 ax3 ax4 ax5 ay0 ay1 ay2 ay3 ay4 DQ QQ Q Q Q Q D D D D D Bank #0 Bank #1 Bank #2 Bank #3 Active Read Write Precharge Idle - 26 - W981216BH Operating Timing Example, contined Auto Precharge Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD tRCD RAb A10 RAa A0-A9, A11 RAa CAw RAb CAx DQM CKE tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 DQ Bank #0 Bank #1 Bank #2 Active Read AP* Active Read AP* Idle Bank #3 * AP is the internal precharge start timing - 27 - Publication Release Date: October 2000 Revision A1 W981216BH Operating Timing Example, contined Auto Precharge Write (Burst Length = 4) (CLK = 100 MHz) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD tRCD RAb RAc A10 A0-A9, A11 DQM RAa RAa CAw RAb CAx RAc CKE DQ aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 Bank #0 Bank #1 Bank #2 Active Write AP* Active Write AP* Active Idle Bank #3 * AP is the internal precharge start timing - 28 - W981216BH Operating Timing Example, contined Auto Refresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRP tRC tRC CS RAS CAS WE BS0,1 A10 A0-A9, A11 DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 29 - Publication Release Date: October 2000 Revision A1 W981216BH Operating Timing Example, contined Self Refresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP RAS CAS WE BS0,1 A10 A0-A9, A11 DQM tSB tCKS tCKS CKE tCKS DQ tRC Self Refresh Cycle No Operation Cycle All Banks Precharge Self Refresh Entry Arbitrary Cycle - 30 - W981216BH Operating Timing Example, contined Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS tRCD WE BS0 BS1 A10 RBa A0-A9, A11 DQM RBa CBv CBw CBx CBy CBz CKE tAC tAC av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 DQ Q Q Q Q D D D Q Q Q Q Bank #0 Active Bank #1 Bank #2 Bank #3 Idle Read Single Write Read - 31 - Publication Release Date: October 2000 Revision A1 W981216BH Operating Timing Example, contined PowerDown Mode (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BS A10 RAa RAa A0-A9 A11 RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS ax0 ax1 ax2 tCKS ax3 tCKS DQ Active NOP Read Active Standby Power Down mode Precharge NOP Active Precharge Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode. When CKE goes high, command input must be No operation at next CLK rising edge. - 32 - W981216BH Operating Timing Example, contined Autoprecharge Timing (Read Cycle) 0 (1) CAS Latency=2 ( a ) burst length = 1 Command 1 2 3 4 5 6 7 8 9 10 11 Read AP tRP Act Q0 DQ ( b ) burst length = 2 Command Read AP tRP Act Q1 AP tRP DQ ( c ) burst length = 4 Command Q0 Read Q0 Read Q0 Act Q3 AP tRP DQ ( d ) burst length = 8 Command Q1 Q2 Act DQ (2) CAS Latency=3 ( a ) burst length = 1 Command Q1 Q2 Q3 Q4 Q5 Q6 Q7 Read AP tRP Act Q0 DQ ( b ) burst length = 2 Command Read AP tRP Act Q0 Q1 AP tRP DQ ( c ) burst length = 4 Command Read Q0 Read Q0 Act Q2 Q3 AP tRP DQ ( d ) burst length = 8 Command Q1 Act Q6 Q7 DQ Q1 Q2 Q3 Q4 Q5 Note ) Read AP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least t RAS(min). - 33 - Publication Release Date: October 2000 Revision A1 W981216BH Operating Timing Example, contined Autoprecharge Timing (Write Cycle) 0 (1) CAS Latency=2 ( a ) burst length = 1 Command 1 2 3 4 5 6 7 8 9 10 11 Write tWR AP tRP Act DQ ( b ) burst length = 2 Command D0 Write tWR AP tRP Act DQ ( c ) burst length = 4 Command D0 Write D1 AP tWR tRP Act DQ ( d ) burst length = 8 Command D0 Write D1 D2 D3 AP tWR tRP Act DQ (2) CAS Latency=3 ( a ) burst length = 1 Command D0 D1 D2 D3 D4 D5 D6 D7 Write tWR AP tRP Act DQ ( b ) burst length = 2 Command D0 Write tWR AP tRP Act DQ ( c ) burst length = 4 Command D0 Write D1 AP tWR tRP Act DQ ( d ) burst length = 8 Command D0 Write D1 D2 D3 AP tWR tRP Act DQ D0 D1 D2 D3 D4 D5 D6 D7 Note ) Write AP Act represents the Write with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min). - 34 - W981216BH Operating Timing Example, contined Timing Chart of Read to Write Cycle In the case of Burst Length = 4 (1) CAS Latency=2 ( a ) Command 0 1 Read 2 Write 3 4 5 6 7 8 9 10 11 DQM DQ D0 Read D1 Write D2 D3 ( b ) Command DQM DQ D0 D1 D2 D3 (2) CAS Latency=3 ( a ) Command DQM Read Write D0 D1 Write D2 D3 DQ ( b ) Command Read DQM DQ D0 D1 D2 D3 Note: The Output data must be masked by DQM to avoid I/O conflict Timing Chart of Write to Read Cycle In the case of Burst Length=4 0 (1) CAS Latency=2 ( a ) Command DQM 1 Write D0 Write D0 Write D0 Write D0 2 Read 3 4 5 6 7 8 9 10 11 DQ Q0 Read D1 Read Q1 Q2 Q3 ( b ) Command DQM DQ Q0 Q1 Q2 Q3 (2) CAS Latency=3 ( a ) Command DQM DQ Q0 Read D1 Q1 Q2 Q3 ( b ) Command DQM DQ Q0 Q1 Q2 Q3 - 35 - Publication Release Date: October 2000 Revision A1 W981216BH Operating Timing Example, contined Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 (1) Read cycle 1 2 3 4 5 6 7 8 9 10 11 ( a ) CAS latency =2 Command Read Q0 Read Q0 Q1 Q1 Q2 BST Q3 BST Q2 Q3 Q4 Q4 DQ ( b )CAS latency = 3 Command DQ (2) Write cycle Command Write BST DQ Q0 Q1 Q2 Q3 Q4 Note: BST represents the Burst stop command Timing Chart of Burst Stop Cycle (Precharge Command) In the case of Burst Lenght = 8 0 (1) Read cycle 1 2 3 4 5 6 7 8 9 10 11 ( a )CAS latency =2 Command Read Q0 Read Q0 Q1 Q1 Q2 PRCG DQ Q3 PRCG Q4 ( b )CAS latency = 3 Command DQ DQ Q2 Q3 Q4 (2) Write cycle ( a ) CAS latency =2 Command DQM Write PRCG tWR DQ D0 Write D1 D2 D3 D4 PRCG t WR ( b )CAS latency = 3 Command DQM DQ D0 D1 D2 D3 D4 - 36 - W981216BH Operating Timing Example, contined CKE/DQM Input Timing (Write Cycle) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ D1 D2 D3 DQM MASK (1) D5 CKE MASK D6 CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ D1 D2 D3 D5 D6 DQM MASK (2) CKE MASK CLK cycle No. External CLK Internal CKE 1 2 3 4 5 6 7 DQM DQ D1 D2 D3 CKE MASK D4 D5 D6 (3) - 37 - Publication Release Date: October 2000 Revision A1 W981216BH Operating Timing Example, contined CKE/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Open Open Q6 (1) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Open Q6 (2) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Q5 Q6 (3) - 38 - W981216BH Operating Timing Example, contined Self Refresh/Power Down Mode Exit Timing Asynchronous Control Input Buffer turn on time ( Power down mode exit time ) is specified by tCKS(min) + tCK(min) A ) tCK < tCKS(min)+t CK(min) tCK CLK CKE tCKS (min) +t CK(min) Command NOP Command Input Buffer Enable B) tCK >= tCKS(min) + t CK (min) t CK CLK CKE tCKS (min) +tCK(min) Command Command Input Buffer Enable Note ) All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode and Self Refresh mode NOP Command Represents the No-Operation command Represents one command - 39 - Publication Release Date: October 2000 Revision A1 W981216BH PACKAGE DIMENSION 54L TSOP (II)-400 mil 54 28 E HE 1 e 27 b C D L A2 ZD A1 A L1 Y SEATING PLANE Controlling Dimension: Millimeters DIMENSION (MM) SYM. DIMENSION (INCH) MAX. 1.20 MIN. A A1 A2 b c D E HE e L L1 Y ZD 0.40 22.12 10.06 11.56 0.24 0.05 NOM. MIN. NOM. MAX. 0.047 0.10 1.00 0.32 0.15 22.22 10.16 11.76 0.80 0.50 0.80 0.15 0.002 0.004 0.039 0.006 0.40 0.009 0.012 0.006 0.016 22.62 10.26 11.96 0.871 0.396 0.455 0.875 0.400 0.463 0.0315 0.905 0.404 0.471 0.60 0.016 0.020 0.032 0.024 0.10 0.71 0.028 0.004 - 40 - W981216BH Headquarters Headquarters No. 4, Creation Rd. III, Science -Based Industrial Park, Hsinchu, Taiwan TEL: 886 -3-5770066 FAX: 886 -3-5796096 http://www.winbond.com.tw/ Voice & Fax -on -demand: 886 -2-27197006 Winbond Electronics (H.K.) Ltd. Unit 9 -15, 22F, Millennium City, No. 378 Kwun Tong Rd; Kowloon, Hong Kong TEL: 852 -27513100 FAX: 852 -27552064 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408 -9436666 FAX: 408 -5441798 Taipei Office 11F, No. 115, Sec. 3, Min Taipei, Taiwan TEL: 886 -2-27190505 FAX: 886 -2-27197502 -Sheng East Rd., Note: All data and specifications are subject to change withou t notice. - 41 - Publication Release Date: October 2000 Revision A1