W9812G2KB
1M 4 BANKS 32 BITS SDRAM
Table of Contents1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
ORDER INFORMATION ............................................................................................................. 4
BALL CONFIGURATION ............................................................................................................ 5
BALL DESCRIPTION .................................................................................................................. 6
BLOCK DIAGRAM (SINGLE CHIP) ............................................................................................ 7
FUNCTIONAL DESCRIPTION.................................................................................................... 8
7.1
Power Up and Initialization ............................................................................................. 8
7.2
Programming Mode Register Set command .................................................................. 8
7.3
Bank Activate Command ................................................................................................ 8
7.4
Read and Write Access Modes ...................................................................................... 8
7.5
Burst Read Command .................................................................................................... 9
7.6
Burst Command .............................................................................................................. 9
7.7
Read Interrupted by a Read ........................................................................................... 9
7.8
Read Interrupted by a Write............................................................................................ 9
7.9
Write Interrupted by a Write ............................................................................................ 9
7.10 Write Interrupted by a Read............................................................................................ 9
7.11 Burst Stop Command ................................................................................................... 10
7.12 Addressing Sequence of Sequential Mode .................................................................. 10
7.13 Addressing Sequence of Interleave Mode .................................................................... 10
7.14 Auto-precharge Command ........................................................................................... 11
7.15 Precharge Command .................................................................................................... 11
7.16 Self Refresh Command ................................................................................................ 11
7.17 Power Down Mode ....................................................................................................... 12
7.18 No Operation Command ............................................................................................... 12
7.19 Deselect Command ...................................................................................................... 12
7.20 Clock Suspend Mode .................................................................................................... 12
OPERATION MODE ................................................................................................................. 13
ELECTRICAL CHARACTERISTICS ......................................................................................... 14
9.1
Absolute Maximum Ratings .......................................................................................... 14
9.2
Recommended DC Operating Conditions .................................................................... 14
9.3
Capacitance .................................................................................................................. 14
9.4
DC Characteristics ........................................................................................................ 15
9.5
AC Characteristics and Operating Condition ................................................................ 16
TIMING WAVEFORMS ............................................................................................................. 18
10.1 Command Input Timing ................................................................................................ 18
10.2 Read Timing.................................................................................................................. 19
10.3 Control Timing of Input/Output Data ............................................................................. 20
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Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.
12.
13.
10.4 Mode Register Set Cycle .............................................................................................. 21
OPERATINOPERATING TIMING EXAMPLE ........................................................................... 22
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ...................................... 22
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ........... 23
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ...................................... 24
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ........... 25
11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 26
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 27
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 28
11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ..................................... 29
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ........................................ 30
11.10 Auto-precharge Write (Burst Length = 4) .................................................................... 31
11.11 Auto Refresh Cycle ..................................................................................................... 32
11.12 Self Refresh Cycle ....................................................................................................... 33
11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3) ............................. 34
11.14 Power down Mode ....................................................................................................... 35
11.15 Auto-precharge Timing (Write Cycle) .......................................................................... 36
11.16 Auto-precharge Timing (Read Cycle) .......................................................................... 37
11.17 Timing Chart of Read to Write Cycle ........................................................................... 38
11.18 Timing Chart of Write to Read Cycle ........................................................................... 38
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) .......................................... 39
11.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 39
11.21 CKE/DQM Input Timing (Write Cycle) ......................................................................... 40
11.22 CKE/DQM Input Timing (Read Cycle) ......................................................................... 41
PACKAGE SPECIFICATION .................................................................................................... 42
REVISION HISTORY ................................................................................................................ 43
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Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
1. GENERAL DESCRIPTION
W9812G2KB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words 4 banks 32 bits. W9812G2KB delivers a data bandwidth of up to 166M words per
second. To fully comply with the personal computer industrial standard, W9812G2KB is sorted into
two grade parts: -6 and -6I. The -6 and-6I grade parts are compliant to the 166MHz/CL3 specification
(the -6I industrial grade which is guaranteed to support -40°C ≤ TA ≤ 85°C).
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle.
The multiple bank nature enables interleaving among internal banks to hide the precharging time.By
having a programmable Mode Register, the system can change burst length, latency cycle, interleave
or sequential burst to maximize its performance. W9812G2KB is ideal for main memory in high
performance applications.
2. FEATURES
3.3V ± 0.3V power supply
1,048,576 words 4 banks 32 bits organization
Self Refresh Current: Standard and Low Power
CAS Latency: 2 & 3
Burst Length: 1, 2, 4, 8 and full page
Sequential and Interleave Burst
Byte data controlled by DQM0-3
Auto-precharge and controlled precharge
Burst read, single write operation
4K refresh cycles/64mS
Interface: LVTTL
Packaged in TFBGA 90 Ball (8 x13 mm2), using Lead free materials with RoHS compliant
Dual-Die-Package (DDP), two pieces of 64M bits chip sealed in one package
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Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
BLOCK DIAGRAM (DDP)
CLK
CLK
VDD
CKE
CKE
VDDQ
CS
CAS, RAS, WE
BS0, BS1
A[11:0]
VSS
CS
64M (x16) bits
SDRAM 1
CAS, RAS, WE
BS0, BS1
VSSQ
LDQM, UDQM
A[11:0]
DQ[15:0]
CLK
VDD
CKE
VDDQ
VDD
VDDQ
VSS
VSSQ
DQM0, DMQ1
DQ[15:0]
VSS
CS
64M (x16) bits
SDRAM 2
CAS, RAS, WE
BS0, BS1
VSSQ
LDQM, UDQM
A[11:0]
DQ[15:0]
DQM2, DQM3
DQ[31:16]
Note:
There two same 4M x16 SDRAM chips sealed in this product. The specification in the following
pages are for the one chip, the 64M bits SDRAM’ except output slew rate, IDD and ball capacitance.
Although each die is tested individually within the dual-die package, some stacked die test results
may vary from a like-die tested within a monolithic die package.
3. ORDER INFORMATION
PART NUMBER
SPEED
SELF REFRESH
CURRENT (MAX.)
OPERATING
TEMPERATURE
W9812G2KB-6
166MHz/CL3
4mA
0°C ~ 70°C
W9812G2KB-6I
166MHz/CL3
4mA
-40°C ~ 85°C
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Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
4. BALL CONFIGURATION
Top View
1
2
3
DQ26
DQ24
VSS
DQ28
VDDQ
VSSQ
4
5
6
7
8
9
A
VDD
DQ23
DQ21
VSSQ
VDDQ
VSSQ
DQ19
DQ27
DQ25
DQ22
DQ20
VDDQ
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
VDDQ
DQ31
NC
NC
DQ16
VSSQ
VSS
DQM3
A3
A2
DQM2
VDD
A4
A5
A6
A10
A7
A8
NC
NC
CLK
CKE
A9
BS0
CS#
RAS#
DQM1
NC
NC
CAS#
WE#
DQM0
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
DQ13
DQ15
VSS
VDD
DQ0
DQ2
B
C
D
E
F
G
A0
A1
BS1
A11
H
J
K
L
M
N
P
R
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Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
5. BALL DESCRIPTION
BALL NUMBER
SYMBOL
FUNCTION
DESCRIPTION
G8,G9,F7,F3,G1,G2,
G3,H1,H2,J3,G7,H9
A0A11
Address
Multiplexed pins for row and column address.
Row address: A0A11. Column address: A0A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
J7,H8
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
Data
Input/ Output
Multiplexed pins for data output and input.
R8,N7,R9,N8,P9,M8
,M7,L8,L2,M3,M2,P1
,N2,R1,N3,R2,E8,D7
DQ0DQ31
,D8,B9,C8,A9,C7,A8
,A2,C3,A1,C2,B1,D2
,D3,E2
J8
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is ignored
and previous operation continues.
J9
RAS
Row Address
Strobe
Command input. When sampled at the rising edge
of the clock RAS , CAS and WE define the
operation to be executed.
K7
CAS
K8
WE
Write Enable
Referred to RAS
K9,K1,F8,F2
DQM0~3
Input/Output
mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with
zero latency.
J1
CLK
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
J2
CKE
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
A7,F9,L7,R7
VDD
Power
Power for input buffers and logic circuit inside DRAM.
A3,F1,L3,R3
VSS
Ground
Ground for input buffers and logic circuit inside DRAM.
B2,B7,C9,D9,E1,L1,
M9,N9,P2,P7
VDDQ
Power for I/O
buffer
Separated power from VDD, to improve DQ noise
immunity.
B8,B3,C1,D1,E9,L9,
M1,N1,P3,P8
VSSQ
Ground for I/O
buffer
Separated ground from VSS, to improve DQ noise
immunity.
E3,E7,H3,H7,K2,K3
NC
No Connection
No connection
Column Address
Referred to RAS
Strobe
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Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
6. BLOCK DIAGRAM (SINGLE CHIP)
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
RAS
GENERATOR
COMMAND
CAS
DECODER
COLUMN DECODER
A10
MODE
REGISTER
A0
CELL ARRAY
BANK #1
SENSE AMPLIFIER
SENSE AMPLIFIER
ADDRESS
BUFFER
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ0
DQ15
COLUMN
UDQM
LDQM
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #2
COLUMN DECODER
ROW DECODER
REFRESH
COUNTER
ROW DECODER
A9
A11
BS0
BS1
CELL ARRAY
BANK #0
COLUMN DECODER
ROW DECODER
ROW DECODER
WE
SENSE AMPLIFIER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE:
The cell array configuration is 4096 * 256 * 16
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Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
7. FUNCTIONAL DESCRIPTION
7.1 Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the “NOP” state. The power up voltage must not exceed VDD + 0.3V
on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required followed
by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power up, it is required that the DQM and CKE pins be held high during the initial pause period.
Once all banks have been precharged, the Mode Register Set Command must be issued to initialize
the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after
programming the Mode Register to ensure proper subsequent operation.
7.2
Programming Mode Register Set command
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to tRSC
has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
7.3
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as tRAS (max.).
7.4
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level
defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The
address inputs determine the starting column address.
Reading or writing to a different row within an activated bank requires the bank be precharged and a
new Bank Activate command be issued. When more than one bank is activated, interleaved bank
Read or Write operations are possible. By using the programmed burst length and alternating the
access and precharge operations between multiple banks, seamless data access operation among
many different pages can be realized. Read or Write Commands can also be issued to the same bank
or between active banks on every clock cycle.
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Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
7.5
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding
RAS and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.
7.6
Burst Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while
holding RAS high at the rising edge of the clock. The address inputs determine the starting column
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.
7.7
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS Latency from the
interrupting Read Command the is satisfied.
7.8
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
7.9
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
7.10 Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
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Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
7.11 Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of
the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS
Latency in a burst read cycle, interrupted by Burst Stop.
7.12 Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
n
BL = 2 (disturb address is A0)
Data 1
n+1
No address carry from A0 to A1
Data 2
n+2
BL = 4 (disturb addresses are A0 and A1)
Data 3
n+3
No address carry from A1 to A2
Data 4
n+4
Data 5
n+5
BL = 8 (disturb addresses are A0, A1 and A2)
Data 6
n+6
No address carry from A2 to A3
Data 7
n+7
7.13 Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
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BL = 4
BL = 8
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
7.14 Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS Latency.
A Read or Write Command with auto-precharge cannot be interrupted before the entire burst
operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is
prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started,
the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of AutoPrecharge command is illegal if the burst is set to full page length. If A10 is high when a Write
Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically
enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred
to as write tWR. The bank undergoing auto-precharge cannot be reactivated until tWR and tRP are
satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Autoprecharge Command, the interval between the Bank Activate Command and the beginning of the
internal precharge operation must satisfy tRAS (min).
7.15 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(tRP).
7.16 Self Refresh Command
The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE
high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. Any subsequent commands can be issued after
tXSR from the end of Self Refresh Command.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
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Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min.) + tCK (min.).
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't Care.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
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Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1), (2))
COMMAND
DEVICE
STATE
CKEn-1 CKEn DQM BS0, 1
A10
A0-A9,
A11
CS
RAS
CAS
WE
Bank Active
Idle
H
x
x
v
v
V
L
L
H
H
Bank Precharge
Any
H
x
x
v
L
x
L
L
H
L
Precharge All
Any
H
x
x
x
H
x
L
L
H
L
Active (3)
H
x
x
v
L
v
L
H
L
L
Active
(3)
H
x
x
v
H
v
L
H
L
L
Read
Active
(3)
H
x
x
v
L
v
L
H
L
H
Read with Auto-precharge
Active (3)
H
x
x
v
H
v
L
H
L
H
Idle
H
x
x
v
v
v
L
L
L
L
Write
Write with Auto-precharge
Mode Register Set
No-Operation
Any
H
x
x
x
x
x
L
H
H
H
Active (4)
H
x
x
x
x
x
L
H
H
L
Device Deselect
Any
H
x
x
x
x
x
H
x
x
x
Auto-Refresh
Idle
H
H
x
x
x
x
L
L
L
H
Self-Refresh Entry
Idle
H
L
x
x
x
x
L
L
L
H
Self Refresh Exit
idle
(S.R)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Clock suspend Mode
Entry
Active
H
L
x
x
x
x
x
x
x
x
Power Down Mode Entry
Idle
Active (5)
H
H
L
L
x
x
x
x
x
x
x
x
H
L
x
H
x
H
X
H
Clock Suspend Mode Exit
Active
L
H
x
x
x
x
x
x
x
X
Power Down Mode Exit
Any
(Power
Down)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
X
H
Data write/Output Enable
Active
H
x
L
x
x
x
x
x
x
x
Data write/Output Disable
Active
x
H
x
x
x
x
x
x
x
Burst Stop
H
Notes:
(1) v = valid, x = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input leve l when commands are provided.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
- 13 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
NOTES
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ VDD + 0.5 (≤ 4.6V max.)
V
1
Voltage on VDD/VDDQ supply
relative to VSS
VDD, VDDQ
-0.5 ~ 4.6
V
1
Operating Temperature for -6
TOPR
0 ~ 70
°C
1
Operating Temperature for -6I
TOPR
-40 ~ 85
°C
Storage Temperature
TSTG
-55 ~ 150
°C
1
TSOLDER
260
°C
1
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
PD
1
W
1
IOUT
50
mA
1
Note:
1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of
the device.
9.2
Recommended DC Operating Conditions
(VDD = 3.3V ± 0.3V, TA = 0°C~70°C for -6, TA = -40°C~85°C for -6I)
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
NOTES
VDD
3.0
3.3
3.6
V
2
VDDQ
3.0
3.3
3.6
V
2
Input High Voltage
VIH
2.0
-
VDD + 0.3
V
2
Input Low Voltage
VIL
-0.3
-
0.8
V
2
SYM.
MIN.
MAX.
UNIT
Ci1
5.0
8
pf
CCLK
5.0
8
pf
Input/Output Capacitance (DQ0DQ31)
Co
4
6.5
pf
Input Capacitance DQM
Ci2
3.0
5.5
pf
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
Note: VIH(max) = VDD/ VDDQ+1.5V for pulse width ≤ 5 nS
VIL(min) = VSS/ VSSQ-1.5V for pulse width ≤ 5 nS
9.3
Capacitance
(VDD =3.3V ± 0.3V, TA = 25°C, f = 1 MHz)
PARAMETER
Input Capacitance
(A0 to A11, BS0, BS1, CS , RAS , CAS , WE , CKE)
Input Capacitance (CLK)
Note: These parameters are periodically sampled and not 100% tested
- 14 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
9.4
DC Characteristics
(VDD = 3.3V ± 0.3V, TA = 0°C~70°C for -6, TA = -40°C~85°C for -6I)
PARAMETER
SYM.
-6/-6I
MAX.
UNIT
NOTES
Operating Current
tCK = min., t RC = min.
Active precharge command cycling without
burst operation
1 Bank Operation
IDD1
100
3
Standby Current
CKE = VIH
IDD2
50
3
(Power Down
mode)
IDD2P
4
3
CKE = VIH
IDD2S
24
IDD2PS
4
IDD3
70
IDD3P
24
IDD4
150
3, 4
IDD5
120
3
IDD6
4
tCK = min., CS = VIH
VIH /L = VIH (min.) / VIL (max.)
Bank: inactive state
CKE = VIL
Standby Current
CLK = VIL, CS = VIH
CLKVIH/L = VIH (min.) / VIL (max.)
Bank: inactive state
CKE = VIL
(Power Down
mode)
No Operating Current
CKE = VIH
tCK = min., CS = VIH (min.)
Bank: active state (4 Banks)
CKE = VIL
(Power Down
mode)
Burst Operating Current
(t CK = min.)
Read/ Write command cycling
Auto Refresh Current
(t CK = min.)
Auto refresh command cycling
Self Refresh Current
(CKE = 0.2V)
Self refresh mode
PARAMETER
mA
SYMBOL
MIN.
MAX.
UNIT
Input Leakage Current
(0V ≤ VIN ≤ VDD, all other pins not under test = 0V)
II(L)
-5
5
µA
Output Leakage Current
(Output disable, 0V ≤ VOUT ≤ VDDQ)
lO(L)
-5
5
µA
LVTTL Output “H” Level Voltage
(IOUT = -2 mA)
VOH
2.4
-
V
LVTTL Output “L” Level Voltage
(IOUT = 2 mA)
VOL
-
0.4
V
- 15 -
NOTES
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
9.5
AC Characteristics and Operating Condition
(VDD = 3.3V ± 0.3V, TA = 0°C~70°C for -6, TA = -40°C~85°C for -6I) (Notes: 5, 6)
PARAMETER
SYM
-6/-6I
MIN.
Ref/Active to Ref/Active Command Period
tRC
60
Active to precharge Command Period
tRAS
42
Active to Read/Write Command Delay Time
tRCD
18
Read/Write(a) to Read/Write(b) Command Period
tCCD
1
Precharge to Active Command Period
tRP
18
Active(a) to Active(b) Command Period
tRRD
12
Write Recovery Time
CLK Cycle Time
CL* = 2
CL* = 3
CL* = 2
CL* = 3
tWR
tCK
MAX.
100000
UNIT
NOTES
nS
tCK
nS
2
tCK
2
10
1000
6
1000
CLK High Level width
tCH
2
8
CLK Low Level width
tCL
2
8
Access Time from CLK
CL* = 2
CL* = 3
Output Data Hold Time
Output Data High Impedance Time
tOH
CL* = 2
CL* = 3
6
tAC
9
5
9
3
6
tHZ
7
5
Output Data Low Impedance Time
tLZ
nS
Power Down Mode Entry Time
tSB
6
Transition Time of CLK (Rise and Fall)
tT
1
Data-in Set-up Time
tDS
1.5
8
Data-in Hold Time
tDH
1
8
Address Set-up Time
tAS
1.5
8
Address Hold Time
tAH
1
8
CKE Set-up Time
tCKS
1.5
8
CKE Hold Time
tCKH
1
8
Command Set-up Time
tCMS
1.5
8
Command Hold Time
tCMH
1
8
Refresh Time (4K/Refresh Cycles)
tREF
Mode register Set Cycle Time
tRSC
2
tCK
Exit self refresh to ACTIVE command
tXSR
72
nS
0
64
9
mS
* CL = CAS Latency
- 16 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
Notes:
1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum
values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with output open.
5. Power up sequence please refer to “Functional Description” section described before.
6. AC test load diagram.
1.4 V
50 ohms
output
Z = 50 ohms
30pF
AC TEST LOAD
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output
level.
8. Assumed input rise and fall time (tT) = 1nS.
If tr & tf is longer than 1nS, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]nS should be added to the parameter
9. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.
- 17 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
10. TIMING WAVEFORMS
10.1 Command Input Timing
tCK
tCL
tCH
VIH
CLK
VIL
tT
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tAS
tAH
tCMH
tT
tCMS
CS
RAS
CAS
WE
A0-A11
BS0,1
tCKS
tCKH
tCKS
tCKH
tCKS
tCKH
CKE
- 18 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
10.2 Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
A0-A11
BS0,1
tAC
tLZ
tAC
tOH
Valid
Data-Out
Valid
Data-Out
DQ
Read Command
tHZ
tOH
Burst Length
- 19 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
10.3 Control Timing of Input/Output Data
Control Timing of Input Data
(Word Mask)
CLK
tCMS
tCMH
tCMH
tCMS
DQM
tDS
tDH
tDS
tDS
Valid
Data-in
Valid
Data-in
DQ0~31
tDH
tDH
tDS
tDH
Valid
Data-in
Valid
Data-in
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tDH
tDS
tDH
tCKS
CKE
tDS
DQ0~31
Valid
Data-in
tDS
Valid
Data-in
tDH
tDS
tDH
Valid
Data-in
Valid
Data-in
Control Timing of Output Data
(Output Enable)
CLK
tCMS
tCMH
tCMH
tCMS
DQM
tAC
tOH
tAC
tLZ
Valid
Data-Out
Valid
Data-Out
DQ0~31
tAC
tHZ
tOH
tOH
tAC
tOH
Valid
Data-Out
OPEN
(Clock Mask)
CLK
tCKS
tCKH
tCKH
tCKS
CKE
DQ0~31
tOH
tOH
Valid
Data-Out
- 20 -
tAC
tAC
tAC
tAC
tOH
Valid
Data-Out
tOH
Valid
Data-Out
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
10.4 Mode Register Set Cycle
tRSC
CLK
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tAS
tAH
CS
RAS
CAS
WE
A0-A11
BS0,1
Register
set data
next
command
A0
A1
A2
0
0
0
0
1
1
1
1
Burst Length
A2
A3
Addressing Mode
A4
A5
CAS Latency
A6
A0
A7
"0"
(Test Mode)
A8
"0"
Reserved
A0
A3
0
1
A6
0
0
0
0
1
WriteA0
Mode
A9
A10
"0"
A0
A11
"0"
BS0
"0"
BS1
"0"
A1
A0 A0
A0
0
0
A0
0
1
A0
1
0
A0
1
1
A0
0
0
A0
0
1
A0
1
0
A0
1
1
Reserved
A5
A0 A4
A0
0
0
A0
0
1
A0
1
0
A0
1
1
A0
0
0
A0
A9
0
1
Burst Length
Sequential
Interleave
1
1
2
2
4
4
8
8
Reserved
Reserved
Full Page
Addressing Mode
Sequential
Interleave
CAS Latency
Reserved
Reserved
2
3
Reserved
Single Write Mode
Burst read and Burst write
Burst read and single write
* "Reserved" should stay "0" during MRS cycle.
- 21 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11. OPERATINOPERATING TIMING EXAMPLE
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
tRC
tRC
RAS
tRAS
tRP
tRP
tRAS
tRAS
tRP
tRAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9,
A11
RAa
tRCD
tRCD
RBb
CAw
tRCD
RAc
CBx
RBb
RAe
RBd
RAc
CAy
RBd
CBz
RAe
DQM
CKE
tAC
DQ
tRRD
Bank #0
Active
Bank #1
aw1
aw2
aw3
bx0
tRRD
Read
Precharge
Active
Read
bx1
bx2
bx3
cy0
tRRD
Active
tAC
tAC
tAC
aw0
cy1
cy2
cy3
tRRD
Precharge
Read
Precharge
Active
Active
Read
Bank #2
Idle
Bank #3
- 22 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)
0
1
2
3
4
5
6
7
8
9
11
10
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
tRCD
tRCD
A10
RAa
RBb
A0-A9,
A11
RAa
CAw RBb
tRCD
RBd
RAc
CBx
RAc
RAe
RBd
CAy
CBz
RAe
DQM
CKE
tAC
DQ
tRRD
Bank #0
Active
Bank #1
aw1
aw2
aw3
bx0
bx1
tRRD
Read
Active
tAC
tAC
tAC
aw0
bx2
bx3
cy0
cy1
tRRD
Active
AP*
Read
cy3
dz0
tRRD
Read
AP*
cy2
Active
AP*
Active
Read
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 23 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9,
A11
RAa
tRCD
tRCD
RBb
CAx
RAc
RBb
RAc
CBy
CAz
DQM
CKE
tAC
DQ
tAC
ax0
ax1
ax2
ax3
tRRD
Bank #0
Active
Bank #1
ax4
ax6
by0
by4
by1
by5
by6
by7
CZ0
tRRD
Read
Precharge
ax5
tAC
Precharge
Active
Read
Active
Read
Precharge
Bank #2
Idle
Bank #3
- 24 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tRC
CS
RAS
tRAS
tRP
tRAS
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9,
A11
RAa
tRCD
tRCD
RAc
RBb
CAx
CBy
RBb
RAc
CAz
DQM
CKE
tAC
DQ
ax0
ax1
ax3
ax2
Active
Bank #1
ax4
ax5
ax6
ax7
by0
by1
by4
Active
Read
by5
by6
CZ0
tRRD
tRRD
Bank #0
tAC
tAC
Read
AP*
Active
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 25 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.5 Interleaved Bank Write (Burst Length = 8)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
CAS
tRCD
tRCD
tRCD
WE
BS0
BS1
A10
A0-A9,
A11
RBb
RAa
RAa
CAx
RAc
CBy
RBb
RAc
CAz
DQM
CKE
DQ
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
tRRD
Bank #0
Active
Bank #1
Bank #2
Bank #3
by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
Precharge
Write
Active
Write
Active
Write
Precharge
Idle
- 26 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRP
tRAS
tRAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9,
A11
RAa
tRCD
tRCD
RBb
CAx
RAb
CBy
RBb
RAc
CAz
DQM
CKE
ax0
DQ
ax1
ax4
ax5
ax6
ax7
by0
by1
AP*
Write
Active
Bank #1
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
tRRD
Bank #0 Active
by2
Write
Active
Write
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 27 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tCCD
tCCD
tCCD
CS
tRAS
tRAS
RAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9,
A11
RAa
tRCD
RBb
CAI
RBb
CBx
CAy
CAm
CBz
DQM
CKE
DQ
a0
a1
a2
a3
tAC
tAC
tAC
tAC
bx0
bx1
tAC
Ay0
Ay1
Ay2
am0
am1
am2
bz0
bz1
bz2
bz3
tRRD
Bank #0 Active
Read
Active
Bank #1
Read
Read
Read
Precharge
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 28 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)
0
1
2
3
5
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRAS
RAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9,
A11
RAa
CAx
CAy
DQM
CKE
tAC
DQ
tWR
ax0
Q Q
Bank #0
Active
ax1
ax3
ax2
Q
Q
ax5
ax4
Q
Read
Q
ay1
ay0
D
D
Write
ay2
D
ay3
D
ay4
D
Precharge
Bank #1
Bank #2
Bank #3
Idle
- 29 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
CAS
WE
BS0
BS1
tRCD
A10
tRCD
RAa
A0-A9,
A11
RAa
RAb
CAw
RAb
CAx
DQM
CKE
tAC
DQ
tAC
aw0
Bank #0
Active
Read
aw1
aw2
AP*
aw3
bx0
Active
Read
bx1
bx2
bx3
AP*
Bank #1
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 30 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.10 Auto-precharge Write (Burst Length = 4)
0
1
2
3
6
5
4
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
tRCD
A10
RAa
A0-A9,
A11
RAa
RAb
CAw
RAb
RAc
CAx
RAc
DQM
CKE
DQ
aw0
Active
Bank #0
Write
aw1
aw2
aw3
bx0
Active
AP*
Write
bx1
bx2
bx3
AP*
Active
Bank #1
Bank #2
Idle
* AP is the internal precharge start timing
Bank #3
- 31 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.11 Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tRP
tRC
tRC
CS
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
CKE
DQ
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
- 32 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.12 Self Refresh Cycle
CLK
CS
tRP
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
tCKS
tSB
CKE
tCKS
DQ
tXSR
Self Refresh Cycle
All Banks
Precharge
Self Refresh
Entry
No Operation / Command Inhibit
Self Refresh
Exit
- 33 -
Arbitrary Cycle
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
t RCD
WE
BS0
BS1
A10
RBa
A0-A9,
A11
RBa
CBv
CBw
CBx
CBy
CBz
aw0
ax0
ay0
az0
az1
az2
az3
D
D
D
Q
Q
Q
Q
DQM
CKE
tAC
tAC
DQ
Bank #0
Active
av0
av1
av2
av3
Q
Q
Q
Q
Read
Single Write Read
Bank #1
Bank #2
Idle
Bank #3
- 34 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.14 Power down Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BS
A10
A0-A9,
A11
RAa
RAa
CAa
RAa
RAa
CAx
DQM
tSB
tSB
CKE
tCKS
tCKS
tCKS
DQ
ax0
Active
ax1
NOP Read
ax2
tCKS
ax3
Precharge
NOP Active
Precharge Standby
Power Down mode
Active Standby
Power Down mode
Note: The Power Down Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Violating refresh requirements during power-down may result in a loss of data.
- 35 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.15 Auto-precharge Timing (Write Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
(1) CAS Latency = 2
(a) burst length = 1
Command
Write
AP
tWR
DQ
Act
tRP
D0
(b) burst length = 2
Command
Write
AP
Act
tWR
DQ
D0
tRP
D1
(c) burst length = 4
Command
AP
Write
DQ
D0
D1
D2
Act
tRP
tWR
D3
(d) burst length = 8
Command
Write
AP
tWR
DQ
D0
D1
D2
D3
D4
D5
D6
Act
tRP
D7
(2) CAS Latency = 3
(a) burst length = 1
Command
Write
AP
Act
tWR
DQ
(b) burst length = 2
Command
tRP
D0
Write
AP
Act
tWR
DQ
D0
tRP
D1
(c) burst length = 4
Command
Write
AP
Act
tWR
DQ
D0
D1
D2
tRP
D3
(d) burst length = 8
Command
Write
AP
tWR
DQ
D0
D1
D2
D3
D4
D5
D6
Act
tRP
D7
Note )
Write
represents the Write with Auto precharge command.
AP
represents the start of internal precharing.
Act
represents the Bank Active command.
When the /auto precharge command is asserted,the period from Bank Activate
command to the start of intermal precgarging must be at least tRAS (min).
- 36 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.16 Auto-precharge Timing (Read Cycle)
0
1
Read
AP
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) burst length = 1
Command
DQ
Act
tRP
Q0
( b ) burst length = 2
Command
Read
AP
Act
tRP
DQ
Q0
Q1
( c ) burst length = 4
Command
Read
AP
Act
tRP
DQ
Q0
Q1
Q2
Q3
( d ) burst length = 8
Command
Read
AP
Q0
DQ
Q1
Q2
Q3
Q4
Q5
Q6
Act
tRP
Q7
(2) CAS Latency=3
( a ) burst length = 1
Command
Read
AP
Act
tRP
Q0
DQ
( b ) burst length = 2
Command
Read
AP
Act
tRP
Q0
DQ
( c ) burst length = 4
Command
Read
Q1
AP
Act
tRP
Q0
DQ
Q1
Q2
Q3
( d ) burst length = 8
Command
Read
AP
Act
tRP
Q0
DQ
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Note )
Read
represents the Read with Auto precharge command.
AP
represents the start of internal precharging.
Act
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at leastRAS
t (min).
- 37 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.17 Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
(1) CAS Latency= 2
0
( a ) Command
1
2
Read
Write
3
4
5
6
D1
D2
D3
D0
D1
D2
D1
D2
D3
D1
D2
7
8
9
10
11
DQM
DQ
D0
Read
( b ) Command
Write
DQM
DQ
D3
(2) CAS Latency= 3
Read
( a ) Command
Write
DQM
D0
DQ
Read
( b ) Command
Write
DQM
D0
DQ
D3
Note: The Output data must be masked by DQM to avoid I/O conflict
11.18 Timing Chart of Write to Read Cycle
In the c as e of B urs t Length=4
0
1
2
3
4
5
6
7
8
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
9
10
11
(1) CAS Latency= 2
( a ) Command
Write Read
DQM
DQ
( b ) Command
D0
Read
Write
DQM
DQ
D0
D1
(2) CAS Latency= 3
( a ) Command
Write Read
DQM
DQ
( b ) Command
D0
Write
Read
DQM
DQ
D0
D1
- 38 -
Q3
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a ) CAS latency =2
C omma nd
Read
BST
Q0
DQ
Q1
Q2
Q0
Q1
Q3
Q4
( b )CAS latency = 3
C omma nd
Read
BST
DQ
Q2
Q3
Q4
(2) Write cycle
C omma nd
DQ
Write
Q0
BST
Q1
Q2
Note:
Q3
Q4
BST
represents the Burst stop command
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
(a) CAS latency =2
Command
Read
PRCG
DQ
(b) CAS latency =3
Command
Q0
Q1
Q2
Read
Q3
Q4
PRCG
DQ
Q0
Q1
Q2
Q3
Q4
(2) Write cycle
Command
PRCG
Write
tWR
DQM
DQ
Q0
Q1
Q2
Q3
- 39 -
Q4
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.21 CKE/DQM Input Timing (Write Cycle)
CLK cycle No.
1
2
3
D1
D2
D3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
D5
DQM MASK
D6
CKE MASK
( 1)
CLK cycle No.
1
2
3
D1
D2
D3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
DQM MASK
D5
D6
5
6
7
D4
D5
D6
CKE MASK
( 2)
CLK cycle No.
1
2
3
D1
D2
D3
4
External
CLK
Internal
CKE
DQM
DQ
CKE MASK
( 3)
- 40 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
11.22 CKE/DQM Input Timing (Read Cycle)
CLK cycle No.
1
2
3
4
Q1
Q2
Q3
Q4
6
5
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Open
Open
(1)
CLK cycle No.
1
2
3
Q1
Q2
Q3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Q4
Open
(2)
CLK cycle No.
1
2
Q1
Q2
3
4
5
6
7
Q4
Q5
Q6
External
CLK
Internal
CKE
DQM
DQ
Q3
(3)
- 41 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
12. PACKAGE SPECIFICATION
TFBGA 90 Balls (8 x 13 mm2, Ball pitch: 0.8mm, Ø =0.45mm)
TOP VIEW
BOTTOM VIEW
Φb
A1 CORNER
A1 CORNER
9 8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
E2
E
e
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
e
D2
D
y
CONTROL DIMENSIONS ARE IN MILLIMETERS.
MILLIMETER
SYMBOL
SEATING PLANE
A1 A
Ball Land
NOM.
MAX.
MIN.
NOM.
MAX.
---
1.20
---
---
0.047
A
---
A1
0.25
---
0.40
0.010
---
0.016
D
7.95
8.00
8.05
0.313
0.315
0.317
6.40 BASIC
D2
E
12.95
e
13.05
0.40
--0.80 BASIC
0.510
0.512
0.514
0.441 BASIC
0.15 BASIC
y
Φb
13.0
0.252 BASIC
11.2 BASIC
E2
Ball Opening
INCH
MIN.
0.006 BASIC
0.50
0.016
---
0.020
0.032 BASIC
Note: Ball land: 0.5mm / Ball opening: 0.4mm
- 42 -
Publication Release Date: Jun. 20, 2014
Revision: A01
W9812G2KB
13. REVISION HISTORY
VERSION
DATE
PAGE
A01
Jun. 20, 2014
All
DESCRIPTION
Initial formally datasheet
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
- 43 -
Publication Release Date: Jun. 20, 2014
Revision: A01
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