W9864G2JH
512K 4 BANKS 32BITS SDRAM
Table of Contents1.
GENERAL DESCRIPTION ......................................................................................................... 3
2.
FEATURES ................................................................................................................................. 3
3.
ORDER INFORMATION ............................................................................................................. 3
4.
PIN CONFIGURATION ............................................................................................................... 4
5.
PIN DESCRIPTION..................................................................................................................... 5
6.
BLOCK DIAGRAM ...................................................................................................................... 6
7.
FUNCTIONAL DESCRIPTION.................................................................................................... 7
8.
7.1
Power Up and Initialization ............................................................................................. 7
7.2
Programming Mode Register .......................................................................................... 7
7.3
Bank Activate Command ................................................................................................ 7
7.4
Read and Write Access Modes ...................................................................................... 7
7.5
Burst Read Command .................................................................................................... 8
7.6
Burst Command .............................................................................................................. 8
7.7
Read Interrupted by a Read ........................................................................................... 8
7.8
Read Interrupted by a Write............................................................................................ 8
7.9
Write Interrupted by a Write ............................................................................................ 8
7.10
Write Interrupted by a Read............................................................................................ 8
7.11
Burst Stop Command ..................................................................................................... 9
7.12
Addressing Sequence of Sequential Mode .................................................................... 9
7.13
Addressing Sequence of Interleave Mode ...................................................................... 9
7.14
Auto-precharge Command ........................................................................................... 10
7.15
Precharge Command .................................................................................................... 10
7.16
Self Refresh Command ................................................................................................ 10
7.17
Power Down Mode ....................................................................................................... 11
7.18
No Operation Command ............................................................................................... 11
7.19
Deselect Command ...................................................................................................... 11
7.20
Clock Suspend Mode .................................................................................................... 11
OPERATION MODE ................................................................................................................. 12
8.1
9.
Simplified Stated Diagram ............................................................................................ 13
ELECTRICAL CHARACTERISTICS ......................................................................................... 14
9.1
Absolute Maximum Ratings .......................................................................................... 14
9.2
Recommended DC Operating Conditions .................................................................... 14
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Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
10.
11.
9.3
Capacitance .................................................................................................................. 15
9.4
DC Characteristics ........................................................................................................ 15
9.5
AC Characteristics and Operating Condition ................................................................ 16
TIMING WAVEFORMS ............................................................................................................. 18
10.1
Command Input Timing ................................................................................................ 18
10.2
Read Timing.................................................................................................................. 19
10.3
Control Timing of Input/Output Data ............................................................................. 20
10.4
Mode Register Set Cycle .............................................................................................. 21
OPERATING TIMING EXAMPLE ............................................................................................. 22
11.1
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ...................................... 22
11.2
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ........... 23
11.3
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ...................................... 24
11.4
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ........... 25
11.5
Interleaved Bank Write (Burst Length = 8) ................................................................... 26
11.6
Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 27
11.7
Page Mode Read (Burst Length = 4, CAS Latency = 3)............................................... 28
11.8
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ..................................... 29
11.9
Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ........................................ 30
11.10
Auto-precharge Write (Burst Length = 4) .................................................................... 31
11.11
Auto Refresh Cycle ..................................................................................................... 32
11.12
Self Refresh Cycle ....................................................................................................... 33
11.13
Bust Read and Single Write (Burst Length = 4, CAS Latency = 3) ............................. 34
11.14
Power Down Mode ...................................................................................................... 35
11.15
Auto-precharge Timing (Write Cycle) .......................................................................... 36
11.16
Auto-precharge Timing (Read Cycle) .......................................................................... 37
11.17
Timing Chart of Read to Write Cycle ........................................................................... 38
11.18
Timing Chart of Write to Read Cycle ........................................................................... 38
11.19
Timing Chart of Burst Stop Cycle (Burst Stop Command) .......................................... 39
11.20
Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 39
11.21
CKE/DQM Input Timing (Write Cycle) ......................................................................... 40
11.22
CKE/DQM Input Timing (Read Cycle) ......................................................................... 41
12.
PACKAGE SPECIFICATION .................................................................................................... 42
13.
REVISION HISTORY ................................................................................................................ 43
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Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
1. GENERAL DESCRIPTION
W9864G2JH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words 4 banks 32 bits. W9864G2JH delivers a data bandwidth of up to 200M words per
second. For different application, W9864G2JH is sorted into the following speed grades: -5, -6, -6I, -6A,
-6K and -7. The -5 parts can run up to 200MHz/CL3. The -6, -6I, -6A and -6K parts can run up to 166
MHz/CL3, -6I industrial grade, -6A automotive grade which is guaranteed to support -40°C ≤ TA ≤ 85°C.
If -6K automotive grade offered, has two simultaneous requirements: ambient temperature (TA)
surrounding the device cannot be less than -40°C or greater than +105°C, and the case temperature
(TCASE) cannot be less than -40°C or greater than +105°C.) The -7 parts can run up to 143 MHz/CL3.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed
at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command.
Column addresses are automatically generated by the SDRAM internal counter in burst operation.
Random column read is also possible by providing its address at each clock cycle. The multiple bank
nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9864G2JH is ideal for main memory in
high performance applications.
2. FEATURES
3.3V ± 0.3V for -5/-6/-6I/-6A/-6K grades power supply
2.7V~3.6V for -7 grade power supply
Up to 200 MHz Clock Frequency
524,288 words 4 banks 32 bits organization
Self Refresh Current: Standard and Low Power
CAS Latency: 2 & 3
Burst Length: 1, 2, 4, 8 and full page
Sequential and Interleave Burst
Byte data controlled by DQM0-3
Auto-precharge and controlled precharge
Burst read, single write operation
4K Refresh cycles/64 mS, @ -40°C ≤ TA / TCASE ≤ 85°C
4K Refresh cycles/16 mS, @ 85°C < TA / TCASE ≤ 105°C
Interface: LVTTL
Packaged in TSOP II 86-pin, using Lead free materials with RoHS compliant
* Note: Not support self refresh function with TA / TCASE > 85°C
3. ORDER INFORMATION
PART NUMBER
W9864G2JH-5
W9864G2JH-6
W9864G2JH-6I
W9864G2JH-6A
W9864G2JH-6K
W9864G2JH-7
SPEED
MAXIMUM SELF
REFRESH CURRENT
200MHz/CL3
166MHz/CL3
166MHz/CL3
166MHz/CL3
166MHz/CL3
143MHz/CL3
2mA
2mA
2mA
2mA
5mA
2mA
-3-
OPERATING
TEMPERATURE
0°C ~ 70°C
0°C ~ 70°C
-40°C ~ 85°C
-40°C ~ 85°C
-40°C ~ 105°C
0°C ~ 70°C
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
4. PIN CONFIGURATION
VDD
1
86
VSS
DQ0
2
85
DQ15
VDDQ
3
84
VSSQ
DQ1
4
83
DQ14
DQ13
DQ2
5
82
VSSQ
6
81
VDDQ
DQ3
7
80
DQ12
DQ11
DQ4
8
79
VDDQ
9
78
VSSQ
DQ5
10
77
DQ10
DQ9
DQ6
11
76
VSSQ
12
75
VDDQ
DQ7
13
74
DQ8
NC
NC
14
73
VDD
15
72
VSS
DQM0
16
71
DQM1
WE
17
70
NC
CAS
18
69
NC
RAS
19
68
CLK
CS
20
67
CKE
NC
21
66
A9
BS0
22
65
A8
BS1
23
64
A7
A10/AP
24
63
A6
A0
25
62
A5
A1
26
61
A4
A2
27
60
A3
DQM2
28
59
DQM3
VDD
29
58
VSS
NC
30
57
NC
DQ16
31
56
DQ31
VSSQ
32
55
VDDQ
DQ17
33
54
DQ30
DQ18
34
53
DQ29
VDDQ
35
52
VSSQ
DQ19
36
51
DQ28
DQ20
37
50
DQ27
VSSQ
38
49
VDDQ
DQ21
39
48
DQ26
DQ22
40
47
DQ25
VDDQ
41
46
VSSQ
DQ23
42
45
DQ24
VDD
43
44
VSS
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Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
5. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
24, 25, 26, 27, 60, 61, 62,
63, 64, 65, 66
A0A10
Address
Multiplexed pins for row and column address.
Row address: A0A10. Column address: A0A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or
bank selected by BS0, BS1.
22, 23
BS0, BS1
Bank Select
Select bank to activate during row address latch
time, or bank to read/write during address latch
time.
2, 4, 5, 7, 8, 10, 11, 13, 31,
33, 34, 36, 37, 39, 40, 42,
45, 47, 48, 50, 51, 53, 54,
56, 74, 76, 77, 79, 80, 82,
83, 85
DQ0DQ31
20
CS
Chip Select
19
RAS
Row Address
Strobe
18
CAS
17
WE
Write Enable
Referred to RAS
16, 28, 59, 71
DQM0DQM3
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency
of 2) when DQM is sampled high in read cycle.
In write cycle, sampling DQM high will block the
write operation with zero latency.
68
CLK
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and
deactivation. When CKE is low, Power Down
mode, Suspend mode, or Self Refresh mode is
entered.
Data
Input/ Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising
edge of the clock RAS , CAS and WE define
the operation to be executed.
Column Address
Referred to RAS
Strobe
67
CKE
Clock Enable
1, 15, 29, 43
VDD
Power
Power for input buffers and logic circuit inside
DRAM.
44, 58, 72, 86
VSS
Ground
Ground for input buffers and logic circuit inside
DRAM.
3, 9, 35, 41, 49, 55, 75, 81
VDDQ
Power for I/O
Buffer
6, 12, 32, 38, 46, 52, 78, 84
VSSQ
Ground for I/O Separated ground from VSS, to improve DQ
Buffer
noise immunity.
14, 21, 30, 57, 69, 70, 73
NC
Separated power from VDD, to improve DQ
noise immunity.
No Connection No connection.
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Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
6. BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
C ON TR OL
CS
SIGN AL
RAS
GEN ER ATOR
COMMAND
CAS
DECODER
COLUMN DECODER
A10
MODE
REGISTER
A0
CELL ARRAY
BANK #1
SENSE AMPLIFIER
SENSE AMPLIFIER
ADDRESS
BUFFER
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ0
DQ31
COLUMN
COUNTER
DQM0~3
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
ROW DECODER
REFRESH
COUNTER
ROW DECODER
A9
BS0
BS1
CELL ARRAY
BANK #0
COLUMN DECODER
ROW DECODER
ROW DECODER
WE
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE:
The cell array configuration is 2048 * 256 * 32
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Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
7. FUNCTIONAL DESCRIPTION
7.1
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the “NOP” state. The power up voltage must not exceed VDD + 0.3V
on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required
followed by a precharge of all banks using the precharge command. To prevent data contention on the
DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required
before or after programming the Mode Register to ensure proper subsequent operation.
7.2
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during
this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to tRSC has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
7.3
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as tRAS (max.).
7.4
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level
defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The
address inputs determine the starting column address. Reading or writing to a different row within an
activated bank requires the bank be precharged and a new Bank Activate command be issued. When
more than one bank is activated, interleaved bank Read or Write operations are possible. By using the
programmed burst length and alternating the access and precharge operations between multiple
banks, seamless data access operation among many different pages can be realized. Read or Write
Commands can also be issued to the same bank or between active banks on every clock cycle.
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Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
7.5
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS
and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.
7.6
Burst Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding
RAS high at the rising edge of the clock. The address inputs determine the starting column address.
Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the
Write Command is issued. The remaining data inputs must be supplied on each subsequent rising
clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.
7.7
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS Latency from the
interrupting Read Command the is satisfied.
7.8
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
7.9
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
7.10 Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
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Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
7.11 Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the
clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS Latency in
a burst read cycle, interrupted by Burst Stop.
7.12 Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
n
BL = 2 (disturb address is A0)
Data 1
n+1
No address carry from A0 to A1
Data 2
n+2
BL = 4 (disturb addresses are A0 and A1)
Data 3
n+3
No address carry from A1 to A2
Data 4
n+4
Data 5
n+5
BL = 8 (disturb addresses are A0, A1 and A2)
Data 6
n+6
No address carry from A2 to A3
Data 7
n+7
7.13 Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
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BL = 4
BL = 8
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
7.14 Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is
entered. During Auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS Latency.
A Read or Write Command with Auto-precharge cannot be interrupted before the entire burst
operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is
prohibited during a read or write cycle with Auto-precharge. Once the precharge operation has started,
the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Autoprecharge command is illegal if the burst is set to full page length. If A10 is high when a Write
Command is issued, the Write with Auto-precharge function is initiated. The SDRAM automatically
enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred
to as write tWR. The bank undergoing Auto-precharge cannot be reactivated until tWR and tRP are
satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Autoprecharge Command, the interval between the Bank Activate Command and the beginning of the
internal precharge operation must satisfy tRAS (min).
7.15 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, BS0 and BS1 are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(tRP).
7.16 Self Refresh Command
The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high
at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. Any subsequent commands can be issued after
tXSR from the end of Self Refresh Command.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
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Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min.) + tCK (min.).
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS , CAS and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS , CAS and WE signals become don’t cares.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
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Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
TABLE 1 TRUTH TABLE (NOTE (1), (2))
COMMAND
Device State CKEn-1
CKEn
DQM
BS0, 1
A10
A0-A9
CS
RAS
CAS
WE
Bank Active
Idle
H
x
x
v
v
V
L
L
H
H
Bank Precharge
Any
H
x
x
v
L
x
L
L
H
L
Precharge All
Any
H
x
L
L
H
L
H
x
x
x
Write
Active
(3)
H
x
x
v
L
v
L
H
L
L
Write with Auto-precharge
Active
(3)
H
x
x
v
H
v
L
H
L
L
Active
(3)
H
x
x
v
L
v
L
H
L
H
Active
(3)
H
x
x
v
H
v
L
H
L
H
H
x
x
v
v
v
L
L
L
L
H
x
x
x
x
x
L
H
H
H
H
x
x
x
x
x
L
H
H
L
Read
Read with Auto-precharge
Mode Register Set
Idle
No-Operation
Any
Burst Stop
Active
(4)
Device Deselect
Any
H
x
x
x
x
x
H
x
x
x
Auto-Refresh
Idle
H
H
x
x
x
x
L
L
L
H
Self-Refresh Entry
Idle
H
L
x
x
x
x
L
L
L
H
Self Refresh Exit
Clock suspend Mode
Entry
Power Down Mode Entry
idle
L
H
x
x
x
x
H
x
x
x
(S.R)
L
H
x
x
x
x
L
H
H
x
Active
H
L
x
x
x
x
x
x
x
x
Idle
H
L
x
x
x
x
H
x
x
X
H
L
x
x
x
x
L
H
H
H
L
H
x
x
x
x
x
x
x
X
Active
(5)
Clock Suspend Mode Exit
Active
Power Down Mode Exit
L
H
x
x
x
x
H
x
x
X
(power
down)
L
H
x
x
x
x
L
H
H
H
Data write/Output Enable
Active
H
x
L
x
x
x
x
x
x
x
Data Write/Output Disable
Active
x
H
x
x
x
x
x
x
x
Any
H
Notes:
(1) v = valid, x = Don’t care, L = Low Level, H = High Level
(2) CKEn signal is input leve l when commands are provided.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
- 12 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
8.1
Simplified Stated Diagram
Self
Refresh
SE
LF
L
SE
Mode
Register
Set
F
MRS
ex
it
REF
CK
CK
E
E
ACT
Power
Down
CKE
e
Writ
ew
Au t
o pr ith
ech
arg
BS
r it
e
d
W
T
ea
CKE
R
WRITEA
SUSPEND
Read
WRITE
ith
dw
Rea arge
ech
o pr
CKE
Au t
Write
Active
Power
Down
CKE
BS
T
ROW
ACTIVE
WRITE
SUSPEND
CBR
Refresh
IDLE
Read
CKE
READ
CKE
Write
READ
SUSPEND
CKE
CKE
READA
CKE
READA
SUSPEND
ge
har
ge
har
te r m
rec
PRE
E(p
WRITEA
ina
PR
tion
)
CKE
tion
PR
ina
E(p
rec
te r m
)
POWER
ON
Precharge
Precharge
Automatic sequence
Manual input
MRS = Mode Register Set
REF = Refresh
ACT = Active
PRE = Precharge
WRITEA = Write with Auto-precharge
READA = Read with Auto-precharge
- 13 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
9. ELECTRICAL CHARACTERISTICS
9.1
Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
NOTES
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ VDD + 0.5 (≤ 4.6V max.)
V
1
Voltage on VDD/VDDQ supply relative to VSS
VDD, VDDQ
-0.5 ~ 4.6
V
1
Operating Temperature for -5/-6/-7
TA
0 ~ 70
°C
1, 2
Operating Temperature for -6I/-6A
TA
-40 ~ 85
°C
1, 2
Operating Temperature for -6K
TA
-40 ~ 105
°C
1, 2
Operating Temperature for -6K
TCASE
-40 ~ 105
°C
1, 3, 4, 5, 6
Storage Temperature
TSTG
-55 ~ 150
°C
1
TSOLDER
260
°C
1
PD
1
W
1
IOUT
50
mA
1
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
Notes:
1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of
the device
2. Operating ambient temperature is the surrounding temperature of the SDRAM.
3. Operating case temperature is the case surface temperature on the center/top side of the SDRAM
4. Supporting -40°C ≤ TA / TCASE ≤ 85°C with full AC and DC specifications.
5. Supporting -40°C ≤ TA / TCASE ≤ 85°C and being able to extend to 105°C with extend Auto Refresh commands in frequency
to a 16 mS period ( tREF = 3.9 µS).
6. During operation, the DRAM operation temperature must be maintained between -40 to 105°C for automotive parts under all
specification parameters.
9.2
Recommended DC Operating Conditions
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
VDD
3.0
3.3
3.6
V
VDDQ
3.0
3.3
3.6
V
VDD
2.7
3.3
3.6
V
VDDQ
2.7
3.3
3.6
V
Input High Voltage
VIH
2
-
VDD + 0.3
V
1
Input Low Voltage
VIL
-0.3
-
+0.8
V
2
Output logic high voltage
VOH
2.4
-
-
V
IOH= -2mA
Output logic low voltage
VOL
-
-
0.4
V
IOL= 2mA
Input leakage current
II(L)
-10
-
10
µA
3
Output leakage current
Io(L)
-10
-
10
µA
4
Power Supply Voltage for -5/-6/-6I/-6A/-6K
Power Supply Voltage (I/O Buffer)
for -5/-6/-6I/-6A/-6K
Power Supply Voltage for -7
Power Supply Voltage (I/O Buffer) for -7
NOTES
Note:
1. VIH (max.) = VDD/VDDQ+1.5V for pulse width ≤ 5 nS.
2. VIL (min.) = VSS/VSSQ-1.5V for pulse width ≤ 5 nS.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Output disabled, 0V ≤ VOUT ≤ VDDQ
- 14 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
9.3
Capacitance
(VDD = 3.3V ± 0.3V for -5/-6/-6I/-6A/-6K, VDD = 2.7V-3.6V for -7, TA = 25°C, f = 1 MHz)
PARAMETER
SYM.
MIN.
MAX.
UNIT
Ci
2.5
4
pf
CCLK
2.5
4
pf
Co
4
6.5
pf
Input Capacitance
(A0 to A10, BS0, BS1, CS , RAS , CAS , WE , DQM, CKE)
Input Capacitance (CLK)
Input/Output capacitance (DQ0DQ31)
Note: These parameters are periodically sampled and not 100% tested
9.4
DC Characteristics
(VDD = 3.3V ± 0.3V for-5/-6, VDD = 2.7V~3.6V for -7 on TA = 0 to 70°C)
(VDD = 3.3V ± 0.3V for-6I/-6A, TA = -40 to 85°C)
(VDD = 3.3V ± 0.3V for-6K, TA / TCASE = -40 to 105°C)
PARAMETER
Operating Current
tCK = min., tRC = min.
Active precharge command
cycling without burst operation
Standby Current
tCK = min., CS = VIH
VIH/L = VIH (min.)/VIL (max.)
Bank: Inactive State
SYM.
-5
MAX.
-6/-6I/-6A -6K
-7
UNIT
NOTES
1 Bank Operation
IDD1
90
80
80
75
3
CKE = VIH
IDD2
25
25
25
25
3
CKE = VIL
(Power Down mode)
IDD2P
2
2
5
2
3
CKE = VIH
IDD2S
15
15
15
15
CKE = VIL
(Power Down mode)
IDD2PS
2
2
5
2
CKE = VIH
IDD3
60
55
55
50
CKE = VIL
(Power Down mode)
IDD3P
10
10
12
10
IDD4
145
130
130
120
3, 4
IDD5
155
140
140
130
3
IDD6
2
2
5
2
Standby Current
CLK = VIL, CS = VIH
VIH/L=VIH (min.)/VIL (max.)
Bank: Inactive State
No Operating Current
tCK = min., CS = VIH (min.)
Bank: Active State (4 Banks)
Burst Operating Current
(tCK = min.)
Read/Write command cycling
Auto Refresh Current
(tCK = min.)
Auto refresh command cycling
Self Refresh Current
Self refresh mode
(CKE = 0.2V)
mA
- 15 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
9.5
AC Characteristics and Operating Condition
(VDD = 3.3V ± 0.3V for-5/-6, VDD = 2.7V~3.6V for -7 on TA = 0 to 70°C)
(VDD = 3.3V ± 0.3V for-6I/-6A, TA = -40 to 85°C)
(VDD = 3.3V ± 0.3V for-6K, TA / TCASE = -40 to 105°C)(Notes: 5, 6)
PARAMETER
SYM.
-5
MIN.
-6/-6I/-6A/-6K
MAX.
MIN.
MAX.
-7
MIN.
55
Active to Read/Write Command Delay Time
tRC
tRAS
tRCD
15
18
20
Read/Write(a) to Read/Write(b) Command
Period
tCCD
1
1
1
tRP
tRRD
15
18
20
10
12
14
2
2
2
2
2
2
Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
CL* = 2
Write Recovery Time
CL* = 3
CL* = 2
CL* = 3
CLK Cycle Time
CLK High Level width
CLK Low Level width
Access Time from CLK
tCK
tCH
tCL
CL* = 2
CL* = 3
Output Data Hold Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
-40°C ≤ TA / TCASE ≤ 85°C
10
5
Exit self refresh to ACTIVE command
tRSC
tXSR
7.5
6
65
100000
1000
1000
45
10
7
100000
nS
tCK
nS
tCK
1000
1000
2
8
2
2
2
8
6
4.5
3
5.5
5
3
6
4.5
0
0
0
9
3
0
5
6
5.5
6
5
1
9
6
5.5
7
0
6
0
1
9
7
nS
1
1.5
1.5
1.5
8
1.0
1.0
1.0
8
1.5
1.5
1.5
8
1.0
1.0
1.0
8
1.5
1.5
1.5
8
1.0
1.0
1.0
8
1.5
1.5
1.5
8
1.0
Refresh Time
(4K/Refresh Cycles) 85°C < TA / TCASE ≤ 105°C tREFA
Mode register Set Cycle Time
1000
1000
42
NOTES
2
tHZ
tLZ
tSB
tT
tDS
tDH
tAS
tAH
tCKS
tCKH
tCMS
tCMH
tREF
100000
UNIT
2
tAC
tOH
CL* = 2
CL* = 3
Output Data High
Impedance Time
tWR
40
60
MAX.
1.0
1.0
8
64
64
64
--
16
--
mS
2
2
2
tCK
70
72
75
nS
*CL = CAS Latency
* -- = not support
- 16 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
Notes:
1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.
2. All voltages are referenced to VSS.
• 2.7V~3.6V power supply for -7 speed grades.
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum
values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with output open.
5. Power up sequence please refer to “Functional Description” section described before.
6. AC test load diagram.
1.4 V
50 ohms
output
Z = 50 ohms
30pF
AC TEST LOAD
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output
level.
8. Assumed input rise and fall time (tT) = 1nS.
If tr & tf is longer than 1nS, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]nS should be added to the parameter.
9. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.
- 17 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
10. TIMING WAVEFORMS
10.1 Command Input Timing
tCK
tCL
tCH
VIH
CLK
VIL
tT
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tAS
tAH
tCMH
tT
tCMS
CS
RAS
CAS
WE
A0-A10
BS0,1
tCKS
tCKH
tCKS
tCKS
tCKH
tCKH
CKE
- 18 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
10.2 Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
A0-A10
BS0,1
tAC
tLZ
Valid
Data-Out
DQ
Read Command
tHZ
tAC
tOH
tOH
Valid
Data-Out
Burst Length
- 19 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
10.3 Control Timing of Input/Output Data
Control Timing of Input Data
(Word Mask)
CLK
tCMS
tCMH
tCMH
tCMS
DQM
tDS
tDH
tDS
tDS
Valid
Data-in
Valid
Data-in
DQ0~31
tDH
tDH
tDS
tDH
Valid
Data-in
Valid
Data-in
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tDH
tDS
tDH
tCKS
CKE
tDS
DQ0~31
Valid
Data-in
tDS
Valid
Data-in
tDH
tDS
tDH
Valid
Data-in
Valid
Data-in
Control Timing of Output Data
(Output Enable)
CLK
tCMS
tCMH
tCMH
tCMS
DQM
tAC
tOH
tAC
tLZ
Valid
Data-Out
Valid
Data-Out
DQ0~31
tAC
tHZ
tOH
tOH
tAC
tOH
Valid
Data-Out
OPEN
(Clock Mask)
CLK
tCKS
tCKH
tCKH
tCKS
CKE
DQ0~31
tAC
tAC
tAC
tAC
tOH
tOH
tOH
Valid
Data-Out
Valid
Data-Out
- 20 -
tOH
Valid
Data-Out
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
10.4 Mode Register Set Cycle
tRSC
CLK
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tAS
tAH
CS
RAS
CAS
WE
A0-A10
BS0,1
Register
set data
next
command
A0
A1
Burst Length
A2
A3
Addressing Mode
A4
A5
CAS Latency
A2
0
0
0
0
1
1
1
1
A6
A7
0
(Test Mode)
A8
0
Reserved
A9
Write Mode
A10
0
Reserved
BS0
0
BS1
0
Mode
Register Set
A1
A0 A0
A0
0
0
A0
0
1
A0
1
0
A0
1
1
A0
0
0
A0
0
1
A0
1
0
A0
1
1
A0
A3
0
1
A6
0
0
0
0
1
A5
A0 A4
A0
0
0
A0
0
1
1
0
A0
1
1
A0
0
0
A0
A9
0
1
* "Reserved" should stay "0" during MRS cycle.
- 21 -
Burst Length
Sequential
Interleave
1
1
2
2
4
4
8
8
Reserved
Reserved
Full Page
Addressing Mode
Sequential
Interleave
CAS Latency
Reserved
Reserved
2
3
Reserved
Single Write Mode
Burst read and Burst write
Burst read and single write
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11. OPERATING TIMING EXAMPLE
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
tRC
tRC
RAS
tRAS
tRP
tRP
tRAS
tRAS
tRP
tRAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9
RAa
tRCD
tRCD
RBb
CAw
tRCD
RAc
CBx
RBb
RAe
RBd
RAc
CAy
RBd
CBz
RAe
DQM
CKE
tAC
DQ
tRRD
Bank #0
Active
Bank #1
aw1
aw2
aw3
bx0
tRRD
Read
Precharge
Active
bx1
bx2
bx3
cy0
tRRD
Active
cy1
cy2
cy3
tRRD
Precharge
Read
Precharge
Read
tAC
tAC
tAC
aw0
Active
Active
Read
Bank #2
Idle
Bank #3
- 22 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)
0
1
2
3
4
5
6
7
8
9
11
10
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9
RAa
tRCD
tRCD
RBb
CAw
tRCD
RBd
RAc
RBb
CBx
RAc
RAe
RBd
CAy
CBz
RAe
DQM
CKE
tAC
DQ
tRRD
Active
Bank #0
aw1
aw2
aw3
bx0
bx1
tRRD
Read
bx2
bx3
cy0
cy1
tRRD
Read
AP*
cy2
cy3
dz0
tRRD
Read
Active
AP*
Active
tAC
tAC
tAC
aw0
AP*
Active
Active
Read
Bank #1
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 23 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9
RAa
tRCD
tRCD
RBb
CAx
RAc
RAc
CBy
RBb
CAz
DQM
CKE
tAC
DQ
tAC
ax0
ax1
tRRD
Bank #0 Active
ax3
ax4
ax5
ax6
tAC
by0
by4
by1
by5
by6
by7
CZ0
tRRD
Read
Precharge
Bank #1
ax2
Precharge
Active
Read
Active
Read
Precharge
Bank #2
Idle
Bank #3
- 24 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tRC
CS
RAS
tRAS
tRP
tRAS
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9
RAa
tRCD
tRCD
RAc
RBb
CAx
CBy
RBb
RAc
CAz
DQM
CKE
tAC
DQ
ax0
ax1
ax2
Active
ax4
ax5
AP*
Read
Active
Bank #1
ax3
ax6
ax7
by0
by1
by4
Active
Read
by5
by6
CZ0
tRRD
tRRD
Bank #0
tAC
tAC
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 25 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.5 Interleaved Bank Write (Burst Length = 8)
1
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
CAS
tRCD
tRCD
tRCD
WE
BS0
BS1
A10
RAa
A0-A9
RAa
RBb
CAx
RAc
CBy
RBb
RAc
CAz
DQM
CKE
DQ
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
tRRD
Active
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
Precharge
Write
Active
Bank #0
by2
Write
Active
Write
Precharge
Bank #1
Bank #2
Idle
Bank #3
- 26 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRP
tRAS
tRAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9
RAa
tRCD
tRCD
RBb
CAx
RAb
CBy
RBb
RAc
CAz
DQM
CKE
ax0
DQ
ax1
ax4
ax5
ax6
ax7
by0
by1
AP*
Write
Active
Bank #1
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
tRRD
Bank #0 Active
by2
Write
Active
Write
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 27 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tCCD
tCCD
tCCD
CS
tRAS
tRAS
RAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9
RAa
tRCD
RBb
CAI
RBb
CBx
CAy
CAm
CBz
DQM
CKE
DQ
a0
a1
a2
a3
tAC
tAC
tAC
tAC
bx0
tAC
Ay0
bx1
Ay1
Ay2
am0
am1
am2
bz0
bz1
bz2
bz3
tRRD
Bank #0 Active
Read
Active
Bank #1
Read
Read
Read
Precharge
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 28 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)
0
1
2
3
5
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRAS
RAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9
RAa
CAx
CAy
DQM
CKE
tAC
DQ
tWR
ax0
Q Q
Bank #0
Active
ax1
ax2
Q
Q
ax3
Q
ax5
ax4
Q
Read
ay1
ay0
D
D
Write
ay2
D
ay3
D
ay4
D
Precharge
Bank #1
Bank #2
Bank #3
Idle
- 29 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9
RAa
tRCD
RAb
CAw
RAb
CAx
DQM
CKE
tAC
DQ
tAC
aw0
Active
Read
aw1
AP*
aw2
aw3
bx0
Active
Read
bx1
bx2
bx3
AP*
Bank #0
Bank #1
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 30 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.10 Auto-precharge Write (Burst Length = 4)
CLK
0
1
2
3
6
5
4
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CS
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
tRCD
A10
RAa
A0-A9
RAa
RAb
CAw
RAb
RAc
CAx
RAc
DQM
CKE
aw0
DQ
Bank #0
Active
Write
aw1
aw2
aw3
bx0
AP*
Active
Write
bx1
bx2
bx3
AP*
Active
Bank #1
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 31 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.11 Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tRP
tRC
tRC
CS
RAS
CAS
WE
BS0,1
A10
A0-A9
DQM
CKE
DQ
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
- 32 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.12 Self Refresh Cycle
CLK
CS
tRP
RAS
CAS
WE
BS0,1
A10
A0-A9
DQM
tCKS
tSB
CKE
tCKS
DQ
tXSR
Self Refresh Cycle
All Banks
Precharge
Self Refresh
Entry
No Operation / Command Inhibit
Self Refresh
Exit
- 33 -
Arbitrary Cycle
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
t RCD
WE
BS0
BS1
A10
RBa
A0-A9
RBa
CBv
CBw
CBx
CBy
CBz
aw0
ax0
ay0
az0
az1
az2
az3
D
D
D
Q
Q
Q
Q
DQM
CKE
tAC
tAC
DQ
Bank #0
Active
Read
av0
av1
av2
av3
Q
Q
Q
Q
Single Write Read
Bank #1
Bank #2
Idle
Bank #3
- 34 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.14 Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BS
A10
RAa
A0-A9
RAa
RAa
CAa
RAa
CAx
DQM
tSB
tSB
CKE
tCKS
tCKS
ax0
Active
tCKS
tCKS
DQ
ax1
ax2
NOP Read
ax3
Precharge
NOP Active
Precharge Standby
Power Down mode
Active Standby
Power Down mode
Note: The Power Down Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Violating refresh requirements during power-down may result in a loss of data.
- 35 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.15 Auto-precharge Timing (Write Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
(1) CAS Latency = 2
(a) burst length = 1
Command
Write
AP
tWR
DQ
Act
tRP
D0
(b) burst length = 2
Command
Write
AP
Act
tWR
DQ
D0
tRP
D1
(c) burst length = 4
Command
AP
Write
DQ
D0
D1
D2
Act
tRP
tWR
D3
(d) burst length = 8
Command
Write
AP
tWR
DQ
D0
D1
D2
D3
D4
D5
D6
Act
tRP
D7
(2) CAS Latency = 3
(a) burst length = 1
Command
Write
AP
Act
tWR
DQ
(b) burst length = 2
Command
tRP
D0
Write
AP
Act
tWR
DQ
D0
tRP
D1
(c) burst length = 4
Command
Write
AP
Act
tWR
DQ
D0
D1
D2
tRP
D3
(d) burst length = 8
Command
Write
AP
tWR
DQ
D0
D1
D2
D3
D4
D5
D6
Act
tRP
D7
Note )
Write
represents the Write with Auto precharge command.
AP
represents the start of internal precharing.
Act
represents the Bank Active command.
When the /auto precharge command is asserted,the period from Bank Activate
command to the start of intermal precgarging must be at least tRAS (min).
- 36 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.16 Auto-precharge Timing (Read Cycle)
0
1
Read
AP
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) burst length = 1
Command
Act
tRP
DQ
Q0
( b ) burst length = 2
Command
Read
AP
Act
tRP
DQ
Q0
Q1
( c ) burst length = 4
Command
Read
AP
Act
tRP
DQ
Q0
Q1
Q2
Q3
( d ) burst length = 8
Command
Read
AP
Q0
DQ
Q1
Q2
Q3
Q4
Q5
Q6
Act
tRP
Q7
(2) CAS Latency=3
( a ) burst length = 1
Command
Read
AP
Act
tRP
Q0
DQ
( b ) burst length = 2
Command
Read
AP
Act
tRP
Q0
DQ
Q1
( c ) burst length = 4
Command
Read
AP
Act
tRP
Q0
DQ
Q1
Q2
Q3
( d ) burst length = 8
Command
Read
AP
Act
tRP
Q0
DQ
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Note:
Read
AP
Act
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least tRAS (min).
- 37 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.17 Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
1
0
2
3
4
5
6
D1
D2
D3
D0
D1
D2
D1
D2
D3
D1
D2
7
8
9
10
11
(1) CAS Latency=2
Read
( a ) Command
Write
DQM
DQ
D0
( b ) Command
Read
Write
DQM
DQ
(2) CAS Latency=3
Read
( a ) Command
D3
Write
DQM
D0
DQ
Read
( b ) Command
Write
DQM
D0
DQ
D3
Note: The Output data must be masked by DQM to avoid I/O conflict.
11.18 Timing Chart of Write to Read Cycle
In the case of Burst Length=4
0
1
2
3
4
5
6
7
8
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
9
10
11
(1) CAS Latency=2
( a ) Command
Write Read
DQM
DQ
( b ) Command
D0
Read
Write
DQM
DQ
D0
D1
(2) CAS Latency=3
( a ) Command
Write Read
DQM
DQ
( b ) Command
D0
Write
Read
DQM
DQ
D0
D1
- 38 -
Q3
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a ) CAS latency =2
C omma nd
Read
BST
Q0
DQ
Q1
Q2
Q0
Q1
Q3
Q4
( b )CAS latency = 3
C omma nd
Read
BST
DQ
Q2
Q3
Q4
(2) Write cycle
C omma nd
DQ
Write
Q0
BST
Q1
Q2
Note:
Q3
Q4
BST
represents the Burst stop command
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
(a) CAS latency =2
Command
Read
PRCG
DQ
(b) CAS latency =3
Command
Q0
Q1
Q2
Read
Q3
Q4
PRCG
DQ
Q0
Q1
Q2
Q3
Q4
(2) Write cycle
Command
PRCG
Write
tWR
DQM
DQ
Q0
Q1
Q2
Q3
Q4
- 39 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.21 CKE/DQM Input Timing (Write Cycle)
CLK cycle No.
1
2
3
D1
D2
D3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
D5
DQM MASK
D6
CKE MASK
( 1)
CLK cycle No.
1
2
3
D1
D2
D3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
DQM MASK
D5
D6
5
6
7
D4
D5
D6
CKE MASK
( 2)
CLK cycle No.
1
2
3
D1
D2
D3
4
External
CLK
Internal
CKE
DQM
DQ
CKE MASK
( 3)
- 40 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
11.22 CKE/DQM Input Timing (Read Cycle)
CLK cycle No.
1
2
3
4
Q1
Q2
Q3
Q4
6
5
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Open
Open
(1)
CLK cycle No.
1
2
3
Q1
Q2
Q3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Q4
Open
(2)
CLK cycle No.
1
2
Q1
Q2
3
4
5
6
7
Q4
Q5
Q6
External
CLK
Internal
CKE
DQM
DQ
Q3
(3)
- 41 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
12. PACKAGE SPECIFICATION
86L TSOP (II)-400 mil
86
44
HE
E
1
43
e
b
C
D
q
A2
A
L
L1
A1
ZD
Y
SEATING PLANE
Controlling Dimension: Millimeters
DIMENSION
(MM)
DIMENSION
(INCH)
SYM.
MIN.
NOM.
A
A1
A2
b
0.05
MAX.
MIN.
1.20
0.15
0.002
0.27
0.21
0.007
0.005
1.00
NOM.
MAX.
0.047
0.006
0.039
c
0.17
0.12
D
22.12
22.22
22.62
0.871
0.875
0.905
E
10.06
10.16
10.26
0.396
0.400
0.404
HE
11.56
11.76
11.96
0.455
0.463
0.471
e
L
L1
0.50
0.40
0.50
0.008
0.020
0.60
0.016
0.80
0.020
0.024
0.032
0.004
0.10
Y
ZD
0.011
0.024
0.61
- 42 -
Publication Release Date: Oct. 07, 2013
Revision A02
W9864G2JH
13. REVISION HISTORY
VERSION
DATE
PAGE
A01
Dec. 01, 2011
All
A02
Oct. 07, 2013
DESCRIPTION
Initial formal datasheet
3, 14~16 Added -6K automotive grade parts
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
- 43 -
Publication Release Date: Oct. 07, 2013
Revision A02
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