W987D2HBGX7I

W987D6HB / W987D2HB 128Mb Mobile LPSDR TABLE OF CONTENTS 1. GENERAL DESCRIPTION ............................................................................................................. 4 2. FEATURES ..................................................................................................................................... 4 3. PIN CONFIGURATION ................................................................................................................... 5 3.1 Ball Assignment: LPSDR X 16 ............................................................................................................ 5 3.2 Ball Assignment: LPSDR X 32 ............................................................................................................ 5 4. PIN DESCRIPTION......................................................................................................................... 6 4.1 Signal Description ............................................................................................................................... 6 4.2 Addressing Table ................................................................................................................................ 6 5. BLOCK DIAGRAM ......................................................................................................................... 7 6. ELECTRICAL CHARACTERISTICS .............................................................................................. 8 6.1 Absolute Maximum Ratings................................................................................................................. 8 6.2 Operating Conditions .......................................................................................................................... 8 6.3 Capacitance ........................................................................................................................................ 8 6.4 DC Characteristics .............................................................................................................................. 9 6.5 Automatic Temperature Compensated Self Refresh Current Feature................................................ 11 6.6 AC Characteristics And AC Operating Conditions ............................................................................. 12 6.6.1 AC Characteristics....................................................................................................................................... 12 6.6.2 AC Test Condition ....................................................................................................................................... 13 6.6.3 AC Latency Characteristics ......................................................................................................................... 14 7. FUNCTION DESCRIPTION .......................................................................................................... 15 7.1 Command Function ........................................................................................................................... 15 7.1.1Table 1. Truth Table ..................................................................................................................................... 15 7.1.2 Functional Truth Table ................................................................................................................................ 16 7.1.3 Function Truth Table for CKE ..................................................................................................................... 19 7.1.4 Bank Activate Command ............................................................................................................................. 20 7.1.5 Bank Precharge Command ......................................................................................................................... 20 7.1.6 Precharge All Command ............................................................................................................................. 20 7.1.7 Write Command .......................................................................................................................................... 20 7.1.8 Write with Auto Precharge Command ......................................................................................................... 20 7.1.9 Read Command .......................................................................................................................................... 20 7.1.10 Read with Auto Precharge Command ...................................................................................................... 20 7.1.11 Extended Mode Register Set Command .................................................................................................. 20 7.1.12 Mode Register Set Command ................................................................................................................... 21 7.1.13 No-Operation Command ........................................................................................................................... 21 7.1.14 Burst Stop Command ................................................................................................................................ 21 7.1.15 Device Deselect Command ....................................................................................................................... 21 7.1.16 Auto Refresh Command ............................................................................................................................ 21 7.1.17 Self Refresh Entry Command ................................................................................................................... 21 7.1.18 Self Refresh Exit Command ...................................................................................................................... 21 7.1.19 Clock Suspend Mode Entry/Power Down Mode Entry Command ............................................................ 21 7.1.20 Clock Suspend Mode Exit/Power Down Mode Exit Command ................................................................. 21 -1- Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 7.1.21 Data Write/Output Enable, Data Mask/Output Disable Command ........................................................... 22 8. OPERATION ................................................................................................................................. 22 8.1 Read Operation ................................................................................................................................. 22 8.2 Write Operation ................................................................................................................................. 22 8.3 Precharge ......................................................................................................................................... 23 8.3.1 Auto Precharge ........................................................................................................................................... 23 8.3.2 READ with auto precharge interrupted by a READ (with or without auto precharge) ................................ 23 8.3.3 READ with auto precharge interrupted by a WRITE (with or without auto precharge) ............................... 24 8.3.4 WRITE with auto precharge interrupted by a READ (with or without auto precharge) ............................... 25 8.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) ............................. 26 8.4 Burst Termination .............................................................................................................................. 27 8.5 Mode Register Operation .................................................................................................................. 28 8.5.1 Burst Length field (A2~A0) .......................................................................................................................... 28 8.5.2 Addressing Mode Select (A3) ..................................................................................................................... 28 8.5.3 Addressing Sequence for Sequential Mode ................................................................................................ 29 8.5.4 Addressing Sequence for Interleave Mode ................................................................................................. 29 8.5.5 Addressing Sequence Example (Burst Length = 8 and Input Addres s is 13) ............................................. 30 8.5.6 Read Cycle CAS Latency = 3................................................................................................................... 30 8.5.7 CAS Latency field (A6~A4) ...................................................................................................................... 31 8.5.8 Mode Register Definition ............................................................................................................................. 31 8.6 Extended Mode Register Description ................................................................................................ 32 8.7 Simplified State Diagram ................................................................................................................... 33 9. CONTROL TIMING WAVEFORMS .............................................................................................. 34 9.1 Command Input Timing ..................................................................................................................... 34 9.2 Read Timing...................................................................................................................................... 35 9.3 Control Timing of Input Data (x16) .................................................................................................... 36 9.4 Control Timing of Output Data (x16) .................................................................................................. 37 9.5 Control Timing of Input Data (x32) .................................................................................................... 38 9.6 Control Timing of Output Data (x32) .................................................................................................. 39 9.7 Mode register Set (MRS) Cycle ......................................................................................................... 40 10. OPERATING TIMING EXAMPLE ............................................................................................... 42 10.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)........................................................ 42 10.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge) ............................. 43 10.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ........................................................ 44 10.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge) ............................. 45 10.5 Interleaved Bank Write (Burst Length = 8) ....................................................................................... 46 10.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge) ............................................................ 47 10.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ................................................................ 48 10.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ..................................................... 49 10.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) .......................................................... 50 10.10 Auto Precharge Write (Burst Length = 4) ....................................................................................... 51 -2- Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.11 Auto Refresh Cycle ....................................................................................................................... 52 10.12 Self Refresh Cycle ........................................................................................................................ 53 10.13 Power Down Mode ........................................................................................................................ 54 10.14 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ............................................. 55 10.15 Deep Power Down Mode Entry ..................................................................................................... 56 10.16 Deep Power Down Mode Exit ........................................................................................................ 57 10.17 Auto Precharge Timing (Read Cycle) ............................................................................................ 58 10.18 Auto Precharge Timing (Write Cycle) ............................................................................................ 59 10.19 Timing Chart of Read to Write Cycle ............................................................................................. 60 10.20 Timing Chart for Write to Read Cycle ............................................................................................ 60 10.21 Timing Chart for Burst Stop Cycle (Burst Stop Command) ............................................................ 61 10.22 Timing Chart for Burst Stop Cycle (Precharge Command) ............................................................ 61 10.23 CKE/DQM Input Timing (Write Cycle) ........................................................................................... 62 10.24 CKE/DQM Input Timing (Read Cycle) ........................................................................................... 63 11. PACKAGE DIMENSION ............................................................................................................. 64 11.1 : LPSDR X 16.................................................................................................................................. 64 11.2 : LPSDR X 32.................................................................................................................................. 65 12.ORDERING INFORMATION ....................................................................................................... 66 13. REVISION HISTORY .................................................................................................................. 67 -3- Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 1. GENERAL DESCRIPTION The W inbond 128Mb Low Power SDRAM is a low power synchronous memory containing 134,217,728 memory cells fabricated with Winbond high performance process technology. It is designed to consum e less power than the ordinary SDRAM with low power features essential for ap plications which use batteries. It is available in two organizations: 1,048,576 words × 4 banks × 32 bits or 2,097,152 words × 4 banks × 16 bits. The device operates in a fully synchronous mode, and the output data are synchronized to positive edges of the system clock and is capable of delivering data at clock rate up to 166MHz. The device supports special low power functions such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh (ATCSR). The Low Power SDRAM is suitable for 2.5G / 3G cellular phone, PDA, digital still camera, mobile game consoles and other handheld applications where large memory density and low power consumption are required. The device operates from 1.8V power supply, and supports the 1.8V LVCMOS bus interface. 2. FEATURES Power supply VDD = 1.7V~1.95V VDDQ = 1.7V~1.95V Frequency : 166MHz (-6) ,133MHz(-75) Programmable Partial Array Self Refresh Power Down Mode Deep Power Down Mode (DPD) Programmable output buffer driver strength Automatic Temperature Compensated Self Refresh CAS Latency: 2 and 3 Burst Length: 1, 2, 4, 8, and full page Refresh: 4K refresh cycle / 64ms Interface: LVCMOS Support package : 54 balls VFBGA (x16) 90 balls VFBGA (x32) Operating Temperature Range Extended (-25°C ~ +85°C) Industrial (-40°C ~ +85°C) -4- Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 3. PIN CONFIGURATION 3.1 Ball Assignment: LPSDR X 16 54Ball FBGA 1 A B C D E F G H J VSS DQ14 DQ12 DQ10 DQ8 UDQM NC A8 VSS 2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5 3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 (Top View) 456 7 VDDQ VSSQ VDDQ VSSQ VDD 8 DQ0 DQ2 DQ4 DQ6 LDQM 9 VDD DQ1 DQ3 DQ5 DQ7 CAS BA0 A0 A3 RAS BA1 A1 A2 WE CS A10 VDD 3.2 Ball Assignment: LPSDR X 32 90Ball FBGA 1 A B C D E F G H J K L M N P R DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 2 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 3 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS (Top View) 456 7 VDD VDDQ DQ22 DQ17 NC A2 A10 NC BA0 8 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 9 DQ21 DQ19 VDDQ VDDQ VSSQ VDD A1 A11 CS RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2 CAS VDD DQ6 DQ1 VDDQ VDD WE DQ7 DQ5 DQ3 VSSQ DQ0 -5- Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 4. PIN DESCRIPTION 4.1 Signal Description BALL NAME A [n : 0] BA0, BA1 DQ0~DQ15 (×16) DQ0~DQ31 (×32) FUNCTION Address Bank Select Data Input/ Output Chip Select Row Address Strobe Column Address Strobe W rite Enable I/O Mask Clock Inputs Clock Enable Power Ground Power for I/O Buffer Ground for I/O Buffer No Connection DESCRIPTION Multiplexed pins for row and column address. A10 is Auto Precharge Select Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock, RAS , CAS and WE define the operation to be executed. Referred to RAS Referred to WE The output buffer is placed at Hi-Z (with latency of 2 in CL=2, 3;) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode or Self Refresh mode is entered. Power supply for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Power supply separated from VDD, used for output buffers to improve noise. Separated ground from VSS, used for output buffers to improve noise. No connection CS RAS CAS WE UDQM / LDQM(x16) DQM0 ~ DQM3 (x32) CLK CKE VDD VSS VDDQ VSSQ NC 4.2 Addressing Table ITEM Number of banks Bank address pins Auto precharge pin X16 Row addresses Column addresses Refresh count Row addresses Column addresses Refresh count 128 Mb 4 BA0,BA1 A10/AP A0-A11 A0-A8 4K A0-A11 A0-A7 4K x32 -6- Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 5. BLOCK DIAGRAM CLK CKE CLOCK BUFFER CS RAS CAS WE COMMAND DECODER CONTROL SIGNAL GENERATOR COLUMN DECODER R O W D E C O R D E R R O W COLUMN DECODER A10 A0 An BA0 BA1 ADDRESS BUFFER MODE REGISTER CELL ARRAY BANK #0 D E C O R D E R CELL ARRAY BANK #1 SENSE AMPLIFIER SENSE AMPLIFIER DMn DATA CONTROL CIRCUIT REFRESH COUNTER COLUMN COUNTER DQ BUFFER DQ0 – DQn DQM COLUMN DECODER R O W D E C O R D E R R O W COLUMN DECODER CELL ARRAY BANK #2 D E C O R D E R CELL ARRAY BANK #3 SENSE AMPLIFIER SENSE AMPLIFIER -7- Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 6. ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings PARAMETER Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Voltage on any pin relative to VSS Operating Temperature Storage Temperature Short Circuit Output Current Power Dissipation SYMBOL VDD VDDQ VIN, VOUT Tc TSTG IOUT PD VALUES MIN −0.3 −0.3 −0.3 -25 -40 −55 M AX 2.7 2.7 2.7 85 85 150 ± 50 1.0 UNITS V V V °C °C mA W 6.2 Operating Conditions (Notes : 1) PARAMETER Supply Voltage Supply Voltage (for I/O Buffer) Input High level Voltage Input Low level Voltage LVCOMS Output H Level Voltage (IOUT = -0.1 mA ) LVCMOS Output L Level Voltage (IOUT = +0.1 mA ) Input Leakage Current (0V VIN VDD, all other pins not under test = 0V) Output Leakage Current (Output disable , 0V VDDQ) VOUT SYMBOL VDD VDDQ VIH VIL VOH VOL II(L) IO(L) MIN. 1.7 1.7 0.8*VDDQ TYP . 1.8 1.8 - M A X. 1.95 1.95 VDDQ + 0.3 UNIT V V V V V V A A -0.3 0.9*VDDQ - +0.3 0.2 1 5 -1 -5 Note: VIH(max) = VDD/ VDDQ+1.2V for pulse width < 5 ns , VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 ns 6.3 Capacitance (VDD = 1.7V~1.9V, f = 1 MHz, TA = 25°C) PARAMETER Input Capacitance : All other input-only Input Capacitance (CLK) Input/Output capacitance Note: These parameters are periodically sampled and not 100% tested. SYMBOL CI CCLK CIO MIN. 1.5 1.5 3.0 M AX. 3.0 3.5 5.0 UNIT pf pf pf -8- Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 6.4 DC Characteristics (X16) PARAMETER / CONDITION Operating current: Active mode, 1 bank, BL = 1, tRC = tRC (min), Iout=0mA, Active Precharge command cycling without burst operation. Standby current: Power-down mode, All banks idle, CKE = LOW . Standby current: Nonpower-down mode, All banks idle, CKE = HIGH. Standby current: Active mode; CKE = LOW , CS# = HIGH, All banks active, No accesses in progress. Standby current: Active mode, CKE = HIGH, CS# = HIGH, All banks active after tRCD met, No accesses in progress. Operating current: Burst mode, All banks active, Iout=0mA, READ/WRITE command cycling, Auto refresh current: tRFC=tRFC (MIN), Auto refresh command cycling Deep Power Down Mode SYM. IDD1 Low power Normal power -6 M AX. 38 0.23 0.28 10 3 -75 M AX. 35 0.23 UNIT mA NOTES 2, 3, 4 Idd2P mA 0.28 10 3 mA mA 5 Idd2N Idd3P 3, 4, 6 Idd3N 20 15 mA 3, 4, 6 Idd4 Idd5 Izz 75 50 10 70 50 10 mA mA μA 2, 3, 4 2, 3, 4, 6 5,8 -9- Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR (X32) PARAMETER / CONDITION Operating current: Active mode, 1 bank, BL = 1, tRC = tRC (min), Iout=0mA, Active Precharge command cycling without burst operation. Standby current: Power-down mode, All banks idle, CKE = LOW . Standby current: Nonpower-down mode, All banks idle, CKE = HIGH. Standby current: Active mode; CKE = LOW , CS# = HIGH, All banks active, No accesses in progress. Standby current: Active mode, CKE = HIGH, CS# = HIGH, All banks active after tRCD met, No accesses in progress. Operating current: Burst mode, All banks active, Iout=0mA, READ/WRITE command cycling, Operating current: Active mode, 1 bank, BL = 1, tRC = tRC (min), Iout=0mA, Active Precharge command cycling without burst operation. Standby current: Power-down mode, All banks idle, CKE = LOW . SYM. IDD1 Low power -6 M AX. 38 0.23 0.28 10 3 -75 M AX. 35 0.23 UNIT mA NOTES 2, 3, 4 Idd2P Normal power mA 0.28 10 3 mA mA 5 Idd2N Idd3P 3, 4, 6 Idd3N 20 15 mA 3, 4, 6 Idd4 75 70 mA 2, 3, 4 Idd5 Izz 50 10 50 10 mA μA 2, 3, 4, 6 5,8 Notes: 1. A full initialization sequence is required before proper device operation is ensured. 2. Idd is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 3. The Idd current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 4. Address transitions average one transition every 2 clocks. 5. Measurement is taken 500ms after entering into this operating mode to provide tester measuring unit settling time. 6. Other input signals can transition only one time for every 2 clocks and are otherwise at valid Vih or Vil levels. 7. CKE is HIGH during the REFRESH command period tRFC (MIN) else CKE is LOW. The Idd7 limit is a nominal value and does not result in a fail value. 8. Typical values at 25°C (not a maximum value). - 10 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 6.5 Automatic Temperature Compensated Self Refresh Current Feature IDD6 TCSR Range Full Array 1/2 Array 1/4 Array 45℃ 180 160 150 Low Power 85℃ 230 200 180 Normal Power 45℃ 220 190 170 85℃ 280 250 230 uA Units Note: 1. A full initialization sequence is required before proper device operation is ensured. 2. Measurement is taken 500ms after entering into this operating mode to provide tester measuring unit settling time. 3. Enables on-die refresh and address counters. 4. Values for Idd6 85°C full array and partial array are guaranteed for the entire temperature range. 5. IDD6 is typical value. - 11 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 6.6 AC Characteristics And AC Operating Conditions 6.6.1 AC Characteristics *CL= CAS Latency; (Notes: 5,6,7) PARAMETER Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b)Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Write-Recovery Time (Last data to Read) CLK Cycle Time CLK High Level width CLK Low Level width Access Time from CLK Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK (Rise and Fall) Data-in Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time CL * = 3 CL * = 2 CL * = 3 CL * = 2 CL * = 3 CL * = 2 SYM -6 MIN. 60 42 18 100000 -75 M AX. MIN. 72.5 50 18 M AX. 100000 - UNIT ns ns ns NOTE 8 8 8 tRC tRAS tRCD tCCD tRP tRRD tWR tLDR tCK tCH tCL tAC tOH tHZ 1 1 - CLK 8 18 12 15 1 6 12 2 2 5.4 6 2.5 5.4 6 1000 1000 18 15 15 1 7.5 12 2.5 2.5 2.5 1 6 1 0 0.3 1 .5 1 1.5 1 1.5 1 1.5 - ns ns ns CLK 8 8 1000 1000 5.4 8 5.4 6 7.5 1.2 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 7 tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS 1 0 0.3 1.5 1 1.5 1 1.5 1 1.5 - 12 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR PARAMETER Command Hold Time Refresh Time Mode register Set Cycle Time Ref to Ref/Active Command period Self Refresh exit to next valid command delay SYM -6 MIN. 1 64 12 72 15 72 -75 M AX. MIN. 1 M AX. 64 - UNIT ns ms ns ns NOTE tCMH tREF tRSC tRFC tXSR 8 115 115 - ns 6.6.2 AC Test Condition SYMBOL VIH(min) VIL(max) VREF VOTR SLEW PARAMETER Input High Voltage Level (AC) Input Low Voltage Level (AC) Input Signal Reference Level Output Signal Reference Level Input Signal Slew Rate VALUE 0.8 x VDDQ 0.2 x VDDQ 0.5 x VDDQ 0.5 x VDDQ 1 UNIT V V V V V/ns VDDQ VIH(min) VREF VIL(max) VSS tT tT output Z = 50 Ω CLOAD = 30pF AC TEST LOAD RT=50Ω VTT=0.9V VOTR SLEW = ( VIH(min)- VIL(max) / tT Transition times are measured between VIH and VIL. - 13 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR Note : 1. Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect deice reliability. 2. All voltages are referenced to VSS and VSSQ. 3. These parameters depend on the cycle rate. These values are measure d at a cycle rate with the minimum values of tCK and tRC . Input signals transition once per tCK period. 4. These parameters depend on the output loading. Specified values are obtained with the output open. 5. Power-up sequence is described in Note 9. 6. AC TEST CONDITIONS : (refer to 6.6.2) 7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. 8. These parameters account for the number of clock cycles and depend on the operating frequency of the cl ock, as follows: The number of clock cycles = specified value of timing / clock period (count fractions as a whole number) 9. Power up Sequence : The SDRAM should be powered up by the following sequence of operations. a. Power must be applied to VDD before or a t the seme time as VDDQ while all input signals are held in the “NOP” state. The CLK signal will be applied at power up with power. b. After power-up a pause of at least 200 uA is required. It is required that DQM and CKE signals must be held “High” (VDD levels ) to ensure that the DQ output is in High-impedance state. c. All banks must be precharged. d. The Mode Register Set command must be issued to initialize the Mode Register. e. The Extended Mode Register Set command must be issued to initialize the Extended Mode Register. f. Issue two or more Auto Refresh dummy cycles to stabilize the internal circuitry of the device. The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles. 6.6.3 AC Latency Characteristics CKE to clock disable (CKE Latency) DQM to output in High-Z (Read DQM Latency) DQM to input data delay (Write DQM Latency) W rite command to input data (Write Data Latency) 1 2 0 0 0 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 2 3 1 2 2 3 1 2 BL+ tRP BL+ tRP BL+1 + tRP BL+1 + tRP Cycle + ns Cycle CS to Command input ( CS Latency) Precharge to DQ Hi-Z Lead time Precharge to Last Valid data out Burst Stop Command to DQ Hi-Z Lead time Burst Stop Command to Last Valid data out Read with Auto Precharge Command to Active/Ref Command W rite with Auto Precharge Command to Active/Ref Command - 14 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 7. FUNCTION DESCRIPTION 7.1 Command Function 7.1.1Table 1. Truth Table (Note (1) and (2) ) BS0, Symbol Command Device State CKEn-1 CKEn DQM(5) BS1 A10 An~A0 CS RAS CAS WE ACT PRE PREA W RIT W RITA READ READA MRS EMRS NOP BST DSL AREF SELF SELEX Bank Activate Bank Precharge Precharge All W rite W rite with Auto Precharge Read Read with Auto Precharge Mode Register Set Extended Mode Register Set No-Operation Burst stop Device Deselect Auto-Refresh Self-Refresh Entry Self-Refresh Exit Clock Suspend Mode Entry Power Down Mode Entry Clock Suspend Mode Exit Power Down Mode Exit Data Write/Output Enable Data Write/Output Disable Deep Power Down Mode Entry Deep Power Down Mode Exit Idle (3) Any Any Active (3) Active (3) Active (3) Active (3) Idle Idle Any Active (4) Any Idle Idle Idle (Self Refresh) Active H H H H H H H H H H H H H H L X X X X X X X X X X X X H L H X X X X X X X X X X X X X X X V V X V V V V V V X X X X X X V L H L H L H V V X X X X X X V X X V V V V V V X X X X X X L L L L L L L L L L L H L L H L L L L H H H H L L H H X L L X H X X H X X H X X H X H H H L L L L L L H H X L L X H X X H X X H X X H X H L L L L H H L L H L X H H X H X X H X X X X X L X CSE H L X X X X X H PD CSEX PDEX DE DD DPD DPDE Idle/Active (6) Active Any (Power Down) Active Active Idle Idle (DPD) H L L H H H L L H H X X L H X X X L H X X X X X X X X X X X X X X X X X L X X L X X X X X X L X X H Note 1. V = Valid, × = Don’t Care, L = Low level, H = High level 2. CKEn signal is input level when commands are issued. CKEn-1 signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BS0, BS1 signals. 4. Device state is Full Page Burst operation. 5. x32: DQM0-3, x16 : LDQM / UDQM 6. Power Down Mode cannot entry in the burst cycle. When this command assert in the burst cycle, device state is clock suspend mode. - 15 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 7.1.2 Functional Truth Table (See Note 1 at the end of this Table) Current State CS RAS CAS WE Address X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code Command DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS Nop Nop Action Nop Nop ILLEGAL ILLEGAL Row activating Nop Refresh or Self refresh Mode register accessing Notes H L L Idle L L L L L H L L Row active L L L L L H L L L Read L L L L L H L L L Write L L L L L X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L 3 3 2 2 Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop Term burst, new read: Determine AP Term burst, begin write: Determine AP ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Continue burst to end. Continue burst to end Burst stop, row active Term burst, start read: Determine AP Term burst, new write: Determine AP ILLEGAL Term burst. precharging ILLEGAL ILLEGAL 4 4 3 5 6 6,7 3 6, 7 6 3 8 - 16 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR Current State CS RAS CAS WE Address X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code Command DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS Action Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Idle after tRP Nop → Idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Idle after tRP ILLEGAL ILLEGAL Nop → Row active after tRCD Nop → Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes H L L Read with auto precharge L L L L L L H L L Write with auto precharge L L L L L L H L L L Precharging L L L L L H L L L Row activating L L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 - 17 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR Current State CS RAS CAS WE Address X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X X X X X X X X X Command DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/WRIT ACT/PRE/PREA AREF/SELF/MRS/ EMRS DSL NOP BST READ/WRIT ACT/PRE/PREA/ AREF/SELF/MRS/ EMRS Action Nop → Maintain Row active after tWR Nop → Maintain Row active after tWR Nop → Maintain Row active after tWR Begin Read Begin new Write ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter precharge after tWR Nop → Enter precharge after tWR Nop → Enter precharge after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Idle after tRFC Nop → Idle after tRFC Nop → Idle after tRFC ILLEGAL ILLEGAL ILLEGAL Nop → Idle after tRSC Nop → Idle after tRSC ILLEGAL ILLEGAL ILLEGAL Notes H L L L Write recovering L L L L L H L L Write recovering with auto precharge L L L L L L H L L Refreshing L L L H L Mode register accessing L L L X H H H H L L L L X H H H H L L L L X H H H L L X H H H L X H H L L H H L L X H H L L H H L L X H H L H L X H H L X X H L H L H L H L X H L H L H L H L X H L X X X X H L X X 7 3 3 3 3 3 3 Note: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle (CKEn-1 = CKEn = ”1”) 2. Illegal if any bank is not idle. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the state of that bank. 4. Illegal if tRCD is not satisfied. 5. Illegal if tRAS is not satisfied. 6. Must satisfy burst interrupt condition. 7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. Must mask preceding data which don’t satisfy tWR. Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data - 18 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 7.1.3 Function Truth Table for CKE Current State CKE n-1 H L Self refresh L L L L H Power-Down L L H Deep Power-Down L L H H H All banks idle H H H H L H H H Row Active H H H L Any state other than listed above H n X H H H H L X H L X H L H L L L L L L X H L L L L L X H CS RAS CAS WE Address X X X X X X X X X X X X X X X X X X X X X X X X X X X X X N/A Action Notes X H L L L X X H L X X X X X H L L L L L X X H L L L L X X X X H H L X X X H X X X X X X H H L H L X X X H L H L X X X X H L X X X X H X X X X X X H H L L X X X X H L L X X X X X H X X X X X H X X X X X X H L H X X X X X H H X X X X Exit Self Refresh → Idle after tRFC Exit Self Refresh → Idle after tRFC ILLEGAL ILLEGAL Maintain Self Refresh N/A Exit Power Down → Idle after 1 clock cycle Maintain Power-Down N/A Exit Deep Power-Down → Exit Sequence Maintain Deep Power-Down Refer to Function Truth Table Enter Power-down Enter Power-Down Enter Deep Power-Down Self Refresh ILLEGAL ILLEGAL Power-Down Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power-Down → Row Active or Maintain PD Refer to Function Truth Table 2 2 2 2 2 3 1 Note: 1. Self refresh can enter only from the all banks idle state. 2. Power-down can enter only from the all banks idle or row active state. 3. Deep power-down can enter only from the all banks idle state. Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data - 19 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 7.1.4 Bank Activate Command ( RAS = L, CAS = H, WE = H, BA0, BA1 = Bank, A0~An = Row Address) The Bank Activate command activates the bank designated by the BS (Bank Select) signal. Row addresses are latched on A0~An when this command is issued and the cell data is read out to the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). 7.1.5 Bank Precharge Command ( RAS = L, RAS = H, WE = L, BA0, BA1 = Bank, A10 =L ) The Bank Precharge command is used to close (or precharge) the bank that is activated. Using this command, systems can designated the bank to be closed by specifying the BS address bit setting in the command set. A Precharge command can be used to precharge each bank separately (Bank Precharge) or all four banks simultaneously (Precharge All). After the Bank Precharge command is issued, any one bank can close, and the closed bank transitions from the active state to the idle state. To re-activate the closed bank, a system has to wait the minimum tRP delay after issuing the Precharge command before issuing the Active Command for the device to complete the Precharge operation. 7.1.6 Precharge All Command ( RAS = L, CAS = H, WE = L, BA0, BA1 = Don’t care, A10 =H ) The Precharge All command is used to precharge all banks simultaneously. After this command is issued, all four banks close a nd transition from the active state to the idle state. 7.1.7 Write Command ( RAS = H, CAS = L, WE = L, BA0, BA1 = Bank, A10 = L ) The Write command initiates a Write operation to the bank selected by B A0 and BA1 address inputs. The write data is latched at the positive edge of CLK. Users should preprogram the length of the write data (Burst Length) and the column access sequence (Addressing Mode) by setting the Mode Resister at power -up prior to using the Write command. 7.1.8 Write with Auto Precharge Command ( RAS = H, CAS = L, WE = L, BA0, BA1 = Bank, A10 = H ) The Write with Auto Precharge command performs the Precharge operation automatically after the Write operation. The internal precharge starts in the cycles immediately following the cycle in which the last data is written independent of CAS Latency. 7.1.9 Read Command ( RAS = H, CAS = L, WE = H, BA0, BA1 = Bank, A10 = L ) The Read command performs a Read operation to the bank designated by B A0-1. The read data is issued sequentially synchronized to the positive edges of CLK. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Write operation. 7.1.10 Read with Auto Precharge Command ( RAS = H, CAS = L, WE = H, BA0, BA1 = Bank, A10 =H ) The Read with Auto Precharge command automatically performs the Precharge operation after the Read operation. W hen the CAS Latency = 3, the internal precharge starts two cycles before the last data is output. When the CAS Latency = 2, the internal precharge starts one cycle before the last data is output. 7.1.11 Extended Mode Register Set Command ( RAS = L, CAS = L, WE = L, BA0, BA1, A0~An = Register Data) The Extended Mode Register Set command is designed to support Partial Array Self Refresh, Temperature Compensated Self Refresh, and Output Driver Strength/Size by allowing users to program each value by setting predefined address bits. The defa ult values in the Extended Mode Register after power-up are undefined; therefore this command must be issued during the power -up sequence. Also, this command can be issued while all banks are in the idle state. - 20 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 7.1.12 Mode Register Set Command ( RAS = L, CAS = L, WE = L, BA0, BA1, A0~An = Register Data) The Mode Register Set command is used to program the values of CAS latency, Addressing Mode and Burst Length in the Mode Register. The default values in the Mode Register after power-up are undefined; therefore this command must be issued during the power-up sequence and re-issued after the Deep Power Down Exit Command. Also, this command can be issued while all banks are in the idle state. 7.1.13 No-Operation Command ( RAS = H, CAS = H, WE = H) The No-Operation command is used in cases such as preventing the device from registering unintended commands. The device performs no operation when this command is registered. This command is functionally equivalent to the Device Deselect command. 7.1.14 Burst Stop Command ( RAS = H, CAS = H, WE = L) The Burst stop command is used to stop the already activated burst operation. The activated page is left unclosed and future commands can be issued to access the same page of the active bank. If this command is issued during a burst read operation, t he read data will go to a Hi-Z state after a delay equal to the CAS latency. If a burst stop command is issued during a burst write operation, then the burst data is terminated and data bus goes to Hi -Z at the same clock that the burst command is activated. Any remaining data from the burst write cycle is ignored. 7.1.15 Device Deselect Command ( CS = H) The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 7.1.16 Auto Refresh Command ( RAS = L, CAS = L, WE = H, CKE = H, BA0, BA1, A0~An = Don’t care) The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The Refresh operation m ust be performed 8192 times within 64 ms. The next command can be issued after tRC from the end of the Auto Refresh command. When the Auto Refresh command is issued, All banks must be in the idle state. The Auto Refresh operation is equivalent to the CAS -before- RAS operation in a conventional DRAM. 7.1.17 Self Refresh Entry Command ( RAS = L, CAS = L, WE = H, CKE = L, BA0, BA1, A0~An = Don’t care) When the Self Refresh Entry command is issued, the device enters the Self Refresh mode. While the device is in Self Refresh mode, the device automatically refreshes memory cells, and all input and I/O buffers (except the CKE buffer) are disabled. By asser ting the CKE signal “high” (and by issuing the Self Refresh Exit command), the device exits the Self Refresh mode. 7.1.18 Self Refresh Exit Command (CKE = H, CS = H or CKE = H, RAS = H, CAS = H) This command is issued to exit out of the Self Refresh mode. One tRC delay is required prior to issuing any subsequent comman d from the end of the Self Refresh Exit command. 7.1.19 Clock Suspend Mode Entry/Power Down Mode Entry Command (CKE = L) The internal CLK is suspended for one cycle when this command is issued (when CKE is asserted “low”). The device state is held intact while the CLK is suspended. On the other hand, when the device is not operating the Burst cycle, this command performs entry into Power Down mode. All input and output buffers (except the CKE buffer) are turned off in Power Down mode. 7.1.20 Clock Suspend Mode Exit/Power Down Mode Exit Command (CKE = H) When the internal CLK has been suspended, operation of the internal CLK is re sumed by providing this command (asserting CKE “high”). When the device is in Power Down mode, the device exits this mode and all disabled buffers are turned on to the acti ve state. Any subsequent commands can be issued after one clock cycle from the end o f this command. - 21 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 7.1.21 Data Write/Output Enable, Data Mask/Output Disable Command (DQM = L/H or LDQM, UDQM = L/H or DQM0-3=L/H) During a Write cycle, the DQM or LDQM, UDQM or DQM0-3 signals mask write data. Each of these signals control the input buffers per byte. During a Read cycle, the DQM or LDQM, UDQM or DQM0 -3 signals control of the output buffers per byte. I/O Org. × 16 M ASK PIN LDQM UDQM: DQM0: M ASKED DQs DQ0~DQ7 DQ8~DQ15 DQ0~DQ7 DQ8~DQ15 DQ16~DQ23 DQ24~DQ31 × 32 DQM1: DQM2: DQM3: 8. OPERATION 8.1 Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized to the positive edges of CLK (a Burst Read operation). The initial read data becomes available after CAS Latency from the issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. In addition, the burst length of read data and Addressing Mode must be set. Each bank is held in the active state unless the Precharge command is issued, so that the sense amplifiers can be used as secondary cache. When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically after the Read cycle, then the bank is switched to the idle state. This command cannot b e interrupted by any other commands. Also, when the Burst Length is 1 and tRCD (min), the timing from the RAS command to the start of the Auto Precharge operation is shorter than t RAS (min). In this case, tRAS (min) must be satisfied by extending tRCD. When the Precharge operation is performed on a bank during a Burst Read operation, the Burst operation is terminated. When the Burst Length is full-page, column data is repeatedly read out until the Burst Stop command or Precharge command is issued. 8.2 W rite Operation Issuing the Write command after tRCD from the Bank Activate command, the input data is latched sequentially, synchronizing with the positive edges of CLK after the Write command (Burst Write operation). The burst length o f the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically after the Write cycl e, then the bank is switched to the idle state. This command cannot be interrupted by any other command for the entire burst data duration. Also, when the Burst Length is 1 and tRCD (min), the timing from the RAS command to the start of the Auto Precharge operation is shorter than tRAS (min). In this case, tRAS (min) must be satisfied by extending tRCD. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Burst Length is full-page, the input data is repeatedly latched until the Burst Stop command or the Precharge command is issued. When the Burst Read and Single Write mode is selected, the write burst length is 1 regardless of the read burst length. - 22 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 8.3 Precharge There are two commands which perform the Precharge operation: Bank Precharge and Precharge All. When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as t RAS (max). Therefore, each bank must be precharged within t RAS (max) from the Bank Activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precha rge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharg ed bank is then switched to the idle state. 8.3.1 Auto Precharge Auto precharge is a feature that performs the same individual -bank PRECHARGE function described previously, without requiring an explicit command. This is accomplished by using A10 to enable a uto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of th e READ or WRITE burst. Auto precharge ensures that the precharg e is initiated at the earliest valid stage within a burst. Another command cannot be issued to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time. Winbond SDRAM supports concurrent auto precharge; cases of concurrent auto precharge for READs and WRITEs are defined below. 8.3.2 READ with auto precharge interrupted by a READ (with or without auto precharge) A READ to bank m will interrupt a READ on bank n following the programmed CAS latency. The precharge to bank n begins when the READ to bank m is registered. T0 CLK T1 T2 T3 T4 T5 T6 T7 Command NOP READ-AP Bank n NOP READ-AP Bank m NOP NOP NOP NOP Bank n Page active READ with burst of 4 Interrupt burst, precharge tRP-bank n Idle tRP-bank m Internal states Bank m Page active READ with burst of 4 Precharge Address Bank n, Col a Bank m, Col d Dout a CL=3 (bank n) CL=3 (bank m) Dout a+1 Dout d Dout d+1 DQ Don’t Care Note: 1. DQM is LOW. - 23 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 8.3.3 READ with auto precharge interrupted by a WRITE (with or without auto precharge) A W RITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The precharge to bank n begins when the WRITE to bank m is registered. T0 CLK T1 T2 T3 T4 T5 T6 T7 Command READ-AP Bank n Page active NOP NOP NOP WRITE-AP Bank m NOP NOP NOP Bank n READ with burst of 4 Interrupt burst, precharge tRP-bank n Idle tWR-bank m Internal states Bank m Page active WRITE with burst of 4 Write-back Address DQM 1 DQ Bank n, Col a Bank m, Col d DOUT a Din d Din d+1 Din d+2 Din d+3 CL=3 (bank n) Don’t Care Note: 1. DQM is HIGH at T2 to prevent DOUTa + 1 from contending with DINd at T4. - 24 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 8.3.4 WRITE with auto precharge interrupted by a READ (with or without auto precharge) A READ to bank m will interrupt a WRITE on bank n when registered, with the data -out appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data in registered one clock prior to the READ to bank m. T0 CLK T1 T2 T3 T4 T5 T6 T7 Command NOP WRITE-AP Bank n NOP READ-AP Bank m NOP NOP NOP NOP Bank n Page active WRITE with burst of 4 Interrupt burst, write-back tWR-bank n precharge tRP-bank n tRP-bank m Internal states Bank m Page active READ with burst of 4 Address Bank n, Col a Din a Din a+1 Bank m, Col d Dout d CL=3 (bank m) Dout d+1 DQ Don’t Care Note: 1. DQM is LOW. - 25 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 8.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) A W RITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prio r to a W RITE to bank m. T0 CLK WRITE-AP Bank m T1 T2 T3 T4 T5 T6 T7 Command NOP WRITE-AP Bank n NOP NOP NOP NOP NOP Bank n Page active WRITE with burst of 4 Interrupt burst, write-back tWR-bank n precharge tRP-bank n tWR-bank m Write-back Internal states Bank m Page active WRITE with burst of 4 Address Bank n, Col a Din a Din a+1 Din a+2 Bank m, Col d Din d Din d+1 Din d+2 Din d+3 DQ Don’t Care Note: 1. DQM is LOW. - 26 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 8.4 Burst Termination The Read or Write command can be issued on any clock cycle. Whenever a Read operation is to be interrupted by a Write command , the output data must be masked by DQM to avoid I/O conflict. Also, when a Write operation is to be interrupted by a Read command, only the input data before the Read command is enable and the input data after the Read command is disabled. - Read Interrupted by a Precharge A Precharge command can be issued to terminate a Burst cycle early. When a Burst Read cycle is interrupted by a Precharge command, the read operation is terminated after ( CAS latency-1) clock cycles from the Precharge command. - W rite Interrupted by a Precharge A burst Write cycle can be interrupted by a Precharge command, the input circuit is reset at the same clock cycle at which th e Precharge command is issued. In this case, the DQM signal must be asserted high to prevent writing the invalid data t o the cell array. - Read Interrupted by a Burst Stop When the Burst Stop command is issued for the bank in a Burst cycle, the Burst operation is terminated. When the Burst Stop command is issued during a Burst Read cycle, the read operation is terminated after clock cycle of ( CAS latency-1) from the Burst Stop command. - W rite Interrupted by a Burst Stop When the Burst Stop command is issued during a Burst Write cycle, the write operation is terminated at the same clock cycle t hat the Burst Stop command is issued. - W rite Interrupted by a Read A burst of write operation can be interrupted by a read comma nd. The read command interrupts the write operation on the same clock that the read command is issued. All the burst writes that are presented on the data bus before the read command is iss ued will be written to the memory. Any remaining burst writes will be ignored once the read command is activated. There must be at least one clock bubble (Hi-Z state) on the data bus to avoid bus contention. - Read Interrupted by a Write A burst of read operation can be interrupted by a write command by driving output d rivers in a Hi-Z state using DQM before write to avoid data conflict. DQM should be utilized if there is data from a Red command on the first and second cycles of the subsequ ent write cycles to ensure the read data are tri -stated. From the third clock cycle, the write command will control the data bus and DQM is not needed. - 27 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 8.5 Mode Register Operation The Mode register designates the operation mode for the Read or Write cycle. This register is divided into three fields; A Bu rst Length field to set the length of burst data, an Addressing Mode selected bits to designate the column access sequence in a Burst cycle, and a CAS Latency field to set the access time in clock cycle. The Mode Register is programmed by the Mode Register Set command when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0~An, BA0, BA1 address inputs. The initial value of the Mode Register after power -up is undefined; therefore the Mode Register Set command must be issued before proper operation. 8.5.1 Burst Length field (A2~A0) This field specifies the data length for column access using the A2~A0 pins and sets the Burst Length to be 1, 2, 4, 8, words , or full-page. A2 0 0 0 0 1 A1 0 0 1 1 1 A0 0 1 0 1 1 BUST LENGTH 1 word 2 words 4 words 8 words Full-Page 8.5.2 Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential mode. When the A3 bit is 0, Sequential mode is selected. When the A3 bit is 1, Interleave mode is selected. Both Addressing modes support burst length of 1, 2, 4 and 8 word s. Additionally, Sequential mode supports the full-page burst. A3 0 1 ADDRESSING MODE Sequential Interleave - 28 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR  Addressing sequence of Sequential mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Lengt h shown as below table. 8.5.3 Addressing Sequence for Sequential Mode DATA Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7  Access Address n Burst Length 2 words (Address bits is A0) n+1 n+2 n+3 not carried from A0 to A1 4 words (Address bits is A1, A0) not carried from A1 to A2 8 words (Address bits is A2, A1, A0) n+4 n+5 n+6 n+7 not carried from A2 to A3 Addressing sequence of Interleave mode A column access is started from the input column address and is performed by inverting the address bits in the sequence shown as below table. 8.5.4 Addressing Sequence for Interleave Mode DATA Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Access Address A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Burst Length 2 words 4 words 8 words - 29 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 8.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13) INTERLEAVE MODE DATA A8 Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 0 0 0 0 0 0 0 0 A7 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 1 1 1 1 1 1 1 1 A2 1 1 1 1 0 0 0 0 A1 0 0 1 1 0 0 1 1 A0 1 0 1 0 1 0 1 0 ADD 13 12 15 14 9 8 11 10 13 13 + 1 13 + 2 13 + 3 13 + 4 13 + 5 13 + 6 13 + 7 ADD 13 14 15 8 9 10 11 12 calculated using A2, A1 and A0 bits not carry from A2 to A3 bit. SEQUENTIAL MODE 8.5.6 Read Cycle CAS Latency = 3 0 1 2 3 4 5 6 7 8 9 10 11 Command Read Address 13 DQ0~DQ7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Data Address { Interleave mode 13 Sequential mode 13 12 14 15 15 14 8 9 9 8 10 11 11 10 12 - 30 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 8.5.7 CAS Latency field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum va lues of CAS Latency depends on the frequency of CLK. The minimum value which satisfies the following formula must be set in this field. A6 0 0   A5 1 1 A4 0 1 CAS Latency 2 clock 3 clock Reserved bits (A7, A8, A10, A11, An, BA0, BA1) These bits are reserved for future operations. They must be set to 0 for normal operation. Single Write mode (A9) This bit is used to select the write mode. When the A9 bit is 0, Burst Read and Burst Write mode are selected. When the A9 bi t is 1, Burst Read and Single Write mode are selected. A9 0 1 8.5.8 Mode Register Definition A0 A1 A2 A3 A4 A5 A6 A0 7 A8 A0 9 A10 A11 A0 An BA0 BA1 "0" "0" "0" "0" "0" A0 Reserved "0" "0" Reserved Reserved Write Mode A0 A6 0 0 0 0 1 CAS Latency Addressing Mode Burst Length A2 0 0 0 0 1 1 1 1 A0 A0 1 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A0 3 A0 0 A0 1 A0 5 A0 0 A0 0 A0 1 A0 1 A0 0 A0 9 A0 0 A0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write BurstA0 Length A0 0 1 0 1 0 1 0 1 Sequential A0 1 A0 2 A0 4 A0 8 Reserved A0 Full 0 A Page Addressing Mode A0 Sequential A0 Interleave A0 A4 0 1 0 1 0 A0 CAS Latency Reserved A0 Reserved 2 A0 3 Reserved Single Write Mode Burst read and Burst write A0 Burst read and single write A0 Interleave A0 A0 1 A0 2 A0 4 A0 8 Reserved A0 - 31 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 8.6 Extended Mode Register Description The Extended Mode Register designates the operation condition while SDRAM is in Self Refresh Mode and selects the output driver strength as full, 1/2, 1/4, or 1/8 strength. The register is divided into two fields; (1) Partial Array Self Refresh field selects how much banks or which part of a bank need to be refreshed during Self Refresh. (2) Driver Strength selected bit to control the size of output buffer. The initial value of the Extended Mode Register after power -up is Full Driver Strength, and all banks are refreshed during Self Refresh Mode. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 An BA0 BA1 Output Driver "0" "0" "0" Reserved "0" "0" Reserved "0" Partial Array Self Refresh A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Self-Refresh coverage All banks Banks 0 and 1 (BA1=0) Bank 0 (BA1=BA0=0) Reserved Reserved Reserved Reserved Reserved A6 "0" "0" "0" "1" Extended Mode Register Set A5 0 1 0 1 Driver Strength Full strength 1/2 strength 1/4 strength 1/8 strength 0 0 1 1 - 32 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 8.7 Simplified State Diagram - 33 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 9. CONTROL TIMING WAVEFORMS 9.1 Command Input Timing tCL tCH tCK CLK VIH VIL tT tCMS tCMH tCMH tT tCMS CS tCMS tCMH RAS tCMS tCMH CAS tCMS tCMH WE tAS tAH Address BA0, BA1 tCKS tCKH tCKS tCKH tCKS tCKH CKE - 34 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 9.2 Read Timing Read CAS Latency CLK CS RAS CAS WE Address BA0, BA1 tAC tLZ tOH tAC tHZ tOH Output Data Valid Burst Length DQ Read Command Output Data Valid - 35 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 9.3 Control Timing of Input Data (x16) (Word Mask) CLK tCMH tCMS tCMH tCMS LDQM tCMH tCMS tCMH tCMS UDQM tDS tDH tDS tDH tDS tDH tDS tDH DQ0~DQ7 Input Data Valid tDS tDH tDS Input Data Valid tDH tDS Input Data Valid tDS Input Data Valid tDH tDH DQ8~DQ15 Input Data Valid Input Data Valid Input Data Valid Input Data Valid (Clock Mask) CLK tCKH tCKS tCKH tCKS CKE tDS tDH tDS tDH tDS tDH tDS tDH DQ0~DQ7 Input Data Valid tDS tDH Input Data Valid tDS tDH Input Data Valid tDS tDH tDS Input Data Valid tDH DQ8~DQ15 Input Data Valid Input Data Valid Input Data Valid Input Data Valid - 36 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 9.4 Control Timing of Output Data (x16) (Output Enable) CLK tCMH tCMS tCMH tCMS LDQM tCMH tCMS tCMH tCMS UDQM tAC tOH tOH tAC tHZ tOH tLZ tAC tOH tAC DQ0~DQ7 tAC tOH Output Data Valid tAC tOH Output Data Valid tAC tOH OPEN tHZ tOH Output Data Valid tLZ tAC DQ8~DQ15 Output Data Valid Output Data Valid Output Data Valid OPEN (Clock Mask) CLK tCKH tCKS tCKH tCKS CKE tAC tOH tAC tOH tAC tOH tOH tAC DQ0~DQ7 tAC tOH Output Data Valid tAC tOH Output Data Valid tAC tOH Output Data Valid tAC tOH DQ8~DQ15 Output Data Valid Output Data Valid Output Data Valid - 37 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 9.5 Control Timing of Input Data (x32) CLK (Word Mask) tCMH tCMS tCMH tCMS DQM0 tCMH tCMS tCMH tCMS DQM1 tDS tDH tDS tDH tDS tDH tDS tDH DQ0~DQ7 Input Data Valid tDS tDH tDS Input Data Valid tDH tDS Input Data Valid Input Data Valid tDS tDH tDH DQ8~DQ15 Input Data Valid Input Data Valid Input Data Valid Input Data Valid tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH DQ16~DQ23 Input Data Valid Input Data Valid tDH Input Data Valid Input Data Valid tDS Input Data Valid tDS tDS tDH tDS tDS tDH tDH tDH DQ24~DQ31 Input Data Valid Input Data Valid Input Data Valid Input Data Valid Input Data Valid *DQM2, 3 = “L” (Clock Mask) CLK tCKH tCKS tCKH tCKS RAS tDS tDH tDS tDH tDS tDH tDS tDH DQ0~DQ7 Input Data Valid tDS tDH tDS Input Data Valid tDH Input Data Valid tDS tDH Input Data Valid tDS tDH DQ8~DQ15 Input Data Valid tDS tDH tDS Input Data Valid tDH Input Data Valid tDS tDH Input Data Valid tDS tDH DQ16~DQ23 Input Data Valid tDS tDH tDS Input Data Valid tDH Input Data Valid tDS tDH Input Data Valid tDS tDH DQ24~DQ31 Input Data Valid Input Data Valid Input Data Valid Input Data Valid *DQM2, 3 = “L” - 38 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 9.6 Control Timing of Output Data (x32) (Output Enable) CLK tCMH tCMS tCMH tCMS DQM0 tCMH tCMS tCMH tCMS DQM1 tAC tOH tAC tOH tHZ tOH tLZ tAC tOH tAC DQ0~DQ7 tAC tOH Output Data Valid tAC tOH Output Data Valid tAC tOH OPEN tHZ tOH Output Data Valid tLZ tAC DQ8~DQ15 tAC tOH Output Data Valid tAC tOH Output Data Valid tAC tOH Output Data Valid tAC tLZ OPEN tOH tAC DQ16~DQ23 tAC tOH Output Data Valid tOH tAC Output Data Valid tAC tOH Output Data Valid tAC tOH Output Data Valid tOH tAC DQ24~DQ31 Output Data Valid Output Data Valid Output Data Valid Output Data Valid DQM2, 3 = “L” (Clock Mask) CLK tCKH tCKS tCKH tCKS CKE tAC tOH tAC tOH tAC tOH tOH tAC DQ0~DQ7 tAC tOH Output Data Valid tAC tOH Output Data Valid tAC tOH Output Data Valid tOH tAC DQ8~DQ15 tAC tOH Output Data Valid tAC tOH Output Data Valid tAC tOH Output Data Valid tOH tAC DQ16~DQ23 tAC tOH Output Data Valid tAC tOH Output Data Valid tAC tOH Output Data Valid tOH tAC DQ24~DQ31 Output Data Valid Output Data Valid Output Data Valid DQM2, 3 = “L” - 39 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 9.7 Mode register Set (MRS) Cycle tRSC CLK tCMS tCMH CS tCMS tCMH RAS tCMS tCMH CAS tCMS tCMH WE tAS tAH Register set data Address BA0,BA1 next command A0 A1 A2 A3 A4 A5 A6 A7 0 A8 A9 0 A10 A0 A11 A0 An BA0 A0 BA1 0 0 0 0 0 Mode Register Set Reserved 0 0 Reserved Reserved A0 Write Mode A6 0 0 0 0 1 CAS Latency Addressing Mode Burst Length A2 0 0 0 0 1 1 1 1 A0 A0 1 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A3 0 A0 0 A0 1 A5 0 A0 0 A0 0 A0 1 A0 1 A0 0 A9 0 A0 0 A0 1 A4 0 1 0 1 0 A0 0 1 0 1 0 1 0 1 BurstA0 Length A0 A0 Sequential Interleave 1 A0 1 A0 A0 2 2 A0 A0 4 4 A0 A0 8 8 A0 Reserved FullA0 Page A0 Addressing Mode A0 Sequential A0 Interleave CAS A0 Latency A0 Reserved A0 Reserved A0 Reserved 2 A0 3 Reserved Single Write Mode A0 Burst read and Burst write A0 Burst read and single write “Reserved” pins should be set to “0” during MRS cycle. - 40 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 9.8 Extended Mode register Set (EMRS) Cycle t RSC CLK t CMS t CMH CS t CMS t CMH RAS t CMS t CMH CAS t CMS t CMH WE tAS tAH Register set data Address BA0, BA1 next command A0 A1 A2 A3 A4 A5 A6 A7 0 A8 A9 0 A 10 A 11 A0 An A0 BA 0 BA0 A1 0 0 0 Reserved 0 0 0 0 1 Extended Mode Register Set A6 A0 A5 A 0 00 0 01 A 1 00 A 1 01 A A0 Output Driver S trength A0 Full Strength A0 1/2 Strength 1/4 Strength A0 A0 1/8 Strength PASR 0 0 Reserved Output Driver A2 0 0 0 0 1 1 1 1 A0 A0 A1 A0 A0 0 A0 1 A0 1 0 A0 1 1 A0 0 A0 1 A0 1 0 A0 1 1 Partial A0 Refresh Self All A0 banks Bank0,A0 BA1=0) 1( Bank0( BA0 = BA1=0) A A0 Reserved "Reserved" pins should be set to "0" during EMRS cycle - 41 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10. OPERATING TIMING EXAMPLE 10.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC tRAS tRP tRAS tRP RAS tRAS tRP tRAS CAS WE BA0 BA1 tRCD tRCD RBb RAc tRCD RBd tRCD RAe A10 RAa Address DQM RAa CAw RBb CBx RAc CAy RBd CBz RAe CKE tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 tAC cy0 cy1 cy2 cy3 tAC DQ tRRD tRRD tRRD tRRD Bank #0 Active Bank #1 Bank #2 Bank #3 Idle Read Active Precharge Read Active Read Precharge Active Precharge Read Active - 42 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC tRAS tRP tRP tRAS RAS tRAS tRP tRAS CAS WE BA0 BA1 tRCD tRCD RBb RAc tRCD RBd tRCD RAe A10 RAa Address DQM CKE RAa CAw RBb CBx RAc CAy RBd CBz RAe tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 tAC cy0 cy1 cy2 cy3 tAC dz0 DQ tRRD tRRD tRRD tRRD Bank #0 Bank #1 Bank #2 Bank #3 Idle Active Read Active AP* Read Active AP* Read Active AP* Read Active * AP is the internal precharge start timing - 43 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC RAS tRAS tRP tRP tRAS tRAS tRP CAS WE BA0 BA1 tRCD tRCD RBb RAc tRCD A10 RAa Address DQM RAa CAx RBb CBy RAc CAz CKE tAC tAC ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 tAC by7 CZ0 DQ tRRD tRRD Bank #0 Bank #1 Bank #2 Bank #3 Active Read Precharge Active Read Precharge Active Read Precharge Idle - 44 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge) 0 1 2 3 4 5 6 7 8 tRC 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRAS tRP CAS WE BA0 BA1 tRCD tRCD RBb RAc tRCD A10 RAa Address DQM RAa CAx RBb CBy RAc CAz CKE DQ tAC ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 tAC by1 by4 by5 tAC by6 cz0 tRRD tRRD Bank #0 Bank #1 Bank #2 Bank #3 Active Read Active AP* Read Active Read AP* Idle * AP is the internal precharge start timing - 45 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.5 Interleaved Bank Write (Burst Length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRP CAS tRCD tRCD tRCD WE BA0 BA1 A10 RAa RBb RAc Address DQM RAa CAx RBb CBy RAc CAz CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 tRRD tRRD Bank #0 Bank #1 Bank #2 Bank #3 Active Write Active Write Precharge Active Write Precharge Idle - 46 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRAS tRP CAS WE BA0 BA1 tRCD tRCD RBb RAc tRCD A10 RAa Address DQM RAa CAx RBb CBy RAc CAz CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 tRRD tRRD Bank #0 Active Bank #1 Bank #2 Bank #3 Idle Write Active AP* | Write Active Write | AP* * AP is the internal precharge start timing - 47 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tCCD tCCD tCCD CS tRAS tRAS tRP tRP RAS CAS WE BA0 BA1 tRCD tRCD RBb A10 Address DQM CKE RAa RAa CAI RBb CBx CAy CAm CBz tAC tAC a l0 a l1 a l2 a l3 bx0 tAC bx1 Ay0 Ay1 tAC Ay2 am0 am1 am2 tAC bz0 bz1 bz2 bz3 DQ tRRD Bank #0 Active Bank #1 Bank #2 Bank #3 Idle Read Active Read Read Read Read Precharge AP* * AP is the internal precharge start timing - 48 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS tRAS tRP WE BA0 BA1 tRCD A10 RAa Address RAa CAx CAy DQM CKE tAC tWR ax0 ax1 ax2 ax3 ax4 ax5 ay0 ay1 ay2 ay3 ay4 DQ QQ Q Q Q Q D D D D D Bank #0 Bank #1 Bank #2 Bank #3 Active Read Write Precharge Idle - 49 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) CLK CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 tRC tRC RAS tRAS tRP tRAS tRP CAS WE BA0 BA1 tRCD tRCD RAb A10 RAa Address DQM CKE RAa CAw RAb CAx tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 DQ Bank #0 Bank #1 Bank #2 Bank #3 Active Read AP* Active Read AP* Idle * AP is the internal precharge start timing - 50 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.10 Auto Precharge Write (Burst Length = 4) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BA0 BA1 tRCD tRCD RAb RAc A10 Address DQM CKE DQ RAa RAa CAw RAb CAx RAc aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 Bank #0 Bank #1 Bank #2 Bank #3 Active Write AP* Active Write AP* Active Idle * AP is the internal precharge start timing - 51 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.11 Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRP tRFC tRFC CS RAS CAS WE BA0,BA1 A10 Address DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 52 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.12 Self Refresh Cycle 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRP RAS CAS WE BA0,BA1 A10 Address DQM tSB CKE tCKS tCKS tCKS DQ tRFC All Bank Precharge Device Deselect (DSL) Cycle Arbitrary Cycle Note: The device exit the Self Refresh mode asynchronously at the rising edge of the CKE signal. After CKE goes high, the Device Deselect or No-operation command must be registered at the immediately following CLK rising edge, and CKE must remain high at least for tCKS delay immediately after exit the Self Refresh Mode. A bust of 8K auto refeesh cycle within 7.8us before entering and exiting is necessary if the system does not use the auto refresh function. Self Refresh Entry Self Refresh Exit - 53 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.13 Power Down Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BA A10 RAa RAa Address RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS ax0 ax1 ax2 tCKS ax3 tCKS DQ Active DSL Power Down Mode Down Mode Power Entry Exit Precharge & Power Down Mode Entry Active Device Deselect Power Down Mode Exit Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode. When CKE goes high, command input must be No operation at next CLK rising edge. Violating refresh requirements during power-down may result in a loss of data. - 54 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.14 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS tRCD WE BA0 BA1 A10 RBa Address DQM CKE RBa CBv CBw CBx CBy CBz tAC tAC av0 av1 Q Q av2 Q av3 D aw0 D ax0 D ay0 Q az0 Q az1 Q az2 Q az3 DQ Q Bank #0 Active Bank #1 Bank #2 Bank #3 Idle Read Single Write Read - 55 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.15 Deep Power Down Mode Entry 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP RAS CAS WE BA0,BA1 A10 Address DQM tSB CKE tCKS DQ Active Banks Precharge Deep Power Down Entry - 56 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.16 Deep Power Down Mode Exit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP tRSC tRSC RAS CAS WE A10 OP-Code OP-Code Address DQM CKE tCKS DQ 200μs DSL All Banks Precharge Mode Register Set Extended Mode Register Set Auto Refresh tRCF Auto Refresh Auto Refresh Arbitrary Cycle Deep Power Down Exit Issue Auto Refresh cycle two or more Note: The device exits the Deep Power Down Mode asynchronously at the rising edge of the CKE signal. After CKE goes high, the Device Deselect or No-operation command must be register at the immediately following CLK rising edge, and CKE must remain high at least for tCKS delay immediately after exiting the Deep Power Down Mode. - 57 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.17 Auto Precharge Timing (Read Cycle) 0 (1) CAS Latency=2 ( a ) burst length = 1 Command 1 AP 2 3 Act 4 5 6 7 8 9 10 11 Read tRP DQ Q0 Read AP tRP ( b ) burst length = 2 Command DQ Act Q1 AP tRP Q0 Read Q0 Read Q0 ( c ) burst length = 4 Command DQ Act Q3 AP tRP Q1 Q2 ( d ) burst length = 8 Command Act DQ Q1 Q2 Q3 Q4 Q5 Q6 Q7 (2) CAS Latency=3 ( a ) burst length = 1 Command Read AP tRP Act Q0 DQ ( b ) burst length = 2 Command DQ Read AP tRP Act Q0 Q1 AP tRP ( c ) burst length = 4 Command DQ Read Q0 Read Q0 Act Q2 Q3 AP tRP Q1 ( d ) burst length = 8 Command Act Q6 Q7 DQ Q1 Q2 Q3 Q4 Q5 Note: Read AP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min). “Dn” = Write data, and “Qn” = Read data - 58 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.18 Auto Precharge Timing (Write Cycle) 0 (1) burst length = 1 Command 1 2 3 4 5 6 7 8 9 10 11 12 Write tWR AP tRP Act DQ (2) burst length = 2 Command D0 Write tWR AP tRP Act DQ (3) burst length = 4 Command D0 Write D1 AP tWR tRP Act DQ (4) burst length = 8 Command D0 Write D1 D2 D3 AP tWR tRP Act DQ D0 D1 D2 D3 D4 D5 D6 D7 Note: Wirte AP Act represents the Write with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min). “Dn” = Write data, and “Qn” = Read data - 59 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.19 Timing Chart of Read to Write Cycle In the case of Burst Length = 4 (1) CAS Latency = 2 DQM Latency = 2 ( a ) Command DQM DQ 0 1 Read 2 Write 3 4 5 6 7 8 9 10 11 D0 Read D1 Write D2 D3 ( b ) Command DQM DQ D0 D1 D2 D3 (2) CAS Latency = 3 DQM Latency = 2 ( a ) Command DQM DQ ( b ) Command DQM Read Write D0 D1 Write D2 D3 Read DQ D0 D1 D2 D3 Note: The Output data must be masked by DQM to avoid I/O conflict. “Dn” = Write data, and “Qn” = Read data 10.20 Timing Chart for Write to Read Cycle In the case of Burst Length=4 0 (1) CAS Latency=2 ( a ) Command DQM DQ ( b ) Command DQM DQ 1 Write D0 Write D0 Write D0 Write D0 tLDR 2 Read 3 4 5 6 7 8 9 10 11 tLDR Q0 tLDR Q1 Q2 Q3 Read Q0 Q1 Q2 Q3 (2) CAS Latency=3 ( a ) Command DQM DQ ( b ) Command DQM DQ D1 Read Q0 tLDR Q1 Q2 Q3 Read Q0 Q1 Q2 Q3 D1 Note: “Dn” = Write data, and “Qn” = Read data - 60 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.21 Timing Chart for Burst Stop Cycle (Burst Stop Command) (1) Read cycle ( a ) CAS latency =2 Command DQ ( b )CAS latency = 3 Command DQ (2) Write cycle Command DQ 0 Read 1 2 3 4 5 BST 6 7 8 9 10 11 Q0 Read Q1 Q2 Q3 BST Q2 Q4 Q0 Q1 Q3 Q4 Write Q0 Q1 Q2 Q3 Q4 BST Note: BST represents the Burst stop command “Dn” = Write data, and “Qn” = Read data 10.22 Timing Chart for Burst Stop Cycle (Precharge Command) In the case of urst Length = 8 (1) Read cycle (a) CAS latency =2 Command DQ 0 Read 1 2 3 4 5 PRCG 6 7 8 9 10 11 Q0 Read Q1 Q2 Q3 PRCG Q4 (b) CAS latency =3 Command DQ Q0 Q1 Q2 Q3 Q4 (2) Write cycle (a) CAS latency =2 Write DQM Latency = 0 DQM DQ Command Write tWR PRCG Q0 Write Q1 Q2 Q3 Q4 PRCG tWR (b) CAS latency =3 Write DQM Latency = 0 DQM DQ Command Q0 Q1 Q2 Q3 Q4 Note: PRCG represents the Precharge command. “Dn” = Write data, and “Qn” = Read data. - 61 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.23 CKE/DQM Input Timing (Write Cycle) CLK cycle No. External CLK Internal CKE DQM DQ 1 2 3 4 5 6 7 D1 D2 D3 DQM MASK (1) D5 CKE MASK D6 CLK cycle No. External CLK Internal CKE DQM DQ 1 2 3 4 5 6 7 D1 D2 D3 DQM MASK (2) CKE MASK D5 D6 CLK cycle No. External CLK Internal CKE DQM DQ 1 2 3 4 5 6 7 D1 D2 D3 CKE MASK (3) D4 D5 D6 Note) “Dn” = Write data, and “Qn” = Read data - 62 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 10.24 CKE/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Open Open Q6 (1) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Open Q6 (2) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Q5 Q6 Note) “Dn” = Write data, and “Qn” = Read data (3) - 63 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 11. PACKAGE DIMENSION 11.1 : LPSDR X 16 VBGA 54Ball (8X9 MM^2, Ball pitch:0.8mm) Note: 1. Ball land:0.5mm. Ball opening:0.4mm. PCB Ball land suggested ≦0.4mm 2. Dimensions apply to Solder Balls Post-Reflow.The Pre-Reflow diameter is 0.42 on a 0.4 SMD Ball Pad - 64 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 11.2 : LPSDR X 32 VBGA90Ball (8X13 MM^2, Ball pitch:0.8mm) Note: 1. Ball land:0.5mm. Ball opening:0.4mm. PCB Ball land suggested ≦0.4mm 2. Dimensions apply to Solder Balls Post-Reflow. The Pre-Reflow diameter is 0.42 on a 0.4 SMD Ball Pad. - 65 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 12.ORDERING INFORMATION Mobile LPDDR/LPSDR SDRAM Package Part Numbering W 98 7 D 6 H B G X 6 I Product Line 98:mobile LPSDR SDRAM 94:mobile LPDDR SDRAM Density 7:27=128M 8:28=256M 9:29=512M Power Supply D:1.8/1.8 VDD / VDDQ I/O Ports width 6:16bit 2:32bit Generation Design revision. Package or KGD K: KGD B: BGA Temperature with standard Idd6 G:-25C~85C with low power Idd6 E:-25C~85C I:-40C~85C Clock rate 5:5ns200MHz 6:6ns166MHz 7:7.5ns133MHz Package Material X: Lead-free + Halogen-free Package configuration code G: 54VFBGA, 8mmx9mm H: 60VFBGA, 8mmx9mm J: 90VFBGA, 8mmx13mm Part number W987D6HBGX6I W987D6HBGX6E W987D6HBGX7I W987D6HBGX7E W987D6HBGX7G W987D2HBGX6I W987D2HBGX6E W987D2HBGX7I W987D2HBGX7E W987D2HBGX7G VDD/VDDQ 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V I/O width 16 16 16 16 16 32 32 32 32 32 Package 54VFBGA 54VFBGA 54VFBGA 54VFBGA 54VFBGA 90VFBGA 90VFBGA 90VFBGA 90VFBGA 90VFBGA Others 166MHz, -40~85C, Low Power 166MHz, -25~85C, Low Power 133MHz, -40~85C, Low Power 133MHz, -25~85C, Low Power 133MHz, -25~85C 166MHz, -40~85C, Low Power 166MHz, -25~85C, Low Power 133MHz, -40~85C, Low Power 133MHz, -25~85C, Low Power 133MHz, -25~85C - 66 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR 13. REVISION HISTORY VERSION A01-001 A01-002 DATE 04/29/2011 06/09/2011 PAGE All 9~11 66 DESCRIPTION Product datasheet for customer. Update IDD4 value , Add Normal power grade & PASR. Update ordering info. - 67 - Publication Release Date: Jun. 09, 2011 Revision A01-002 W987D6HB / W987D2HB 128Mb Mobile LPSDR Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wher e in personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. ----------------------------------------------------------------------------------------------------------------------------- -------------------Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in the datasheet belong to their respective owners. - 68 - Publication Release Date: Jun. 09, 2011 Revision A01-002