74HC373

74HC373 GENERAL DESCRIPTION Octal Transparent D-type Latches W ith 3-State Outputs 74HC373 is fabricated with high-speed silicon gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits. The eight latches in 74HC373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the levels that were set up at the D inputs. An output-enable input (OE) makes the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high- impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. These 8-bit latches with 3-state outputs are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bi-directional bus drivers, and working registers. FEATURES • • • • • W ide operating supply voltage range: 2-6V 8 high-current latches with 3-state outputs in a single package Full parallel access for loading Low input current: 1µA (Max.) Low power consumption: 80µA (Max.) LOGIC DIAGRAM 1Q (2) OE (1) 2Q (5) 3Q (6) 4Q (9) 5Q (12) 6Q (15) 7Q (16) 8Q (19) C1 1D C1 2D C1 3D C1 4 D C1 5D C1 6D C1 7 D C1 8 D LE (11) 1D (3) 2D (4) 3D (7) 4D (8) 5D (13) 6D (14) 7D (17) 8D (18) FUNCTIONAL DESCRIPTION Truth Table OE L L L H Inputs LE H H L X D H L X X Outputs Q H L Q0 Z H = High Level (steady state). L= Low Level (steady state) X = Irrelevant (any input, including transitions) 1 WS74HC373 ABSOLUTE MAXIMUM RATINGS Parameter Value Unit DC supply voltage (Vcc) - 0.5 ~ + 7.0 V DC input or output Voltage (VIN, VOUT) -0.5 to Vcc +0.5 V DC Current Drain per pin, any output (Iout) ±35 mA DC Current per pin, Vcc or GND (Icc) ±70 mA Storage Temperature( TSTG) -65 ~ +150 ℃ Note: 1. Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. RECOMMENDED OPERATING CONDITONS Parameter Min. Normal Max. Unit V Vcc Supply Voltage VIH High-level Input Voltage VIL Low-level Input Voltage VCC = 2.0V VCC = 4.5V VCC = 6.0V VCC= 2.0V VCC = 4.5V VCC = 6.0V 2.0 1.5 3.15 4.2 5.0 6.0 V VI Input Voltage 74HC373 0 0.5 1.35 1.8 Vcc V V VO Output Voltage Operating Temperature (TA) 0 Vcc V -40 +85 ℃ VCC = 2.0V 1000 ns 500 VCC = 4.5V 400 VCC = 6.0V Note: 2. All unused inputs of the device must be held at Vcc or GND to ensure proper device operation. DC ELECTRICAL CHARACTERISTICS ( apply across temperature range unless otherwise specified) TA＝25 C Min. Typ. Max. o Input Rise/Fall Times (tr, tf) -40 ~ +85 Parameter Test Conditions Vcc Min. Max. Unit 2V 1.9 1.998 1.9 IOH = -20uA 4.5V 4.4 4.499 4.4 VOH VI =VIH or VIL IOH = -6mA 6V 5.9 5.999 5.9 V 4.5V 3.98 4.3 3.84 IOH=-7.8mA 6V 2V 4.5V 5.48 5.8 0.002 0.001 5.34 0.1 0.1 0.1 0.1 IOL = 20uA VOL VI =VIH or VIL 6V IOL = 6mA IOL = 7.8mA 0.001 0.17 0.15 0.1 0.26 0.26 0.1 0.33 0.33 V 4.5V 6V II IOZ ICC VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, IO = 0 6V 6V 6V ±0.1 ±100 ±1000 ±5 80 nA µA µA ±0.01 ±0.5 8 Ci 2V～6V 3 10 10 pF 2 WS74HC373 TIMING REQUIREMENTS OVER RECOMMENDED OPERATING TEMPERATURE (unless otherwise specified) T A = 25℃ -40 ~ +85 Parameter VDD 2.0 V 4.5V 6.0 V 2.0 V 4.5V 6.0 V 2.0 V 4.5V 6.0 V Min 80 16 14 50 10 9 20 10 10 Max Min Max 100 20 17 63 Unit tw Pulse duration, LE high ns tsu Setup time, data before LE↓ th Hold time, data after LE↓ 13 11 24 12 ns ns 12 AC ELECTRICAL CHARACTERISTICS TEMPERATURE, CL = 50 pF OVER RECOMMENDED OPERATING (unless otherwise specified) Parameter From (Input) To (Output) VDD Min D Q tpd LE Any Q ten ___ OE ___ OE Any Q tdis Any Q tt Any Q 2.0 V 4.5V 6.0 V 2.0 V 4.5V 6.0 V 2.0 V 4.5V 6.0 V 2.0 V 4.5V 6.0 V 2.0 V 4.5V 6.0 V T A = 25℃ Typ Max Min 150 58 15 30 13 26 175 73 18 35 15 30 150 65 17 30 14 26 150 50 30 15 13 26 28 60 12 8 6 10 -40 ~ +85 Max 190 38 32 220 44 38 190 38 32 190 38 32 75 15 13 Unit ns ns ns 3 WS74HC373 AC ELECTRICAL CHARACTERISTICS TEMPERATURE, CL = 150 pF OVER RECOMMENDED OPERATING (unless otherwise specified) Parameter From (Input) To (Output) VDD Min D Q tpd LE Any Q ten ___ OE Any Q tt Any Q 2.0 V 4.5V 6.0 V 2.0 V 4.5V 6.0 V 2.0 V 4.5V 6.0 V 2.0 V 4.5V 6.0 V T A = 25℃ Typ Max Min 200 82 22 40 34 19 100 225 24 45 20 38 90 200 23 40 34 19 45 210 17 42 13 36 -40 ~ +85 Max 250 50 43 285 57 48 250 50 43 265 53 45 Unit ns ns ns AC SWITCHING WAVEFORM AND AC TEST CIRCUIT High-Level Pulse 50% V cc Vcc 0V 50% 0V Reference Input 50% tw Low-Level Pulse tsu th 50% 50% Vcc 0V Data Input 50% 10% 90% tr 90% Vcc 50% 10% tf 0V Voltage Waveforms Pulse Durations Voltage Waveforms Setup & Hold and Input Rise & Fall Times Output Control (Low-Level Enabling) Output Waveform1 Input Vcc 50% 50% tPLH In-Phase Output 50% 10% 90% tPHL 90% 0V VOH 50% tPZL ≈Vcc 50% 50% tPLZ Vcc 0V ≈Vcc tr Out-of-Phase Output tPHL 90% 50% 10% 50% 10% VOL tf tPLH VOH 90% 50% 10% VOL 10% 90% tPHZ VOL VOH ≈0 V tPZH Output Waveform 2 50% tf tr Voltage Waveforms Propagation Delay and Output Transition Times Voltage Waveforms Enable and Disable Times for 3-State Outputs 4 WS74HC373 VDD Test Point CL (see Note A) Parameter RL S1 RL ten tPZH 1kΩ From Output Under Test tPZL CL 50 pF or 150 pF S1 S2 Open Closed Closed Open S2 tdis tPHZ 1kΩ 50 pF Open Closed tPLZ Closed Open tpd or tt - 50 pF or 150 pF Open Open Notes: A. B. C. D. E. F. G. CL includes probe and test-fixture capacitance. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR≤ 1 MHz, Zo = 50Ω, tr=6ns, tf =6ns. The outputs are measured one at a time with one input transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPLH and tPHL are the same as tpd. PIN DESCRIPTION PIN NO. 3, 4, 7, 8, 13, 14, 17, 18 2, 5, 6, 9, 12, 15, 16, 19 10 1 11 20 SYMBOL 1D - 8D 1Q - 8Q GND OE LE VCC DESCRIPTION Data Inputs Outputs Ground (0V) Output-enable latch-enable Positive power supply 11 OE 1Q 1 20 VCC 8Q 3 4 1D 2D 3D 4D 5D 6D 7D 8D LE 1Q 2 5 6 9 1D 2D 2Q 8D 7 2Q 3Q 4Q 7D 8 7Q 13 3Q 3D 4D 6Q 14 5Q 12 6Q 15 7Q 16 6D 17 5D 18 4Q GND 5Q 8Q 19 OE 1 10 11 LE Pin Configuration (DIP-20) Logic Symbol 5 WS74HC373 PAD DIAGRAM 5Q LE GND 4Q The Coordinate of Each Pad 4D 5D 8Q 6D 3D (-326.1, -808.7) 4Q (237.7, 718.5) VCC (-151.7, -816.1) OE (82.5, -808.7) 1Q (237.7, -808.7) 74HC373 GND (42.5, 729.9) LE (-160.5, 718.6) 5Q (-326.1, 718.6) 5D (-476.5, 568.7) 6D 6Q 7Q 7D 8D (-476.5, 352.9) (-476.5, 24.7) (-476.5, -135.0) (-476.5, -457.2) (-476.5, -673.0) 1D 3Q (388.3, -673.1) 6Q Die Size = 49 mil x 77 mil Pad size = 90 um x 90 um 2D (388.3, -457.3) 2Q 7Q 2Q (388.0, -132.2) 3Q (388.0, 25.6) 3D (388.1, 351.8) (388.1, 567.6) 7D 2D 4D 8D VCC OE 1Q 1D Note: Substrate should be connected to Vcc or left it open. 8Q 6