WM8146

WM8146 12-bit (8+4-bit) Linear Sensor Image Processor Product Preview, January 2000 Rev 1.1 DESCRIPTION The WM8146 is a 12-bit analogue front end/digitiser IC, which processes and digitises the analogue output signals from linear CCD sensors at pixel sample rates of up to 6MSPS. The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset adjust functions. The output from each of these channels is time multiplexed into a single high-speed 12-bit Analogue to Digital Converter. The digital output data is available in 8+4-bit wide multiplexed format, with no missing codes. The WM8146 is controlled via a configurable serial interface, which is compatible with all of Wolfson’s imaging devices. Powered from an analogue supply voltage of 5V and a digital interface supply of either 5V or 3.3V, the WM8146 typically only consumes 175mW when operating from 5V supplies. FEATURES • • • • • • • • • • • • No missing codes guaranteed 6MSPS sample rate Colour pixel by pixel or line by line sampling Monochrome sampling Selectable reset level clamp voltage Pixel by pixel or line by line clamping Correlated double sampling 5-bit programmable gain amplifier 8-bit + sign offset adjustment 5V or 3.3V digital interface compatibility Serial control interface 28-pin SOIC package APPLICATIONS • • • • Flatbed scanners Multi-function peripherals Copier scanners CCD sensor interfaces BLOCK DIAGRAM VRLC (26) AVDD (21) VRT (24) VRB (23) VMID (25) AGND1 (22) AGND2 (2) VSMP (5) MCLK (7) RLC (6) DGND (8) DVDD1 (3) DVDD2 (10) MUX TIMING CONTROL VMID CL RS VS OFFSET RINP (1) S/H CDS 5-BIT REG 8-BIT + SIGN DAC S/H PGA + + WM8146 VMID OFFSET (4) OEB GINP(28) S/H CDS S/H PGA + + M U X 12-bit ADC 8+4 MUX 5-BIT REG 8-BIT + SIGN DAC (13) OP[0] (14) OP[1] (15) OP[2] (16) OP[3] (17) OP[4] (18) OP[5] (19) OP[6] (20) OP[7] VMID OFFSET BINP(27) S/H CDS S/H PGA 5-BIT REG + + CONFIGURABLE SERIAL CONTROL INTERFACE (11) SDI (12) SCK (9) SEN 8-BIT + SIGN DAC VMID WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk Product Preview data sheets contain specifications for products in the formative phase of development. These products may be changed or discontinued without notice. 1999 Wolfson Microelectronics Ltd. WM8146 PIN CONFIGURATION RINP AGND2 DVDD1 OEB VSMP RLC MCLK DGND SEN DVDD2 SDI SCK OP[0] OP[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 GINP BINP VRLC VMID VRT VRB AGND1 AVDD OP[7] OP[6] OP[5] OP[4] OP[3] OP[2] Product Preview ORDERING INFORMATION DEVICE XWM8146CDW/V TEMP. RANGE 0 to 70 C o PACKAGE 28-pin SOIC WM8146 22 21 20 19 18 17 16 15 PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME RINP AGND2 DVDD1 OEB VSMP RLC MCLK DGND SEN DVDD2 SDI SCK OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7] AVDD AGND1 VRB VRT VMID VRLC BINP GINP TYPE Analogue input Supply Supply Digital input Digital input Digital input Digital input Supply Digital input Supply Digital input Digital input Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Supply Supply Analogue output Analogue output Analogue output Analogue output Analogue input Analogue input Analogue supply (5V). This must be operated at the same potential as DVDD1. Analogue ground (0V). Lower reference point of ADC reference string This pin must be connected to AGND via a decoupling capacitor. Upper reference point of ADC reference string This pin must be connected to AGND via a decoupling capacitor. Buffered mid-point of ADC reference string This pin must be connected to AGND via a decoupling capacitor. Selectable analogue output voltage for RLC. This pin must be connected to AGND via a decoupling capacitor. Blue channel input video. Green channel input video. OEB = 0: ADC output data is available in (8+4bit) multiplexed format on pins OP[7] to OP[0]. See Operational Timing diagrams for details. OEB = 1: Output is Hi=Z. DESCRIPTION Red channel input video. Analogue ground (0V). Digital supply (5V) for logic and clock generator. This must be operated at the same potential as AVDD. Output Hi-Z control, all digital outputs disabled when OEB = 1. Video sample synchronisation pulse. Selects reset level clamp on a pixel-by-pixel basis – active high. Tie high to use on every pixel. Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). Digital ground (0V). Enables the serial interface when high. Digital supply (5V/3.3V), all digital I/O pins. Serial interface data input. Serial interface clock. Digital multiplexed output data bus. WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 2 Product Preview WM8146 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount assembly. CONDITION Analogue supply voltage: AVDD Digital supply voltages: DVDD1 − 2 Digital ground: DGND Analogue grounds: AGND1 − 2 Digital inputs, digital outputs and digital I/O pins Analogue inputs (RINP, GINP, BINP) Other pins Operating temperature range: TA Storage temperature Lead temperature (soldering, 10 sec) Lead temperature (soldering, 2 mins) MIN GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V 0°C -65°C MAX GND + 7V GND + 7V GND + 0.3V GND + 0.3V DVDD2 + 0.3V AVDD + 0.3V AVDD + 0.3V +70°C +150°C +260°C +183°C Notes: 1. GND denotes the voltage of any ground pin. 2. AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. RECOMMENDED OPERATING CONDITIONS CONDITION Operating temperature range Analogue supply voltage Digital core supply voltage Digital I/O supply voltage 5V I/O 3.3V I/O SYMBOL TA AVDD DVDD1 DVDD2 DVDD2 MIN 0 4.75 4.75 4.75 2.97 5.0 5.0 5.0 3.3 TYP MAX 70 5.25 5.25 5.25 3.63 UNITS °C V V V V WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 3 WM8146 ELECTRICAL CHARACTERISTICS Product Preview Test Conditions AVDD = DVDD1 = DVDD2 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Overall System Specification (including 12-bit ADC, PGA, Offset and CDS functions) NO MISSING CODES GUARANTEED Full-scale transition error Zero-scale transition error Differential non-linearity References Upper reference voltage Lower reference voltage DAC reference voltage RLC switching impedance Reset level clamp options VRLC AVDD = 5V Voltage set by register configuration 1.46 2.46 3.46 250 x denotes the channel selected VRT VRB VMID AVDD = 5V AVDD = 5V AVDD = 5V 3.47 1.47 2.47 3.5 1.5 2.5 500 1.5 2.5 3.5 500 2 Gx ±25 ±25 DNL ±100 ±100 +1.5 3.53 1.53 2.53 1.54 2.54 3.54 750 mV mV LSB V V V Ω V V V Ω Vp-p % bits Impedance VRT to VRB Input Multiplexer CDS mode full scale input range (VVS-VRS) Channel to channel gain matching Offset DAC (monotonicity guaranteed) Resolution Zero code voltage Full scale voltage error Differential non-linearity Integral non-linearity Step size Output voltage DNL INL DACRNG=0 DACRNG=1 DACRNG=0 DACRNG=1 1 8 (+sign) VMID-20 0 0.1 0.25 4.9 7.4 +/-1.25 +/-1.875 5 GMAX GMIN 8.25 0.5 1 VMID+20 20 0.5 1 mV mV LSB LSB mV/step mV/step V V bits V/V V/V % Programmable Gain Amplifier (monotonicity guaranteed) Resolution Max gain, each channel Min gain, each channel Gain error, each channel DIGITAL SPECIFICATIONS Digital Inputs High level input voltage Low level input voltage High level input current Low level input current Input capacitance Digital Outputs High level output voltage Low level output voltage High impedance output current VOH VOL IOZ IOH = 1mA IOL = 1mA DVDD2 0.5 DGND + 0.5 1 V V µA VIH VIL IIH IIL CI 5 0.8 ∗ DVDD2 0.2 ∗ DVDD2 1 1 V V µA µA pF WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 4 Product Preview WM8146 Test Conditions AVDD = DVDD1 = DVDD2 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated. PARAMETER Supply Currents Total supply current − active Supply current − full power down mode 35 5 mA mA SYMBOL TEST CONDITIONS MIN TYP MAX UNIT INPUT VIDEO SAMPLING tPER MCLK tVSMPSU VSMP INPUT tVSU VIDEO tVH tRSU tRH tVSMPH tMCLKH tMCLKL Figure 1 Input Video Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated PARAMETER MCLK period MCLK high period MCLK low period VSMP set-up time VSMP hold time Video level set-up time Video level hold time Reset level set-up time Reset level hold time Notes: 1. 2. SYMBOL tPER tMCLKH tMCLKL tVSMPSU tVSMPH tVSU tVH tRSU tRH TEST CONDITIONS MIN 83.3 37.5 37.5 10 10 10 15 10 15 TYP MAX UNITS ns ns ns ns ns ns ns ns ns tVSU and tRSU denote the set-up time required after the input video signal has settled. Parameters are measured at 50% of the rising/falling edge. OUTPUT DATA TIMING MCLK tPD OP[7:0] Figure 2 Output Data Timing WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 5 WM8146 Product Preview OEB t PZE OP[7:0] Hi-Z t PEZ Hi-Z Figure 3 Output Data Enable Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated PARAMETER Output propagation delay Output enable time Output disable time SYMBOL tPD tPZE tPEZ TEST CONDITIONS IOH = 1mA, IOL = 1mA MIN TYP MAX 75 50 25 UNITS ns ns ns SERIAL INTERFACE tS P E R SCK tS S U SDI tS C E SEN tS E W tS E C tS H tS C K L tS C K H Figure 4 Serial Interface Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated PARAMETER SCK period SCK high SCK low SDI set-up time SDI hold time SCK to SEN set-up time SEN to SCK set-up time SEN pulse width SYMBOL tSPER tSCKH tSCKL tSSU tSH tSCE tSEC tSEW TEST CONDITIONS MIN 83.3 37.5 37.5 10 10 20 20 50 TYP MAX UNITS ns ns ns ns ns ns ns ns Note: Parameters are measured at 50% of the rising/falling edge. WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 6 Product Preview WM8146 DEVICE DESCRIPTION GENERAL OPERATION A block diagram of the device showing the signal path is presented on Page 1. The WM8146 samples the three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal with respect to the video reset level or the reference level VMID using three processing channels. Each processing channel consists of an input sampling block with optional reset level clamping (RLC) and correlated double sampling (CDS), a 5-bit programmable gain amplifier (PGA) and an 8bit (+sign) programmable offset DAC. For colour operation, the resulting analogue outputs from the three channels are multiplexed into a 12-bit ADC. For monochrome operation the resulting analogue output from the selected channel only is multiplexed into the ADC. The ADC then converts the analogue signal to a 12-bit digital word. The digital output from the ADC is presented on an 8-bit wide output bus, in 8+4-bit multiplexed format. Internal control registers determine the configuration of the device, including the gain and offset applied to each channel. These registers are programmable via the serial interface. RESET LEVEL CLAMPING (RLC) CONFIGURATION To ensure that the signal applied to the WM8146 lies within its input range, the CCD output signal is usually level shifted by a.c. coupling through a capacitor, CIN. The RLC circuit clamps the WM8146 side of this capacitor to a selected voltage during the CCD reset level. The RLC voltage VRLC, is selected by control bits RLC[1:0] in setup register 3. A typical input configuration demonstrating reset level clamping and CDS circuitry is shown in Figure 5. A clamp pulse, CL, is generated from MCLK and VSMP by the timing control block. When CL is active the voltage on the WM8146 side of CIN, at RINP, is forced to the RLC voltage VRLC by switch 1. When the CL pulse turns off, the voltage at RINP initially remains at VRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to RINP. Reset level clamping is compatible with both CDS and non-CDS operating modes, as selected by switch 2. RLC MCLK VSMP TIMING CONTROL CL RS VS FROM CONTROL INTERFACE C IN S/H + RINP 1 RLC 2 + S/H CDS INPUT SAMPLING BLOCK FOR RED CHANNEL TO PGA CDS VRLC VRLC VMID FROM CONTROL INTERFACE AGND Figure 5 Reset Level Clamping and CDS Circuitry WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 7 WM8146 TIMING Product Preview Figure 6 illustrates the use of the RLC pin, MCLK and VSMP to control the timing of the CL pulse for a typical CCD waveform. The CL pulse is applied during the reset period. The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0], as shown in Figure 7. The VRLC pin outputs the analogue RLC voltage selected via control set-up register 3 bits RLC[1:0]. MCLK VSMP RLC 1 X Programmable Delay X 0 X X 0 CL (CDSREF = 01) INPUT VIDEO RGB RGB RLC on this Pixel RGB No RLC on this Pixel Figure 6 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL CDS/NON-CDS PROCESSING For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel common mode noise. For CDS operation, the video level is processed with respect to the video reset level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must be set to 1 (default), this controls switch 2 (Figure 5) and causes the signal reference to come from the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 7 . For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed with respect to the reference voltage VMID. MCLK VSMP VS R S /CL (CDSREF = 00) R S /CL (CDSREF = 01) R S /CL (CDSREF = 10) R S /CL (CDSREF = 11) Figure 7 Reset Sample and Clamp Timing WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 8 Product Preview WM8146 The output from the CDS block is a differential signal, which is amplified by a 5-bit PGA then added to the output of an 8-bit (+sign) offset DAC to compensate for sensor d.c. offsets. The gain and offset for each channel are independently programmable by writing to control bits DAC[7:0] and PGA[4:0]. The following diagram shows the signal path through the device. OFFSET ADJUST AND PROGRAMMABLE GAIN INPUT SAMPLING BLOCK PGA BLOCK OFFSET DAC BLOCK ADC BLOCK OUTPUT INVERT BLOCK TO MULTIPLEXER FOR 8-BIT OUTPUT V1 V IN CDS = 1 V RESET CDS = 0 V MID V2 V3 ++ V 3 x ( 4096/V F S ) + 2 0 4 7 analog D1 di g ital D2 + - X D2 = D1 if INVOP = 0 D2 =4095-D1 if INVOP = 1 PGA gain A = 0.5+(PGA[4:0]*0.25) Offset DAC (1-2*DSIGN)*(DAC[7:0]/255)*(V MID /2 + V MID / 4 * D A C R N G ) V IN i s RINP or GINP or BINP V R E S E T i s V IN s ampled during reset clamp V MID i s AVDD/2 CDS, DAC[7:0], DSIGN, DACRNG, PGA[4:0] and INVOP are set by programming internal control registers. CDS=1 for CDS, 0 for non-CDS Figure 8 Signal Flow Diagram The following equations enable the user to calculate the settings required for the PGAs and offset DACs. INPUT SAMPLING AND REFERENCING If CDS=1, the previously sampled reset level, VRESET, is subtracted from the input video signal VIN (i.e. CDS operation). V1 = VIN - VRESET If CDS=0, the simultaneously sampled VMID is subtracted instead (i.e. non-CDS operation). V1 = VIN - VMID GAIN ADJUST The signal is then multiplied by the PGA gain, approximately 0.5 to 8.25 in 32 equal gain steps. V2 = V1 * G = V1 * (0.5+(PGA[4:0]*0.25)) OFFSET (BLACK-LEVEL) ADJUST The resultant signal is added to the Offset DAC output which has a range of VMID/2 (or 1.5*VMID/2 if the DACRNG bit is set). V3 = V2 + VDAC = V2 + [(1-2*DSIGN) * DAC_CODE/255 * (VMID/2 + VMID/4 * DACRNG)] ANALOGUE TO DIGITAL CONVERSION The analogue signal is then converted to a 12-bit unsigned number. This is equivalent to a multiplication by 4096/(VFS), where VFS = 2V . D1 == INT{ (V3/VFS) * 4096 } + 2047 At this stage, the input to the ADC should be between -1V and +1V, so D1[11:0] should lie between -2047 and +2048. If the input is over-range, it will be clipped to within the range (-2047,2048). 2047 is added to the ADC output, to give code 2047 for zero input signal to the ADC. This is equivalent to the +VMID shown in the block diagram on page 1. WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 9 WM8146 DIGITAL POLARITY ADJUST Product Preview The polarity of the digital output may be inverted by control bit INVOP. If INVOP=0, negative-going input video will give negative-going digital output. If INVOP=1, negative-going video will give positivegoing digital output. D2 = D1 D2 = 4095 – D1 … … (INVOP=0) (INVOP=1) DIGITAL CONTROL AND I/O FUNCTIONS OUTPUT DATA Data appears on the pins OP[7:0] and changes after every negative-going MCLK edge, as shown in Figure 9 . tP D MCLK OP[7:0] A B Figure 9 WM8146 Output Timing A = d11, d10, d9, d8, d7, d6, d5, d4 B = d3, d2, d1, d0, 0, CC[1], CC[0], OVRNG Where CC1/CC0: These bits show from which channel the current output was taken. 00 = RED, 01 = GREEN, 10 = BLUE. OVRNG: This bit indicates if the current output pixel has exceeded the maximum or minimum range during processing. 1 = out of range, 0 = within range. Pin OP[7] to OP[0] Pin OP[7] to OP[0] CONTROL INTERFACE The internal control registers are programmable via the serial digital control interface. REGISTER WRITE The serial interface involves three dedicated pins, SCK, SDI, SEN (refer to Figure 10). A six-bit address is clocked in through SDI MSB first followed by an eight-bit data word, also MSB first. Each bit is latched on the rising edge of SCK. Once the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register. Note all valid registers have address bit a4 equal to 0. SCK SDI a5 0 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 Address SEN Data Word Figure 10 Register Write Timing TIMING REQUIREMENTS To use this device a master clock (MCLK) of up to 12MHz and a per-pixel synchronisation clock (VSMP) of up to 6MHz are required. These clocks drive a timing control block, which produces WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 10 Product Preview WM8146 internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum sample rates for the various modes are shown in Table 1. POWER SUPPLY The WM8146 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface) supplies. OPERATING MODES Table 1 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE MAX SAMPLE RATE SENSOR INTERFACE DESCRIPTION TIMING REQUIREMENTS REGISTER CONTENTS WITH CONTROL BIT CDS=1 SetReg1: 03(hex) REGISTER CONTENTS WITH CONTROL BIT CDS=0 SetReg1: 01(hex) 1 Colour Pixel-by-Pixel Yes 2MSPS 2 Monochrome/ Colour Line-by-Line Yes 2MSPS The 3 input channels are sampled in parallel. The signal is then gain and offset adjusted before being multiplexed into a single data stream and converted by the ADC, giving an output data rate of 6MSPS max. As mode 1 except: Only one input channel at a time is continuously sampled. MCLK max = 12MHz MCLK:VSMP ratio is 6:1 MCLK max = 12MHz MCLK:VSMP ratio is 6:1 3 Fast Monochrome/ Colour Line-by-Line Maximum speed Monochrome/ Colour Line-by-Line Yes 4MSPS Identical to mode 2 MCLK max = 12MHz MCLK:VSMP ratio is 3:1 MCLK max = 12MHz MCLK:VSMP ratio is 2:1 4 No 6MSPS Identical to mode 2 SetReg1: 07(hex) SetReg3 bits 7:6 determine which input is to be sampled Identical to mode 2 plus SetReg3: bits 5:4 must be set to 0(hex) CDS not possible SetReg1: 05(hex) SetReg3 bits 7:6 determine which input is to be sampled Identical to mode 2 5 Slow Colour Pixel-by-Pixel Yes 1.5MSPS Identical to mode 1 6 Slow Monochrome/ Colour Line-by-Line Yes 1.5MSPS Identical to mode 2 MCLK max = 12MHz MCLK:VSMP ratio is 2n:1, n ≥ 4 MCLK max = 12MHz MCLK:VSMP ratio is 2n:1, n ≥ 4 Identical to mode 1 SetReg1: 45(hex) SetReg3 bits 7:6 determine which input is to be sampled Identical to mode 1 Identical to mode 2 Identical to mode 2 Table 1 WM8146 Operating Modes WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 11 WM8146 OPERATING MODE TIMING DIAGRAMS Product Preview The following diagrams output data, MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 1 . The diagrams are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown as R, G and B respectively. X denotes invalid data. 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB Figure 11 Mode 1 Operation 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] RA RB X X X X RA RB X X X X RA RB X X X X RA RB X X X X RA RB Figure 12 Mode 2 Operation 23.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB Figure 13 Mode 3 Operation WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 12 Product Preview WM8146 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB Figure 14 Mode 4 Operation 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB Figure 15 Mode 5 Operation (MCLK:VSMP Ratio = 8:1) 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0]) X X RA RB X X X X X X RA RB X X X X X X RA RB X X X X X X Figure 16 Mode 6 Operation (MCLK:VSMP Ratio = 8:1) WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 13 WM8146 DEVICE CONFIGURATION REGISTER MAP Product Preview Table 2 describes the location of each control bit used to determine the operation of the WM8146. The register map is programmed by writing the required codes to the appropriate addresses via the serial interface. Address 000001 000010 000011 000100 000101 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 Setup Register 1 Setup Register 2 Setup Register 3 Software Reset Setup Register 4 DAC Value (Red) DAC Value (Green) DAC Value (Blue) DAC Value (R+G+B) DAC Sign (Red) DAC Sign (Green) DAC Sign (Blue) DAC Sign (R+G+B) PGA Gain (Red) PGA Gain (Green) PGA Gain (Blue) PGA Gain (R+G+B) Description Def (hex) 03 00 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PGA[4] PGA[4] PGA[4] PGA[4] PGA[3] PGA[3] PGA[3] PGA[3] PGA[2] PGA[2] PGA[2] PGA[2] PGA[1] PGA[1] PGA[1] PGA[1] DAC[7] DAC[7] DAC[7] DAC[7] DAC[6] DAC[6] DAC[6] DAC[6] DAC[5] DAC[5] DAC[5] DAC[5] DAC[4] DAC[4] DAC[4] DAC[4] DAC[3] DAC[3] DAC[3] DAC[3] DAC[2] DAC[2] DAC[2] DAC[2] DACRNG DAC[1] DAC[1] DAC[1] DAC[1] DAC[0] DAC[0] DAC[0] DAC[0] DSIGN DSIGN DSIGN DSIGN PGA[0] PGA[0] PGA[0] PGA[0] CHAN[1] CHAN[0] CDSREF[1] CDSREF[0] b7 b6 VSMP6M b5 b4 BIT b3 b2 MONO INVOP RLC[1] RLC[0] b1 CDS b0 ENADC Table 2 Register Map WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 14 Product Preview WM8146 REGISTER MAP DESCRIPTION REGISTER Setup Register 1 BIT NO 0 1 2 6 Setup Register 2 Setup Register 3 2 BIT NAME(S) ENADC CDS MONO VSMP6M INVOP DEFAULT 1 1 0 0 0 DESCRIPTION ADC standby control : 0=standby, 1=active Select correlated double sampling mode: 0=single ended mode, 1=CDS mode Mono/colour select: 0=colour, 1=monchrome operation Required when VSMP at 6MSPS: 0=other mode, 1=VSMP at 6MSPS Digitally inverts the polarity of input data. 0= negative going video gives negative going output, 1=negative-going video gives positive going output data. Reset Level Clamp Voltage: 00 = 1.5V; 01 = 2.5V; 10 = 1.5V; 11 = Reserved CDS mode reset timing adjust 00 = advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods Monochrome mode channel select 00 = Red channel select 01 = Green channel select 10 = Blue channel select 11 = Reserved Write any value to the Software Reset register to cause all cells to be reset. 1 DACRNG 0 Offset DAC Output Range: 0 = DAC Output range =VMID/2 = +/-1.25V 1 = DAC output Range = 1.5*VMID/2 = +/-1.875V Polarity of Offset DAC output 0 = Positive Output (Offset added) 1 = Negative Output (Offset removed) 1:0 5:4 RLC[1:0] CDSREF[1:0] 01 01 7:6 CHAN[1:0] 00 Software Reset Setup Register 4 Registers 100100 to 100111 0 DSIGN 0 Table 3 Register Control Bits WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 15 WM8146 RECOMMENDED EXTERNAL COMPONENTS DVDD1 (5V) DVDD2 (3.3V or 5V) 3 10 AVDD (5V) 21 C5 C6 8 Product Preview C1 C2 C3 C4 DVDD1 DVDD2 DGND AVDD AGND1 AGND2 22 2 AGND AGND 1 28 27 VRT RINP VMID GINP VRB BINP 24 25 23 C7 C8 C9 C10 C11 C12 VIDEO INPUTS 26 C13 C14 VRLC AGND WM8146 AGND OP[7] 7 MCLK VSMP RLC OP[6] OP[5] OP[4] OP[3] 12 11 SCK SDI SEN OP[2] OP[1] OP[0] 20 19 18 17 16 15 14 13 TIMING SIGNALS 5 6 OUTPUT DATA BUS INTERFACE CONTROLS 9 4 OEB N O T E S : 1. C1-14 should be fitted as close to WM8146 as possible. 2. AGND and DGND should be connected as close to WM8146 as possible. Figure 17 External Components Diagram COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 SUGGESTED VALUE 100nF 10µF 100nF 10µF 100nF 10µF 100nF 10µF 100nF 22µF 100nF 10µF 100nF 10µF DESCRIPTION De-coupling for DVDD1. Reservoir capacitor for DVDD1. De-coupling for DVDD2. Reservoir capacitor for DVDD2 De-coupling for AVDD. Reservoir capacitor for AVDD De-coupling for VRB.. Reservoir capacitor for VRB. De-coupling for VMID Reservoir capacitor for VMID. De-coupling for VRT Reservoir capacitor for VRT De-coupling capacitor for VRLC Reservoir capacitor VRLC Table 4 External Components Descriptions WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 16 Product Preview WM8146 PACKAGE DIMENSIONS D: 28 PIN SOICW 7.5mm (0.3") Wide Body, 1.27mm Lead Pitch DM016.B e B 28 15 ZONE A E H L ZONE B h x 45 o 1 14 D α C A1 -CSEATING PLANE A 0.10 (0.004) Symbols A A1 B C D e E h H L α REF: Dimensions (mm) MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 17.70 18.10 1.27 BSC 7.40 7.60 0.25 0.75 10.00 10.65 0.40 1.27 o o 8 0 Dimensions (Inches) MIN MAX 0.0926 0.1043 0.0040 0.0118 0.0130 0.0200 0.0091 0.0125 0.6969 0.7125 0.0500 BSC 0.2914 0.2992 0.0100 0.0290 0.3940 0.4190 0.0160 0.0500 o o 0 8 JEDEC.95, MS-013 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-013, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. E. PIN ONE INDICATORS WILL BE LOCATED IN EITHER ZONE A OR ZONE B. WOLFSON MICROELECTRONICS LTD PP Rev 1.1 January 2000 17