WM8150CDS

WM8150 Single Channel 12-bit CIS/CCD AFE with 4-bit Wide Output DESCRIPTION The WM8150 is a 12-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 8MSPS. The device includes a complete analogue signal processing channel containing Reset Level Clamping, Correlated Double Sampling, Programmable Gain and Offset adjust functions. Internal multiplexers allow fast switching of offset and gain for line-by-line colour processing. The output from this channel is time multiplexed into a high-speed 12-bit Analogue to Digital Converter. The digital output data is available in 4-bit wide multiplexed format. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 5V, a digital core voltage of 5V, and a digital interface supply of either 5V or 3.3V, the WM8150 typically only consumes 160mW when operating from a single 5V supply. FEATURES • • • • • • • • • • • • • 12-bit ADC 8MSPS conversion rate Low power - 170mW typical 5V single supply or 5V/3.3V dual supply operation Single channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) Programmable clamp voltage 4-bit wide multiplexed data output format Internally generated voltage references 20-pin SSOP package Serial control interface APPLICATIONS • • • • Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals High-performance CCD sensor interface BLOCK DIAGRAM VSMP MCLK AVDD DVDD1 DVDD2 VRT VRX VRB CL RS VS TIMING CONTROL VREF/BIAS R M GU X B 8 OFFSET DAC + PGA 8 VINP RLC CDS + I/P SIGNAL POLARITY ADJUST 12BIT ADC DATA I/O PORT OP[0] OP[1] OP[2] OP[3]/SDO VRLC/VBIAS R G B M U X W WM8150 RLC DAC 4 CONFIGURABLE SERIAL CONTROL INTERFACE SEN SCK SDI AGND1 AGND2 DGND WOLFSON MICROELECTRONICS plc w :: www.wolfsonmicro.com Production Data, November 2002, Rev 3.0 Copyright 2002 Wolfson Microelectronics plc WM8150 PIN CONFIGURATION AGND2 DVDD1 VSMP MCLK DGND SEN DVDD2 SDI SCK OP[0] 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 VINP VRLC/VBIAS VRX VRT VRB AGND1 AVDD OP[3]/SDO OP[2] OP[1] Production Data ORDERING INFORMATION DEVICE WM8150CDS WM8150CDS/R Note: Reel quantity = 2,000 TEMP. RANGE 0 to 70oC 0 to 70oC PACKAGE 20-pin SSOP 20-pin SSOP (tape and reel) WM8150 15 14 13 12 11 PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 NAME AGND2 DVDD1 VSMP MCLK DGND SEN DVDD2 SDI SCK TYPE Supply Supply Digital input Digital input Supply Digital input Supply Digital input Digital input DESCRIPTION Analogue ground (0V). Digital core (logic and clock generator) supply (5V) Video sample synchronisation pulse. Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). Digital ground (0V). Enables the serial interface when high. Digital supply (5V/3.3V), all digital I/O pins. Serial data input. Serial clock. Digital multiplexed output data bus. ADC output data (d11:d0) is available in 4-bit multiplexed format as shown below. A 10 11 12 13 OP[0] OP[1] OP[2] OP[3]/SDO Digital output Digital output Digital output Digital output d8 d9 d10 d11 B d4 d5 d6 d7 C d0 d1 d2 d3 D OVRNG CC0 CC1 0 Alternatively, pin OP[3]/SDO may be used to output register read-back data when address bit 4=1 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. 14 15 16 17 18 19 AVDD AGND1 VRB VRT VRX VRLC/VBIAS Supply Supply Analogue output Analogue output Analogue output Analogue I/O Analogue supply (5V) Analogue ground (0V). Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. Video input. 20 VINP Analogue input w PD Rev 3.0 November 2002 2 Production Data WM8150 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. The WM8150 has been classified as MSL1, which has an unlimited floor life at 4095 D1[11:0] = 0 D1[11:0] = 4095 PGAFS[1:0] = 00 or 01 ...... PGAFS[1:0] = 11 ............... PGAFS[1:0] = 10 ............... Eqn. 6 Eqn. 7 Eqn. 8 OUTPUT INVERT BLOCK: POLARITY ADJUST The polarity of the digital output may be inverted by control bit INVOP. D2[11:0] = D1[11:0] D2[11:0] = 4095 – D1[11:0] (INVOP = 0) ...................... (INVOP = 1) ...................... Eqn. 9 Eqn. 10 w PD Rev 3.0 November 2002 12 Production Data WM8150 OUTPUT DATA FORMAT The digital data output from the ADC is available to the user in 4-bit wide multiplexed. Latency of valid output data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing Diagrams section. Figure 10 shows the output data formats for Mode 1 and 3 – 6. Figure 11 shows the output data formats for Mode 2. Table 2 summarises the output data obtained for each format. MCLK MCLK 4+4+4-BIT OUTPUT 4+4+4-BIT OUTPUT A B C D ABABC D Figure 10 Output Data Formats (Modes 1, 3, 4) OUTPUT FORMAT 4+4+4+4-bit (nibble) OUTPUT PINS OP[3:0] Figure 11 Output Data Formats (Mode 2) OUTPUT A = d11, d10, d9, d8 B = d7, d6, d5, d4 C = d3, d2, d1, d0 D = 0, CC[1], CC[0], OVRNG Table 2 Details of Output Data Shown in Figure 10 and Figure 11. FLAGS The OVRNG flag that is output during nibble D indicates that the current output data was produced by an input signal that exceeded the input range limit of the device. 1 = Out of range, 0 = within range. The CC[1:0] flags that are output during nibble D are used to indicate which set of offset and gain registers have been used for the current data. CC[1:0] = 00 indicates Red, CC[1:0] = 01 indicates Green and CC[1:0] = 10 indicates that the Blue offset and gain registers were applied during the processing. w PD Rev 3.0 November 2002 13 WM8150 CONTROL INTERFACE Production Data The internal control registers are programmable via the serial digital control interface. The register contents can be read back via the serial interface on pin OP[3]/SDO. It is recommended that a software reset is carried out after the power-up sequence, before writing to any other register. This ensures that all registers are set to their default values (as shown in Table 4). SERIAL INTERFACE: REGISTER WRITE Figure 12 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode. SCK SDI a5 0 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 Address SEN Data Word Figure 12 Serial Interface Register Write A software reset is carried out by writing to Address “000100” with any value of data, (i.e. Data Word = XXXXXXXX. SERIAL INTERFACE: REGISTER READ-BACK Figure 13 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge of SCK). Note that pin SDO is shared with an output pin, OP[3], so no data can be read when reading from a register. The next word may be read in to SDI while the previous word is still being output on SDO. SCK SDI a5 1 a3 a2 a1 a0 x x x x x x x x Address SEN Data Word SDO d7 d6 d5 d4 d3 d2 d1 d0 Output Data Word Figure 13 Serial Interface Register Read-back TIMING REQUIREMENTS To use this device a master clock (MCLK) of up to 16MHz and a per-pixel synchronisation clock (VSMP) of up to 8MHz are required. These clocks drive a timing control block, which produces internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum sample rates for the various modes are shown in Table 3. w PD Rev 3.0 November 2002 14 Production Data WM8150 PROGRAMMABLE VSMP DETECT CIRCUIT The VSMP input is used to determine the sampling point and frequency of the WM8150. Under normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal may not be readily available. The programmable VSMP detect circuit in the WM8150 allows the sampling point to be derived from any signal of the correct frequency, such as a CCD shift register clock, when applied to the VSMP pin. When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge (determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse. This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits. Figure 14 shows the internal VSMP pulses that can be generated by this circuit for a typical clock input signal. The internal VSMP pulse is then applied to the timing control block in place of the normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams. MCLK INPUT PINS VSMP POSNNEG = 1 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP POSNNEG = 0 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS Figure 14 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit w PD Rev 3.0 November 2002 15 WM8150 REFERENCES Production Data The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS when this is configured as an output. POWER SUPPLY The WM8150 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface) supplies. POWER MANAGEMENT Power management for the device is performed via the Control Interface. The device can be powered on or off completely by setting the EN bit low. All the internal registers maintain their previously programmed value in power down mode and the Control Interface inputs remain active. OPERATING MODES Table 3 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE Yes MAX SAMPLE RATE 2.67MSPS TIMING REQUIREMENTS MCLK max = 16MHz MCLK:VSMP ratio is 6:1 MCLK max = 16MHz MCLK:VSMP ratio is 3:1 MCLK max = 16MHz MCLK:VSMP ratio is 2:1 MCLK max = 16MHz MCLK:VSMP ratio is 2n:1, n ≥ 4 REGISTER CONTENTS WITH CDS SetReg1: 0F(hex) REGISTER CONTENTS WITHOUT CDS SetReg1: 0D(hex) 1 Monochrome/ Colour Line-by-Line Fast Monochrome/ Colour Line-by-Line 2 Yes 5.33MSPS Identical to Mode 1 plus SetReg3: bits 5:4 must be set to 0(hex) CDS not possible Identical to Mode 1 3 Maximum speed Monochrome/ Colour Line-by-Line Slow Monochrome/ Colour Line-by-Line No 8MSPS SetReg1: 4D(hex) 4 Yes 2MSPS Identical to Mode 1 Identical to Mode 1 Table 3 WM8150 Operating Modes w PD Rev 3.0 November 2002 16 Production Data WM8150 OPERATING MODE TIMING DIAGRAMS The following diagrams show 4-bit multiplexed output data and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 3. The diagrams are identical for both CDS and non-CDS operation. 16.5 MCLK PERIODS MCLK VSMP VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11) ABC ABC D ABC D ABC D ABC D ABCD D ABC D ABC D ABC D ABC D D ABC D ABC D ABC D ABC D D ABC D ABC D ABC D ABCD Figure 15 Mode 1 Operation 23.5 MCLK PERIODS MCLK VSMP VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11) CDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCD CDABABCDABABCDAB AB CDABABCDABABCDABABCDABABCDABABCDABABCDABAB CDABABCDABABCD CDABABCDA BABCDABABCDABABCDABABCDABABCDA BABCDABAB CDA BABCDAB AB CDABABCDABABCD CDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCD Figure 16 Mode 2 Operation w PD Rev 3.0 November 2002 17 WM8150 16.5 MCLK PERIODS Production Data MCLK VSMP VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11) ABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCD ABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCD ABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCD ABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCD Figure 17 Mode 3 Operation 16.5 MCLK PERIODS MCLK VSMP VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11) ABC D ABC D ABC D ABC D D ABC D ABC D ABC D D ABC D ABC D ABC D D ABC D ABC D ABCD Figure 18 Mode 4 Operation (MCLK:VSMP Ratio = 8:1) w PD Rev 3.0 November 2002 18 Production Data WM8150 DEVICE CONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8150. The register map is programmed by writing the required codes to the appropriate addresses via the serial interface. ADDRESS 000001 000010 000011 000100 000110 000111 001000 001001 001010 001011 001100 100000 100001 100010 100011 101000 101001 101010 101011 DESCRIPTION DEF (hex) RW b7 RW RW RW W RW R RW RW RW RW RW RW RW RW W RW RW RW W 0 0 0 TCLK 0 0 0 DACR[7] DACG[7] BIT b6 MODE3 DEL[0] 0 b5 PGAFS[1] RLCDACRNG CDSREF [1] b4 PGAFS[0] 0 CDSREF [0] b3 1 VRLCEXT RLCV[3] b2 1 INVOP RLCV[2] b1 CDS 1 RLCV[1] b0 EN 1 RLCV[0] Setup Reg 1 Setup Reg 2 Setup Reg 3 Software Reset Setup Reg 4 Revision Number Setup Reg 5 Test Reg 1 Reserved Reserved Reserved DAC Value (Red) DAC Value (Green) DAC Value (Blue) DAC Value (RGB) PGA Gain (Red) PGA Gain (Green) PGA Gain (Blue) PGA Gain (RGB) 0F 23 1F 00 05 41 00 00 00 00 00 80 80 80 80 00 00 00 00 0 DEL[1] 0 0 1 0 0 0 0 0 DACR[6] DACG[6] INTM[1] 0 0 0 0 0 0 DACR[5] DACG[5] DACB[5] DAC[5] PGAR[5] PGAG[5] PGAB[5] PGA[5] INTM[0] 0 POSNNEG 0 0 0 0 DACR[4] DACG[4] DACB[4] DAC[4] PGAR[4] PGAG[4] PGAB[4] PGA[4] RLCINT 0 VDEL[2] 0 0 0 0 DACR[3] DACG[3] DACB[3] DAC[3] PGAR[3] PGAG[3] PGAB[3] PGA[3] 1 0 VDEL[1] 0 0 0 0 DACR[2] DACG[2] DACB[2] DAC[2] PGAR[2] PGAG[2] PGAB[2] PGA[2] 0 0 VDEL[0] 0 0 0 0 DACR[1] DACG[1] DACB[1] DAC[1] PGAR[1] PGAG[1] PGAB[1] PGA[1] 1 1 VSMPDET 0 0 0 0 DACR[0] DACG[0] DACB[0] DAC[0] PGAR[0] PGAG[0] PGAB[0] PGA[0] DACB[7] DAC[7] PGAR[7] PGAG[7] DACB[6] DAC[6] PGAR[6] PGAG[6] PGAB[7] PGA[7] PGAB[6] PGA[6] Table 4 Register Map w PD Rev 3.0 November 2002 19 WM8150 REGISTER MAP DESCRIPTION Production Data The following table describes the function of each of the control bits shown in Table 4. REGISTER Setup Register 1 BIT NO 0 1 5:4 BIT NAME(S) EN CDS PGAFS[1:0] DEFAULT 1 1 00 DESCRIPTION 0 = complete power down, 1 = fully active. Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 00 = Zero output (use for bipolar video) 01 = Zero output 6 Setup Register 2 2 MODE3 INVOP 0 0 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video) Required when operating in MODE3: 0 = other modes, 1 = MODE3. Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data. When set powers down the RLCDAC, changing its output to Hi-Z, allowing VRLC/VBIAS to be externally driven. Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to VDD (approximately), 1 = RLCDAC ranges from 0 to VRT (approximately). Sets the output latency in ADC clock periods. 1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC clock period = 3 MCLK periods. 00 = Minimum latency 01 = Delay by one ADC clock period 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods 3 5 VRLCEXT RLCDACRNG 0 1 7:6 DEL[1:0] 00 Setup Register 3 3:0 RLCV[3:0] 1111 Controls RLCDAC driving VRLC pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. CDS mode reset timing adjust. 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods 5:4 CDSREF[1:0] 01 Software Reset Setup Register 4 3 5:4 RLCINT INTM[1:0] 0 00 Any write to Software Reset causes all cells to be reset. It is recommended that a software reset be performed after a power-up before any other register writes. This bit is used to determine whether Reset Level Clamping is enabled. 0 = RLC disabled, 1 = RLC enabled. Colour selection bits used in internal modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 1 for details. w PD Rev 3.0 November 2002 20 Production Data REGISTER Setup Register 5 BIT NO 0 BIT NAME(S) VSMPDET DEFAULT 0 DESCRIPTION WM8150 0 = Normal operation, signal on VSMP input pin is applied directly to Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 14, Internal VSMP Pulses Generated for details. When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 14 for further details. 0 = Normal Operation, OP[3:0] output ADC data. 1 = Internal Clock Test Mode. This allows internal timing signals to be multiplexed onto the OP[3:0] pins as follows. PIN OP[3] OP[2] OP[1] OP[0] TCLK=0 OP[3] OP[2] OP[1] OP[0] TCLK=1 INTVSMP Video sample clock ADC clock Reset sample clock 3:1 VDEL[2:0] 000 4 POSNNEG 0 Test Register 1 7 TCLK 0 Offset DAC (Red) Offset DAC (Green) Offset DAC (Blue) Offset DAC (RGB) PGA gain (Red) PGA gain (Green) PGA gain (Blue) PGA gain (RGB) 7:0 7:0 7:0 7:0 7:0 DACR[7:0] DACG[7:0] DACB[7:0] DAC[7:0] PGAR[7:0] 80 80 80 Red channel offset DAC value. Used under control of the INTM[1:0] control bits. Green channel offset DAC value. Used under control of the INTM[1:0] control bits. Blue channel offset DAC value. Used under control of the INTM[1:0] control bits. A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value 0 Determines the gain of the red channel PGA according to the equation: Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. Determines the gain of the green channel PGA according to the equation: Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. Determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. A write to this register location causes the red, green and blue PGA gain registers to be overwritten by the new value 7:0 PGAG[7:0] 0 7:0 PGAB[7:0] 0 7:0 PGA[7:0] Table 5 Register Control Bits w PD Rev 3.0 November 2002 21 WM8150 RECOMMENDED EXTERNAL COMPONENTS DVDD2 DVDD1 Production Data DVDD2 DVDD1 C1 C2 AVDD C3 DGND DGND AVDD DGND AGND1 AGND2 AGND AGND Video Input VINP VRT VRX VRB C6 C7 C8 C4 C5 WM8150 VRLC/VBIAS C9 AGND AGND DVDD2 MCLK DVDD1 + C11 AVDD + C12 Timing Signals VSMP + C10 OP[3]/SDO SCK OP[2] OP[1] OP[0] Interface Controls SDI SEN Output Data Bus DGND DGND AGND NOTES: 1. C1-9 should be fitted as close to WM8150 as possible. 2. AGND and DGND should be connected as close to WM8150 as possible. Figure 19 External Components Diagram COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 SUGGESTED VALUE 100nF 100nF 100nF 10nF 1µF 100nF 100nF 100nF 100nF 10µF 10µF 10µF DESCRIPTION De-coupling for DVDD2. De-coupling for DVDD1. De-coupling for AVDD. High frequency de-coupling between VRT and VRB. Low frequency de-coupling between VRT and VRB (non-polarised). De-coupling for VRB. De-coupling for VRX. De-coupling for VRT. De-coupling for VRLC. Reservoir capacitor for DVDD2. Reservoir capacitor for DVDD1. Reservoir capacitor for AVDD. Table 6 External Components Descriptions w PD Rev 3.0 November 2002 22 Production Data WM8150 PACKAGE DIMENSIONS DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm) DM0015.B b 20 e 11 E1 E 1 10 GAUGE PLANE Θ D A A2 A1 -C0.10 C SEATING PLANE c L L1 0.25 Symbols A A1 A2 b c D e E E1 L L1 θ REF: MIN ----0.05 1.65 0.22 0.09 6.90 7.40 5.00 0.55 0 o Dimensions (mm) NOM --------1.75 0.30 ----7.20 0.65 BSC 7.80 5.30 0.75 0.125 REF o 4 JEDEC.95, MO-150 MAX 2.0 ----1.85 0.38 0.25 7.50 8.20 5.60 0.95 8 o NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. w PD Rev 3.0 November 2002 23 WM8150 IMPORTANT NOTICE Production Data Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: Wolfson Microelectronics plc 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PD Rev 3.0 November 2002 24