WM8152SCDS

WM8152 Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output DESCRIPTION The WM8152 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 12MSPS. The device includes a complete analogue signal processing channel containing Reset Level Clamping, Correlated Double Sampling, Programmable Gain and Offset adjust functions. Internal multiplexers allow fast switching of offset and gain for line-by-line colour processing. The output from this channel is time multiplexed into a high-speed 16-bit Analogue to Digital Converter. The digital output data is available in 4-bit wide multiplexed format. An internal 4-bit DAC is supplied for internal reference level generation. This may be used to reference CIS signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 5V, a digital core voltage of 5V, and a digital interface supply of either 5V or 3.3V, the WM8152 typically only consumes 225mW when operating from a single 5V supply. FEATURES • • • • • • • • • • • • • 16-bit ADC 12MSPS conversion rate Low power - 225mW typical 5V single supply or 5V/3.3V dual supply operation Single channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) Programmable clamp voltage 4-bit wide multiplexed data output format Internally generated voltage references 20-pin SSOP package Serial control interface APPLICATIONS • • • • Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals High-performance CCD sensor interface BLOCK DIAGRAM VSMP MCLK AVDD DVDD1 DVDD2 VRT VRX VRB CL RS VS TIMING CONTROL VREF/BIAS R M GU X B 8 OFFSET DAC + PGA 8 VINP RLC CDS + I/P SIGNAL POLARITY ADJUST 16BIT ADC DATA I/O PORT OP[0] OP[1] OP[2] OP[3]/SDO VRLC/VBIAS R G B M U X W WM8152 RLC DAC 4 CONFIGURABLE SERIAL CONTROL INTERFACE SEN SCK SDI AGND1 AGND2 DGND WOLFSON MICROELECTRONICS plc w :: www.wolfsonmicro.com Production Data, January 2004, Rev 4.0 Copyright 2004 Wolfson Microelectronics plc WM8152 TABLE OF CONTENTS Production Data DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 INPUT VIDEO SAMPLING ............................................................................................. 8 OUTPUT DATA TIMING ................................................................................................ 8 SERIAL INTERFACE ..................................................................................................... 9 DEVICE DESCRIPTION.......................................................................................10 INTRODUCTION.......................................................................................................... 10 INPUT SAMPLING ....................................................................................................... 10 RESET LEVEL CLAMPING (RLC) ............................................................................... 10 CDS/NON-CDS PROCESSING ................................................................................... 11 OFFSET ADJUST AND PROGRAMMABLE GAIN....................................................... 12 ADC INPUT BLACK LEVEL ADJUST .......................................................................... 13 OVERALL SIGNAL FLOW SUMMARY ........................................................................ 13 CALCULATING OUTPUT FOR ANY GIVEN INPUT .................................................... 13 OUTPUT DATA FORMAT............................................................................................ 15 CONTROL INTERFACE .............................................................................................. 16 TIMING REQUIREMENTS ........................................................................................... 16 PROGRAMMABLE VSMP DETECT CIRCUIT ............................................................. 17 REFERENCES............................................................................................................. 18 POWER SUPPLY ........................................................................................................ 18 POWER MANAGEMENT ............................................................................................. 18 OPERATING MODES .................................................................................................. 18 OPERATING MODE TIMING DIAGRAMS ................................................................... 19 DEVICE CONFIGURATION .................................................................................21 REGISTER MAP .......................................................................................................... 21 REGISTER MAP DESCRIPTION ................................................................................. 22 APPLICATIONS INFORMATION .........................................................................24 RECOMMENDED EXTERNAL COMPONENTS........................................................... 24 RECOMMENDED EXTERNAL COMPONENTS VALUES............................................ 24 PACKAGE DIMENSIONS ....................................................................................25 IMPORTANT NOTICE ..........................................................................................26 ADDRESS:................................................................................................................... 26 w PD Rev 4.0 January 2004 2 Production Data WM8152 PIN CONFIGURATION AGND2 DVDD1 VSMP MCLK DGND SEN DVDD2 SDI SCK OP[0] 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 VINP VRLC/VBIAS VRX VRT VRB AGND1 AVDD OP[3]/SDO OP[2] OP[1] WM8152 15 14 13 12 11 ORDERING INFORMATION DEVICE W M8152CDS W M8152SCDS W M8152CDS/R W M8152SCDS/R Note: Reel quantity = 2,000 TEMP. RANGE 0 to 70oC 0 to 70oC 0 to 70oC 0 to 70oC PACKAGE 20-pin SSOP 20-pin SSOP (lead free) 20-pin SSOP (tape and reel) 20-pin SSOP (lead free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 MSL1 MSL1 MSL1 w PD Rev 4.0 January 2004 3 WM8152 PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 NAME AGND2 DVDD1 VSMP MCLK DGND SEN DVDD2 SDI SCK TYPE Supply Supply Digital input Digital input Supply Digital input Supply Digital input Digital input DESCRIPTION Analogue ground (0V). Digital core (logic and clock generator) supply (5V) Video sample synchronisation pulse. Production Data Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). Digital ground (0V). Enables the serial interface when high. Digital supply (5V/3.3V), all digital I/O pins. Serial data input. Serial clock. Digital multiplexed output data bus. ADC output data (d15:d0) is available in 4-bit multiplexed format as shown below. A B d8 d9 d10 d11 C d4 d5 d6 d7 D d0 d1 d2 d3 10 11 12 13 OP[0] OP[1] OP[2] OP[3]/SDO Digital output Digital output Digital output Digital output d12 d13 d14 d15 Alternatively, pin OP[3]/SDO may be used to output register read-back data when address bit 4=1 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. 14 15 16 17 18 19 AVDD AGND1 VRB VRT VRX VRLC/VBIAS Supply Supply Analogue output Analogue output Analogue output Analogue I/O Analogue supply (5V) Analogue ground (0V). Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. Video input. 20 VINP Analogue input w PD Rev 4.0 January 2004 4 Production Data WM8152 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at