WM8195

w DESCRIPTION The WM8195 is a 14-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 12MSPS. The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset Adjust functions. Three multiplexers allow single channel processing. The output from each of these channels is time multiplexed into a single high-speed 14-bit analogue-to-digital converter. The digital output data is available in 14-bit parallel or 8, 7 or 4-bit wide multiplexed format, with no missing codes. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Level Clamping to clamp CCD signals. Alternatively an external reference level may be applied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 5V and a digital interface supply of either 5V or 3.3V, the WM8195 typically only consumes 210mW when operating from a single 5V supply and less than 20µA when in power down mode. WM8195 14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser FEATURES • • • • • • • • • • • • • • 14-bit ADC No missing codes guaranteed 12MSPS conversion rate Low power – 210mW typical 5V single supply or 5V/3.3V dual supply operation Single or 3 channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) Programmable clamp voltage 14-bit parallel or 8, 7 or 4-bit wide multiplexed data output formats Internally generated voltage references 48-lead TQFP package Serial or parallel control interface APPLICATIONS • • • • Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals High-performance CCD sensor interface BLOCK DIAGRAM VRLC/VBIAS VSMP MCLK AVDD1-2 DVDD1-3 VRT VRX VRB w CL RS VS TIMING CONTROL R G B M U X 8 WM8195 VREF/BIAS OFFSET DAC + PGA 8 OEB + I/P SIGNAL POLARITY ADJUST M U X 14BIT ADC DATA I/O PORT OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7] OP[8] OP[9] OP[10] OP[11] OP[12] OP[13]/SDO RINP RLC M U X CDS R G B M U X GINP RLC CDS 8 + OFFSET DAC PGA 8 + I/P SIGNAL POLARITY ADJUST BINP RLC CDS 8 + OFFSET DAC PGA 8 + I/P SIGNAL POLARITY ADJUST CONFIGURABLE SERIAL/ PARALLEL CONTROL INTERFACE SEN/STB SCK/RNW SDI/DNA RLC/ACYC NRESET RLC DAC 4 AGND1-6 DGND1-5 WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Production Data July 2005 Rev 4.1 Copyright 2005 Wolfson Microelectronics plc. WM8195 TABLE OF CONTENTS Production Data DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATING CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7 INPUT VIDEO SAMPLING............................................................................................... 9 OUTPUT DATA TIMING .................................................................................................. 9 SERIAL INTERFACE ..................................................................................................... 11 PARALLEL INTERFACE......................................................................................12 INTRODUCTION ........................................................................................................... 13 INPUT SAMPLING......................................................................................................... 13 RESET LEVEL CLAMPING (RLC) ................................................................................. 13 CDS/NON-CDS PROCESSING ..................................................................................... 14 OFFSET ADJUST AND PROGRAMMABLE GAIN......................................................... 15 ADC INPUT BLACK LEVEL ADJUST ............................................................................ 16 OVERALL SIGNAL FLOW SUMMARY .......................................................................... 16 CALCULATING OUTPUT FOR ANY GIVEN INPUT ...................................................... 17 OUTPUT FORMATS...................................................................................................... 18 CONTROL INTERFACE ................................................................................................ 19 TIMING REQUIREMENTS............................................................................................. 20 PROGRAMMABLE VSMP DETECT CIRCUIT ............................................................... 21 REFERENCES............................................................................................................... 21 POWER SUPPLY .......................................................................................................... 22 POWER MANAGEMENT ............................................................................................... 22 LINE-BY-LINE OPERATION .......................................................................................... 22 OPERATING MODES .................................................................................................... 24 OPERATING MODE TIMING DIAGRAMS ..................................................................... 25 DEVICE CONFIGURATION .................................................................................27 REGISTER MAP ............................................................................................................ 27 REGISTER MAP DESCRIPTION................................................................................... 28 RECOMMENDED EXTERNAL COMPONENTS ..................................................31 PACKAGE DIMENSIONS ....................................................................................32 IMPORTANT NOTICE ..........................................................................................33 ADDRESS:..................................................................................................................... 33 w PD Rev 4.1 July 2005 2 Production Data WM8195 PIN CONFIGURATION OP[13]/SDO OP[12] OP[11] NRESET NC DGND5 VRB AGND6 AGND5 AVDD2 AVDD1 VRT VRX VRLC/VBIAS AGND1 BINP AGND2 GINP AGND3 RINP AGND4 DVDD1 OEB SEN/STB 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 DGND4 DVDD3 OP[10] OP[9] OP[8] OP[7] DGND3 OP[6] OP[5] OP[4] OP[3] DGND2 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VSMP RLC/ACYC SDI/DNA SCK/RNW MCLK DGND1 ORDERING INFORMATION DEVICE TEMPERATURE RANGE 0 to 70°C PACKAGE 48-lead TQFP 1mm thick body (Pb-free) 48-lead TQFP 1mm thick body (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL2 PEAK SOLDERING TEMPERATURE 260oC XWM8195SCFT/V XWM81955CFT/RV 0 to 70°C DVDD2 OP[0] OP[1] OP[2] NC NC MSL2 260oC Note: Reel quantity = 2,200 w PD Rev 4.1 July 2005 3 WM8195 PIN DESCRIPTION PIN 1 2 NAME VRX VRLC/VBIAS TYPE Analogue output Analogue I/O DESCRIPTION Input return bias voltage. This pin must be decoupled to AGND via a capacitor. Production Data Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be decoupled to AGND via a capacitor. VRLC can be externally driven if programmed Hi-Z. Analogue ground (0V). Blue channel input video. Analogue ground (0V). Green channel input video. Analogue ground (0V). Red channel input video. Analogue ground (0V). Digital supply (5V) for logic and clock generator. This must be operated at the same potential as AVDD. Output Hi-Z control, all digital outputs disabled when OEB = 1. Serial interface: enable pulse, active high Parallel interface: strobe, active low Latched on NRESET rising edge: if Low then device control is via serial interface, if high then device control is via parallel interface. 3 4 5 6 7 8 9 10 11 12 AGND1 BINP AGND2 GINP AGND3 RINP AGND4 DVDD1 OEB SEN/STB Supply Analogue input Supply Analogue input Supply Analogue input Supply Supply Digital input Digital input 13 14 SDI/DNA SCK/RNW Digital input Digital input Serial interface: serial input data signal Serial interface: serial clock signal Parallel interface: High = data, Low = address Parallel interface: High: OP[13:6] is output bus. Low: OP[13:6] is input bus (Hi-Z). ACYC autocycles between R, G, B inputs when in Line-by-Line mode. 15 16 VSMP RLC/ACYC Digital input Digital input Video sample synchronisation pulse. RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if used on every pixel. 17 18 19 20 21 22 23 MCLK DGND1 NC NC OP[0] OP[1] OP[2] Digital input Supply Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). Digital ground (0V). No connection. No connection. Digital output Digital output Digital output Pins OP[13:0] form a Hi-Z digital bi-directional bus. There are several modes: Hi-Z: when OEB = 1. 14-bit output: 14-bit data is output on OP[13:0]. 8-bit multiplexed output: data is output on OP[13:6] at 2 ∗ ADC conversion rate. 7-bit multiplexed output: data is output on OP[13:6] at 2 ∗ ADC conversion rate. 4-bit multiplexed output: data is output on OP[13:10] at 4 ∗ ADC conversion rate. See Output Formats section in Device Description for further details. Input 8-bit: control data is input on OP[13:6] in parallel mode when SCK/RNW = 0, and SEN/STB = 0. Output 8-bit: register read back data is output in parallel on OP[13:6] when SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1. Digital I/O supply (3.3V/5V). Digital ground (0V). See pins 21 to 23 for details. 24 25 26 27 28 29 30 DVDD2 DGND2 OP[3] OP[4] OP[5] OP[6] DGND3 Supply Supply Digital output Digital output Digital output Digital I/O Supply Digital ground (0V). w PD Rev 4.1 July 2005 4 Production Data PIN 31 32 33 34 35 36 37 38 39 NAME OP[7] OP[8] OP[9] OP[10] DVDD3 DGND4 OP[11] OP[12] OP[13]/SDO TYPE Digital I/O Digital I/O Digital I/O Digital I/O Supply Supply Digital I/O Digital I/O Digital I/O Digital I/O supply (3.3V/5V). Digital ground (0V). DESCRIPTION See pins 21 to 23 for details. WM8195 See pins 21 to 23 for details. If the device has been configured to use the serial interface, pin OP[13]/SDO may be used to output register read-back data when OEB = 0 and SEN has been pulsed high. See Serial Interface sections in Device Description for further details. Digital ground (0V). No connection. Reset input, active low. This signal forces a reset of all internal registers and selects whether the serial or parallel control interface is used. See pin SEN/STB. Analogue supply (5V). Analogue supply (5V). Analogue ground (0V). Analogue ground (0V). Lower reference voltage. This pin must be capacitively decoupled to AGND. Lower reference voltage. This pin must be capacitively decoupled to AGND. 40 41 42 43 44 45 46 47 48 DGND5 NC NRESET AVDD1 AVDD2 AGND5 AGND6 VRB VRT Supply Digital input Supply Supply Supply Supply Analogue output Analogue output w PD Rev 4.1 July 2005 5 WM8195 ABSOLUTE MAXIMUM RATINGS Production Data Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at