WM8196SCDS

w DESCRIPTION The WM8196 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 12MSPS. The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset adjust functions. Three multiplexers allow single channel processing. The output from each of these channels is time multiplexed into a single high-speed 16-bit Analogue to Digital Converter. The digital output data is available in 8 or 4-bit wide multiplexed format. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 5V and a digital interface supply of either 5V or 3.3V, the WM8196 typically only consumes 300mW when operating from a single 5V supply. WM8196 (8 + 8) Bit Output 16-bit CIS/CCD AFE/Digitiser FEATURES • • • • • • • • • • • • • 16-bit ADC 12MSPS conversion rate Low power – 320mW typical 5V single supply or 5V/3.3V dual supply operation Single or 3 channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) Programmable clamp voltage 8 or 4-bit wide multiplexed data output formats Internally generated voltage references 28-lead SSOP package Serial control interface APPLICATIONS • • • • Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals High-performance CCD sensor interface BLOCK DIAGRAM VRLC/VBIAS VSMP MCLK AVDD DVDD1 DVDD2 VRT VRX VRB w CL RS VS TIMING CONTROL R G B M U X 8 WM8196 VREF/BIAS OFFSET DAC + PGA 8 OEB + I/P SIGNAL POLARITY ADJUST M U X 16BIT ADC DATA I/O PORT OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7]/SDO RINP RLC M U X CDS R G B M U X GINP RLC CDS 8 + OFFSET DAC PGA 8 + I/P SIGNAL POLARITY ADJUST BINP RLC CDS 8 + OFFSET DAC PGA 8 + I/P SIGNAL POLARITY ADJUST RLC DAC 4 CONFIGURABLE SERIAL CONTROL INTERFACE SEN SCK SDI RLC/ACYC AGND1 AGND2 DGND WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Production Data, March 2007, Rev 4.3 Copyright ©2007 Wolfson Microelectronics plc WM8196 TABLE OF CONTENTS Production Data DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 THERMAL PERFORMANCE .................................................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 INPUT VIDEO SAMPLING ............................................................................................. 8 OUTPUT DATA TIMING ................................................................................................ 8 SERIAL INTERFACE ................................................................................................... 10 INTERNAL POWER ON RESET CIRCUIT ..........................................................11 DEVICE DESCRIPTION.......................................................................................13 INTRODUCTION.......................................................................................................... 13 INPUT SAMPLING ....................................................................................................... 13 RESET LEVEL CLAMPING (RLC) ............................................................................... 13 CDS/NON-CDS PROCESSING ................................................................................... 14 OFFSET ADJUST AND PROGRAMMABLE GAIN....................................................... 15 ADC INPUT BLACK LEVEL ADJUST .......................................................................... 16 OVERALL SIGNAL FLOW SUMMARY ........................................................................ 16 CALCULATING OUTPUT FOR ANY GIVEN INPUT .................................................... 16 OUTPUT FORMATS .................................................................................................... 17 CONTROL INTERFACE .............................................................................................. 18 TIMING REQUIREMENTS ........................................................................................... 19 PROGRAMMABLE VSMP DETECT CIRCUIT ............................................................. 19 REFERENCES............................................................................................................. 20 POWER SUPPLY ........................................................................................................ 20 POWER MANAGEMENT ............................................................................................. 20 LINE-BY-LINE OPERATION ........................................................................................ 21 OPERATING MODES .................................................................................................. 22 OPERATING MODE TIMING DIAGRAMS ................................................................... 23 DEVICE CONFIGURATION .................................................................................26 REGISTER MAP .......................................................................................................... 26 REGISTER MAP DESCRIPTION ................................................................................. 27 APPLICATIONS INFORMATION .........................................................................30 RECOMMENDED EXTERNAL COMPONENTS........................................................... 30 RECOMMENDED EXTERNAL COMPONENT VALUE ................................................ 30 PACKAGE DIMENSIONS ....................................................................................31 IMPORTANT NOTICE ..........................................................................................32 ADDRESS:................................................................................................................... 32 w PD Rev 4.3 March 2007 2 WM8196 PIN CONFIGURATION RINP AGND2 DVDD1 OEB VSMP RLC/ACYC MCLK DGND SEN DVDD2 SDI SCK OP[0] OP[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GINP BINP VRLC/VBIAS VRX VRT VRB AGND1 AVDD OP[7]/SDO OP[6] OP[5] OP[4] OP[3] OP[2] Production Data ORDERING INFORMATION DEVICE TEMPERATURE RANGE 0 to 70 C 0 to 70oC o PACKAGE 28-lead SSOP (Pb free) 28-lead SSOP (Pb free, tape and reel) MOISTURE SENSITIVITY LEVELS MSL1 PEAK SOLDERING TEMPERATURE 260 C 260oC o W M8196SCDS W M8196SCDS/R Note: Reel quantity = 2,000 MSL1 w PD Rev 4.3 March 2007 3 WM8196 PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 NAME RINP AGND2 DVDD1 OEB VSMP RLC/ACYC MCLK DGND SEN DVDD2 SDI SCK TYPE Analogue input Supply Supply Digital input Digital input Digital input Digital input Supply Digital input Supply Digital input Digital input DESCRIPTION Red channel input video. Analogue ground (0V). Production Data Digital supply (5V) for logic and clock generator. This must be operated at the same potential as AVDD. Output Hi-Z control, all digital outputs disabled when OEB = 1. Video sample synchronisation pulse. RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if used on every pixel. ACYC autocycles between R, G, B inputs. Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). Digital ground (0V). Enables the serial interface when high. Digital supply (5V/3.3V), all digital I/O pins. Serial data input. Serial clock. Digital multiplexed output data bus. ADC output data (d15:d0) is available in two multiplexed formats as shown, under the control of register MUXOP [1:0] See ‘Output Formats’ description in Device Description section for further details. 8+8-bit A B d0 d1 d2 d3 d4 d5 d6 d7 d12 d13 d14 d15 d8 d9 d10 d11 d4 d5 d6 d7 d0 d1 d2 d3 A B 4+4+4+4-bit C D 13 14 15 16 17 18 19 20 OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7]/SDO Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output d8 d9 d10 d11 d12 d13 d14 d15 Alternatively, pin OP[7]/SDO may be used to output register read-back data when OEB = 0 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. 21 22 23 24 25 26 AVDD AGND1 VRB VRT VRX VRLC/VBIAS Supply Supply Analogue output Analogue output Analogue output Analogue I/O Analogue supply (5V). This must be operated at the same potential as DVDD1. Analogue ground (0V). Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. Blue channel input video. Green channel input video. 27 28 BINP GINP Analogue input Analogue input w PD Rev 4.3 March 2007 4 WM8196 ABSOLUTE MAXIMUM RATINGS Production Data Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at