WM8214SCDS

w 40MSPS 16-bit CCD Digitiser DESCRIPTION The WM8214 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 40MSPS. The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset adjust functions. Three multiplexers allow single channel processing. The output from each of these channels is time multiplexed into a single high-speed 16-bit Analogue to Digital Converter. The digital output data is available in 8-bit wide multiplexed format and there is also an optional single byte output mode, or 4-bit multiplexed LEGACY mode. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 3.3V and a digital interface supply of 3.3V, the WM8214 typically only consumes 390mW. WM8214 FEATURES • • • • • • • • • • • • • • • • 16-bit ADC 40MSPS conversion rate Low power – 390mW typical 3.3V single supply operation Single, 2 or 3 channel operation Correlated double sampling Programmable gain (9-bit resolution) Programmable offset adjust (8-bit resolution) Flexible clamp control with programmable clamp voltage Flexible timing, can be made compatible with WM819X and WM815X parts. 8-bit wide multiplexed data output format 8-bit only output mode 4-bit LEGACY multiplexed nibble mode Internally generated voltage references 28-lead SSOP package, pin compatible with WM8199 Serial control interface APPLICATIONS • • • • High speed USB2.0 compatible scanners Multi-function peripherals High-performance CCD sensor interface Digital Copiers BLOCK DIAGRAM VRLC/VBIAS RSMP VSMP MCLK AVDD DVDD1 DVDD2 VRT VRX VRB w CLMP RS VS TIMING CONTROL R G B M U X 8 WM8214 VREF/BIAS OFFSET DAC + PGA 9 OEB + I/P SIGNAL POLARITY ADJUST M U X 16BIT ADC DATA O/P PORT OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7]/SDO RINP RLC CDS R G B M U X GINP RLC CDS 8 + OFFSET DAC PGA 9 + I/P SIGNAL POLARITY ADJUST BINP RLC CDS 8 + OFFSET DAC PGA 9 + I/P SIGNAL POLARITY ADJUST RLC DAC 4 CONFIGURABLE SERIAL CONTROL INTERFACE SEN SCK SDI AGND1 AGND2 DGND WOLFSON MICROELECTRONICS plc Production Data, March 2007, Rev 4.1 To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Copyright ©2007 Wolfson Microelectronics plc. WM8214 TABLE OF CONTENTS Production Data DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 THERMAL PERFORMANCE .................................................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 INPUT VIDEO SAMPLING ............................................................................................ 8 SERIAL INTERFACE................................................................................................... 10 INTERNAL POWER ON RESET CIRCUIT ..........................................................11 INTRODUCTION ......................................................................................................... 13 INPUT SAMPLING ...................................................................................................... 13 RESET LEVEL CLAMPING (RLC)............................................................................... 14 CDS/NON-CDS PROCESSING................................................................................... 16 OFFSET ADJUST AND PROGRAMMABLE GAIN ...................................................... 17 ADC INPUT BLACK LEVEL ADJUST.......................................................................... 18 OVERALL SIGNAL FLOW SUMMARY........................................................................ 19 CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT ..................................... 20 OUTPUT FORMATS ................................................................................................... 21 REFERENCES ............................................................................................................ 21 POWER MANAGEMENT ............................................................................................ 21 LINE-BY-LINE OPERATION ....................................................................................... 22 CONTROL INTERFACE.............................................................................................. 22 NORMAL OPERATING MODES ................................................................................. 24 LEGACY MODE INFORMATION................................................................................. 25 LEGACY OPERATING MODES .................................................................................. 26 LEGACY MODE TIMING DIAGRAMS ......................................................................... 27 DEVICE CONFIGURATION .................................................................................29 REGISTER MAP ......................................................................................................... 29 REGISTER MAP DESCRIPTION ................................................................................ 30 APPLICATIONS INFORMATION .........................................................................34 RECOMMENDED EXTERNAL COMPONENTS .......................................................... 34 RECOMMENDED EXTERNAL COMPONENT VALUES ............................................. 34 PACKAGE DIMENSIONS ....................................................................................35 IMPORTANT NOTICE ..........................................................................................36 ADDRESS: .................................................................................................................. 36 w PD Rev 4.1 March 2007 2 Production Data WM8214 PIN CONFIGURATION RINP AGND2 DVDD1 OEB VSMP RSMP MCLK DGND SEN DVDD2 SDI SCK OP[0] OP[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GINP BINP VRLC/VBIAS VRX VRT VRB AGND1 AVDD OP[7]/SDO OP[6] OP[5] OP[4] OP[3] OP[2] ORDERING INFORMATION DEVICE W M8214SCDS W M8214SCDS/R Note: Reel quantity = 2,000 TEMP. RANGE 0 to 70oC 0 to 70oC PACKAGE 28-lead SSOP (Pb-free) 28-lead SSOP (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 MSL1 PEAK SOLDERING TEMPERATURE 260oC 260oC w PD Rev 4.1 March 2007 3 WM8214 PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 NAME RINP AGND2 DVDD1 OEB VSMP RSMP MCLK DGND SEN DVDD2 SDI SCK TYPE Analogue input Supply Supply Digital input Digital input Digital input Digital input Supply Digital input Supply Digital input Digital input DESCRIPTION Red channel input video. Analogue ground reference. Production Data Digital supply for logic and clock generator. This must be operated at the same potential as AVDD. Output Hi-Z control, all digital outputs disabled when register bit OEB = 1 or register bit OPD = 1. Video sample timing pulse. Reset sample timing pulse (also used for RLC control). Master (ADC) clock. This determines the ADC conversion rate. Digital ground reference. Enables the serial interface when high. Digital supply, all digital I/O pins. Serial data input. Serial clock. Digital multiplexed output data bus. ADC output data (d15:d0) is available in multiplexed format as shown. See ‘Output Formats’ description in Device Description section for details of other output modes. A B d0 d1 d2 d3 d4 d5 d6 d7 13 14 15 16 17 18 19 20 OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7]/SDO Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output d8 d9 d10 d11 d12 d13 d14 d15 Alternatively, pin OP[7]/SDO may be used to output register read-back data when register bit OEB = 0, OPD = 0 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. 21 22 23 24 25 26 AVDD AGND1 VRB VRT VRX VRLC/VBIAS Supply Supply Analogue output Analogue output Analogue output Analogue I/O Analogue supply. This must be operated at the same potential as DVDD1. Analogue ground reference. Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. Blue channel input video. Green channel input video. 27 28 BINP GINP Analogue input Analogue input w PD Rev 4.1 March 2007 4 Production Data WM8214 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at Red… offset and gain registers applied to the red input channel. When auto-cycling is enabled, the RSMP pin cannot be used to control reset level clamping. The CLMPCTRL bit may be used instead (enabled when high, disabled when low). NB, when auto-cycling is enabled, the RSMP pin cannot be used for reset sampling (i.e. CDS must be set to 0). When LINEBYLINE=0 or ACYC=1 this bit has no effect. When LINEBYLINE=1 and ACYC=0: Controls the PGA/offset mux selector: 00 = Red PGA/Offset registers applied to input channel 01 = Green PGA/Offset registers applied to input channel 10 = Blue PGA/Offset registers applied to input channel 11 = Reserved. 1 ACYC 0 3:2 INTM[1:0] 00 7:4 Setup Register 5 0 1 2 3 Reserved REDPD GRNPD BLUPD ADCPD 0000 0 0 0 0 Must be set to 0 When set powers down red S/H, PGA When set powers down green S/H, PGA When set powers down blue S/H, PGA When set powers down ADC. Allows reduced power consumption without powering down the references which have a long time constant when switching on/off due to the external decoupling capacitors. When set powers down 4-bit RLCDAC, setting the output to a high impedance state and allowing an external reference to be driven in on the VRLC/VBIAS pin. When set disables VRT, VRB buffers to allow external references to be used. When set disables VRX buffer to allow an external reference to be used. Must be set to 0 When LEGACY=0 this register bit has no effect. When LEGACY=1: 0 = Normal operation, signal on VSMP input pin is applied directly to Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block in place of VSMP. When LEGACY=0 or VSMPDET=0 these bits have no effect. The VDEL bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 20, Internal VSMP Pulses Generated for details. 4 VRLCDACPD 0 5 6 7 Setup Register 6 0 ADCREFPD VRXPD Reserved VSMPDET 0 0 0 0 3:1 VDEL[2:0] 000 w PD Rev 4.1 March 2007 32 Production Data REGISTER BIT NO 4 BIT NAME(S) POSNNEG DEFAULT 0 DESCRIPTION WM8214 When LEGACY=0 or VSMPDET=0 this bit has no effect. When LEGACY=1 and VSMPDET=1 this bit controls whether positive or negative edges on the VSMP input pin are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 20 for further details. Reset Level Clamp Enable. When set Reset Level Clamping is enabled. The method of clamping is determined by CLAMPCTRL and LEGACY. In LEGACY mode clamping will still occur on every pixel at a time defined by the CDSREF[1:0] bits. This bit has no effect if LEGACY=1. See Table 2 for more information. 0 = RLC switch is controlled directly from RSMP input pin: RSMP = 0: switch is open RMSP = 1: switch is closed 1 = RLC switch is controlled by logical combination of RSMP and VSMP. RSMP && VSMP = 0: switch is open RSMP && VSMP = 1: switch is closed 5 RLCEN 1 6 CLAMPCTRL 0 7 Offset DAC (Red) Offset DAC (Green) Offset DAC (Blue) Offset DAC (RGB) PGA Gain LSB (Red) PGA Gain LSB (Green) PGA Gain LSB (Blue) PGA Gain LSB (RGB) PGA gain MSBs (Red) PGA gain MSBs (Green) PGA gain MSBs (Blue) PGA gain MSBs(RGB) 0 0 7:0 7:0 7:0 7:0 0 Reserved DACR[7:0] DACG[7:0] DACB[7:0] DACRGB[7:0] PGAR[0] 0 0 0 0 0 0 Must be set to 0 Red channel 8-bit offset DAC value (mV) = 260*(DACR[7:0]-127.5)/127.5 Green channel 8-bit offset DAC value (mV) = 260*(DACG[7:0]-127.5)/127.5 Blue channel 8-bit offset DAC value (mV) = 260*(DACB[7:0]-127.5)/127.5 A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value This register bit forms the LSB of the red channel PGA gain code. PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 28 hex. This register bit forms the LSB of the green channel PGA gain code. PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 29 hex. This register bit forms the LSB of the blue channel PGA gain code. PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 2A hex. 0 PGAG[0] 0 PGAB[0] 0 PGARGB[0] 0 Writing a value to this location causes red, green and blue PGA LSB gain values to be overwritten by the new value. 7:0 PGAR[8:1] 0D Bits 8 to 1 of red PGA gain. Combined with red LSB register bit to form complete PGA gain code. This determines the gain of the red channel PGA according to the equation: Red channel PGA gain (V/V) = 0.66 + PGAR[8:0]x7.34/511 Bits 8 to 1 of green PGA gain. Combined with green LSB register bit to form complete PGA gain code. This determines the gain of the green channel PGA according to the equation: Green channel PGA gain (V/V) = 0.66 + PGAG[8:0]x7.34/511 Bits 8 to 1 of blue PGA gain. Combined with blue LSB register bit to form complete PGA gain code. This determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain (V/V) = 0.66 + PGAB[8:0]x7.34/511 A write to this register location causes the red, green and blue PGA MSB gain registers to be overwritten by the new value. 7:0 PGAG[8:1] 0D 7:0 PGAB[8:1] 0D 7:0 PGARGB[8:1] 0 Table 8 Register Control Bits w PD Rev 4.1 March 2007 33 WM8214 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS DVDD1 DVDD2 3 10 C1 C2 AVDD 21 C3 DGND AGND 1 RINP GINP VRB BINP VRT VRX 24 25 23 C6 C7 C8 C4 C5 AVDD AGND1 AGND2 22 2 8 Production Data DVDD1 DVDD2 DGND AGND Video Inputs 28 27 26 C9 VRLC/VBIAS AGND WM8214 AGND 7 MCLK VSMP RSMP OP[7]/SDO OP[6] OP[5] OP[4] OP[3] 12 11 SCK SDI SEN OP[2] OP[1] OP[0] 5 6 20 DVDD1 DVDD2 19 18 17 16 15 14 13 + C10 + C11 AVDD + C12 Timing Signals Output Data Bus DGND AGND Interface Controls 9 4 OEB NOTES: 1. C1-9 should be fitted as close to WM8214 as possible. 2. AGND and DGND should be connected as close to WM8214 as possible. Figure 25 External Components Diagram RECOMMENDED EXTERNAL COMPONENT VALUES COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 SUGGESTED VALUE 100nF 100nF 100nF 10nF 1µF 100nF 100nF 100nF 100nF 10µF 10µF 10µF DESCRIPTION De-coupling for DVDD1. De-coupling for DVDD2. De-coupling for AVDD. High frequency de-coupling between VRT and VRB. Low frequency de-coupling between VRT and VRB (non-polarised). De-coupling for VRB. De-coupling for VRX. De-coupling for VRT. De-coupling for VRLC. Reservoir capacitor for DVDD1. Reservoir capacitor for DVDD2. Reservoir capacitor for AVDD. Table 9 External Components Descriptions w PD Rev 4.1 March 2007 34 Production Data WM8214 PACKAGE DIMENSIONS DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) DM007.E b 28 e 15 E1 E 1 D 14 GAUGE PLANE Θ c A A2 A1 L 0.25 L1 -C0.10 C SEATING PLANE Symbols A A1 A2 b c D e E E1 L L1 θ REF: MIN ----0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 0 o Dimensions (mm) NOM --------1.75 0.30 ----10.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 JEDEC.95, MO-150 MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95 8 o NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. w PD Rev 4.1 March 2007 35 WM8214 IMPORTANT NOTICE Production Data W olfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. 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Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: W olfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PD Rev 4.1 March 2007 36