WM8580_08

w DESCRIPTION The WM8580 is a multi-channel audio CODEC with S/PDIF transceiver. The WM8580 is ideal for DVD and surround sound processing applications for home hi-fi, automotive and other audiovisual equipment. Integrated into the device is a stereo 24-bit multi-bit sigma delta ADC with support for digital audio output word lengths from 16-bit to 32-bit, and sampling rates from 8kHz to 192kHz. Also included are three stereo 24-bit multi-bit sigma delta DACs, each with a dedicated oversampling digital interpolation filter. Digital audio input word lengths from 16bits to 32-bits and sampling rates from 8kHz to 192kHz are supported. Each DAC channel has independent digital volume and mute control. Two independent audio data interfaces support I2S, Left Justified, Right Justified and DSP digital audio formats. Each audio interface can operate in either Master Mode or Slave Mode. The S/PDIF transceiver is IEC-60958-3 compatible and supports frame rates from 32k/s to 96k/s. It has four multiplexed inputs and one output. Status and error monitoring is built-in and results can reported over the serial interface or via GPO pins. S/PDIF Channel Block configuration is also supported. The device has two PLLs that can be configured independently to generate two system clocks for internal or external use. Device control and setup is via a 2-wire or 3-wire (SPI compatible) serial interface. The serial interface provides access to all features including channel selection, volume controls, mutes, de-emphasis, S/PDIF control/status, and power management facilities. Alternatively, the device has a Hardware Control Mode where device features can be enabled/disabled using selected pins. The device is available in a 48-lead TQFP package. • • • • • • WM8580 Multichannel CODEC with S/PDIF Transceiver FEATURES • • • Multi-channel CODEC with 3 Stereo DACs and 1 Stereo ADC Integrated S/PDIF / IEC-60958-3 transceiver Audio Performance − − 103dB SNR (‘A’ weighted @ 48kHz) DAC -90dB THD (48kHz) DAC − 100dB SNR (‘A’ weighted @ 48kHz) ADC − -87dB THD (48kHz) ADC DAC Sampling Frequency: 8kHz – 192kHz ADC Sampling Frequency: 8kHz – 192kHz Independent ADC and DAC Sample Rates 2 and 3-Wire Serial Control Interface with readback, or Hardware Control Interface GPO pins allow visibility of user selected status flags Programmable Audio Data Interface Modes − I2S, Left, Right Justified or DSP − 16/20/24/32 bit Word Lengths Three Independent Stereo DAC Outputs with Digital Volume Controls Two Independent Master or Slave Audio Data Interfaces Flexible Digital Interface Routing with Clock Selection Control 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital Supply Operation 48-lead TQFP Package • • • • • APPLICATIONS • • • • Digital TV DVD Players and Receivers Surround Sound AV Processors and Hi-Fi systems Automotive Audio WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Production Data, February 2008, Rev 4.5 Copyright ©2008 Wolfson Microelectronics plc WM8580 BLOCK DIAGRAM Production Data w PD Rev 4.5 February 2008 2 Production Data WM8580 TABLE OF CONTENTS DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................2 TABLE OF CONTENTS .........................................................................................3 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 MULTI-FUNCTION PINS............................................................................................... 6 ABSOLUTE MAXIMUM RATINGS.........................................................................8 RECOMMENDED OPERATING CONDITIONS .....................................................9 ELECTRICAL CHARACTERISTICS ......................................................................9 TERMINOLOGY .......................................................................................................... 12 MASTER CLOCK TIMING ........................................................................................... 12 DIGITAL AUDIO INTERFACE – MASTER MODE ....................................................... 13 DIGITAL AUDIO INTERFACE – SLAVE MODE .......................................................... 14 CONTROL INTERFACE TIMING – 3-WIRE MODE .................................................... 15 CONTROL INTERFACE TIMING – 2-WIRE MODE .................................................... 16 DEVICE DESCRIPTION.......................................................................................17 INTRODUCTION ......................................................................................................... 17 CONTROL INTERFACE OPERATION ........................................................................ 18 DIGITAL AUDIO INTERFACES................................................................................... 22 AUDIO DATA FORMATS ............................................................................................ 24 AUDIO INTERFACE CONTROL.................................................................................. 28 DAC FEATURES......................................................................................................... 30 ADC FEATURES......................................................................................................... 39 DIGITAL ROUTING OPTIONS .................................................................................... 40 CLOCK SELECTION ................................................................................................... 42 PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (SOFTWARE MODE) ................ 53 PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (HARDWARE MODE) ............... 60 S/PDIF TRANSCEIVER............................................................................................... 60 POWERDOWN MODES ............................................................................................. 73 INTERNAL POWER ON RESET CIRCUIT.................................................................. 75 HARDWARE CONTROL MODE.................................................................................. 77 REGISTER MAP ......................................................................................................... 81 DIGITAL FILTER CHARACTERISTICS ...............................................................96 DAC FILTER RESPONSES......................................................................................... 97 DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................... 98 ADC FILTER RESPONSES......................................................................................... 98 ADC HIGH PASS FILTER ........................................................................................... 99 APPLICATIONS INFORMATION .......................................................................100 RECOMMENDED EXTERNAL COMPONENTS ........................................................ 100 PACKAGE DIMENSIONS ..................................................................................102 IMPORTANT NOTICE ........................................................................................103 ADDRESS: ................................................................................................................ 103 w PD Rev 4.5 February 2008 3 WM8580 PIN CONFIGURATION Production Data ORDERING INFORMATION DEVICE W M8580AGEFT/V W M8580AGEFT/RV Note: Reel quantity = 2,200 TEMPERATURE RANGE -40 to +85oC -40 to +85oC PACKAGE 48-lead TQFP (Pb-free) 48-lead TQFP (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 MSL1 PEAK SOLDERING TEMPERATURE 260°C 260°C w PD Rev 4.5 February 2008 4 Production Data WM8580 PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 NAME PGND PVDD XTI XTO MFP10 MFP9 MFP8 MFP7 MFP6 SPDIFOP MFP5 MFP4 MFP3 SPDIFIN1 CLKOUT DVDD DGND MUTE DIN1 DIN2 DIN3 PAIFRX_LRCLK PAIFRX_BCLK MCLK DOUT PAIFTX_LRCLK MFP1 MFP2 HWMODE SWMODE SDO SDIN SCLK CSB AINR AINL ADCREFP VMID AGND AVDD VOUT1L VOUT1R VOUT2L VOUT2R VREFP VREFN TYPE Supply Supply Digital Input Digital Output Digital Output Digital Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input Digital Output Supply Supply Digital Input/Output Digital Input Digital Input Digital Input Digital Input/Output Digital Input/Output Digital Input/Output Digital Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input Digital Input/Output Digital Output Digital Input/Output Digital Input Digital Input Analogue Input Analogue Input Analogue Output Analogue Output Supply Supply Analogue Output Analogue Output Analogue Output Analogue Output Analogue Input Analogue Input PLL ground PLL positive supply Crystal or CMOS clock input Crystal output Multi-Function Pin (MFP) 10. See Table 1 for details of all MFP pins. Multi-Function Pin (MFP) 9. See Table 1 for details of all MFP pins. Multi-Function Pin (MFP) 8. See Table 1 for details of all MFP pins. Multi-Function Pin (MFP) 7. See Table 1 for details of all MFP pins. Multi-Function Pin (MFP) 6. See Table 1 for details of all MFP pins. S/PDIF transmitter output. Multi-Function Pin (MFP) 5. See Table 1 for details of all MFP pins. Multi-Function Pin (MFP) 4. See Table 1 for details of all MFP pins. Multi-Function Pin (MFP) 3. See Table 1 for details of all MFP pins. S/PDIF receiver input 1 PLL or crystal oscillator clock output Digital positive supply Digital ground DAC mute-all Input / All-DAC Infinite Zero Detect (IZD) flag output Primary Audio Interface (PAIF) receiver data input 1 Primary Audio Interface (PAIF) receiver data input 2 Primary Audio Interface (PAIF) receiver data input 3 Primary Audio Interface (PAIF) receiver left/right word clock Primary Audio Interface (PAIF) receiver bit clock System Master clock; 256, 384, 512, 768, 1024 or 1152 fs Primary Audio Interface (PAIF) transmitter data output Primary audio interface transmitter left/right word clock Multi-Function Pin (MFP) 1. See Table 1 for details of all MFP pins. Multi-Function Pin (MFP) 2. See Table 1 for details of all MFP pins. Configures control to be either Software Mode or Hardware Mode Configures software interface to be either 2-wire or 3-wire. See note 2. 3-wire control interface data output. See note 3. Control interface data input (and output under 2-wire control) Control interface clock 3-wire control interface latch signal / device address selection ADC Right Channel Input ADC Left Channel Input ADC reference buffer decoupling pin; 10uF external decoupling Midrail divider decoupling pin; 10uF external decoupling Analogue ground Analogue positive supply DAC channel 1 left output DAC channel 1 right output DAC channel 2 left output DAC channel 2 right output DAC and ADC positive reference DAC and ADC ground reference DESCRIPTION w PD Rev 4.5 February 2008 5 WM8580 PIN 47 48 Notes : 1. 2. 3. Digital input pins have Schmitt trigger input buffers. Pins 32, 33, 34 are 5V tolerant. In hardware control mode, pin 30 is used for UNLOCK flag output. In hardware control mode, pin 31 is used for NON_AUDIO flag output. NAME VOUT3L VOUT3R TYPE Analogue Output Analogue Output DAC channel 3 left output DAC channel 3 right output DESCRIPTION Production Data MULTI-FUNCTION PINS The WM8580 has 8 Multi-Function Input/Output pins (MFP1 etc.). The function and direction (input/output) of these pins are configured using the HWMODE input pin and software register control as shown below. If HWMODE is set, the MFPs have the function shown in column 1 of Table 1. If HWMODE is not set, and the register SAIF_EN is set, the MFPs have the function shown in column 2. Otherwise, the GPOnOP registers determine the MFP function as shown in columns 3 and 4. Y HWMODE = 1 N Y SAIF_EN = 1 N GPIOnOP PIN NAME HARDWARE CONTROL MODE FUNCTION 1 PAIFTX_BCLK ADCMCLK DR1 DR2 DR3 DR4 ALLPD C SFRM_CLK 192BLK SECONDARY AUDIO INTERFACE FUNCTION 2 n/a1 n/a 1 S/PDIF INPUT & INDEPENDENT CLOCKING 3 PAIFTX_BCLK2 ADCMCLK3 SPDIFIN2 SPDIFIN3 SPDIFIN4 GPO6 GPO7 GPO8 GPO9 GPO10 GENERAL PURPOSE OUTPUT FUNCTION 4 GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 GPO8 GPO9 GPO10 MFP1 MFP2 MFP3 MFP4 MFP5 MFP6 MFP7 MFP8 MFP9 MFP10 n/a1 n/a 1 n/a1 SAIF_BCLK SAIF_LRCLK SAIF_DIN SAIF_DOUT n/a1 Table 1 Multi-Function Pin Configuration Notes: 1. 2. These pins are not used as part of the Secondary Audio Interface, so their function is that of either Column 3 or Column 4. MFP1 usage can be described as follows: IF (ADC_CLKSEL = MCLK) AND (PAIFTXMS_CLKSEL = MCLK) THEN MFP1 = GPO1; ELSE MFP1 = PAIFTX_BCLK ; (default) w PD Rev 4.5 February 2008 6 Production Data Notes for MFP1: ADC_CLKSEL selected in REG 8, default is ADC_MCLK. WM8580 PAIFTXMS_CLKSEL selects PLLACLK if PAIF sources SPDIF Rx, otherwise PAIFTXMS_CLKSEL selects ADC_CLK (register 8) 3. MFP2 usage can be described as follows: IF AND AND ELSE MFP2 = ADCMCLK; PIN FUNCTION PAIFTX_BCLK ADCMCLK SAIF_DIN SAIF_DOUT SAIF_BCLK SAIF_LRCLK SPDIFIN2/3/4 GPO1 – GPO10 DR1/2/3/4 ALLPD C SFRM_CLK TYPE Digital Input/Output Digital Input Digital Input Digital Output Digital Input/Output Digital Input/Output Digital Input Digital Output Digital Input Digital Input Digital Output Digital Output DESCRIPTION Primary Audio Interface Transmitter (PAIFTX) Bit Clock Master ADC clock; 256fs, 384fs, 512fs ,786fs, 1024fs or 1152fs Secondary Audio Interface (SAIF) Receiver data input Secondary Audio Interface (SAIF) Transmitter data output Secondary Audio Interface (SAIF) Bit Clock Secondary Audio Interface (SAIF) Left/Right Word Clock S/PDIF Receiver Input General Purpose Output Internal Digital Routing Configuration in Hardware Mode Chip Powerdown in Hardware Mode Recovered channel-bit for current S/PDIF sub-frame Indicates current S/PDIF sub-frame: 1 = Sub-frame A 0 = Sub-frame B Indicates start of S/PDIF 192-frame block. High for duration of frame 0. (ADC_CLKSEL ≠ ADCMCLK) (TX_CLKSEL ≠ ADCMCLK) (SAIFMS_CLKSEL ≠ ADCMCLK) THEN (controlled by reg 8) (controlled by reg 8) (controlled by reg 8) MFP2 = GPO2; 192BLK Digital Output Table 2 Multi-Function Pin Description w PD Rev 4.5 February 2008 7 WM8580 ABSOLUTE MAXIMUM RATINGS Production Data Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. The WM8580 has been classified as MSL1, which has an unlimited floor life at 0.555fs 0.555fs -60 dB f > 0.5465fs DAC Filter ±0.05 dB -3dB 0.487fs ±0.05 dB 0.444fs 0.5465fs -65 dB TEST CONDITIONS ADC Filter ±0.01 dB -6dB 0 0.5fs ±0.01 dB 0.4535fs MIN TYP MAX UNIT w PD Rev 4.5 February 2008 96 Production Data WM8580 0.2 DAC FILTER RESPONSES 0 0.15 -20 0.1 Response (dB) Response (dB) -40 0.05 0 -0.05 -0.1 -60 -80 -100 -0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 -120 Figure 43 DAC Digital Filter Frequency Response – 44.1, 48 and 96kHz Figure 44 DAC Digital Filter Ripple –44.1, 48 and 96kHz 0.2 0 0 -20 -0.2 Response (dB) Response (dB) -40 -0.4 -60 -0.6 -0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 45 DAC Digital Filter Frequency Response – 192kHz Figure 46 DAC Digital Filter Ripple – 192kHz w PD Rev 4.5 February 2008 97 WM8580 DIGITAL DE-EMPHASIS CHARACTERISTICS Production Data 0 0.4 0.3 -2 0.2 Response (dB) Response (dB) -4 0.1 0 -0.1 -0.2 -6 -8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20 Figure 47 De-Emphasis Frequency Response (44.1kHz) 0 Figure 48 De-Emphasis Error (44.1kHz) 1 0.8 -2 0.6 0.4 Response (dB) -4 Response (dB) 0.2 0 -0.2 -0.4 -6 -8 -0.6 -0.8 -10 0 5 10 15 Frequency (kHz) 20 -1 0 5 10 15 Frequency (kHz) 20 Figure 49 De-Emphasis Frequency Response (48kHz) Figure 50 De-Emphasis Error (48kHz) ADC FILTER RESPONSES 0.02 0 0.015 0.01 -20 Response (dB) -40 Response (dB) 0.005 0 -0.005 -0.01 -0.015 -0.02 -60 -80 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 51 ADC Digital Filter Frequency Response Figure 52 ADC Digital Filter Ripple PD Rev 4.5 February 2008 98 w Production Data WM8580 ADC HIGH PASS FILTER The WM8580 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial. H(z) = 1 - z-1 1 - 0.9995z-1 0 Response (dB) -5 -10 -15 0 0.0005 0.001 Frequency (Fs) 0.0015 0.002 Figure 53 ADC Highpass Filter Response w PD Rev 4.5 February 2008 99 WM8580 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Production Data Figure 54 Recommended External Components w PD Rev 4.5 February 2008 100 Production Data WM8580 Figure 55 Recommended External Components w PD Rev 4.5 February 2008 101 WM8580 PACKAGE DIMENSIONS FT: 48 PIN TQFP (7 x 7 x 1.0 mm) DM004.C Production Data b e 25 36 37 24 E1 E 48 1 12 13 Θ c D1 D L A A2 A1 -Cccc C SEATING PLANE Symbols A A1 A2 b c D D1 E E1 e L Θ ccc REF: Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 3.5 7 0 Tolerances of Form and Position 0.08 JEDEC.95, MS-026 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. w PD Rev 4.5 February 2008 102 Production Data WM8580 IMPORTANT NOTICE W olfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. 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Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: W olfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PD Rev 4.5 February 2008 103