WM8716EDS

WM8716 High Performance 24-bit, 192kHz Stereo DAC Production Data, April 2001, Rev 3.1 DESCRIPTION The WM8716 is a high performance stereo DAC designed for audio applications such as CD, DVD, home theatre systems, set top boxes and digital TV. The WM8716 supports data input word lengths from 16 to 24-bits and sampling rates up to 192kHz. The WM8716 consists of a serial interface port, digital interpolation filter, multi-bit sigma delta modulator and stereo DAC in a small 28-pin SSOP package. The WM8716 also includes a digitally controllable mute and attenuator function on each channel. The internal digital filter has two selectable roll-off characteristics. A sharp or slow roll-off can be selected dependent on application requirements. Additionally, the internal digital filter can be by-passed and the WM8716 used with an external digital filter. The WM8716 supports two connection schemes for audio DAC control. The SPI-compatible serial control port provides access to a wide range of features including onchip mute, attenuation and phase reversal. A hardware controllable interface is also available. FEATURES • • • • • • • 112dB SNR (‘A’ weighted @ 48kHz), THD: -97dB @ -1dB FS Sampling frequency: 8kHz to 192kHz Selectable digital filter roll-off Optional interface to industry standard external filters Differential mono mode Input data word: 16 to 24-bit Hardware or SPI compatible serial port control modes: − Hardware mode: mute, de-emphasis, audio format control − Serial mode: mute, de-emphasis, attenuation (256 steps), phase reversal Compatible upgrade to PCM1716 • APPLICATIONS • • • • CD, DVD audio Home theatre systems Set top boxes Digital TV BLOCK DIAGRAM MODE ML/I2S MC/DM1 MD/DM0 DIFFHW MUTEB CSBIWO RSTB ZERO MODE8X AGNDR AVDDR (24) (28) (27) (26) (17) (25) (23) (22) (21) (12) (10) (9) WM8716 CONTROL INTERFACE (11) VMIDR BCKIN (3) LRCIN (1) DIN (2) SERIAL INTERFACE MUTE/ ATTEN DIGITAL FILTERS MUX SIGMA DELTA MODULATOR RIGHT DAC LOW PASS FILTER (13) VOUTR MUX MUTE/ ATTEN SIGMA DELTA MODULATOR LEFT DAC LOW PASS FILTER (16) VOUTL (18) VMIDL CRYSTAL/OSC (4) (5) CLKO XTI (6) XTO (15) (8) AVDD DVDD (20) (19) (14) AVDDL. AGNDL AGND (7) DGND WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk www.wolfsonmicro.com Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ Terms and Conditions. 2001 Wolfson Microelectronics Ltd. WM8716 PIN CONFIGURATION LRCIN DIN BCKIN CLKO XTI XTO DGND DVDD AVDDR AGNDR VMIDR MODE8X VOUTR AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ML/I2S MC/DM1 MD/DM0 MUTEB MODE CSBIWO RSTB ZERO AVDDL AGNDL VMIDL DIFFHW VOUTL AVDD Production Data ORDERING INFORMATION DEVICE WM8716EDS TEMP. RANGE -25 to +85°C PACKAGE 28-pin SSOP ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION Supply voltage Reference input Operating temperature range, TA Storage temperature Package body temperature (soldering, 10 seconds) Package body temperature (soldering, 2 minutes) -25°C -65°C MIN -0.3V MAX +7.0V VDD + 0.3V +85°C +150°C +240°C +183°C RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range Analogue supply range Ground Difference DGND to AGND Analogue supply current Digital supply current Analogue supply current Digital supply current AVDD = 5V DVDD = 5V AVDD = 3.3V DVDD = 3.3V SYMBOL DVDD AVDD AGND, DGND -0.3 TEST CONDITIONS MIN -10% -10% TYP 3.3 to 5 3.3 to 5 0 0 26 22 25 13 +0.3 40 35 MAX +10% +10% UNIT V V V V mA mA mA mA WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 2 Production Data WM8716 ELECTRICAL CHARACTERISTICS TEST CONDITIONS AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER DAC Circuit Specifications SNR (See Notes 1 and 2) THD (full-scale) (See Note 2) Dynamic range (See Note 2) Filter Characteristics (Sharp Roll-off) Passband Stopband Passband ripple Stopband Attenuation Delay time Filter Characteristics (Slow Roll-off) Passband Stopband Passband ripple Stopband Attenuation Delay time Internal Analogue Filter Bandwidth Passband edge response Digital Logic Levels Input LOW level Input HIGH level (See Note 3) Output LOW level Output HIGH level Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth. All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. Except for Pin 12 (MODE8X) and Pin 17 (DIFFHW), where VIH = 2.6V min. VIL VIH VOL VOH IOL = 2mA IOH = 2mA AVDD - 0.3V 2.0 AVSS + 0.3V 0.8 V V -3dB 20kHz 195 -0.043 kHz dB f > 0.732fs -82 9/fs ±0.001dB -3dB 0.274fs 0.459fs ±0.001 dB dB s f > 0.5465fs -82 30/fs ±0.0012 dB -3dB 0.4535fs 0.491fs ±0.0012 dB dB s dB 0dB FS -1dB FS THD @ -60dB FS 105 105 112 -92 -97 112 dB dB dB dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 3. TERMINOLOGY 1. 2. Signal-to-noise ratio (dB) (SNR) is a measure of the difference in level between the full-scale output and the output with no signal applied. Dynamic range (dB) (DNR) is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (eg THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) is a ratio of the r.m.s. values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) (also known as Cross-Talk) is a measure of the amount one channel is isolated from the other. Normally measured by sending a full-scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region. 3. 4. 5. 6. WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 3 WM8716 TEST CONDITIONS AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER Analogue Output Levels Output level Into 10kohm, full scale 0dB, (5V supply) Into 10kohm, full scale 0dB, (3.3V supply) To midrail or AC coupled (5V supply) To midrail or AC coupled (3.3V supply) 5V or 3.3V 1.1 0.72 1 600 100 AVDD/2 0.5 2 SYMBOL TEST CONDITIONS MIN TYP Production Data MAX UNIT VRMS VRMS kohms ohms pF V %FSR Minimum resistance load Maximum capacitance load Output DC level Gain mismatch channel to channel Reference Levels Potential divider resistance Voltage at VMIDL/VMIDR POR POR threshold AVDD to VMIDL/VMIDR and VMIDL/VMIDR to AGND 10 AVSS/2 2.5V kohms V LRCIN tBCH BCKIN tBCY DIN tDS tDH tBL tBCL tLB Figure 1 Audio Data Input Timing TEST CONDITIONS AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER BCKIN pulse cycle time BCKIN pulse width high BCKIN pulse width low BCKIN rising edge to LRCIN edge LRCIN rising edge to BCKIN rising edge DIN setup time DIN hold time SYMBOL tBCY tBCH tBCL tBL tLB tDS tDH TEST CONDITIONS MIN 100 50 50 30 30 30 30 TYP MAX UNIT ns ns ns ns ns ns ns Audio Data Input Timing Information WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 4 Production Data tSCKIL SCKI tSCKIH WM8716 Figure 2 System Clock Timing Requirements TEST CONDITIONS AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER System Clock Timing Information SCKI System clock pulse width high SCKI System clock pulse width low tSCKIH tSCKIL 13 13 ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT tMLL ML/I2S (PIN 28) tMCY tMCH tMCL tMHH tMLH tMLS MC/DM1 (PIN 27) tMDS MD/DM0 (PIN 26) tCSML CSBIWO (PIN 23) tMDH LSB tMLCS Figure 3 Program Register Input Timing TEST CONDITIONS AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER Program Register Input Information MC/DM1 Pulse cycle time MC/DM1 Pulse width LOW MC/DM1 Pulse width HIGH MD/DM0 Hold time MD/DM0 Set-up time ML/I2S Low level time (See Note 3) ML/I2S High level time (See Note 3) ML/I2S Hold time ML/I2S Set-up time CSBIWO Low to ML/I2S low time ML/I2S High to CSBIWO high time Note: 3. System clock cycle. PD Rev 3.1 April 2001 SYMBOL tMCY tMCL tMCH tMDH tMDS tMLL tMHH tMLH tMLS tCSML tMLCS TEST CONDITIONS MIN 100 40 40 40 40 40 + 1SYSCLK 40 + 1SYSCLK 40 40 10 10 TYP MAX UNIT ns ns ns ns ns ns ns ns ns ns ns WOLFSON MICROELECTRONICS LTD 5 WM8716 PIN DESCRIPTION PIN NAME TYPE DESCRIPTION Hardware Mode Normal Mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 LRCIN DIN BCKIN CLKO XTI XTO DGND DVDD AVDDR AGNDR VMIDR MODE8X VOUTR AGND AVDD VOUTL DIFFHW VMIDL AGNDL AVDDL ZERO RSTB CSBIWO Digital input Digital input Digital input Digital output Analogue input Analogue output Supply Supply Supply Supply Analogue output Digital input Analogue output Supply Supply Analogue output Digital input Analogue output Supply Supply Digital output Digital input Digital input Internal pull-down Sample rate clock input. Audio data serial input Audio data bit clock input. Oscillator buffered output (system clock). Oscillator input. Oscillator output. Digital ground supply. Digital positive supply. Analogue positive supply. Analogue ground supply. Mid rail right channel. Internal pull-down, active high, 8 x fs mode. Right channel DAC output. Analogue ground supply. Analogue positive supply. Left channel DAC output. Internal pull-down, active high, differential mono mode Mid rail left channel. Analogue ground supply. Analogue positive supply. DINL Differential Mode 8X Mode Production Data Software Mode Audio data serial input Infinite zero detect – active low. Open drain type output with active pull-down. Reset input – active low. Internal pull-up. Wordlength: Low for 16-bit data. High for 20-bit (normal) or 24-bit I2S data. Low for hardware mode. Wordlength: Low for 16-bit data. High for 20-bit (normal) or 24-bit I2S data. Low for left mono mode. High for right mono mode Low to soft mute. High for normal operation. Z for automute. Wordlength: Low for 20-bit data. High for 24-bit data. Low for serial interface operation. High for software mode. Low to soft mute. High for normal operation. Z for automute. Control serial interface data signal. Control serial interface clock signal. Control serial interface load signal. 24 MODE Digital input Internal pull-up DINR 25 MUTEB Digital input Internal pull-up Low to soft mute. High for normal operation. Z for automute. Low to soft mute. High for normal operation. Z for automute. 26 MD/DM0 Digital input Internal pull-up De-emphasis mode select bit 0. Low for no de-emphasis. High for 44.1kHz de-emphasis. Low for normal filter operation. High for filter slow roll-off. Audio serial format: Low – right justified. High – I2S. LRP – LRCLK polarity select. 27 MC/DM1 Digital input Internal pull-up De-emphasis mode select bit 1. Unused. Leave unconnected. 28 ML/I2S Digital input Internal pull-up Audio serial format: Low – right justified. High – I2S. Input data format: Low – right justified. High – left justified. Note: Digital input pins have Schmitt trigger input buffers except Pin 12 and Pin 17. WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 6 Production Data WM8716 DEVICE DESCRIPTION The WM8716 is a high performance 128fs oversampling rate stereo DAC employing a novel 64 level sigma delta DAC design which provides optimised signal-to-noise performance and clock jitter tolerance. It is ideally suited to high quality audio applications such as CD, DVD-audio, home theatre receivers and professional mixing consoles. The WM8716 supports sample rates from 8ks/s to 192ks/s. The control functions of the WM8716 are either pin selected (hardware mode) or programmed via the serial interface (software mode). Control functions that are available include: data input word length and format selection (16-24 bits: I2S, left justified or right justified): de-emphasis sample rate selection (48kHz, 44.1kHz and 32kHz); differential output modes; a software or hardware mute and independently digitally controllable attenuation on both channels. The digital filtering may be bypassed entirely by selecting MODE8X. Data is then input directly to the DAC, bypassing the digital filters. Left and right channels are input separately, using the MODE pin as the right channel input. This mode allows the use of alternative digital filters, such as the Pacific Microsonics PMD100 HDCD filter. In addition to the normal stereo operating mode the WM8716 may also be used in dual differential mode with either the left or right channel (selectable) being output differentially. Two WM8716s can then be used in parallel to implement a stereo channel, each supporting a single channel differentially. This mode is available in both software and hardware modes and may also be used in conjunction with MODE8X. SYSTEM CLOCK Sample rates from 8ks/s up to 96ks/s are available, and automatically selected, with a system clock of 256fs, 384fs, 512fs or 768fs. In addition a system clock of 128fs or 192fs may be used, with sample rates up to 192ks/s. With a 128fs or 192fs system clock 64x oversampling mode operation is automatically selected and the first stage of the digital filter is bypassed. WM8716 has an asynchronous monitor circuit, which in the event of removal of the master system clock, resets the digital filters and analogue circuits, muting the output. Re-application of the system clock re-starts the filters from an intitialised state. Control registers are not reset under this condition. The WM8716 is tolerant of asynchronous bit clock jitter. The internal signal processing resynchronises to the external LRCIN once the phase difference between bit clock and the system clock exceeds half an LRCIN period. During this re-synch period the interpolating filters will either miss or repeat an audio sample, minimising the audible effects of the operation. Table 1 shows the typical system clock frequency inputs for the WM8716. SAMPLING RATE (LRCIN) 32kHz 44.1kHz 48kHz 96kHz 192kHz SYSTEM CLOCK FREQUENCY (MHZ) 128fs 4.096 5.6448 6.114 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 Unavailable 384fs 12.288 16.9340 18.432 36.864 Unavailable 512fs 16.384 22.5792 24.576 Unavailable Unavailable 768fs 24.576 33.8688 36.864 Unavailable Unavailable Table 1 System Clock Frequencies Versus Sampling Rate WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 7 WM8716 AUDIO DATA INTERFACE Production Data Data may be input at a rate corresponding to the system clock having a rate of 256fs or 384fs or 512fs or 768fs, in which case an oversampling ratio of 128x is selected. Alternatively a rate of 128fs or 192fs may be used, in which case the first filter stage is bypassed and an oversampling ratio of 64x results. Finally, in MODE8X, data may be input at 8x the normal rate, in which case separate input pins are used to input the two stereo channels of data (unless DIFFHW mode and MODE8X are both selected, in which case only a mono channel is converted differentially). In MODE8X all filter stages are by-passed, prior to the sigma delta modulator. Data is input MSB first in all modes. NORMAL SAMPLE RATE In normal mode, the data is input serially on one pin for both left and right channels. Data can be “right justified” meaning that the last 16, 20 or 24 bits (depending on chosen PCM word length) that were clocked in prior to the transition on LRCIN are valid. Alternatively data can be “left justified” (20 and 24-bit PCM data only), where the bits are clocked in as the first 20 or 24 bits after a transition on LRCIN. For the three I2S modes supported (16-bit, 20-bit and 24-bit PCM data), data is clocked “left justified” except with one additional preceding clock cycle. 1/fs LEFT LRCIN (PIN 1) RIGHT BCKIN (PIN 3) 16-BIT RIGHT JUSTIFIED DIN (PIN 2) 20-BIT RIGHT JUSTIFIED DIN (PIN 2) 24-BIT RIGHT JUSTIFIED DIN (PIN 2) 24-BIT LEFT JUSTIFIED DIN (PIN 2) 20-BIT LEFT JUSTIFIED DIN (PIN 2) B2 B1 B0 B15 B2 B1 B0 B15 B2 B1 B0 B2 B1 B0 B19 B18 B17 B2 B1 B0 B19 B18 B17 B2 B1 B0 B2 B1 B0 B23 B22 B21 B20 B19 B2 B1 B0 B23 B22 B21 B20 B19 B2 B1 B0 B0 B23 B22 B21 B4 B3 B2 B1 B0 B23 B22 B21 B4 B3 B2 B1 B0 B0 B19 B18 B17 B0 B19 B18 B17 B0 LEFT LRCIN (PIN 1) RIGHT BCKIN (PIN 3) 16-BIT I2S DIN (PIN 2) B15 B2 B1 B0 B15 B2 B1 B0 B15 24-BIT I2S DIN (PIN 2) B23 B6 B5 B4 B3 B2 B1 B0 B23 B6 B5 B4 B3 B2 B1 B0 B23 20-BIT I2S DIN (PIN 2) B19 B2 B1 B0 B19 B2 B1 B0 B19 Figure 4 Audio Data Input Format WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 8 Production Data WM8716 8 X FS INPUT SAMPLE RATE Due to the higher speed of the interface in 8 x fs mode, audio data is input on two pins. The MODE pin (pin 24) is used as the second input for the right channel data and left data is input on DIN (pin 2). In this mode, software control of the device is not available. The data can be input in two formats, left or right justified, selectable by ML/I2S and two word lengths (20 or 24 bit), selectable by CSBIWO. In both modes the data is always clocked in MSB first. For left justified data the word start is marked by the falling edge of LRCIN. The data is clocked in on the next 20/24 BCKIN rising edges. This format is compatible with devices such as the PMD100. For right justified the data is justified to the rising edge of LRCIN and the data is clocked in on the preceding 20/24 BCKIN rising edges before the LRCIN rising edge. This format is compatible with devices such as the DF1704 or SM5842. In both modes the polarity of LRCIN can be switched using MD/DM0. Differential hardware mode can be used in conjunction with 8fs mode by setting the DIFFHW pin high. In differential 8fs mode the data is input on DIN and output differentially. MODE is unused and must be tied low. 1/8fs LRCIN (PIN 1) BCKIN (PIN 3) LEFT AUDIO DATA DIN (PIN 2) RIGHT AUDIO DATA MODE (PIN 24) B23 B22 B21 B20 B19 B2 B1 B0 B23 B22 B21 B20 B23 B22 B21 B20 B19 B2 B1 B0 B23 B22 B21 B20 1/8fs LRCIN (PIN 1) BCKIN (PIN 3) LEFT AUDIO DATA DIN (PIN 2) RIGHT AUDIO DATA MODE (PIN 24) B23 B22 B21 B20 B19 B2 B1 B0 B23 B22 B21 B20 B19 B2 B1 B0 Figure 5 Audio Data Input Format (8 x fs Operation) WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 9 WM8716 MODES OF OPERATION Production Data Control of the various modes of operation is either by software control over the serial interface, or by hard-wired pin control. Selection of software or hardware mode is via MODE pin. The following functions may be controlled either via the serial control interface or by hard wiring of the appropriate pins. HARDWARE CONTROL MODES When the MODE pin is held ‘low’ the following hardware modes of operation are available. In Hardware differential mode or 8X mode some of these modes/control words are altered or unavailable. DE-EMPHASIS CONTROL MDDM1 PIN 27 L L H H Table 2 De-Emphasis Control MCDMO PIN 26 L H L H DE-EMPHASIS Off 48kHz 44.1kHz 32kHz AUDIO INPUT FORMAT CSBIIS PIN 28 L L H H Table 3 Audio Input Format CSBIWO PIN 23 L H L H DATA FORMAT 16 bit normal right justified 20 bit normal right justified 16 bit I2S 24 bit I2S SOFT MUTE MUTEB PIN 25 L Z H Table 4 Soft Mute A logic low on the MUTEB pin will cause the attenuation to ramp to infinite attenuation at a rate of 128/fs seconds per 0.5dB step. Setting MUTEB high will cause the attenuation to ramp back to its previous value. Leaving MUTEB undriven allows operation of the automute circuit in both hardware and software modes. On receiving 1024 consecutive zero value audio samples, the analogue stage output mute is asserted. This may be overdriven from the MUTEB pin to disable the automute function, or output as a weak (10kohm) output signal. FUNCTION Mute On (no output) Automute Mute Off (normal operation) SOFTWARE CONTROL INTERFACE The WM8716 can be controlled using a 3-wire serial interface. MD/DM0 (pin 26) is used for the program data, MC/DM1 (pin 22) is used to clock in the program data and ML/I2S (pin 28) is use to latch in the program data. The 3-wire interface protocol is shown in Figure 6. CSB/IWO (pin 23) must be low when writing. WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 10 Production Data WM8716 ML/I2S (PIN 28) MC/DM1 (PIN 27) MD/DM0 (PIN 26) B15 B14 B13 B2 B1 B0 Figure 6 Three-Wire Serial Interface REGISTER MAP WM8716 controls the special functions using 4 program registers, which are 16-bits long. These registers are all loaded through input pin MD/DM0. After the 16 data bits are clocked in, ML/I2S is used to latch in the data to the appropriate register. Table 5 shows the complete mapping of the 4 registers. Note that in hardware differential mode and 8X modes, software control is not available. The hardware differential mode (Diff[1:0]) clock loss detector disable (CDD) can only be accessed by writing to M2[8:5] with the pattern 1111. Register M4 is then accessible by setting A[2:0] to 110. B15 M0 M1 M2 M3 M4 B14 B13 B12 B11 B10 B9 A0(0) A0(1) A0(0) A0(1) A0(0) B8 LDL LDR IZD B7 AL7 AR7 SF1 B6 AL6 AR6 SF0 B5 AL5 AR5 CK0 B4 AL4 AR4 IW1 REV B3 AL3 AR3 IW0 SR0 B2 AL2 AR2 OPE ATC B1 AL1 AR1 DEM LRP B0 AL0 AR0 MUT I2S - A2 (0) A1(0) A2(0) A2(0) A2(0) A2(1) A1(0) A1(1) A1(1) A1(1) CDD DIFF1 DIFF0 Table 5 Mapping of Program Registers REGISTER 0 1 2 BITS [7:0] 8 [7:0] 8 0 1 2 [4:3] 3 0 1 2 3 4 5 [7:6] 8 4 [5:4] 6 NAME AL[7:0] LDL AR[7:0] LDR MUT DEM OPE IW[1:0] I2S LRP ATC SR0 REV CKO SF[1:0] IZD DIFF CDD DEFAULT FF 0 FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DESCRIPTION Attenuation data for left channel. Attenuation data load control for left channel. Attenuation data for right channel. Attenuation data load control for right channel. Left and right DACs soft mute control. De-emphasis control. Left and right DACs operation control. Input audio data bit select. Audio data format select. Polarity of LRCIN select. Attenuator control. Digital filter slow roll-off select. Output phase reverse. CLKO frequency select. Sampling rate select. Infinite zero detection circuit control. Differential output mode. Clock loss detector disable. Table 6 Register Bit Descriptions WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 11 WM8716 DAC OUTPUT ATTENUATION The level of attenuation for eight bit code X, is given by: 0.5 ∗ (X - 255) dB, 1 ≤ X ≤ 255 - ∞dB (mute), X=0 Production Data Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in B[7:0]. When LDL is set to 0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in register 1 has the same function for right channel attenuation. Only when LDL or LDR is set to ’1’ will the filter attenuation be updated. This permits left and right channel attenuation to be updated simultaneously. Attenuation level is controlled by AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels are given in Table 4. X[7:0] 00(hex) 01(hex) : : FD(hex) FE(hex) FF(hex) Table 7 Attenuation Control Level Bit 2 in Reg3 is used to control the attenuator (ATC). When ATC is “high”, the attenuation data loaded in program register 0 is used for both the left and the right channels. When ATC is low, the attenuation data for each register is applied separately to left and right channels. ATTENUATION LEVEL - ∞dB (mute) -127.0dB : : -1.0dB -0.5dB 0.0dB SOFT MUTE MUT (REG2, B0) L H Table 8 Soft Mute Setting MUT causes the attenuation to ramp from the current value down to 00. The values held in the attenuation registers are unchanged. When MUT is reset the attenuation will ramp back up to the previous value. The ramp rate is 128/fs s/0.5dB step. Soft Mute off (normal operation) Soft Mute on (no output) DIGITAL DE-EMPHASIS DEM (REG2, B1) L H De-emphasis off De-emphasis on Table 9 Digital De-Emphasis DAC OPERATION ENABLE OPE (REG2,B2) L H Normal operation DAC output forced to bipolar zero, irrespective of input data. Table 10 DAC Operation Enable WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 12 Production Data WM8716 AUDIO DATA INPUT FORMAT I2S (REG3, B0) 0 0 0 0 1 1 1 1 IW1 (REG2, B4) 0 0 1 1 0 0 1 1 IW0 (REG2, B3) 0 1 0 1 0 1 0 1 AUDIO INTERFACE 16-bit standard right justified 20-bit standard right justified 24-bit standard right justified 24-bit left justified (MSB first) 16-bit I2S 24-bit I2S 20-bit I2S 20-bit left justified (MSB first) Table 11 Audio Data Input Format POLARITY OF LR INPUT CLOCK The left channel data for a particular sample instant is always input first, then the right channel data. LRP (REG3, B1) L H LR High – left channel LR Low – right channel LR Low – left channel LR High – right channel Table 12 Polarity of LR Input Clock INDIVIDUAL OR COMMON ATTENUTATION CONTROL ATC (REG3, B2) L H Individual control Common control from Reg0 Table 13 Individual or Common Attenuation Control DIGITAL FILTER ROLL-OFF SELECTION SRO (REG3, B3) L H Sharp Slow Table 14 Digital Filter Roll-Off Selection ANALOGUE OUTPUT POLARITY REVERSAL REV (REG3, B4) L H Normal Inverted Table 15 Analogue Output Polarity Reversal CLKO OUTPUT FREQUENCY CKO (REG3, B5) L H XTI XTI/2 Table 16 CLKO Output Frequency WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 13 WM8716 DE-EMPHASIS SAMPLE RATE SF1 (REG3, B7) 0 0 1 1 SF0 (REG3, B6) 0 1 0 1 SAMPLE RATE No de-emphasis 48kHz 44.1kHz 32kHz Production Data Table 17 De-Emphasis Sample Rate INFINITE ZERO DETECT IZD (REG3, B8) L H Zero detect mute off Zero detect mute on Table 18 Infinite Zero Detect DIFFERENTIAL MONO MODE Using bits 4 and 5, the differential output mode may be selected to be one of normal stereo, reversed stereo, mono left or mono right, as shown in Table 19. DIFF[1:0] B[4:5]) 00 01 10 DIFFERENTIAL OUTPUT MODE Stereo Stereo reverse. Mono left – differential outputs. VOUTL is left channel. VOUTR is the negative of left channel. Mono right – differential outputs. VOUTL is the negative right channel. VOUTR is right channel. 11 Table 19 Differential Output Modes Using these controls a pair of WM8716 devices may be used to build a ‘dual differential’ stereo implementation with higher performance and differential output. CLOCK LOSS DETECTOR DISABLE CDD (REG4, B6) L R Clock loss detector on Clock loss detector off Table 20 Clock Loss Detector Disable When the system clock is inactive for approximately 100µs, the clock loss detector circuit detects the loss of clock and the analogue circuitry is forced into a mute condition and the digital filters reset. Setting the CDD bit disables this behaviour. WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 14 Production Data WM8716 The device has various mute modes. DIGITAL FILTER ANRES Reg bit OPE = ‘1’ MUTEB pin Unaffected Gain ramped to zero On release volume ramps to previous value Automute has no effect on digital filters As MUTEB pin Gain = -∞dB Gain initialised to 0dB Not running (no clock). On clock restart, filters initialised, RAM initialised. Registers unchanged Filters initialised, RAM initialised. Registers unchanged Reset – gain initialised to 0dB Reset Asserted ANALOGUE ANMUTE Asserted Asserted when gain = 0 Asserted after 1024 zero input samples if IZD = 1 As MUTEB pin Asserted Asserted Asserted MUTE MODES AUTOMUTE (detect 1024 zero input samples) Reg bit MUT Gain = 00 (left & right) RAM initialise Loss of system clock No LRCLK or invalid SCLK/LRCLK ratio RB Power-on reset Table 21 Mute Modes • • • Asserted Asserted Asserted Asserted Asserted Asserted • ANRES is the reset to the switched capacitor filter. ANMUTE is an analogue muting signal gating the analogue signal at the output (after the SC filter) AUTOMUTE is asserted when both the IZD register bit is asserted and the input audio data has been zero on both left and right channels for 1024 input samples. The first non-zero sample deasserts. Applying a logic low to MUTEB or setting MUT in Reg2 causes the gain registers to ramp to zero. When a logic high is applied, the gain ramps slowly back up to the value held in the appropriate attenuation register (AL or AR). The ramp rate = 128/fs s/0.5dB step. If SOFTMUTE is set or MUTEB=0 then GAINL and GAINR are overridden to 00 GAINL[0:7] GAINR[0:7] Signal Processing SOFTMUTE MUTEB gain ramps between previous and new gain setting Automute: Detect 1024 zero input samples IZD OPE FREQ_INVALID INIT ANMUTE ZERO Figure 7 Mute Modes WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 15 WM8716 FILTER RESPONSES Production Data Figure 8 Digital Filter Response (Sharp Roll-off Mode) Figure 9 Digital Filter Response (Sharp Roll-off Mode) Figure 10 Digital Filter Response (Slow Roll-off Mode) Figure 11 Digital Filter Response (Slow Roll-off Mode) 0 -20 Response (dB) -40 -60 -80 -100 -120 0 0.2 0.4 0.6 0.8 1 1.2 Frequency (Fs) 1.4 1.6 1.8 2 Figure 12 Digital Filter Response 128fs Mode (192kHz Sample Rate) Normal Mode – Solid, Slow Mode – Dashed WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 16 Production Data 1 0.8 1 0.8 WM8716 Impulse Response Impulse Response 0.6 0.4 0.2 0 -0.2 -0.4 0 10 20 30 40 Time (input samples) 50 60 0.6 0.4 0.2 0 -0.2 -0.4 0 10 20 30 40 Time (input samples) 50 60 Figure 13 Impulse Response (Normal Roll-off, no De-emphasis) Figure 14 Impulse Response (Slow Roll-off, no De-emphasis) WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 17 WM8716 RECOMMENDED EXTERNAL COMPONENTS DVDD 8 + C1 C2 7 DGND DVDD AVDD AVDDR AVDDL 15 9 20 + C3 AGND AGNDR AGNDL 28 27 ML/I2S MC/DM1 MD/DM0 CSB/IWO RSTB VOUTR 13 C7 14 10 19 AGND C4 C5 C6 AVDD Production Data DGND Software I/F or Hardware Control 26 23 22 12 MODE8X VOUTL 16 C8 + + AC-Coupled Output to External LPF W M8716 17 DIFFHW AVDD R1 24 MODE ZERO 21 25 MUTEB VMIDR VMIDL 11 18 + C11 C9 C10 C12 + 1 LRCIN DIN BCKIN CLKO XTI XTO 4 Audio Serial Data I/F 2 3 AGND System Clock Input or Oscillator Input/Output 5 6 XTI Buffered Output NOTES: 1. AGND and DGND should be connected as close to the WM8716 as possible. 2. C2 to C5, C9 and C11 should be positioned as close to the WM8716 as possible. 3. Capacitor type used can have a big effect on device performance. It is recommended that capacitors with very low ESR are used and that ceramics are either NPO or COG type material to achieve best performance from the WM8716. Figure 15 External Components Diagram RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT REFERENCE C1 and C6 C2 to C5 C7 and C8 C9 and C11 C10 and C12 R1 SUGGESTED VALUE 10µF 0.1µF 10µF 0.1µF 10µF 10kΩ DESCRIPTION De-coupling for DVDD and AVDD. De-coupling for DVDD and AVDD. Output AC coupling caps to remove VMID DC level from outputs. Reference de-coupling capacitors for VMIDR and VMIDL. Resistor to AVDD for open drain output operation. Table 22 External Components Description WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 18 Production Data WM8716 RIGHT DAC DVDD 8 + 7 DVDD AVDD AVDDR DGND AVDDL 15 9 20 + 14 10 19 AVDD LRCIN 1 2 3 LRCIN DIN BCKIN AGND AGNDR AGNDL AUDIO SERIAL DATA DIN BCKIN SCKI 5 6 4 DVDD 24 25 22 XTI XTO CLKO VOUTR 13 + LPF WM8716 VOUTL 16 - RIGHT OUTPUT DATA MODE MUTEB RSTB ZERO 21 VMIDR VMIDL 11 18 + + 28 ML/I2S MC/DM1 MD/DM0 CSB/IWO MODE8X 12 AVDD DIFFHW 17 Hardware Control 27 26 23 LEFT DAC DVDD 8 + 7 DVDD AVDD AVDDR DGND AVDDL 15 9 20 + 14 10 19 AVDD 1 2 3 LRCIN DIN BCKIN AGND AGNDR AGNDL 5 6 4 DVDD 24 25 22 XTI XTO CLKO VOUTR 13 + LPF WM8716 VOUTL 16 - LEFT OUTPUT DATA MODE MUTEB RSTB ZERO 21 VMIDR VMIDL 11 18 + + 28 27 26 23 ML/I2S MC/DM1 MD/DM0 CSB/IWO MODE8X 12 AVDD DIFFHW 17 NOTE: 1. MODE selects left/right data. High for right, Low for left. Figure 16 Example of 2 WM8716 Stereo DACs Configured in Hardware Differential Mode to Provide an Optimum Performance Stereo Output WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 19 WM8716 Production Data +VDD MODE8X SCKI XTI PMD-100 Serial Interface Data LRCIN BCKIN DIN XTI WCKO LRCI BCKO BCKI DOL DIN DOR PROG MODE DIN VOUTL BCKIN LRCIN WM8716 VOUTR +VDD ML/I2S (STAND ALONE MODE) NOTES: 1. ML/I2S selects left or right justified inputs. 2. MD/DM0 selects LRCLK polarity. 3. CSBIWO selects 20 or 24-bit data. CSB/IWO MD/DM0 MUTEB Figure 17 Example of WM8716 in MODE8X Operation WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 20 Production Data WM8716 PACKAGE DIMENSIONS DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) DM007.C b 28 e 15 E1 E 1 D 14 GAUGE PLANE Θ 0.25 c A A2 A1 L -C0.10 C SEATING PLANE Symbols A A1 A2 b c D e E E1 L θ REF: MIN ----0.05 1.62 0.22 0.09 9.90 7.40 5.00 0.55 o 0 Dimensions (mm) NOM --------1.75 --------10.20 0.65 BSC 7.80 5.30 0.75 o 4 JEDEC.95, MO-150 MAX 2.0 ----1.85 0.38 0.25 10.50 8.20 5.60 0.95 o 8 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD PD Rev 3.1 April 2001 21