WM8729

WM8729 24-bit, 192kHz Stereo DAC Product Preview, Rev 1.2, April 2001 DESCRIPTION The WM8729 is a high performance stereo DAC designed for audio applications such as DVD, home theatre systems, and digital TV. The WM8729 supports data input word lengths from 16 to 24-bits and sampling rates up to 192kHz. The WM8729 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo DAC in a small 16-pin SOIC package. The WM8729 has a hardware control interface for selection of audio data interface format and de-emphasis. The WM8729 is an ideal device to interface to AC-3, DTS, and MPEG audio decoders for surround sound applications, or for use in DVD players, including supporting the implementation of 2 channels at 192kHz for high-end DVD-Audio applications. FEATURES • • Stereo DAC Audio Performance 106dB SNR (‘A’ weighted @ 48kHz) DAC -97dB THD DAC Sampling Frequency: 8kHz – 192kHz Pin Selectable Audio Data Interface Format I2S or Right Justified 3.0V - 5.5V Supply Operation 16-pin SOIC Package Exceeds Dolby Class A Performance Requirements • • • • • APPLICATIONS • • • • DVD-Audio and DVD ‘Universal’ Players Home theatre systems Digital TV Digital broadcast receivers BLOCK DIAGRAM FORMAT MUTEB DEM CONTROL INTERFACE WM8729 MUTE BCKIN LRCIN DIN MUTE SERIAL INTERFACE DIGITAL FILTERS SIGMA DELTA MODULATOR RIGHT DAC LOW PASS FILTER VOUTR SIGMA DELTA MODULATOR LEFT DAC LOW PASS FILTER VOUTL VMID MCLK AVDD DVDD VREFP VREFN AGND DGND WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk www.wolfsonmicro.com Product Preview data sheets contain specifications for products in the formative phase of development. These products may be changed or discontinued without notice. 2001 Wolfson Microelectronics Ltd. WM8729 Product Preview PIN CONFIGURATION LRCIN DIN BCKIN MCLK DGND DVDD VOUTR AGND 1 2 3 4 5 6 7 8 16 15 14 FORMAT ORDERING INFORMATION DEVICE XWM8729ED TEMP. RANGE -25 to +85oC PACKAGE 16-pin SOIC DEM MUTEB WM8729 13 12 11 10 9 VREFP VREFN VMID VOUTL AVDD PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NAME LRCIN DIN BCKIN MCLK DGND DVDD VOUTR AGND AVDD VOUTL VMID VREFN VREFP MUTEB DEM TYPE Digital Input Digital Input Digital Input Analogue Input Supply Supply Analogue Output Supply Supply Analogue Output Analogue Output Supply Supply Digital Bi-directional Digital Input Serial Audio Data Input Audio Data Bit Clock Input. Master Clock Input Digital Ground Supply Digital Positive Supply Right Channel DAC Output Analogue Ground Supply Analogue Positive Supply Left Channel DAC Output Mid Rail Decoupling Point DAC Negative Reference – normally AGND, must not be below AGND DAC Positive Reference – normally AVDD, must not be above AVDD Mute Control, (L = Mute on, H = Mute off, Z = Automute Enabled) De-Emphasis Select 0 = De-Emphasis Off 1 = De-Emphasis On Digital Audio Data Input Format Selection 0 = Right justified Audio Data 1 = I2S Audio Data DESCRIPTION DAC Sample Rate Clock Input 16 FORMAT Digital Input (Pull-Up) Note: Digital input pins have Schmitt trigger input buffers. WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 2 WM8729 Product Preview ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) Note: Analogue and digital grounds must always be within 0.3V of each other. MIN -0.3V -0.3V DGND -0.3V AGND -0.3V -25°C -65°C MAX +7V +7V DVDD +0.3V AVDD +0.3V 50MHz +85°C +150°C +220°C +183°C WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 3 WM8729 Product Preview DC ELECTRICAL CHARACTERISTICS PARAMETER Digital supply range Analogue supply range Ground Difference DGND to AGND Analogue supply current Digital supply current Analogue supply current Digital supply current AVDD = 5V DVDD = 5V AVDD = 3.3V DVDD = 3.3V SYMBOL DVDD AVDD AGND, DGND -0.3 TEST CONDITIONS MIN 3.0 3.0 0 0 19 8 18 4 +0.3 TYP MAX 5.5 5.5 UNIT V V V V mA mA mA mA ELECTRICAL CHARACTERISTICS Test Conditions AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage VMID (VREFP VREFN)/2 50mV (VREFP VREFN)/2 12k At DAC outputs A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted @ fs = 192kHz A-weighted, @ fs = 48kHz AVDD, DVDD = 3.3V A-weighted @ fs = 96kHz AVDD, DVDD = 3.3V Non ‘A’ weighted @ fs = 48kHz 1kHz, 0dBFs 1kHz, -60dBFs 100 1.1 x AVDD/5 106 106 106 105 (VREFP VREFN)/2 + 50mV V VIL VIH VOL VOH IOL = 1mA IOH = 1mA AVDD - 0.3V 2.0 AGND + 0.3V 0.8 V V V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Potential divider resistance DAC Output (Load = 10k ohms. 50pF) 0dBFs Full scale output voltage SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) RVMID ohms Vrms dB dB dB dB SNR (Note 1,2,3) 103 dB SNR (Note 1,2,3) THD (Note 1,2,3) THD+N (Dynamic range, Note 2) DAC channel separation Analogue Output Levels Output level 106 -97 100 106 100 dB dB dB dB VRMS VRMS Load = 10k ohms, 0dBFS Load = 10k ohms, 0dBFS, (AVDD = 3.3V) 1.1 0.726 Gain mismatch channel-to-channel ±1 %FSR WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 4 WM8729 Test Conditions AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Minimum resistance load SYMBOL TEST CONDITIONS To midrail or a.c. coupled To midrail or a.c. coupled (AVDD = 3.3V) 5V or 3.3V MIN TYP 1 600 MAX Product Preview UNIT kohms ohms Maximum capacitance load Output d.c. level Power On Reset (POR) POR threshold 100 (VREFP VREFN)/2 2.4 pF V V Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth. 2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). TERMINOLOGY 1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. 3. 4. 5. WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 5 WM8729 MASTER CLOCK TIMING tMCLKL MCLK tMCLKH tMCLKY Product Preview Figure 1 Master Clock Timing Requirements Test Conditions AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information MCLK Master clock pulse width high MCLK Master clock pulse width low MCLK Master clock cycle time MCLK Duty cycle SYMBOL tMCLKH tMCLKL tMCLKY TEST CONDITIONS MIN 13 13 26 40:60 TYP MAX UNIT ns ns ns 60:40 DIGITAL AUDIO INTERFACE tBCH BCKIN tBCY tBCL LRCIN tDS DIN tDH tLRH tLRSU Figure 2 Digital Audio Data Timing Test Conditions AVDD, DVDD = 5V, AGND = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER BCKIN cycle time BCKIN pulse width high BCKIN pulse width low LRCIN set-up time to BCKIN rising edge LRCIN hold time from BCKIN rising edge DIN set-up time to BCKIN rising edge DIN hold time from BCKIN rising edge SYMBOL tBCY tBCH tBCL tLRSU tLRH tDS tDH TEST CONDITIONS MIN 40 16 16 8 8 8 8 TYP MAX UNIT ns ns ns ns ns ns ns Audio Data Input Timing Information WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 6 WM8729 Product Preview DEVICE DESCRIPTION INTRODUCTION The WM8729 is a high performance DAC designed for digital consumer audio applications. Its range of features make it ideally suited for use in DVD players, AV receivers and other high end consumer audio equipment. The WM8729 is a complete 2-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and output smoothing filters. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. Control of internal functionality of the device is provided by hardware control (pin programmed). Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically controlled. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate system clock is input. Support is also provided for up to 192ks/s using a master clock of 128fs or 192fs. The audio data interface supports right justified or I2S (Philips left justified, one bit delayed) interface formats. The device is packaged in a small 16-pin SOIC. CLOCKING SCHEMES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The external master clock can be applied directly through the MCLK input pin with no configuration necessary for sample rate selection. Note that on the WM8729, MCLK is used to derive clocks for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC. DIGITAL AUDIO INTERFACE Audio data is applied to the internal DAC filters via the Digital Audio Interface. Two popular interface formats are supported: Right Justified mode I2S mode Both formats send the MSB first. The WM8729 supports word lengths of 16 or 24 bits in I2S mode and 16 or 20 bits in right justified mode. In right justified and I2S modes, the digital audio interface receives data on the DIN input. Audio Data is time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used as a timing reference to indicate the beginning or end of the data words. In right justified and I2S modes, the minimum number of BCKINs per LRCIN period is 2 times the selected word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements are met. WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 7 WM8729 RIGHT JUSTIFIED MODE Product Preview In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN transition. LRCIN is high during the left samples and low during the right samples. 1/fs LEFT CHANNEL LRCIN RIGHT CHANNEL BCKIN DIN 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n MSB LSB MSB LSB Figure 3 Right Justified Mode Timing Diagram I S MODE In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN transition. LRCIN is low during the left samples and high during the right samples. 2 1/fs LEFT CHANNEL LRCIN RIGHT CHANNEL BCKIN 1 BCKIN 1 BCKIN 3 n-2 n-1 n 1 2 3 n-2 n-1 n DIN 1 2 MSB LSB MSB LSB Figure 4 I2S Mode Timing Diagram AUDIO DATA SAMPLING RATES The master clock for WM8729 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8729 has a master clock detection circuit that automatically determines the relation between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The master clock should be synchronised with LRCIN, although the WM8729 is tolerant of phase differences or jitter on this clock. SAMPLING RATE (LRCIN) 32kHz 44.1kHz 48kHz 96kHz 192kHz MASTER CLOCK FREQUENCY (MHZ) (MCLK) 128fs 4.096 5.6448 6.114 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 Unavailable 384fs 12.288 16.9340 18.432 36.864 Unavailable 512fs 16.384 22.5792 24.576 Unavailable Unavailable 768fs 24.576 33.8688 36.864 Unavailable Unavailable Table 1 Master Clock Frequencies Versus Sampling Rate WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 8 WM8729 HARDWARE CONTROL MODES Product Preview The WM8729 is hardware programmable providing the user with options to select input audio data format, de-emphasis and mute. MUTE AND AUTOMUTE OPERATION Pin 14 (MUTEB) controls selection of MUTE directly, and can be used to enable and disable the automute function, or as an output of the automuted signal. MUTEB PIN 0 1 Floating Mute DAC channels Normal Operation Enable IZD, MUTEB becomes an output to indicate when IZD occurs. DESCRIPTION Table 2 Mute and Automute Control 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006 Figure 5 Application and Release of MUTEB The MUTEB pin is an input to select mute or not mute. MUTEB is active low; taking the pin low causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTEB high again allows data into the filter. Refer to Figure 5. The Infinite Zero Detect (IZD) function detects a series of zero value audio samples of 1024 samples long being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED) is connected through a 10kohm resistor to the MUTEB pin. Thus if the MUTEB pin is not being driven, the automute function will assert mute. If MUTEB is tied high, AUTOMUTED is overridden and will not mute. If MUTEB is driven from a bi-directional source, then both MUTE and automute functions are available. If MUTEB is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-zero input. A diagram showing how the various Mute modes interact is shown below in Figure 6. WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 9 WM8729 Product Preview AUTOMUTED (Internal Signal) 10kΩ MUTEB PIN SOFTMUTE (Internal Signal) Figure 6 Selection Logic for MUTE Modes INPUT FORMAT SELECTION FORMAT (pin 16) controls the data input format. FORMAT 0 1 Table 3 Input Format Selection Notes: 1. In 24 bit I2S mode, any width of 24 bits or more is supported provided that LRCIN is high for a minimum of 24 BCKINs and low for a minimum of 24 BCKINs, unless Note 2. If exactly 16 BCKIN cycles occur in both the low and high period of LRCIN the WM8729 will assume the data is 16 bit and accept the data accordingly. INPUT DATA MODE 20-bit right justified (note 2) 24-bit I2S (note 2) 2. DE-EMPHASIS CONTROL DEM (pin 15) is an input control for selection of de-emphasis filtering to be applied. DEM 0 1 Table 4 De-emphasis Control DE-EMPHASIS Off On WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 10 WM8729 DIGITAL FILTER CHARACTERISTICS PARAMETER Passband Edge Passband Ripple Stopband Attenuation Table 5 Digital Filter Characteristics SYMBOL TEST CONDITIONS -3dB f < 0.444fs f > 0.555fs -60 MIN TYP 0.487fs ±0.05 MAX Product Preview UNIT dB dB DAC FILTER RESPONSES 0.2 0 0.15 -20 0.1 Response (dB) Response (dB) -40 0.05 0 -0.05 -0.1 -60 -80 -100 -0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 -120 Figure 7 DAC Digital Filter Frequency Response -44.1, 48 and 96kHz Figure 8 DAC Digital Filter Ripple -44.1, 48 and 96kHz 0.2 0 0 -20 Response (dB) Response (dB) -0.2 -40 -0.4 -60 -0.6 -0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 9 DAC Digital Filter Frequency Response -192kHz Figure 10 DAC Digital Filter Ripple -192kHz WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 11 WM8729 Product Preview DIGITAL DE-EMPHASIS CHARACTERISTICS 0 1 0.5 -2 0 Response (dB) Response (dB) -4 -0.5 -1 -1.5 -2 -6 -8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16 Figure 11 De-Emphasis Frequency Response (32kHz) 0 Figure 12 De-Emphasis Error (32kHz) 0.4 0.3 -2 0.2 Response (dB) Response (dB) -4 0.1 0 -0.1 -0.2 -6 -8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20 Figure 13 De-Emphasis Frequency Response (44.1kHz) 0 Figure 14 De-Emphasis Error (44.1kHz) 1 0.8 -2 0.6 0.4 Response (dB) -4 Response (dB) 0.2 0 -0.2 -0.4 -6 -8 -0.6 -0.8 -10 0 5 10 15 Frequency (kHz) 20 -1 0 5 10 15 Frequency (kHz) 20 Figure 15 De-Emphasis Frequency Response (48kHz) Figure 16 De-Emphasis Error (48kHz) WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 12 WM8729 Product Preview RECOMMENDED EXTERNAL COMPONENTS DVDD 6 + C1 C2 5 DGND DGND AGND VREFN 8 12 DVDD AVDD VREFP 9 13 AVDD + C3 C4 C5 AGND 16 FORMAT DEM MUTEB VOUTR 7 C6 Hardware Control 15 14 W M8729 VOUTL 1 4 10 C7 AC-Coupled VOUTR/L to External LPF + + LRCIN MCLK BCKIN DIN Audio Serial Data I/F 3 2 VMID 11 + C8 C9 AGND Notes: 1. AGND and DGND should be connected as close to the WM8729 as possible. 2. C2, C3, C4 and C8 should be positioned as close to the WM8729 as possible. 3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance. Figure 17 External Component Diagram RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT REFERENCE C1 and C5 C2 to C4 C6 and C7 C8 C9 SUGGESTED VALUE 10µF 0.1µF 10µF 0.1µF 10µF DESCRIPTION De-coupling for DVDD and AVDD/VREFP De-coupling for DVDD and AVDD/VREFP Output AC coupling caps to remove midrail DC level from outputs. Reference de-coupling capacitors for VMID pin. Table 6 External Components Description WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 13 WM8729 Product Preview RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL) 4.7kΩ 4.7kΩ +VS _ 51Ω 10uF 1.8kΩ 7.5KΩ + + 1.0nF 47kΩ 680pF -VS Figure 18 Recommended Low Pass Filter (Optional) WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 14 WM8729 Product Preview PACKAGE DRAWING D: 16 PIN SOIC 3.9 mm Body DM012.B e B 16 9 E H 1 8 D L h x 45 o A1 -CA SEATING PLANE α C 0.10 (0.004) Symbols A A1 B C D E e H h L α REF: Dimensions (mm) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.27 0o 8o Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3859 0.3937 0.1497 0.1574 0.05 BSC 0.2284 0.2440 0.0099 0.0196 0.0160 0.0500 0o 8o JEDEC.95, MS-012 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 15