WM8750L

WM8750L Stereo CODEC for Portable Audio Applications DESCRIPTION The WM8750L is a low power, high quality stereo codec designed for portable digital audio applications. The device integrates complete interfaces to stereo or mono microphones and a stereo headphone. External component requirements are drastically reduced as no separate microphone or headphone amplifiers are required. Advanced on-chip digital signal processing performs graphic equaliser, 3-D sound enhancement and automatic level control for the microphone or line input. The WM8750L can operate as a master or a slave, with various master clock frequencies including 12 or 24MHz for USB devices, or standard 256fs rates like 12.288MHz and 24.576MHz. Different audio sample rates such as 96kHz, 48kHz, 44.1kHz are generated directly from the master clock without the need for an external PLL. The WM8750L operates at supply voltages down to 1.8V, although the digital core can operate at voltages down to 1.42V to save power, and the maximum for all supplies is 3.6 Volts. Different sections of the chip can also be powered down under software control. The WM8750L is supplied in a very small and thin 5x5mm QFN package, ideal for use in hand-held and portable systems. FEATURES • • • • • DAC SNR 98dB (‘A’ weighted), THD -95B at 48kHz, 3.3V ADC SNR 95dB (‘A’ weighted), THD -90dB at 48kHz, 3.3V Complete Stereo / Mono Microphone Interface - Programmable ALC / Noise Gate On-chip 400mW BTL Speaker Driver (mono) On-chip Headphone Driver - >40mW output power on 16Ω / 3.3V - THD –80dB at 20mW, SNR 90dB with 16Ω load - No DC blocking capacitors required (capless mode) Separately mixed mono output Digital Graphic Equaliser Low Power - 7mW stereo playback (1.8V / 1.5V supplies) - 14mW record & playback (1.8V / 1.5V supplies) Low Supply Voltages - Analogue 1.8V to 3.6V - Digital core: 1.42V to 3.6V - Digital I/O: 1.8V to 3.6V 256fs / 384fs or USB master clock rates: 12MHz, 24MHz Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96kHz generated internally from master clock 5x5x0.9mm QFN package • • • • • • • APPLICATIONS • • • • MP3 Player / Recorder AAC/WMA/Multi-Format Player / Recorder Minidisc Player / Recorder Portable Digital Music Systems BLOCK DIAGRAM DGND M U X LMIXSEL DC MEASUREMENT LINPUT1 LINPUT2 LINPUT3 M U X LINSEL DIFF. INPUT L1-R1 OR L2-R2 RINSEL PGA + MIC BOOST ADC DIGITAL FILTERS Å WM8750L AUDIO INTERFACE BCLK ADCLRC ADCDAT DACLRC DACDAT DCVDD DBVDD HPGND HPVDD OUT3SW VREF ROUT1 LEFT LD2LO MIXER MONOOUT LI2LO M U X -1 OUT3 LOUT1 RD2LO DAC MONO LD2MO MIXER RI2LO LI2MO LOUT1VOL DIGITAL FILTERS GRAPHIC EQUALISER BASS BOOST VOLUME ANALOGUE MONO MIX DIGITAL MONO MIX MONOOUT (phone TX) RD2MO RI2MO LI2RO MONOVOL RINPUT3/ HPDETECT RINPUT2 RINPUT1 M U X PGA + MIC BOOST ADC 3D ENHANCE DAC RIGHT LD2RO MIXER ROUT1 RD2RO RI2RO ROUT1VOL DC MEASUREMENT M U X RMIXSEL LOUT2VOL LOUT2 L - (-R) = L+R ROUT2 ROUT2VOL MICBIAS 50K 50K -1 CLOCK CIRCUITRY CONTROL INTERFACE ROUT2 INV AGND VREF MODE SCLK SDIN CSB MCLK AVDD VMID WOLFSON MICROELECTRONICS plc www.wolfsonmicro.com Product Preview, May 2003, Rev 1.77 Copyright 2003 Wolfson Microelectronics plc WM8750L TABLE OF CONTENTS Product Preview DESCRIPTION ......................................................................................................1 FEATURES ...........................................................................................................1 APPLICATIONS ....................................................................................................1 BLOCK DIAGRAM................................................................................................1 PIN CONFIGURATION .........................................................................................4 ORDERING INFORMATION .................................................................................4 PIN DESCRIPTION ...............................................................................................4 ABSOLUTE MAXIMUM RATINGS........................................................................5 RECOMMENDED OPERATION CONDITIONS ....................................................5 ELECTRICAL CHARACTERISTICS .....................................................................6 HEADPHONE / SPEAKER OUTPUT THD VERSUS POWER......................................8 POWER CONSUMPTION ...................................................................................11 SIGNAL TIMING REQUIREMENTS....................................................................12 SYSTEM CLOCK TIMING ..........................................................................................12 AUDIO INTERFACE TIMING – MASTER MODE........................................................12 AUDIO INTERFACE TIMING – SLAVE MODE ...........................................................13 DEVICE DESCRIPTION......................................................................................16 INTRODUCTION ........................................................................................................16 INPUT SIGNAL PATH ................................................................................................16 AUTOMATIC LEVEL CONTROL (ALC) ......................................................................22 3D STEREO ENHANCEMENT ...................................................................................25 OUTPUT SIGNAL PATH.............................................................................................26 ANALOGUE OUTPUTS ..............................................................................................31 ENABLING THE OUTPUTS........................................................................................33 HEADPHONE SWITCH ..............................................................................................33 THERMAL SHUTDOWN.............................................................................................35 HEADPHONE OUTPUT..............................................................................................35 DIGITAL AUDIO INTERFACE ....................................................................................36 PP Rev 1.77 May 2003 2 Product Preview WM8750L AUDIO INTERFACE CONTROL .................................................................................39 MASTER CLOCK AND AUDIO SAMPLE RATES .......................................................40 CONTROL INTERFACE .............................................................................................42 POWER SUPPLIES....................................................................................................43 POWER MANAGEMENT............................................................................................44 REGISTER MAP .................................................................................................46 DIGITAL FILTER CHARACTERISTICS..............................................................47 TERMINOLOGY .........................................................................................................47 DAC FILTER RESPONSES ................................................................................48 ADC FILTER RESPONSES ................................................................................49 DE-EMPHASIS FILTER RESPONSES ...............................................................50 HIGHPASS FILTER ............................................................................................51 APPLICATIONS INFORMATION ........................................................................52 RECOMMENDED EXTERNAL COMPONENTS .........................................................52 LINE INPUT CONFIGURATION .................................................................................53 MICROPHONE INPUT CONFIGURATION .................................................................53 MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS .......................................54 POWER MANAGEMENT EXAMPLES........................................................................54 PACKAGE DIMENSIONS ...................................................................................55 IMPORTANT NOTICE........................................................................................ 54 ADDRESS: .................................................................................................................56 PP Rev 1.77 May 2003 3 WM8750L PIN CONFIGURATION RINPUT3 / HPDETECT Product Preview ORDERING INFORMATION ORDER CODE W M8750LEFL 16 15 14 13 12 11 10 9 LINPUT3 MICBIAS HPVDD AGND AVDD VREF VMID TEMPERATURE RANGE -25°C to +85°C -25°C to +85°C PACKAGE 32-pin QFN (5x5x0.9mm) 32-pin QFN (5x5x0.9mm) (lead free) 32-pin QFN (5x5x0.9mm) (tape and reel) 32-pin QFN (5x5x0.9mm) (lead free, tape and reel) 24 23 22 21 20 19 18 17 RINPUT2 25 LINPUT2 26 RINPUT1 27 LINPUT1 28 MODE 29 CSB 30 SDIN 31 SCLK 32 1 2 3 4 5 6 7 8 LOUT2 ROUT2 HPGND LOUT1 ROUT1 OUT3 MONOOUT ADCLRC W M8750LSEFL W M8750LEFL/R -25°C to +85°C W M8750LSEFL/R -25°C to +85°C DACDAT DACLRC ADCDAT DCVDD DBVDD DGND MCLK BCLK Note: Reel quantity = 3500 PIN DESCRIPTION PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME MCLK DCVDD DBVDD DGND BCLK DACDAT DACLRC ADCDAT ADCLRC MONOOUT OUT3 ROUT1 LOUT1 HPGND ROUT2 LOUT2 HPVDD AVDD AGND VREF VMID MICBIAS RINPUT3 / HPDETECT LINPUT3 RINPUT2 LINPUT2 RINPUT1 LINPUT1 MODE CSB SDIN SCLK Supply Supply Supply Digital Input / Output Digital Input Digital Input / Output Digital Output Digital Input / Output Analogue Output Analogue Output Analogue Output Analogue Output Supply Analogue Output Analogue Output Supply Supply Supply Analogue Output Analogue Output Analogue Output Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Digital Input Digital Input Digital Input/Output Digital Input TYPE Digital Input Master Clock Digital Core Supply Digital Buffer (I/O) Supply Digital Ground (return path for both DCVDD and DBVDD) Audio Interface Bit Clock DAC Digital Audio Data Audio Interface Left / Right Clock/Clock Out ADC Digital Audio Data Audio Interface Left / Right Clock Mono Output Analogue Output 3 (can be used as Headphone Pseudo Ground) Right Output 1 (Line or Headphone) Left Output 1 (Line or Headphone) Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2) Right Output 1 (Line or Headphone or Speaker) Left Output 1 (Line or Headphone or Speaker) Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2, MONOUT) Analogue Supply Analogue Ground (return path for both AVDD and MVDD) Reference Voltage Decoupling Capacitor Midrail Voltage Decoupling Capacitor Microphone Bias Right Channel Input 3 or Headphone Plug-in Detection Left Channel Input 3 Right Channel Input 2 Left Channel Input 2 Right Channel Input 1 Left Channel Input 1 Control Interface Selection Chip Select / Device Address Selection Control Interface Data Input / 2-wire Acknowledge output Control Interface Clock Input PP Rev 1.77 May 2003 4 DESCRIPTION Product Preview WM8750L ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. The WM8750L has been classified as MSL1, which has an unlimited floor life at 0.584fs +/- 0.05dB -6dB 0.5465fs f > 0.5465fs -3dB -0.5dB -0.1dB DAC Filter Type 0 (USB mode, 250fs operation) Passband Passband Ripple Stopband Stopband Attenuation Passband Passband Ripple Stopband Stopband Attenuation Table 44 Digital Filter Characteristics f > 0.5465fs 0.5465fs -50 dB f > 0.584fs +/- 0.03dB -6dB 0.584fs -50 0 0.5fs +/- 0.03 dB 0.4535fs dB +/- 0.03dB -6dB 0 0.5fs +/-0.03 dB 0.416fs -60 3.7 10.4 21.6 dB Hz -60 0 0.5fs +/- 0.05 dB 0.4535fs dB dB ADC Filter Type 1 (USB mode, 272fs or Normal mode operation) DAC Filter Type 1 (USB mode, 272fs or Normal mode operation) TERMINOLOGY 1. 2. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple – any variation of the frequency response in the pass-band region PP Rev 1.77 May 2003 47 WM8750L DAC FILTER RESPONSES 0.02 0 Product Preview 0.01 -20 0 Response (dB) -40 Response (dB) 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.01 -0.02 -0.03 -0.04 -0.05 -60 -80 -100 -0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 21 DAC Digital Filter Frequency Response – Type 0 Figure 22 DAC Digital Filter Ripple – Type 0 0.02 0 0.01 -20 0 Response (dB) -40 Response (dB) -0.01 -0.02 -0.03 -0.04 -60 -80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 23 DAC Digital Filter Frequency Response – Type 1 Figure 24 DAC Digital Filter Ripple – Type 1 0.02 0 0.01 -20 0 Response (dB) -40 Response (dB) -0.01 -0.02 -0.03 -0.04 -60 -80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 25 DAC Digital Filter Frequency Response – Type 2 Figure 26 DAC Digital Filter Ripple – Type 2 PP Rev 1.77 May 2003 48 Product Preview 0.25 0 WM8750L 0.2 -20 0.15 0.1 Response (dB) Response (dB) -40 0.05 0 -0.05 -0.1 -60 -80 -0.15 -0.2 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.25 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 27 DAC Digital Filter Frequency Response – Type 3 Figure 28 DAC Digital Filter Ripple – Type 3 ADC FILTER RESPONSES 0.04 0 0.03 -20 0.02 Response (dB) -40 Response (dB) 0.01 0 -0.01 -0.02 -60 -80 -0.03 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 29 ADC Digital Filter Frequency Response – Type 0 0 Figure 30 ADC Digital Filter Ripple – Type 0 0.02 0.01 -20 0 Response (dB) -40 Response (dB) -0.01 -0.02 -0.03 -0.04 -60 -80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 31 ADC Digital Filter Frequency Response – Type 1 Figure 32 ADC Digital Filter Ripple – Type 1 PP Rev 1.77 May 2003 49 WM8750L 0.25 0 Product Preview 0.2 -20 0.15 0.1 Response (dB) Response (dB) -40 0.05 0 -0.05 -0.1 -60 -80 -0.15 -0.2 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.25 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 33 ADC Digital Filter Frequency Response – Type 2 Figure 34 ADC Digital Filter Ripple – Type 2 0.25 0 0.2 0.15 -20 0.1 Response (dB) Response (dB) -40 0.05 0 -0.05 -0.1 -60 -80 -0.15 -0.2 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.25 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 35 ADC Digital Filter Frequency Response – Type 2 Figure 36 ADC Digital Filter Ripple – Type 3 DE-EMPHASIS FILTER RESPONSES 0 0.4 0.3 -2 0.2 Response (dB) -4 Response (dB) 0.1 0 -0.1 -0.2 -6 -8 -0.3 -10 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000 -0.4 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000 Figure 37 De-emphasis Frequency Response (32kHz) Figure 38 De-emphasis Error (32kHz) PP Rev 1.77 May 2003 50 Product Preview 0 0.4 0.3 WM8750L -2 0.2 Response (dB) Response (dB) -4 0.1 0 -0.1 -0.2 -6 -8 -0.3 -0.4 -10 0 5000 10000 Frequency (Fs) 15000 20000 0 5000 10000 Frequency (Fs) 15000 20000 Figure 39 De-emphasis Frequency Response (44.1kHz) 0 Figure 40 De-emphasis Error (44.1kHz) 0.4 0.3 -2 0.2 Response (dB) Response (dB) -4 0.1 0 -0.1 -0.2 -6 -8 -0.3 -0.4 -10 0 5000 10000 Frequency (Fs) 15000 20000 0 5000 10000 Frequency (Fs) 15000 20000 Figure 41 De-emphasis Frequency Response (48kHz) Figure 42 De-emphasis Error (48kHz) HIGHPASS FILTER The WM8750L has a selectable digital highpass filter in the ADC filter path to remove DC offsets. The filter response is characterised by the following polynomial: H(z) = 1 - z-1 1 - 0.9995z-1 0 Response (dB) -5 -10 -15 Figure 43 ADC Highpass Filter Response 0 0.0005 0.001 Frequency (Fs) 0.0015 0.002 PP Rev 1.77 May 2003 51 WM8750L APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Product Preview DVDD AVDD 3 2 18 17 DBVDD DCVDD AVDD HPVDD DGND 4 DGND HPGND AGND 14 19 AGND C1 C2 C3 C4 DGND AGND 1 MCLK BCLK ADCLRC DACLRC DACDAT ADCDAT LOUT2 16 + ROUT2 15 8 OHM LOUDSPEAKER + C13 AUDIO INTERFACE (I2S/LJ/RJ/DSP) 5 9 7 6 8 MONOOUT 10 OUT3 11 32 OHM EAR SPEAKER + C14 + C15 HIGH for 3-wire LOW for 2-wire CONTROL INTERFACE (2 OR 3-WIRE) C7 C8 C9 29 LOUT1 MODE ROUT1 13 12 30 31 32 CSB SDIN SCLK WM8750L MICBIAS VREF VMID 22 20 16 OR 32 OHM HEADPHONES 28 27 26 25 24 23 LINPUT1 RINPUT1 LINPUT2 RINPUT2 AVDD + C5 DVDD + C6 C18 + C19 C20 21 C16 + C21 + C17 AGND C10 C11 LINPUT3 RINPUT3 / HPDETECT AGND DGND AGND See External Components Descriptions for details C12 Layout Notes: 1. C1 to C4, C16, C18 and C20 should be as close to the relative WM8750L connecting pin as possible. 2. AGND and DGND should be joined as close to the WM8750L as possible. Recommended External Components Diagram PP Rev 1.77 May 2003 52 Product Preview WM8750L SUGGESTED VALUE 100nF 10uF 1uF 2.2uF 220uF 100nF 10uF 100nF 10uF 100nF 10uF DESCRIPTION De-coupling for DBVDD, DCVDD, AVDD, HPVDD Reservoir capacitor for DVDD, AVDD. Should the supplies use separate sources then additional capacitors will be required of each additional source. AC input coupling capacitors Output AC coupling capacitors to remove DC level from MONOOUT Output AC coupling capacitors to remove DC level from headphone output (If used as a line-out only, use 2.2uF caps. In capless mode using OUT3 , no caps are needed) De-coupling for VMID. Reservoir capacitor for VMID De-coupling for VREF Reservoir capacitor for VREF De-coupling for MICBIAS – Not required if MICBIAS output is not used Reservoir capacitor for MICBIAS – Not required if MICBIAS output is not used COMPONENT REFERENCE C1 – C4 C5 – C6 C7 – C12 C13 C14 & C15 C16 C17 C18 C19 C20 C21 External Components Descriptions Note: 2 For Capacitors C5, C6, C17, C19 and C21 it is recommended that very low ESR components are used. LINE INPUT CONFIGURATION W hen LINPUT1/RINPUT1 or LINPUT2/RINPUT2 are used as line inputs, the microphone boost and ALC functions should normally be disabled. In order to avoid clipping, the user must ensure that the input signal does not exceed AVDD. This may require a potential divider circuit in some applications. It is also recommended to remove RF interference picked up on any cables using a simple first-order RC filter, as high-frequency components in the input signal may otherwise cause aliasing distortion in the audio band. AC signals with no DC bias should be fed to the WM8750L through a DC blocking capacitor, e.g. 1µF. MICROPHONE INPUT CONFIGURATION MICBIAS R1 680 Ohm to 2.2kOhm check microphone's specification LINPUT1/2/3 RINPUT1/2/3 FROM MICROPHONE C2 1uF AGND R2 47kOhm C1 220pF AGND AGND Figure 44 Recommended Circuit for Line Input For interfacing to a microphone, the ALC function should be enabled and the microphone boost switched on. Microphones held close to a speaker’s mouth would normally use the 13dB gain setting, while tabletop or room microphones would need a 29dB boost. The recommended application circuit is shown above. R1 and R2 form part of the biasing network (refer to Microphone Bias section). R1 connected to MICBIAS is necessary only for electret type microphones that require a voltage bias. R2 should always be present to prevent the microphone input from charging to a high voltage which may damage the microphone on connection. R1 and R2 PP Rev 1.77 May 2003 53 WM8750L Product Preview should be large so as not to attenuate the signal from the microphone, which can have source impedance greater than 2kOhm. C1 together with the source impedance of the microphone and the WM8750L input impedance forms an RF filter. C2 is a DC blocking capacitor to allow the microphone to be biased at a different DC voltage to the MICIN signal. MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS To minimise any pop or click noise when the system is powered up or down, the following procedures are recommended. POWER UP • Switch on power supplies. By default the WM8750L is in Standby Mode, the DAC is digitally muted and the Audio Interface, Line outputs and Headphone outputs are all OFF (DACMU = 1 Power Management registers 1 and 2 are all zeros). Enable Vmid and VREF, then wait for time TBD Enable DACs as required Enable line and / or headphone output buffers as required. Set DACMU = 0 to soft-un-mute the audio DACs. Set DACMU = 1 to soft-mute the audio DACs. Disable all output buffers, then wait for time TBD. Switch off the power supplies. • • • • • • • POWER DOWN POWER MANAGEMENT EXAMPLES OPERATION MODE VR POWER MANAGEMENT (1) PGAs AI POWER MANAGEMENT (2) DACs MBI DAL DAR LO1 ADCs ADR Output Buffers RO1 LO2 RO2 MO HPD PGL PGR ADL Stereo Headphone Playback Stereo Line-in Record Stereo Microphone Record Mono Microphone Record Stereo Line-in to Headphone Out Phone Call Speaker Phone Call [ROUT2INV = 1] Record Phone Call [L channel = mic with boost, R channel = RX, enable mono mix] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 x 0 0 0 x x 0 x PP Rev 1.77 May 2003 54 Product Preview WM8750L PACKAGE DIMENSIONS FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH DM030.C CORNER TIE BAR 5 25 D2 B D2/2 32 SEE DETAIL A D L 24 1 INDEX AREA (D/2 X E/2) E2/2 A E2 SEE DETAIL B E 17 8 2X 16 e 15 B 9 b 2X aaa C aaa C TOP VIEW ccc C (A3) 1 A 0.08 C A1 SEATING PLANE 1 e/2 TERMINAL TIP L 1 DETAIL A 32x b bbb M C A B CORNER TIE BAR 5 C 43 0. DETAIL B DATUM m m 6 56 0. 32x K m m EXPOSED CENTRE PAD R e 1 L1 L1 R Symbols A A1 A3 b D D2 E E2 e L L1 R K aaa bbb ccc REF: MIN 0.85 0 0.18 4.90 3.2 4.90 3.2 0.35 1 b(min)/2 0.20 Tolerances of Form and Position 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VKKD-2 Dimensions (mm) NOM MAX 0.90 1.00 0.02 0.05 0.2 REF 0.23 0.30 5.00 5.10 3.3 3.4 5.00 5.10 3.3 3.4 0.5 BSC 0.4 0.45 0.1 NOTE 1 2 2 NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF ETCHING OF LEADFRAME. 2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY PP Rev 1.77 May 2003 55 WM8750L IMPORTANT NOTICE Product Preview W olfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: W olfson Microelectronics plc 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com PP Rev 1.77 May 2003 56