WM8756

WM8756 192kHz, Six Channel SACD™ Compatible Audio DAC DESCRIPTION The WM8756 is a high performance 6-channel DAC designed for audio applications such as SACD™ players, DVD-V and DVD-A, home audio and theatre systems. The device supports data input word lengths from 16 to 32-bits and sampling rates up to 192kHz. The WM8756 can implement 2 or 6 channels at 192kHz for high-end DVDAudio, or 6 channels at up to 192kHz for surround applications. Additionally 64x DSD bitstream support is offered on all 6 channels. The WM8756 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and 6 DACs in a 48-pin TQFP package. The WM8756 also includes a digitally controllable mute and attenuator function on each channel, accessible during PCM operation. An on-chip multiplexer selects between PCM or DSD audio data input pins. The WM8756 supports hardware or software connection schemes for audio DAC control. The serial control interface provides access to a wide range of features including onchip mute, attenuation and phase reversal. Hardware pincontrollable operation is also available. The WM8756 is an ideal device for all surround sound applications supporting the SACD™ audio format, such as SACD players, multi-format players and home entertainment systems. FEATURES • • • • • • • • 6-Channel DAC with PCM or Bitstream (DSD) operation. DSD 64x Bitstream Support for Super Audio CD™ Independent input pins for PCM and DSD data with onchip multiplexer THD –96dB, SNR 106dB (‘A’ weighted @ 48kHz) PCM mode Sampling Rate: 8kHz – 192kHz Master or slave operation with Normal or Phase modulation method of DSD data transfer 3-Wire Serial Control Interface Programmable PCM Audio Data Interface Modes − I2S, Left, Right Justified or DSP − 16/20/24/32 bit Word Lengths Independent Digital Volume Control on Each Channel with 127.5dB Range in 0.5dB Steps (in PCM mode) 3.0V – 5.5V Supply (3.3V digital / 5V analogue option) 48-pin TQFP Package • • • APPLICATIONS • • • Super Audio CD (SACD™) Players Universal and Multi-Format disc players Home theatre systems BLOCK DIAGRAM CSB SCKI ML/I2S MC/IWL MD/DM DSDB MODE MUTE DMSLV DMCKSEL CONTROL INTERFACE PCM/DSD BCKIN LRCIN LRCIN2 DIN0 DIN1 DIN2 PCM DATA DIGITAL FILTERS SIGMA DELTA MODULATOR MUX RIGHT DAC LOW PASS FILTER LOW PASS FILTER OUT0R GR0 SIGMA DELTA MODULATOR MUX PCM/DSD SIGMA DELTA MODULATOR AUDIO INTERFACE DSDCLK128 DSDCLK64 PCM/DSD DSD0 DSD1 DSD2 DSD3 DSD4 DSD5 DSD DATA DIGITAL FILTERS SIGMA DELTA MODULATOR MUX RIGHT DAC LOW PASS FILTER LOW PASS FILTER OUT2R GR2 SIGMA DELTA MODULATOR MUX LEFT DAC OUT2L DIGITAL FILTERS RIGHT DAC LOW PASS FILTER LOW PASS FILTER LEFT DAC OUT0L MUX OUT1R GR1 SIGMA DELTA MODULATOR MUX LEFT DAC OUT1L DVDD DGND AGND1 AGND2 AGND3 AVDD1 AVDD2 WOLFSON MICROELECTRONICS LTD www.wolfsonmicro.com Advance Information October 2001, Rev 1.3 Copyright 2001 Wolfson Microelectronics Ltd. WM8756 PIN CONFIGURATION DMCKSEL DMSLV Advance Information ORDERING INFORMATION DEVICE AVDD1 TEMP. RANGE -25 to +85oC PACKAGE 48-pin TQFP BCKIN LRCIN DVDD SCKI DIN0 WM8756EFT nc nc nc DIN1 DIN2 DSD0 DSD1 DSD2 DSD3 DSD4 DSD5 DSDCLK64 DSDCLK128 MODE MUTE 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 nc OUT0R GR0 OUT0L AGND3 OUT1R GR1 OUT1L AGND2 AGND1 OUT2R GR2 OUT2L 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DGND DSDB CSB MC/IWL nc MD/DM CAP LRCIN2 AVDD2 ML/I2S nc nc AI Rev 1.3 October 2001 2 WM8756 PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37-39 40 41 42 43 44 45 46 47 48 NAME DIN1 DIN2 DSD0 DSD1 DSD2 DSD3 DSD4 DSD5 DSDCLK64 DSDCLK128 MODE MUTE LRCIN2 DSDB DGND ML/I2S MC/IWL MD/DM CSB n.c. AVDD2 n.c. CAP n.c. OUT2L GR2 OUT2R AGND1 AGND2 OUT1L GR1 OUT1R AGND3 OUT0L GR0 OUT0R nc AVDD1 nc DMSLV DMCKSEL DVDD SCKI BCKIN LRCIN DIN0 TYPE Digital input Digital input Digital input p.d. Digital input p.d. Digital input p.d. Digital input p.d. Digital input p.d. Digital input p.d. Digital In/Out Digital In/Out Digital input Digital In/Out Digital input p.d. Digital input p.u. Supply Digital input p.u. Digital input p.u. Digital input Digital input p.d. n.c. Supply n.c. Analogue output n.c. Analogue output Analogue input Analogue output Supply Supply Analogue output Analogue input Analogue output Supply Analogue output Analogue input Analogue output nc Supply nc Digital input p.d. Digital input p.d. Supply Digital input Digital input Digital input Digital input DESCRIPTION Channel 1 Serial Audio Data Input in PCM Mode. Channel 2 Serial Audio Data Input in PCM Mode. Channel 0 Left DSD format audio data input Channel 0 Right DSD format audio data input Channel 1 Left DSD format audio data input Channel 1 Right DSD format audio data input Channel 2 Left DSD format audio data input Channel 2 Right DSD format audio data input DSD format data clock at 64fs Advance Information DSD format data clock at 128fs (used in ‘modulated data’ mode) Control Method Selection Pin in PCM Mode. ‘lo’ = software mode Mute Control Pin in PCM Mode. ‘lo’ = not muted Second LRCIN input for dual rate mode DSD or PCM audio data format select; ‘lo’ = DSD mode, ‘hi’ = PCM mode Digital GND Software mode: in 3-Wire Serial Control mode, Latch input. Hardware Mode: Input Format Selection: Software Mode: In 3-Wire Serial Control Mode, Clock Input. Hardware mode: Input Word Length Selection: Software mode: In 3-Wire Serial Control Mode, Data Input. Hardware mode: De-emphasis selection 3-wire Serial Port Chip select – active low No internal connection Analogue Positive DAC Reference No internal connection Analogue Internal Mid-Rail Reference De-Coupling Point No internal connection Left Channel 2 Output. Channel 2 Negative Reference. Right Channel 2 Output. Analogue GND Analogue GND Left Channel 1 Output. Channel 1 Negative Reference. Right Channel 1 Output. Analogue GND Left Channel 0 Output. Channel 0 Negative Reference. Right Channel 0 Output. No internal connection Analogue positive supply No internal connection DSD mode master or slave operation select; ‘lo’ = SLAVE (clocks are input) DSD Master Mode Clock Select (lo for 256fs; hi for 384fs) Digital Positive Supply. Master Clock Input Audio Data Bit Clock Input. DAC Sample Rate Clock Input in PCM Mode Channel 0 Serial Audio Data Input in PCM Mode. Note - Digital input pins have Schmitt trigger input buffers. Pins marked ‘p.u.’ or ‘p.d.’ have internal pull-up or pull down. AI Rev 1.3 October 2001 3 WM8756 ABSOLUTE MAXIMUM RATINGS Advance Information Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature Lead temperature (soldering 10 seconds) Lead temperature (soldering 2 minutes) Table 1 Absolute maximum ratings MIN -0.3V -0.3V DGND -0.3V AGND -0.3V -25°C -65°C MAX +7V +7V DVDD +0.3V AVDD +0.3V 37MHz +85°C +150°C +240°C +183°C AI Rev 1.3 October 2001 4 WM8756 DC ELECTRICAL CHARACTERISTICS PARAMETER Digital supply range Analogue supply range Ground Difference of DGND to AGND Difference of GR to AGND Analogue supply current Digital supply current Analogue supply current Digital supply current Analogue supply current Digital supply current Table 2 DC electrical characteristics Note: 1. AVDD must be equal or greater than DVDD. DVDD = 3V, AVDD = 5V is allowed. AVDD = 5V DVDD = 5V AVDD = 3.3V DVDD = 3.3V Power down, stop clock Power down, stop clock SYMBOL DVDD AVDD AGND, DGND -0.3 -0.3 TEST CONDITIONS MIN 3.0 3.0 0 0 0 58 22 57 11 0.4 0.09 TYP Advance Information MAX 5.5 5.5 +0.3 +0.3 UNIT V V V V V mA mA mA mA mA mA 2. Where used AVDD represents AVDD1 = AVDD2, AGND represents AGND1 = AGND2 = AGND3 and GR represents GR0 = GR1 = GR2. AC ELECTRICAL CHARACTERISTICS Test Conditions AVDD = DVDD = 3V, AGND = 0V = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage Potential divider resistance 0dBFs Full scale output voltage SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) VCAP RCAP At DAC outputs A-weighted, @ fs = 48KHz A-weighted @ fs = 96KHz A-weighted @ fs = 192KHz A-weighted, @ fs = 48KHz AVDD=DVDD=3.3V A-weighted @ fs = 96KHz AVDD=DVDD=3.3V 100 98 AVDD2 – GR2/2 25K 1.1 x AVDD1/5 106 105 105 103 V Ohms Vrms dB dB dB dB VIL VIH VOL VOH IOL = 2mA IOH = 2mA 2.4 2.0 0.4 0.8 V V V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC Output (Load = 10K ohms. 50pF) SNR (Note 1,2,3) 103 dB AI Rev 1.3 October 2001 5 WM8756 Advance Information Test Conditions AVDD = DVDD = 3V, AGND = 0V = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SNR (Note 1,2,3) SYMBOL TEST CONDITIONS Non ‘A’ weighted @ fs = 48kHz AVDD=DVDD=5V 1KHz, 0dBFs 1kHz, -60dBFs -90 100 MIN TYP 103 MAX UNIT dB THD (Note 1,2,3) THD+N (Dynamic range, Note 2) DAC channel separation Analogue Output Levels Output level -95 -106 0.555fs SYMBOL TEST CONDITIONS ±0.05 dB -3dB MIN 0.444fs 0.487fs TYP Advance Information MAX UNIT dB ±0.05 -60 dB dB SACD FILTER CHARACTERISTICS With 64fs DSD data where fs = 44.1ks/s. RESPONSE Pass band peak ripple Attenuation at 20kHz Attenuation at 50kHz Attenuation at 100kHz FILTER RESPONSE WITHOUT POSTFILTER 0.017dB -0.012dB -2.3dB -15.5dB FILTER RESPONSE WITH 3RD ORDER BUTTERWORTH POST-FILTER (-3dB AT 55KHZ) 0.017dB -0.021dB -3.9dB -31dB Table 5 Overall frequency response in SACD mode. TERMINOLOGY 1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region. 3. 4. 5. 6. AI Rev 1.3 October 2001 7 WM8756 MASTER CLOCK TIMING tSCKIL SCKI tSCKIH tSCKIY Advance Information Figure 1 Master Clock Timing Requirements Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER System Clock Timing Information SCKI System clock pulse width high SCKI System clock pulse width low SCKI System clock cycle time SCKI Duty cycle SYMBOL tSCKIH tSCKIL tSCKIY TEST CONDITIONS MIN 13 13 26 40:60 TYP MAX UNIT ns ns ns 60:40 Table 6 Master Clock Timing Requirements DIGITAL AUDIO INTERFACE TIMING LRCIN tBCH BCKIN tBCY DIN0/1/2 tDS tDH tBL tBCL tLB Figure 2 PCM Digital Audio Data Timing Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER BCKIN cycle time BCKIN pulse width high BCKIN pulse width low LRCIN set-up time to BCKIN rising edge LRCIN hold time from BCKIN rising edge DIN0/1/2 set-up time to BCKIN rising edge DIN0/1/2 hold time from BCKIN rising edge Table 7 PCM Digital Audio Timing AI Rev 1.3 October 2001 8 SYMBOL tBCY tBCH tBCL tLB tBL tDS tDH TEST CONDITIONS MIN 40 16 16 8 8 8 8 TYP MAX UNIT ns ns ns ns ns ns ns Audio Data Input Timing Information WM8756 DSD AUDIO MONOPHASE INTERFACE t DCL DSDCLK64 tDCY DSD[0:5] tDS tDH t DCH Advance Information Figure 3 DSD Audio Data Timing – Normal Mode Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER DSDCLK64 cycle time DSDCLK64 pulse width high DSDCLK64 pulse width low DSD[5:0] set-up time to DSDCLK64 rising edge DSD[5:0] hold time from DSDCLK64 rising edge SYMBOL tDCY tDCH tDCL tDS tDH 80 80 10 10 TEST CONDITIONS MIN TYP 354.4 MAX UNIT ns ns ns ns ns Audio Data Input Timing Information Table 8 DSD Audio Data Timing – Normal Mode AI Rev 1.3 October 2001 9 WM8756 DSD AUDIO BIPHASE INTERFACE Advance Information tDIFF DSDCLK64 t BDCH DSDCLK128 t BDCL t BDCY64 tBDCY128 DSD[0:5] inverse D(n-1) t BDS D(n) t BDH inverse D(n) Figure 4 DSD Audio Data Timing - Phase Modulation Mode Test Conditions AVDD= DVDD = 5V, AGND= GR= DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER DSDCLK64 cycle time DSDCLK128 cycle time DSDCLK128 pulse width high DSDCLK128 pulse width low DSD[0:5] set-up time to DSDCLK128 rising edge DSD[0:5] hold time from DSDCLK128 rising edge Difference in edge timing of DSDCLK64 to DSDCLK128 Table 9 DSD Digital Audio Timing SYMBOL tBDCY64 tBDCY128 tBDCH tBDCL tBDS tBDH tDIFF 80 80 10 10 20 TEST CONDITIONS MIN TYP 354.4 177.2 MAX UNIT ns ns ns ns ns ns ns Audio Data Input Timing Information AI Rev 1.3 October 2001 10 WM8756 DIGITAL CONTROL INTERFACE TIMING tMLL ML/I2S tMCY tMCH MC/IWL tMCL tSCS tCSS tMLH Advance Information MD/DM tDSU tDHO LSB Figure 5 Control Interface Input Timing: 3-Wire Serial Control Mode Test Conditions AVDD= DVDD = 5V, AGND= GR= DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER MC/IWL rising edge to ML/I2S rising edge MC/IWL pulse cycle time MC/IWL pulse width low MC/IWL pulse width high MD/DM to MC/IWL set-up time MC/IWL to MD/DM hold time ML/I2S pulse width low ML/I2S pulse width high ML/I2S rising to MC/IWL rising SYMBOL tSCS tMCY tMCL tMCH tDSU tDHO tMLL tMLH tCSS TEST CONDITIONS MIN 60 80 20 20 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns Program Register Input Information Table 10 Control Interface Input Timing Information AI Rev 1.3 October 2001 11 WM8756 DEVICE DESCRIPTION INTRODUCTION Advance Information WM8756 is a complete 6-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and output smoothing filters. The device is implemented as three separate stereo DACs in a single package and controlled by a single interface. Each DAC has its own data input DIN0/1/2, and LRCIN, BCKIN and SCKI are shared between them. Additionally DSD compatible bitstream operation at 64x oversampling is supported on all 6 channels. Selection of normal PCM operation or this additional DSD mode is determined by the input level on the DSDB pin (14). Control of internal functionality of the device is by either hardware control (pin programmed) or software control (3-wire serial control interface). The MODE pin selects between hardware and software control. In software control mode, a 3 wire SPI type interface is used. This interface may be asynchronous to the audio data interface. Control data will be re-synchronized to the audio processing internally. Operation using a system clock of 256fs, 384fs or 512fs is provided, selection between clock rates being automatically controlled in hardware mode, or serially controlled when in software mode. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate system clock is input. Support is also provided for up to 192ks/s using a system clock of 128fs or 192fs. In normal PCM mode, the audio data interface supports right, left and I2S (Philips left justified, one bit delayed) interface formats along with a highly flexible DSP serial port interface. When in hardware mode, the three serial interface pins become control pins to allow selection of input data format type (I2S or right justified), input word length (16, 20, 24, or 32-bit) and de-emphasis functions. In DSD mode, a separate bitstream data input pin is required for each of the 6 channels, plus a 64fs dataclock DSDCLK64. These signals are applied via separate pins (pins 3-9) and the signals multiplexed internally into the DAC circuits, under control of the DSDB mode select pin (14). Additionally in DSD mode, a Phase Modulation scheme is supported, where the audio data is transmitted as a Manchester type, bi-phase encoded bitstream. This has the advantage of removing the significant audio spectral energy from the datastream, so minimising digital signal corruption of the analogue outputs. In order to simplify decoding of this phase modulated data, a 2x speed clock (DSDCLK128) is used to sample the incoming data. This ‘modulated’ mode is auto-detected from the presence of a clock signal on the DSDCLK128 pin. In DSD mode, clocks for the DAC can be inputs (WM8756 in SLAVE mode) or outputs (WM8756 in MASTER mode). When clocks are outputs, SCKI remains an input, the lower rate clocks being derived by dividing this master clock signal. Depending upon the setting on the DMCKSEL pin, a master clock of either 256fs or 384fs may be used as input, from which the DSD clocks will be derived appropriately. AUDIO DATA SAMPLING RATES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The external master system clock can be applied directly through the SCKI input pin with no software configuration necessary. Note that on the WM8756, SCKI is used to derive clocks for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC. The system clock for WM8756 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The system clock is used to operate the digital filters and the noise shaping circuits. The WM8756 has a system clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 system clocks). If greater than 32 clocks error, the interface switches to 768fs and holds the output at the level of the last sample. The system clock should be synchronised with LRCIN, although the WM8756 is tolerant of phase differences or jitter on this clock. Table 11 shows the typical system clock frequency inputs for the WM8756. AI Rev 1.3 October 2001 12 WM8756 SAMPLING RATE (LRCIN) 32kHz 44.1kHz 48kHz 96kHz 192kHz SYSTEM CLOCK FREQUENCY (MHZ) 128fs 4.096 5.6448 6.114 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 Unavailable 384fs 12.288 16.9340 18.432 36.864 Unavailable Advance Information 512fs 16.384 22.5792 24.576 Unavailable Unavailable 768fs 24.576 33.8688 36.864 Unavailable Unavailable Table 11 System Clock Frequencies Versus Sampling Rate DSD MODE When pin 14, DSDB pin is held low, the device is reconfigured to operate as a DSD or ‘bitsteam’ compatible DAC. That is, the input audio data is in a sigma delta modulated form, or pulse density modulated. In this case the only signals required are the bitstream for each channel supported, and the oversampling clock. WM8756 supports this mode when run at a 64x oversample rate. That is, the bitstream data is supplied at a rate of 64 bits per normal word clock. Of course no word clock is provided, and the actual spectral content of the data is determined by the noise shaping that was used to create the bitstream. WM8756 can support six channels of bitstream or DSD audio. Data BITSTREAMS and the 64fs clock are applied to pins 3-9 and 10, if the DSDCLK128 pin is used. Signals applied to the PCM input pins 1,2, 45-48 are ignored. The DSDB signal controls an internal multiplexor which switches the signals on the DSD input pins into the DAC rather than the PCM signals. In DSD mode operation, the entire digital filter on WM8756 is disabled, and the bitstream data is applied directly to the multi-bit switched capacitor DAC’s in the analogue part of the device. There, rather than operate as oversampled multi bit DACs, the DAC inputs are reconfigured to act as analogue FIR filters, so providing both D to A conversion of the bitstream data, and analogue smoothing of the sampled waveform with no phase distortion. Filter responses of the analogue filter that results are shown in Figure 26 - Figure 29. Note in DSD mode software controlled functions such as digital volume control and phase reversal, are not available. The FIR filter response is designed such that by adding only a 3rd order Butterworth type post DAC filter, which may be implemented with a single op-amp, the Scarlet book specified filter requirements may be met, saving cost over the 5th order filter normally needed. It is normally desirable to use an external analogue post-DAC filter, particularly in the case of DSD operation due to the presence of high frequency energy as a result of the aggressive high order noise shaping used in the creation of the modulated DSD datastream. The analogue FIR filter used in WM8756 provides useful filtering of this noise, but it may be desirable to add further post filtering using active RC filters. Figure 26 - Figure 29 show the overall filter response of the combined DAC filter operating in DSD mode with an external 3th order Butterworth active RC post-DAC filter. PCM DIGITAL AUDIO INTERFACE PCM audio data is applied to the internal DAC filters via the PCM Digital Audio Interface. 5 popular interface formats are supported: • • • • • Left Justified mode Right Justified mode I2S mode DSP Early mode DSP Late mode All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits except that 32 bit data is not supported in right justified mode. DIN0/1/2 and LRCIN are sampled on the rising, or falling edge of BCKIN. In left justified, right justified and I2S modes, the digital audio interface receives data on the DIN0/1/2 inputs. Audio Data for each stereo channel is time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of BCKINs per LRCIN period is 2 times the selected word length. LRCIN must be high for a minimum of word length BCKINs and low for a AI Rev 1.3 October 2001 13 WM8756 Advance Information minimum of word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements are met. The WM8756 will automatically detect when data with a LRCIN period of exactly 32 is sent, and select 16 bit mode - overriding any previously programmed word length. Word length will revert to the previously programmed value if a LRCIN period other than 32 is detected. In DSP early or DSP late mode, all 6 channels are time multiplexed onto DIN0. LRCIN is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCKINs per LRCIN period is 6 times the selected word length. Any mark to space ratio is acceptable on LRCIN provided the rising edge is correctly positioned (see Figures 9 and 10). LEFT JUSTIFIED MODE In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN transition. LRCIN is high during the left samples and low during the right samples. 1/fs LEFT CHANNEL LRCIN RIGHT CHANNEL BCKIN DIN0/1/2 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n MSB LSB MSB LSB Figure 6 Left Justified Mode Timing Diagram RIGHT JUSTIFIED MODE In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN transition. LRCIN is high during the left samples and low during the right samples. 1/fs LEFT CHANNEL LRCIN RIGHT CHANNEL BCKIN DIN0/1/2 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n MSB LSB MSB LSB Figure 7 Right Justified Mode Timing Diagram AI Rev 1.3 October 2001 14 WM8756 I S MODE 2 Advance Information In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN transition. LRCIN is low during the left samples and high during the right samples. 1/fs LEFT CHANNEL LRCIN RIGHT CHANNEL BCKIN 1 BCKIN 1 BCKIN 3 n-2 n-1 n 1 2 3 n-2 n-1 n DIN0/1/2 1 2 MSB LSB MSB LSB Figure 8 I2S Mode Timing Diagram DSP EARLY MODE In DSP early mode, the first bit is sampled on the BCKIN edge following the one which detects a low to high transition on LRCIN. 1 BCKIN 1/fs 1 BCKIN LRCIN BCKIN CHANNEL 0 LEFT DIN0 1 2 n-1 n 1 2 CHANNEL 0 RIGHT n-1 n CHANNEL 1 LEFT 1 2 CHANNEL 2 RIGHT n-1 n NO VALID DATA MSB LSB Input Word Length (IWL) Figure 9 DSP Early Mode Timing Diagram DSP LATE MODE In DSP late mode, the first bit is sampled on the BCKIN edge which detects a low to high transition on LRCIN. 1/fs LRCIN BCKIN CHANNEL 0 LEFT DIN0 1 2 n-1 n 1 2 CHANNEL 0 RIGHT n-1 n CHANNEL 1 LEFT 1 2 CHANNEL 2 RIGHT n-1 n NO VALID DATA 1 MSB LSB Input Word Length (IWL) Figure 10 DSP Late Mode Timing Diagram In both early and late DSP modes, DAC0 left is always sent first, followed immediately by data words for the other 5 channels. No BCKIN edges are allowed between the data words. The word order is DAC0 left, DAC0 right, DAC1 left, DAC1 right, DAC2 left, DAC2 right. AI Rev 1.3 October 2001 15 WM8756 SPLIT RATE MODE Advance Information The WM8756 can be used with differing sample rates on the front and rear channels. This allows extremely high quality audio to be played on the front two channels whilst the other channels use normal high quality data streams. This mode will only work with a front data rate of 192kHz and a rear rate of 96kHz but can be used with all the normal data formats except the two DSP modes and with the system at either 128fs or 192fs see Figure 11. When running in split rate mode all the channels are clocked in using a common BCKIN; the front channels using LRCIN and all the other channels using LRCIN2 see Figure 11. 2/fs LEFT CHANNEL LRCIN RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL BCKIN DIN0 12 n 12 n 12 n 12 n MSB LSB MSB LSB MSB LSB MSB LSB LRCIN2 LEFT CHANNEL RIGHT CHANNEL DIN1/2 12 n 12 n MSB LSB MSB LSB Figure 11 Split Rate Audio Mode Timing Diagram Notes: 1. Figure 11 shows the timing for left justified. However, this is similar for right justified and I2S. 2. The edges of LRCIN and LRCIN2 must be coincidental. AI Rev 1.3 October 2001 16 WM8756 MODES OF OPERATION Advance Information Control of the various modes of operation for the WM8756 is either by software control over the serial interface, or by hardwired pin control. Selection of software or hardware mode is via the MODE pin. The following functions may be controlled either via the serial control interface or by hard wiring of the appropriate pins. Note : In DSD mode, the control interface is available but none of the functions will have any effect except the PDWN bit because the DSD data by-passes the majority of the signal processing. FUNCTION OPTIONS Input audio data format Right justified Left justified I2S format DSP formats 16 20 24 32 On Off On Off Normal Inverted Lch, Rch individually Lch, Rch common On Off SOFTWARE CONTROL DEFAULT VALUE PIN 11: MODE = 0 FMT = 00 (default) FMT = 01 FMT = 10 FMT = 11 IWL[1:0] = 00 IWL[1:0] = 01 IWL[1:0] = 10 (default) IWL[1:0] = 11 DEEMPH = 1 DEEMPH = 0 (Default) MUTE = 1 MUTE = 0 (default) LRP = 0 (default) LRP = 1 ATC = 0; 0dB (default) ATC = 1 IZD = 1 IZD = 0 (default) HARDWARE CONTROL BEHAVIOUR PIN 11: MODE = 1 Pin 16, 17: ML/I2S, MC/IWL = 00, 01 or 10 Not available in hardware mode Pin 16, 17: ML/I2S, MC/IWL = 11 Not available in hardware mode Pin 16, 17: ML/I2S, MC/IWL = 00 (RJ) Pin 16, 17: ML/I2S, MC/IWL = 01 (RJ) Pin 16, 17: ML/I2S, MC/IWL = 10 (RJ) Pin 16, 17: ML/I2S, MC/IWL = 11 (I2S) Pin 18: MD/DM = 1 Pin 18: MD/DM = 0 Pin 12: MUTE = 1 Pin 12: MUTE = 0 Not available in hardware mode, default value set Not available in hardware mode, gain defaults to 0dB Input word length De-emphasis selection Mute Input LRCIN polarity Volume control Infinite zero detect Automute function controlled from MUTE pin low = never mute floating = automute enable high = mute Run SCKI Stop SCKI Not available in hardware mode Power down DAC output control Chip on Chip off See Table 13 for all options PDWN = 0 (default) PDWN = 1 Default is PL[3:0] = 1001, stereo mode Table 12 Control Function Summary AI Rev 1.3 October 2001 17 WM8756 SOFTWARE CONTROL MODES DIGITAL AUDIO INTERFACE CONTROL REGISTERS Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS 0000011 Interface Control BIT 1:0 LABEL FMT[1:0] DEFAULT 00 Advance Information DESCRIPTION Interface format Select 00 : right justified mode 01: left justified mode 10: I2S mode 11: DSP (early or late) mode In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCIN. If this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 6, Figure 7 and Figure 8. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. REGISTER ADDRESS 0000011 Interface Control BIT 2 LABEL LRP DEFAULT 0 DESCRIPTION LRCIN Polarity 0 : normal LRCIN polarity 1: inverted LRCIN polarity In DSP modes, the LRCIN register bit is used to select between early and late modes: REGISTER ADDRESS 0000011 Interface Control BIT 2 LABEL LRP DEFAULT 0 DESCRIPTION DSP Format 0 : Early DSP mode 1: Late DSP mode By default, LRCIN and DIN0/1/2 are sampled on the rising edge of BCKIN and should ideally change on the falling edge. Data sources which change LRCIN and DIN0/1/2 on the rising edge of BCKIN can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the inverse of that shown in Figures 6, 7 and 8. REGISTER ADDRESS 0000011 Interface Control BIT 3 LABEL BCP DEFAULT 0 DESCRIPTION BCKIN Polarity 0 : normal BCKIN polarity 1: inverted BCKIN polarity The IWL[1:0] bits are used to control the input word length. REGISTER ADDRESS 0000011 Interface Control BIT 5:4 LABEL IWL[1:0] DEFAULT 10 DESCRIPTION Input Word Length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data Note: If 32-bit mode is selected in right justified mode, the WM8756 defaults to 24 bits. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8756 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. AI Rev 1.3 October 2001 18 WM8756 Advance Information The REV[2:0] bits are used to invert the phase of the DAC outputs. REV0 controls phase of DAC0, REV1 controls phase of DAC1 and REV2 controls phase of DAC2. REGISTER ADDRESS 0000011 Interface Control BIT 8:6 LABEL REV[2:0] DEFAULT 000 DESCRIPTION Output phase direction 1 in bit 6 reverses OUT0L/R. 1 in bit 7 reverses OUT1L/R. 1 in bit 8 reverses OUT2L/R. MUTE MODES Setting the MUTE register bit will apply a 'soft' mute to the input of the digital filters: REGISTER ADDRESS 0000010 DAC Channel Control BIT 0 LABEL MUTE DEFAULT 0 DESCRIPTION Soft Mute select 0 : Normal Operation 1: Soft mute all channels 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006 Figure 12 Application and Release of Soft Mute Figure 12 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VCAP with a time constant of approximately 64 input samples. If MUTE is applied for 1024 or more input samples, the outputs will be connected directly to VCAP - this feature can be disabled using the IZD (infinite zero detect) bit. When MUTE is de-asserted, the output will restart almost immediately from the current input sample. Note that all other means of muting the DAC channels (setting the PL[3:0] bits to 0, setting the PDWN bit or setting attenuation to 0) will cause much more abrupt muting of the output. Setting the IZD register bit will enable the internal analogue mute feature: REGISTER ADDRESS 0000010 DAC Channel Control BIT 4 LABEL IZD DEFAULT 0 DESCRIPTION Internal Analogue Mute Disable 0 : Disable Analogue Mute 1: Enable Analogue Mute AI Rev 1.3 October 2001 19 WM8756 Advance Information With IZD enabled, applying MUTE for 1024 consecutive input samples will cause all outputs to be connected directly to VCAP. Additionally, if 2048 consecutive zero input samples are applied to all 6 channels, and IZD=0, internal analogue mute will be applied. It will be removed as soon as any channel receives a non-zero input. The MUTE pin can be used as an input. In this case it performs the same function as the MUTE register bit. Driving the MUTE pin high will apply a 'soft' mute. Driving it low again, will remove the MUTE immediately. Note that this hardware mute feature doesn't require the MODE pin to be set high. MUTE PIN 0 1 floating Normal Operation Mute all DAC channels DESCRIPTION Enable IZD, Mute becomes an output to indicate when IZD occurs. A diagram showing how the various Mute modes interact is shown below in Figure 13. IZD (Register Bit) AUTOMUTED (Internal Signal) 10kΩ MUTE PIN SOFTMUTE (Internal Signal) MU (Register Bit) Figure 13 Selection Logic for MUTE Modes The MUTE pin behaves as a bi-directional function, that is, as an input to select MUTE or NOT-MUTE, or as an output indication of automute operation. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of zero value audio samples of 1024 samples long being applied to all 6 channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR’ed through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert MUTE. If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a source follower, or diode, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits. The automute signal is AND’ed with IZD, this qualified mute signal then being OR’ed into the SOFTMUTE control. Therefore, in software mode, automute operation may be controlled with IZD control bit. AI Rev 1.3 October 2001 20 WM8756 DE-EMPHASIS MODE Advance Information Setting the DEEMPH register bit puts the all the digital filters into de-emphasis mode: REGISTER ADDRESS 0000010 DAC Channel Control BIT 1 LABEL DEEMPH DEFAULT 0 DESCRIPTION De-emphasis mode select: 0 : Normal Mode 1: De-emphasis Mode Refer to Figure 20 - Figure 25 for details of the De-Emphasis filtering effects at different sample rates. In hardware mode (MODE=1) driving the MD/DM pin high has the same effect as setting the DEEMPH bit: MODE PIN 0 1 1 MD/DM PIN ignored 0 1 Normal Mode De-Emphasis Mode DESCRIPTION De-Emphasis controlled from DEEMPH register bit POWERDOWN MODE Setting the PDWN register bit immediately connects all outputs to VCAP and selects a low power mode. All trace of the previous input samples is removed, but all control register settings are preserved. When PDWN is cleared again the first 16 input samples will be ignored as the FIR will repeat it's power-on initialisation sequence. REGISTER ADDRESS 0000010 DAC Channel Control BIT 2 LABEL PDWN DEFAULT 0 DESCRIPTION Power Down Mode Select: 0 : Normal Mode 1: Power Down Mode ATTENUATOR CONTROL MODE Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channels for all three pairs of DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS 0000010 DAC Channel Control BIT 3 LABEL ATC DEFAULT 0 DESCRIPTION Attenuator Control Mode: 0 : Right channels use Right attenuations 1: Right Channels use Left Attenuations AI Rev 1.3 October 2001 21 WM8756 DAC OUTPUT CONTROL Advance Information The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS 0000010 DAC Control BIT 8:5 LABEL PL[3:0] DEFAULT 1001 PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 13 Input to output control DESCRIPTION Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2 AI Rev 1.3 October 2001 22 WM8756 ATTENUATION CONTROL (ONLY APPLICABLE TO PCM MODE) Advance Information Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 7 Attenuation control words. All attenuation registers are double latched allowing new values to be pre-latched to several channels before being updated synchronously. Setting the UPDATE bit on any attenuation write will cause all pre-latched values to be immediately applied to the DAC channels. A master attenuation register is also included, allowing all attenuations to be set to the same value in a single write. REGISTER ADDRESS 0000 Attenuation DACL0 BIT 7:0 8 LABEL L0A[7:0] UPDATE DEFAULT 11111111 (0dB) Not latched DESCRIPTION Attenuation level of left channel DACL0 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACL0 in intermediate latch (no change to output) 1: Store DACL0 and update attenuation on all channels. Attenuation level of right channel DACR0 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACR0 in intermediate latch (no change to output) 1: Store DACR0 and update attenuation on all channels. Attenuation level of left channel DACL1 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACL1 in intermediate latch (no change to output) 1: Store DACL1 and update attenuation on all channels. Attenuation level of right channel DACR1 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACR1 in intermediate latch (no change to output) 1: Store DACR1 and update attenuation on all channels. Attenuation level of left channel DACL2 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACL2 in intermediate latch (no change to output) 1: Store DACL2 and update attenuation on all channels. Attenuation level of right channel DACR2 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACR2 in intermediate latch (no change to output) 1: Store DACR2 and update attenuation on all channels. Attenuation of all channels in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store MASTA[7:0] in all intermediate latches (no change) 1: Store MASTA[7:0] and update attenuation on all channels. 0001 Attenuation DACR0 7:0 8 R0A[7:0] UPDATE 11111111 (0dB) Not latched 0100 Attenuation DACL1 7:0 8 L1A[7:0] UPDATE 11111111 (0dB) Not latched 0101 Attenuation DACR1 7:0 8 R1A[7:0] UPDATE 11111111 (0dB) Not latched 0110 Attenuation DACL2 7:0 8 L2A[7:0] UPDATE 11111111 (0dB) Not latched 0111 Attenuation DACR2 7:0 8 R2A[7:0] UPDATE 11111111 (0dB) Not latched 1000 Master Attenuation (all channels) 7:0 8 MASTA[7:0] UPDATE 11111111 (0dB) Not latched Table 14 Attenuation Register Map Notes: 1. The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the relevant DAC. If UPDATE=1, all pre-latched values will be applied from the next input sample. Writing to MASTA[7:0] overwrites any values previously sent to L0A[7:0], L1A[7:0], L2A[7:0], R0A[7:0], R1A[7:0], R2A[7:0]. The attenuation level is only applied when the input data passes through midrail unless the ZCD function (register 9, bit 1) is disabled where it will change immediately. AI Rev 1.3 October 2001 23 2. WM8756 DAC OUTPUT ATTENUATION Advance Information Register bits [7:0] of L0A and R0A control the left and right channel attenuation of DAC 0. Register bits [7:0] of L1A and R1A control the left and right channel attenuation of DAC 1. Register bits [7:0] of L2A and R2A control the left and right channel attenuation of DAC 2. Register bits [7:0] of MASTA are a register that can be used to control attenuation of all channels. Table 15 shows how the attenuation levels are selected from the 8-bit words. AX[7:0] 00(hex) 01(hex) : : : FE(hex) FF(hex) Table 15 Attenuation Control Levels ATTENUATION LEVEL -∞dB (mute) -127.5dB : : : -0.5dB 0dB EXTENDED INTERFACE CONTROL It is possible to run the WM8756 channels at different rates with the front two channels running at twice the rate of the rear four channels. In this mode which is enabled by bit 0 of register 9, the interface runs at the faster data rate but pin 13 acts as the framing LRCIN for the rear channels see Figure 11. REGISTER ADDRESS 0001001 Split rate mode BIT 0 LABEL 2SPD DEFAULT 0 DESCRIPTION Activates the split rate mode 0: Normal operation. 1: Split rate operation. When the WM8756 receives updates to the volume levels it will, by default, wait for the signal to pass through midrail before applying the change to the output. This ensures that minimal distortion is seen on the output when the volume is changed. This function applies individually to each channel. REGISTER ADDRESS 0001001 Zero crossing detect BIT 1 LABEL ZCD DEFAULT 0 DESCRIPTION Controls the ZCD 0: Enabled. 1: Disabled. AI Rev 1.3 October 2001 24 WM8756 HARDWARE CONTROL MODES Advance Information When the MODE pin is held high, and DSDB pin is high, the following hardware modes of operation are available. MUTE AND AUTOMUTE OPERATION In both hardware and software modes pin 12 (MUTE) controls selection of MUTE directly, and can be used to enable and disable the automute function, or as an output of the automuted signal. AUTOMUTED (Internal Signal) 10kΩ MUTE PIN SOFTMUTE (Internal Signal) Figure 14 Mute Circuit Operation The MUTE pin behaves as a bi-directional function, that is, as an input to select MUTE or NOT-MUTE, or as an output indication of automute operation. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of zero value audio samples of 1024 samples long being applied to all 6 channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR’ed through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert MUTE. If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a source follower, or diode, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits. INPUT FORMAT SELECTION In hardware mode, pins 16 and 17 become input controls for selection of input data format type and input data word length (see Table 16). I2S mode is designed to support any word length provided enough bit clocks are sent. ML/I2S 0 0 1 1 MC/IWL 0 1 0 1 INPUT DATA MODE 16-bit right justified 20-bit right justified 24-bit right justified I2S mode Table 16 Control of Input Data Format Type and Input Data Word Length MD/DM DE-EMPHASIS In hardware mode, pin 18 becomes an input control for selection of de-emphasis filtering to be applied (see Table 17). MD/DM 0 1 Table 17 De-emphasis Control DE-EMPHASIS MODE De-emphasis off De-emphasis on AI Rev 1.3 October 2001 25 WM8756 DSDB MODE SELECT Advance Information This pin puts the device into DSD mode when taken low. Due to the nature of DSD operation only a single software controlled function is available in this mode. This is the PDWN bit. DSDB 0 1 Table 18 DSD mode Control DSD MODE Device in DSD mode Device in normal PCM operation DSD DIGITAL AUDIO INTERFACE DSD mode is selected by taking the DSDB pin low. In this mode the internal digital filters are by-passed, and the already modulated bitstream data is applied directly to the Switched Capacitor DAC filter where it is converted and low-pass filtered. Two formats are supported for data transfer, NORMAL or PHASE MODULATED. In Normal mode, DSD data is simply clocked into the device using the rising edge of the 64fs DSDCLK64 signal (see Figure 3). In Phase Modulation mode, the data is supplied in Manchester encoded form (a bit transition occurs during every data bit, which shapes the spectral energy minimising corruption of the analogue outputs). A secondary clock DSDCLK128, at 128fs is used to simplify data recovery, the data simply being clocked with the falling edge of DSDCLK128 when DSDCLK64 is low (see Figure 4). Operation of PHASE MODULATED mode is auto-detected by the presence of a clock signal on the DSDCLK128 pin. DSD clocks are either inputs (when DMSLV = ‘0’) or outputs (when DMSLV = ‘1’). When DMSLV is ‘1’ the clocks are derived by using the SCKI as detailed below: DMCKSEL 0 1 DSDCLK64 SCKI/4 SCKI/6 DSDCLK128 SCKI/2 SCKI/3 Table 19 Master/Slave clock selection DMSLV 0 1 Table 20 Master/Slave function See Figure 3 and Figure 4 for details of DSD interface timing CLOCKS inputs outputs AI Rev 1.3 October 2001 26 WM8756 SOFTWARE CONTROL INTERFACE Advance Information The software control interface uses a 3-wire serial control interface. Selection of interface format is achieved by setting the state of the MODE pin. MODE 0 1 INTERFACE FORMAT Software Control Mode Hardware Control Mode Table 21 Control Interface Mode Selection 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE The WM8756 can be controlled using a 3-wire serial interface. MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is use to latch in the program data. The 3-wire interface protocol is shown in Figure 15. ML/I2S MC/IWL MD/DM A6 A5 A4 A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 15 3-wire Serial Interface Notes: 1. 2. A[6:0] are Control Address Bits D[8:0] are Control Data Bits AI Rev 1.3 October 2001 27 WM8756 REGISTER MAP Advance Information There are 9 registers with 9 bits per register. These can be controlled using the Control Interface.Table 22 below gives an overview of all the WM8756 control registers. Details of each register’s function are summarised on the following pages (Table 23). A6 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 D8 UPDATE UPDATE PL3 REV2 UPDATE UPDATE UPDATE UPDATE UPDATE 0 D7 L0A7 R0A7 PL2 REV1 L1A7 R1A7 L2A7 R2A7 MASTA7 0 D6 L0A 6 R0A 6 PL1 REV0 L1A 6 R1A 6 L2A 6 R2A 6 MASTA 6 0 D5 L0A 5 R0A 5 PL0 IWL1 L1A 5 R1A 5 L2A 5 R2A 5 MASTA 5 0 D4 L0A 4 R0A 4 IZD IWL0 L1A 4 R1A 4 L2A 4 R2A 4 MASTA 4 0 D3 L0A 3 R0A 3 ATC BCP L1A 3 R1A 3 L2A 3 R2A 3 MASTA 3 0 D2 L0A 2 R0A 2 PDWN LRP L1A 2 R1A 2 L2A 2 R2A 2 MASTA 2 0 D1 L0A 1 R0A 1 DEEMPH FMT1 L1A 1 R1A 1 L2A 1 R2A 1 MASTA 1 ZCD D0 L0A 0 R0A 0 MUTE FMT0 L1A 0 R1A 0 L2A 0 R2A 0 MASTA 0 2SPD Table 22 Register Map AI Rev 1.3 October 2001 28 WM8756 REGISTER ADDRESS 0000000 Attenuation DACL0 BIT 7:0 LABEL L0A[7:0] DEFAULT 11111111 (0dB) Not latched DESCRIPTION Advance Information Attenuation level of left channel DACL0 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACL0 in intermediate latch (no change to output) 1: Store DACL0 and update attenuation on all channels. Attenuation level of right channel DACR0 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACR0 in intermediate latch (no change to output) 1: Store DACR0 and update attenuation on all channels. Left and Right DACs soft mute control 0: No Mute 1: Mute De-emphasis Control 0: Normal Response (see Figure 16 - Figure 19) 1: De-emphasis Response (see Figure 20 - Figure 25) Left and Right DACs Power-down Control 0: All DACs running, output is active 1: All DACs in power saving mode, output muted Attenuator Control 0: All DACs use attenuations as programmed. 1: Right chan. DACs use corresponding left DAC attenuations Infinite zero detection circuit control and automute control 0: Infinite zero detect disabled 1: Infinite zero detect enabled DAC Output Control PL[3:0] Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left PL[3:0] Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2 8 UPDATE 0000001 Attenuation DACR0 7:0 R0A[7:0] 11111111 (0dB) Not latched 8 UPDATE 0000010 DAC Control 0 MUTE 0 1 DEEMPH 0 2 PDWN 0 3 ATC 0 4 IZD 0 8:5 PL[3:0] 1001 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AI Rev 1.3 October 2001 29 WM8756 0000011 Interface Control 1:0 FMT[1:0] 00 Interface format select 00: right justified mode 01: left justified mode 10: I2S mode 11: DSP mode LRCIN Polarity or LRCIN Phase Left Justified / Right Justified / I2S 0: Standard LRCIN Polarity 1: Inverted LRCIN Polarity 3 BCP 0 Advance Information 2 LRP 0 DSP Mode 0: DSP early mode 1: DSP late mode BCKIN Polarity 0: Normal (DIN[2:0] and LRCIN sampled on rising edge) 1: Inverted (DIN[2:0] and LRCIN sampled on falling edge) Input Word Length 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) Controls the output phase of the three stereo channels 1 in bit 6 reverses the phase of data output on OUT0L/R. 1 in bit 7 reverses the phase of data output on OUT1L/R. 1 in bit 8 reverses the phase of data output on OUT2L/R. Attenuation level of left channel DACL1 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACL1 in intermediate latch (no change to output) 1: Store DACL1 and update attenuation on all channels. Attenuation level of right channel DACR1 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACR1 in intermediate latch (no change to output) 1: Store DACR1 and update attenuation on all channels. Attenuation level of left channel DACL2 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACL2 in intermediate latch (no change to output) 1: Store DACL2 and update attenuation on all channels. Attenuation level of right channel DACR2 in 0.5dB steps, see Table 15 Attenuation Control Levels. Controls simultaneous update of all Attenuation Latches 0: Store DACR2 in intermediate latch (no change to output) 1: Store DACR2 and update attenuation on all channels. Attenuation level of all channels in 0.5dB steps. See Table 15 Attenuation Control Levels Controls simultaneous update of all Attenuation Latches 0: Store MASTA[7:0] in all intermediate latches (no change to output) 1: Store MASTA[7:0] and update attenuation on all channels. 5:4 IWL[1:0] 0 8:6 REV[2:0] 000 0000100 Attenuation DACL1 7:0 L1A[7:0] 11111111 (0dB) Not latched 8 UPDATE 0000101 Attenuation DACR1 7:0 R1A[7:0] 11111111 (0dB) Not latched 8 UPDATE 0000110 Attenuation DACL2 7:0 L2A[7:0] 11111111 (0dB) Not latched 8 UPDATE 0000111 Attenuation DACR2 7:0 R2A[7:0] 11111111 (0dB) Not latched 8 UPDATE 0001000 Master Attenuation (all channels) 7:0 MASTA[7:0] 11111111 (0dB) Not latched 8 UPDATE AI Rev 1.3 October 2001 30 WM8756 REGISTER ADDRESS 0001001 Extended interface control BIT 0 LABEL 2SPD DEFAULT 0 DESCRIPTION Advance Information Activates the split rate mode where the front channels run at 192kHz and the rear four channels run at 96kHz. 0: Normal operation. 1: Split rate operation. Controls the operation of the zero crossing detect mechanism which ensures that the volume is only updated on each channel when the signal passes through midrail. 0: Enable zero detect. 1: Disable zero detect. 1 ZCD 0 Table 23 Register Map Description AI Rev 1.3 October 2001 31 WM8756 DAC FILTER RESPONSES 0.2 0 0.15 -20 0.1 Response (dB) Response (dB) Advance Information -40 0.05 0 -0.05 -0.1 -60 -80 -100 -0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 -120 Figure 16 DAC Digital Filter Frequency Response – 44.1, 48 and 96KHz Figure 17 DAC Digital Filter Ripple –44.1, 48 and 96kHz 0.2 0 0 -20 Response (dB) Response (dB) -0.2 -40 -0.4 -60 -0.6 -0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 18 DAC Digital Filter Frequency Response 192kHz Figure 19 DAC Digital filter Ripple 192kHz AI Rev 1.3 October 2001 32 WM8756 DIGITAL DE-EMPHASIS CHARACTERISTICS 0 1 0.5 -2 0 Response (dB) Response (dB) Advance Information -4 -0.5 -1 -1.5 -2 -6 -8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16 Figure 20 De-Emphasis Frequency Response (32kHz) 0 Figure 21 De-Emphasis Error (32KHz) 0.4 0.3 -2 0.2 Response (dB) Response (dB) -4 0.1 0 -0.1 -0.2 -6 -8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20 Figure 22 De-Emphasis Frequency Response (44.1KHz) 0 Figure 23 De-Emphasis Error (44.1KHz) 1 0.8 -2 0.6 0.4 Response (dB) -4 Response (dB) 0.2 0 -0.2 -0.4 -6 -8 -0.6 -0.8 -10 0 5 10 15 Frequency (kHz) 20 -1 0 5 10 15 Frequency (kHz) 20 Figure 24 De-Emphasis Frequency Response (48kHz) Figure 25 De-Emphasis Error (48kHz) AI Rev 1.3 October 2001 33 WM8756 DSD MODE CHARACTERISTICS Advance Information The following filter responses show the DAC output frequency response in SACD or DSD mode, with and without an external 3rd order Lowpass filter. Table 15 gives details of the attenuation versus frequency of the two cases. 0.05 Chip output Output and 3rd order Butterworth filter 0 0 Chip output Output and 3rd order Butterworth filter -2 -0.05 Gain (dB) Gain (dB) -4 -0.1 -6 -0.15 -0.2 -8 -0.25 0 5000 10000 15000 Frequency (Hz) 20000 25000 -10 0 10000 20000 30000 Frequency (Hz) 40000 50000 60000 Figure 26 DSD Mode Frequency Response – to 25kHz 10 Chip output Output and 3rd order Butterworth filter Figure 27 DSD Mode Frequency Response – to 60kHz 20 Chip output Output and 3rd order Butterworth filter 0 0 -20 -10 -40 Gain (dB) -20 Gain (dB) 0 20000 40000 60000 Frequency (Hz) 80000 100000 120000 -60 -80 -30 -100 -40 -120 -50 -140 0 200000 400000 600000 Frequency (Hz) 800000 1e+06 Figure 28 DSD Mode Frequency Response - to 120kHz Figure 29 DSD Mode Frequency Response – to 1MHz AI Rev 1.3 October 2001 34 WM8756 RECOMMENDED EXTERNAL COMPONENTS DVDD 44 + C1 C2 15 DGND DVDD AVDD AVDD1 AVDD2 40 21 + C3 16 17 ML/I2S MC/IWL MD/DM DSDB MODE MUTE CSB OUT0R LRCIN2 SCKI BCKIN LRCIN OUT1R DIN0 DIN1 OUT1L DIN2 DSD0 OUT2R DSD1 DSD2 OUT2L DSD3 DSD4 CAP DSD5 DSDCLK64 DSDCLK128 DMSLV DMCKSEL Pins 20, 22, 24, 37-39 and 41are no connects AGND C12 C13 23 + 25 27 30 OUT0L 34 36 AGND1 AGND2 AGND3 GR0 GR1 GR2 28 29 33 35 31 26 C6 AGND C4 C5 Advance Information DGND Software I/F or Hardware Control 18 14 11 12 19 13 45 46 47 C7 W M8756 AC-Coupled OUT0R/L to External LPF AC-Coupled OUT1R/L to External LPF AC-Coupled OUT2R/L to External LPF Audio PCM Data I/F 32 C8 + + 48 1 2 3 4 5 6 C9 C10 C11 + + + + Audio DSD Data I/F 7 8 9 10 42 43 NOTES: 1. 2. 3. AGND and DGND should be connected as close to the WM8756 as possible. C2, C3, C4 and C12 should be positioned as close to the WM8756 as possible. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance. Figure 30 External Components Diagram RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT REFERENCE C1 and C5 C2 to C4 C6 to C11 C12 C13 SUGGESTED VALUE 10µF 0.1µF 10µF 0.1µF 10µF DESCRIPTION De-coupling for DVDD and AVDD. De-coupling for DVDD and AVDD. Output AC coupling caps to remove midrail DC level from outputs. Reference de-coupling capacitors for CAP pin. Table 24 External Components Description AI Rev 1.3 October 2001 35 WM8756 SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS Advance Information For PCM operation, the low out of band noise from the WM8756 means that a low order post DAC filter can be used such as 2nd order Salen and Key type. External 2nd OrderLPF x2 for Stereo Operation 10kΩ OUTnR OUTnL 1000pF 1.8kΩ 7.5kΩ 10kΩ + 680pF Filtered Analogue Output Figure 31 Second order active RC low pass filter For SACD operation a 3rd order filter may be used to meet Scarlet book standards (-3dB point at maximum 50kHz, minimum 30dB attenuation at 100kHz) when combined with the filter response of the internal FIR filter. Such a filter may be built using a single opamp in similar fashion to the second order filter above, so costing little extra to implement. The same filter may also be used very satisfactorily for PCM operation. External 3rd OrderLPF x2 for Stereo Operation 10kΩ OUTnR OUTnL 10kΩ 1500pF 10kΩ 680pF 10kΩ 10kΩ + 100pF Filtered Analogue Output Figure 32 Third order active RC low pass filter RECOMMENDED APPLICATIONS PCM Decoder e.g. AC-3, DTS DIN0 DIN1 DIN2 BCKIN LRCIN SCKI Audio data carrier e.g. DVD, SACD TM WM8756 6-channel DAC Front left Front right Surround left Surround right Centre LFE DSD decoder Figure 33 Combined PCM and DSD Circuit Configuration AI Rev 1.3 October 2001 36 DSD5 DSD4 DSD3 DSD2 DSD1 DSD0 DSDCLK64 DSDCLK128 WM8756 BCKAO DSDCLK64 Advance Information PHREFO DSDCLK128 DSAL DSD0 DSAR DSD1 CXD2753R DSAC DSD2 WM8756 DSASW DSD3 DSALS DSD4 DSARS DSD5 Figure 34 Connection of WM8756 as Slave to Sony 6-CH DSD Decoder Chip in Normal mode To use the WM8756 with the Sony CXD2753R there are several configuration options: 1. In DSD mode if the WM8756 is being run in NORMAL mode as a SLAVE device the only clock input which the WM8756 requires is DSDCLK64, this should be connected to the BCKAO pin of the CXD2753R. In this BCKAO should be a falling edge set as illustrated on page 20 of the CXD2753R datasheet (Rev PE01704-PS). In DSD mode if the WM8756 is being run in PHASE MODULATION mode as a SLAVE device the clock inputs which the WM8756 requires are DSDCLK64 and DSDCLK128. DSDCLK64 and DSDCLK128 should be connected to PHREFO and BCKAO respectively on the CXD2753R. In Phase Modulation mode phase 2 should be selected for the PHREFO clock and BCKAO should be a rising edge set, as illustrated on page 20 of the CXD2753R datasheet (Rev PE01704-PS). To run the WM8756 in DSD mode but as a MASTER SCLK must be present on the device. If the device is intended to be used for both PCM and DSD data in either MASTER or SLAVE mode SCLK can be present on the WM8756 at all times as this pin is ignored by the WM8756 when it is not required. 2. − − AI Rev 1.3 October 2001 37 WM8756 PACKAGE DIMENSIONS FT: 48 PIN TQFP (7 x 7 x 1.0 mm) DM004.C Advance Information b e 25 36 37 24 E1 E 48 13 1 12 Θ c D1 D L A A2 A1 -Cccc C SEATING PLANE Symbols A A1 A2 b c D D1 E E1 e L Θ ccc REF: Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 0 3.5 7 Tolerances of Form and Position 0.08 JEDEC.95, MS-026 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. AI Rev 1.3 October 2001 38 WM8756 IMPORTANT NOTICE Advance Information Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: Wolfson Microelectronics Ltd 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom Tel :: +44 (0)131 667 9386 Fax :: +44 (0)131 667 5176 Email :: sales@wolfsonmicro.com AI Rev 1.3 October 2001 39