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WM8955LSEFL

WM8955LSEFL

  • 厂商:

    WOLFSON

  • 封装:

  • 描述:

    WM8955LSEFL - Stereo DAC For Portable Audio Applications - Wolfson Microelectronics plc

  • 数据手册
  • 价格&库存
WM8955LSEFL 数据手册
w DESCRIPTION The WM8955L is a low power, high quality stereo DAC with integrated headphone and loudspeaker amplifiers, designed to reduce external component requirements in portable digital audio applications. The on-chip headphone amplifiers can deliver 40mW into a 16Ω load. Advanced on-chip digital signal processing performs bass and treble tone control. The WM8955L can operate as a master or a slave, and includes an on-chip PLL. It can use most master clock frequencies commonly found in portable systems, including USB, GSM, CDMA or PDC clocks, or standard 256fs clock rates. Different audio sample rates such as 48kHz, 44.1kHz, 8kHz and many others are supported. The WM8955L operates on supply voltages from 1.8V up to 3.6V, although the digital core can operate on a separate supply down to 1.42V, saving power. Different sections of the chip can also be powered down under software control. The WM8955L is supplied in a very small and thin 5x5mm QFN package, ideal for use in hand-held and portable systems. WM8955L Stereo DAC For Portable Audio Applications FEATURES • • • • • • • • • • • DAC SNR 98dB, THD -86dB (‘A’ weighted @ 48kHz, 3.3V) On-chip 400mW BTL Speaker Driver (mono) On-chip Headphone Driver - 40mW output power on 16Ω / 3.3V - SNR 96dB, THD –79dB at 20mW with 16Ω load Stereo and Mono Line-in mix into DAC output Separately Mixed Stereo and Mono Outputs Digital Tone Control and Bass Boost Low Power - Down to 7mW for stereo playback (1.8V / 1.5V supplies) - 10µW Shutdown Mode Low Supply Voltages - Analogue and Digital I/O: 1.8V to 3.6V - Digital core: 1.42V to 3.6V Master clocks supported: GSM, CDMA, PDC, USB or standard audio clocks Audio sample rates supported: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96kHz 32-lead QFN package, 5x5x0.9mm size, 0.5mm lead pitch APPLICATIONS • • Smartphone / Multimedia Phone Digital Audio Player BLOCK DIAGRAM WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Production Data, March 2006, Rev 4.2 Copyright 2006 Wolfson Microelectronics plc WM8955L TABLE OF CONTENTS Production Data DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 TERMINOLOGY............................................................................................................. 7 OUTPUT PGA’S LINEARITY ......................................................................................... 8 HEADPHONE OUTPUT THD VERSUS POWER........................................................... 9 SPEAKER THD AND NOISE VERSUS POWER ......................................................... 10 POWER CONSUMPTION ....................................................................................11 AUDIO PATHS OVERVIEW .................................................................................12 SIGNAL TIMING REQUIREMENTS .....................................................................13 SYSTEM CLOCK TIMING............................................................................................ 13 AUDIO INTERFACE TIMING – MASTER MODE ......................................................... 13 AUDIO INTERFACE TIMING – SLAVE MODE ............................................................ 14 CONTROL INTERFACE TIMING – 3-WIRE MODE ..................................................... 14 CONTROL INTERFACE TIMING – 2-WIRE MODE ..................................................... 15 INTERNAL POWER ON RESET CIRCUIT ..........................................................16 DEVICE DESCRIPTION.......................................................................................17 INTRODUCTION.......................................................................................................... 17 SIGNAL PATH ............................................................................................................. 17 LINE INPUTS AND OUTPUT MIXERS ........................................................................ 21 ANALOGUE OUTPUTS ............................................................................................... 24 DIGITAL AUDIO INTERFACE...................................................................................... 28 MASTER CLOCK AND PHASE LOCKED LOOP ......................................................... 31 AUDIO SAMPLE RATES.............................................................................................. 33 CONTROL INTERFACE .............................................................................................. 35 POWER SUPPLIES ..................................................................................................... 36 POWER MANAGEMENT ............................................................................................. 37 REGISTER MAP...................................................................................................39 DIGITAL FILTER CHARACTERISTICS ...............................................................40 TERMINOLOGY........................................................................................................... 40 DAC FILTER RESPONSES ......................................................................................... 40 APPLICATIONS INFORMATION .........................................................................42 RECOMMENDED EXTERNAL COMPONENTS........................................................... 42 MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS ........................................ 43 LINE OUTPUT CONFIGURATION............................................................................... 43 HEADPHONE OUTPUT CONFIGURATION ................................................................ 44 SPEAKER OUTPUT CONFIGURATION...................................................................... 44 PACKAGE DIMENSIONS ....................................................................................45 IMPORTANT NOTICE ..........................................................................................46 ADDRESS:................................................................................................................... 46 w PD Rev 4.2 March 2006 2 Production Data WM8955L PIN CONFIGURATION TOP VIEW ORDERING INFORMATION ORDER CODE W M8955LSEFL TEMPERATURE RANGE -25°C to +85°C -25°C to +85°C PACKAGE 32-lead QFN (5x5x0.9mm) (Pb-free) 32-lead QFN (5x5x0.9mm) (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 PEAK SOLDERING TEMPERATURE 260oC 260oC W M8955LSEFL/R MSL1 Note: Reel quantity = 3,500 w PD Rev 4.2 March 2006 3 WM8955L PIN DESCRIPTION PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME MCLK DCVDD DBVDD DGND BCLK DACDAT DACLRC CLKOUT PLLGND MONOOUT OUT3 ROUT1 LOUT1 HPGND ROUT2 LOUT2 HPVDD AVDD AGND VREF VMID NC HPDETECT NC MONOINMONOIN+ LINEINR LINEINL MODE CSB SDIN SCLK TYPE Digital Input Supply Supply Supply Digital Input / Output Digital Input Digital Input / Output Digital Output Supply Analogue Output Analogue Output Analogue Output Analogue Output Supply Analogue Output Analogue Output Supply Supply Supply Analogue Output Analogue Output No Connect Logic Input No Connect Analogue Input Analogue Input Analogue Input Analogue Input Digital Input Digital Input Digital Input/Output Digital Input Master Clock Digital Core Supply Digital Buffer (I/O) Supply DESCRIPTION Production Data Digital Ground (return path for both DCVDD and DBVDD) Audio Interface Bit Clock DAC Digital Audio Data Audio Interface Left / Right Clock Buffered Clock Output (from MCLK or internal PLL) Internally connected to AGND. Connect this pin to AGND externally for best PLL performance, or leave floating. Mono Output Output 3 (can be used as Headphone Pseudo Ground) Right Output 1 (Line or Headphone) Left Output 1 (Line or Headphone) Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2) Right Output 1 (Line or Headphone or Speaker) Left Output 1 (Line or Headphone or Speaker) Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2, MONOUT) Analogue Supply Analogue Ground (return path for AVDD) Reference Voltage Decoupling Capacitor Midrail Voltage Decoupling Capacitor No Internal Connection Headphone / Speaker switch (referred to AVDD) No Internal Connection Negative end of MONOIN+, for differential mono signals Analogue Line-in to mixers (mono channel) Analogue Line-in to mixers (right channel) Analogue Line-in to mixers (left channel) Control Interface Selection Chip Select / Device Address Selection Control Interface Data Input / 2-wire Acknowledge output Control Interface Clock Input Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB. w PD Rev 4.2 March 2006 4 Production Data WM8955L ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at
WM8955LSEFL 价格&库存

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