WM8971LGEFL

w DESCRIPTION The WM8971L is a low power, high quality stereo codec designed for portable digital audio applications. The device integrates complete interfaces to stereo or mono microphones and a stereo headphone. External component requirements are drastically reduced as no separate microphone or headphone amplifiers are required. Advanced on-chip digital signal processing performs graphic equaliser, and automatic level control for the microphone or line input. The WM8971L can operate as a master or a slave, with various master clock frequencies including 12 or 24MHz for USB devices, or standard 256fs rates like 12.288MHz and 24.576MHz. Different audio sample rates such as 96kHz, 48kHz, 44.1kHz are generated directly from the master clock without the need for an external PLL. The WM8971L operates at supply voltages down to 1.8V, although the digital core can operate at voltages down to 1.42V to save power, and the maximum for all supplies is 3.6 Volts. Different sections of the chip can also be powered down under software control. The WM8971L is supplied in a very small and thin 5x5mm QFN package, ideal for use in hand-held and portable systems. WM8971L Stereo CODEC for Portable Audio Applications FEATURES • • • • • DAC SNR 98dB (‘A’ weighted), THD –84dB at 48kHz, 3.3V ADC SNR 95dB (‘A’ weighted), THD -82dB at 48kHz, 3.3V Complete Stereo / Mono Microphone Interface - Programmable ALC / Noise Gate On-chip 400mW BTL Speaker Driver (mono) On-chip Headphone Driver - >40mW output power on 16Ω / 3.3V - THD –80dB at 20mW, SNR 90dB with 16Ω load - No DC blocking capacitors required (capless mode) Separately mixed mono output Digital Graphic Equaliser Low Power - 7mW stereo playback (1.8V / 1.5V supplies) - 14mW record and playback (1.8V / 1.5V supplies) Low Supply Voltages - Analogue 1.8V to 3.6V - Digital core: 1.42V to 3.6V - Digital I/O: 1.8V to 3.6V 256fs / 384fs or USB master clock rates: 12MHz, 24MHz Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96kHz generated internally from master clock 5x5x0.9mm QFN package • • • • • • • APPLICATIONS • • • • Digital Still Cameras MP3 Player / Recorders Minidisc Player / Recorders Portable Digital Music Systems BLOCK DIAGRAM WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Production Data, August 2005, Rev 4.1 Copyright 2005 Wolfson Microelectronics plc WM8971L TABLE OF CONTENTS Production Data DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATION CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7 OUTPUT PGA’S LINEARITY ......................................................................................... 9 HEADPHONE OUTPUT THD VERSUS POWER......................................................... 10 SPEAKER THD AND NOISE VERSUS POWER ......................................................... 11 POWER CONSUMPTION ....................................................................................12 SIGNAL TIMING REQUIREMENTS .....................................................................13 SYSTEM CLOCK TIMING............................................................................................ 13 AUDIO INTERFACE TIMING – MASTER MODE ......................................................... 13 AUDIO INTERFACE TIMING – SLAVE MODE ............................................................ 14 INTERNAL POWER ON RESET CIRCUIT ..........................................................17 DEVICE DESCRIPTION.......................................................................................18 INTRODUCTION.......................................................................................................... 18 INPUT SIGNAL PATH.................................................................................................. 18 AUTOMATIC LEVEL CONTROL (ALC) ....................................................................... 25 OUTPUT SIGNAL PATH.............................................................................................. 28 ANALOGUE OUTPUTS ............................................................................................... 33 ENABLING THE OUTPUTS ......................................................................................... 35 HEADPHONE SWITCH ............................................................................................... 35 THERMAL SHUTDOWN .............................................................................................. 37 HEADPHONE OUTPUT ............................................................................................... 37 DIGITAL AUDIO INTERFACE...................................................................................... 38 AUDIO INTERFACE CONTROL .................................................................................. 42 CLOCKING AND SAMPLE RATES .............................................................................. 44 CONTROL INTERFACE .............................................................................................. 46 POWER SUPPLIES ..................................................................................................... 47 POWER MANAGEMENT ............................................................................................. 47 REGISTER MAP...................................................................................................50 DIGITAL FILTER CHARACTERISTICS ...............................................................51 TERMINOLOGY........................................................................................................... 51 DAC FILTER RESPONSES ......................................................................................... 52 ADC FILTER RESPONSES ......................................................................................... 53 DE-EMPHASIS FILTER RESPONSES ........................................................................ 54 HIGHPASS FILTER ..................................................................................................... 55 APPLICATIONS INFORMATION .........................................................................56 RECOMMENDED EXTERNAL COMPONENTS........................................................... 56 LINE INPUT CONFIGURATION................................................................................... 57 MICROPHONE INPUT CONFIGURATION .................................................................. 57 MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS ........................................ 57 POWER MANAGEMENT EXAMPLES ......................................................................... 58 w PD Rev 4.1 August 2005 2 Production Data WM8971L IMPORTANT NOTICE ..........................................................................................60 ADDRESS:................................................................................................................... 60 w PD Rev 4.1 August 2005 3 WM8971L Production Data PIN CONFIGURATION ORDERING INFORMATION ORDER CODE W M8971LGEFL W M8971LGEFL/R Note: Reel quantity = 3500 TEMPERATURE RANGE -25°C to +85°C -25°C to +85°C PACKAGE 32-lead QFN (5x5x0.9mm) (Pb-free) 32-lead QFN (5x5x0.9mm) (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 MSL1 PEAK SOLDERING TEMPERATURE 260°C 260°C w PD Rev 4.1 August 2005 4 Production Data WM8971L PIN DESCRIPTION PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB. NAME MCLK DCVDD DBVDD DGND BCLK DACDAT DACLRC ADCDAT ADCLRC MONOOUT NC ROUT1 LOUT1 HPGND ROUT2 LOUT2 HPVDD AVDD AGND VREF VMID MICBIAS HPDETECT NC MIC NC RINPUT1 LINPUT1 MODE CSB SDIN SCLK Supply Supply Supply Digital Input / Output Digital Input Digital Input / Output Digital Output Digital Input / Output Analogue Output No Connect Analogue Output Analogue Output Supply Analogue Output Analogue Output Supply Supply Supply Analogue Output Analogue Output Analogue Output Analogue Input No Connect Analogue Input No Connect Analogue Input Analogue Input Digital Input Digital Input Digital Input/Output Digital Input TYPE Digital Input Master Clock Digital Core Supply Digital Buffer (I/O) Supply Digital Ground (return path for both DCVDD and DBVDD) Audio Interface Bit Clock DAC Digital Audio Data Audio Interface Left / Right Clock/Clock Out ADC Digital Audio Data Audio Interface Left / Right Clock Mono Output No Connect Right Output 1 (Line or Headphone) Left Output 1 (Line or Headphone) Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2) Right Output 1 (Line or Headphone or Speaker) Left Output 1 (Line or Headphone or Speaker) Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2, MONOUT) Analogue Supply Analogue Ground (return path for AVDD) Reference Voltage Decoupling Capacitor Midrail Voltage Decoupling Capacitor Microphone Bias Headphone Plug-in Detection No Connect Single Ended Microphone Input No Connect Right Channel Input 1 Left Channel Input 1 Control Interface Selection Chip Select / Device Address Selection Control Interface Data Input / 2-wire Acknowledge output Control Interface Clock Input DESCRIPTION w PD Rev 4.1 August 2005 5 WM8971L ABSOLUTE MAXIMUM RATINGS Production Data Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at 0.5465fs 0.5465fs -50 dB f > 0.584fs +/- 0.03dB -6dB 0.584fs -50 0 0.5fs +/- 0.03 dB 0.4535fs dB +/- 0.03dB -6dB 0 0.5fs +/-0.03 dB 0.416fs -60 3.7 10.4 21.6 dB Hz -60 0 0.5fs +/- 0.05 dB 0.4535fs dB dB ADC Filter Type 1 (USB mode, 272fs or Normal mode operation) DAC Filter Type 1 (USB mode, 272fs or Normal mode operation) Table 43 ADC/DAC Digital Filters Group Delay TERMINOLOGY 1. 2. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple – any variation of the frequency response in the pass-band region w PD Rev 4.1 August 2005 51 WM8971L DAC FILTER RESPONSES 0.02 0 Production Data 0.01 -20 0 Response (dB) -40 Response (dB) 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.01 -0.02 -0.03 -0.04 -0.05 -60 -80 -100 -0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 29 DAC Digital Filter Frequency Response – Type 0 Figure 30 DAC Digital Filter Ripple – Type 0 0.02 0 0.01 -20 0 Response (dB) -40 Response (dB) -0.01 -0.02 -0.03 -0.04 -60 -80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 31 DAC Digital Filter Frequency Response – Type 1 Figure 32 DAC Digital Filter Ripple – Type 1 0.02 0 0.01 -20 0 Response (dB) -40 Response (dB) -0.01 -0.02 -0.03 -0.04 -60 -80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 33 DAC Digital Filter Frequency Response – Type 2 Figure 34 DAC Digital Filter Ripple – Type 2 w PD Rev 4.1 August 2005 52 Production Data 0.25 0 WM8971L 0.2 -20 0.15 0.1 Response (dB) Response (dB) -40 0.05 0 -0.05 -0.1 -60 -80 -0.15 -0.2 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.25 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 35 DAC Digital Filter Frequency Response – Type 3 Figure 36 DAC Digital Filter Ripple – Type 3 ADC FILTER RESPONSES 0.04 0 0.03 -20 0.02 Response (dB) -40 Response (dB) 0.01 0 -0.01 -0.02 -60 -80 -0.03 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 37 ADC Digital Filter Frequency Response – Type 0 0 Figure 38 ADC Digital Filter Ripple – Type 0 0.02 0.01 -20 0 Response (dB) -40 Response (dB) -0.01 -0.02 -0.03 -0.04 -60 -80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 39 ADC Digital Filter Frequency Response – Type 1 Figure 40 ADC Digital Filter Ripple – Type 1 w PD Rev 4.1 August 2005 53 WM8971L 0.25 0 Production Data 0.2 -20 0.15 0.1 Response (dB) Response (dB) -40 0.05 0 -0.05 -0.1 -60 -80 -0.15 -0.2 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.25 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 41 ADC Digital Filter Frequency Response – Type 2 Figure 42 ADC Digital Filter Ripple – Type 2 0.25 0 0.2 0.15 -20 0.1 Response (dB) Response (dB) -40 0.05 0 -0.05 -0.1 -60 -80 -0.15 -0.2 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.25 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 43 ADC Digital Filter Frequency Response – Type 2 Figure 44 ADC Digital Filter Ripple – Type 3 DE-EMPHASIS FILTER RESPONSES 0 0.4 0.3 -2 0.2 Response (dB) -4 Response (dB) 0.1 0 -0.1 -0.2 -6 -8 -0.3 -10 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000 -0.4 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000 Figure 45 De-emphasis Frequency Response (32kHz) Figure 46 De-emphasis Error (32kHz) w PD Rev 4.1 August 2005 54 Production Data 0 0.4 0.3 WM8971L -2 0.2 Response (dB) Response (dB) -4 0.1 0 -0.1 -0.2 -6 -8 -0.3 -0.4 -10 0 5000 10000 Frequency (Fs) 15000 20000 0 5000 10000 Frequency (Fs) 15000 20000 Figure 47 De-emphasis Frequency Response (44.1kHz) 0 Figure 48 De-emphasis Error (44.1kHz) 0.4 0.3 -2 0.2 Response (dB) -4 Response (dB) 0.1 0 -0.1 -0.2 -6 -8 -0.3 -0.4 -10 0 5000 10000 Frequency (Fs) 15000 20000 0 5000 10000 Frequency (Fs) 15000 20000 Figure 49 De-emphasis Frequency Response (48kHz) Figure 50 De-emphasis Error (48kHz) HIGHPASS FILTER The WM8971L has a selectable digital highpass filter in the ADC filter path to remove DC offsets. The filter response is characterised by the following polynomial: H(z) = 1 - z-1 1 - 0.9995z-1 0 Response (dB) -5 -10 -15 0 0.0005 0.001 Frequency (Fs) 0.0015 0.002 Figure 51 ADC Highpass Filter Response w PD Rev 4.1 August 2005 55 WM8971L APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Production Data Figure 52 Recommended External Components Diagram w PD Rev 4.1 August 2005 56 Production Data WM8971L LINE INPUT CONFIGURATION W hen LINPUT1/RINPUT1 or MIC are used as line inputs, the microphone boost and ALC functions should normally be disabled. In order to avoid clipping, the user must ensure that the input signal does not exceed AVDD. This may require a potential divider circuit in some applications. It is also recommended to remove RF interference picked up on any cables using a simple first-order RC filter, as high-frequency components in the input signal may otherwise cause aliasing distortion in the audio band. AC signals with no DC bias should be fed to the WM8971L through a DC blocking capacitor, e.g. 1µF. MICROPHONE INPUT CONFIGURATION MICBIAS R1 680 Ohm to 2.2kOhm check microphone's specification L/RINPUT1 MIC FROM MICROPHONE C2 1uF AGND R2 47kOhm C1 220pF AGND AGND Figure 53 Recommended Circuit for Line Input For interfacing to a microphone, the ALC function should be enabled and the microphone boost switched on. Microphones held close to a speaker’s mouth would normally use the 13dB gain setting, while tabletop or room microphones would need a 29dB boost. The recommended application circuit is shown above. R1 and R2 form part of the biasing network (refer to Microphone Bias section). R1 connected to MICBIAS is necessary only for electret type microphones that require a voltage bias. R2 should always be present to prevent the microphone input from charging to a high voltage which may damage the microphone on connection. R1 and R2 should be large so as not to attenuate the signal from the microphone, which can have source impedance greater than 2kOhm. C1 together with the source impedance of the microphone and the WM8971L input impedance forms an RF filter. C2 is a DC blocking capacitor to allow the microphone to be biased at a different DC voltage to the MICIN signal. MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS To minimise any pop or click noise when the system is powered up or down, the following procedures are recommended. POWER UP • Switch on power supplies. By default the WM8971L is in Standby Mode, the DAC is digitally muted and the Audio Interface, Line outputs and Headphone outputs are all OFF (DACMU = 1 Power Management registers 1 and 2 are all zeros). Enable Vmid and VREF. Enable DACs as required Enable line and / or headphone output buffers as required. Set DACMU = 0 to soft-un-mute the audio DACs. • • • • • • • POWER DOWN Set DACMU = 1 to soft-mute the audio DACs. Disable all output buffers. Switch off the power supplies. w PD Rev 4.1 August 2005 57 WM8971L POWER MANAGEMENT EXAMPLES OPERATION MODE VREF Production Data POWER MANAGEMENT (1) AINL/R POWER MANAGEMENT (2) DACs MBI DAL DAR LO1 PGAs ADCs ADR Output Buffers RO1 LO2 RO2 MO PGL PGR ADL Stereo Headphone Playback Stereo Line-in Record Stereo Microphone Record Mono Microphone Record Stereo Line-in to Headphone Out Phone Call Speaker Phone Call [ROUT2INV = 1] Record Phone Call [L channel = mic with boost, R channel = RX, enable mono mix] 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 Table 44 Register Settings for Power Management w PD Rev 4.1 August 2005 58 Production Data WM8971L PACKAGE DIMENSIONS FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH DM030.E CORNER TIE BAR 5 25 D2 B D2/2 32 SEE DETAIL A D L 24 EXPOSED GROUND 6 PADDLE A 1 INDEX AREA (D/2 X E/2) E2/2 E2 SEE DETAIL B E 17 8 2X 16 e 15 B 9 b 2X aaa C aaa C BOTTOM VIEW ccc C (A3) 1 A 0.08 C bbb M C A B 1 TOP VIEW DETAIL A 32x b CORNER TIE BAR 5 C SIDE VIEW SEATING PLANE 1 e/2 TERMINAL TIP A1 L 43 0. m m 6 56 0. 32x K DETAIL B DATUM m m EXPOSED GROUND PADDLE R 1 L1 e Symbols A A1 A3 b D D2 E E2 e L L1 R K aaa bbb ccc REF: MIN 0.85 0 0.18 4.90 3.2 4.90 3.2 0.35 1 b(min)/2 0.20 Tolerances of Form and Position 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VHHD-2 Dimensions (mm) NOM MAX 0.90 1.00 0.02 0.05 0.2 REF 0.23 0.30 5.00 5.10 3.3 3.4 5.00 5.10 3.3 3.4 0.5 BSC 0.4 0.45 0.1 L1 R NOTE 1 2 2 NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF ETCHING OF LEADFRAME. 2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. w PD Rev 4.1 August 2005 59 WM8971L IMPORTANT NOTICE Production Data W olfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: W olfson Microelectronics plc 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PD Rev 4.1 August 2005 60 Production Data WM8971L Revision History DATE RELEASE 14/08/03 30/03/04 2.0 3.0 Initial Release DESCRIPTION OF CHANGES Pin Configuration – Pins 11, 24 and 26 renamed Ordering Information – Peak Soldering Temp added and order codes changed Pin Description – Pin Descriptions for 11, 24 and 26 changed Speaker Output Power updated Updated to Production Data Block Diagram ROUT2 updated to show inverting buffer, buffer added to LD2MO and RD2MO Pin Diagram rotated Pin Description, Ground padded note added Recommended Operating Conditions, DBVDD to 1.7 Electrical Characteristics updated, Speaker Output Speaker THD and Noise Versus Power added Fig 3, Bit Clock Mode added Control Interface Timing 3-wire mode test conditions table updated Power on Reset added Speaker Output THD Versus Power removed PGA Control text updated Automatic Level Control text updated Note added to Noise Gate Control table Output Mixers, mono mixer para added Timing Diagrams, Figs, 17,18 and 19 updated LRP = 1 changed to LRP = 0 DSP diagrams updated, Figs 20, 21 Bit Clock added Clock Output table and text updated Updates to Table 38 Power Management Register Map HPFLREN added to R27, R8, Bit 8 & 7 BCM[1:0] added Group Delay added Recommended External Component diagram updated to show component values, ground paddle added External component values table deleted Ref updated in Package Drawing Ordering information – leaded parts removed Pin description - Changed pin 19 description Electrical Characteristics – ADC THD max values removed Updated Operation Mode table (Stereo Headphone playback, AINL/UR changed from 1 to 0) Package Drawing updated to DM030.E to include ground paddle info PAGES 4 5 8 1 4 5 6 8 11 14 16 17 21 25 27 31 39 41 43 44 48 50 51 56 57 59 4 5 7 58 59 12/05/04 4.0 16/08/05 4.2 w PD Rev 4.1 August 2005 61