WM9713L

w AC’97 Audio + Touchpanel CODEC DESCRIPTION The WM9713L is a highly integrated input/output device designed for mobile computing and communications. The chip is architected for dual CODEC operation, supporting Hi-Fi stereo Codec functions via the AC link interface, and additionally supporting voice Codec functions via a PCM type Synchronous Serial Port (SSP). A third, auxiliary DAC is provided which may be used to support generation of supervisory tones, or ring-tones at different sample rates to the main codec. The device can connect directly to a 4-wire or 5-wire touchpanel, mono or stereo microphones, stereo headphones and a stereo speaker, reducing total component count in the system. Cap-less connections to the headphones, speakers, and earpiece may be used, saving cost and board area. Additionally, multiple analog input and output pins are provided for seamless integration with analog connected wireless communication devices. All device functions are accessed and controlled through a single AC-Link interface compliant with the AC’97 standard. The 24.576 MHz masterclock can be input directly or generated internally from a 13MHz (or other frequency) clock by an on-chip PLL. The PLL supports a wide range of input clock from 2.048MHz to 78.6MHz. The WM9713L operates at supply voltages from 1.8V to 3.6V. Each section of the chip can be powered down under software control to save power. The device is available in a small leadless 7x7mm QFN package, ideal for use in hand-held portable systems. WM9713L FEATURES • AC’97 Rev 2.2 compatible stereo codec - DAC SNR 94dB, THD –85dB - ADC SNR 87dB, THD –86dB - Variable Rate Audio, supports all WinCE sample rates - Tone Control, Bass Boost and 3D Enhancement • On-chip 45mW headphone driver • On-chip 400mW mono or stereo speaker drivers • Stereo, mono or differential microphone input - Automatic Level Control (ALC) - Mic insert and mic button press detection • Auxiliary mono DAC (ring tone or DC level generation) • Seamless interface to wireless chipset • Resistive touchpanel interface - Supports 4-wire and 5-wire panels - 12-bit resolution, INL ±2 LSBs ( -15dB 0Eh:4-0 00000 = +12dB 11111 = -34.5dB PCBEEP 6dB -> -15dB AUXDAC MICCM PCBEEP MONOIN LINER LINEL MICA MICB 1-8 16h:1 1-8 h:1 1A 1-8 :1 8h 1 6dB -> -15dB VXDAC MONOMIX HPMIXR SPKMIX HPMIXL INV1 14h:2-0 18 Bit ADC Variable Slot 5C:1-0 (ASS) 5C:3 (HPF) 5C:4 (ADCO) ALC:5Ch/60h/62h Sent to Both PCM Link AC'97 Link LINEL MONOIN PCBEEP LINER MICA MICB 1Eh:12-10 12h:6 (GRR=0) 12h:3:0 0000 = 0db 1111 = +22.5dB 12h:6 (GRR=1) 12h:5-0 11111 = +30dB 00000 = -17.25dB PCBEEP LINER DACR DACL LINEL MICA MICB RECMUXL MONOIN RECMUXR 14h:6 0 = 0dB 1 = 20dB AUXDAC VXDAC INV1 HPMIXL PR Bit Code PR0 - Audio ADCs & record mux PR1 - Stereo DAC PR2 - Input PGAs & mixers PR3 - Refs, input PGAs, mixers & output PGAs PR6 - Output PGAs Note: PR bits are active low - i.e. 0 = "ON"; 1 = "OFF" => Enable when { (PR0 || PR2) && PR3 } are low AVDD AGND CAP VREF MONOMIX HPMIXR SPKMIX INV2 INV2 VMICBIAS Figure 1 Audio Paths Overview w PP Rev 3.0 June 2006 13 WM9713L CLOCK GENERATION Pre-Production W M9713L supports clocking from 2 separate sources, which can be selected via the AC’97 interface: • • External clock input MCLKA External clock input MCLKB The source clock is divided to appropriate frequencies in order to run the AC’97 interface, PCM interface, voice DAC and Hi-fi DSP by means of a programmable divider block. Clock rates may be changed during operation via the AC’97 link in order to support alternative modes, for example low power mode when voice data is being transmitted only. A PLL is present to add flexibility in selection of input clock frequencies, typical choices being 2.048MHz, 4.096MHz or 13MHz. Default mode on power-up assumes a clock will be present on MCLKA with the PLL powered down. This enables data to be clocked via the AC’97 link to define the desired clock divider mode and whether PLL needs to be activated. Note: This clock can be any available frequency. When muxing between MCLKA and MCLKB both clocks must be active for at least two clock cycles after the switching event. CLOCK DIVISION MODES Figure 2 shows the clocking strategy for WM9713L. Clocking is controlled by CLK_MUX, CLK_SRC and S[6:0]. • • • • CLKAX2, CLKBX2 – clock doublers on inputs MCLKA and MCLKB. CLK_MUX - selects between MCLKA and MCLKB. CLK_SRC – selects between external or PLL derived clock reference. S[3:0] – sets the voice DAC clock rate and PCM interface clock when in master mode (division ratio 1 to 16 available). S[6:4] - sets the hi-fi clocking rate (division ratio 1 to 8 available). • The registers used to set these switches can be accessed from register address 44h (see Table 2). If a mode change requires switching from an external clock to a PLL generated clock then it is recommended to set the clock division ratios required for the PLL clock scheme prior to switching between clocks. This option is accommodated by means of two sets of registers. SPLL[6:0] is used to set the divide ratio of the clock when in PLL mode and SEXT[6:0] is used to divide the clock when it is derived from an external source. If the PLL is selected (CLK_SRC = 0), S[6:0] = SPLL[6:0]. SPLL[6:0] is defined in register 46h (see Table 4) and is written to using the page address mode. More details on page address mode for controlling the PLL are found on page 20. Register 46h also contains a number of separate control bits relating to the PLL’s function. If an external clock is selected (CLK_SRC = 1) S[6:0] = SEXT[6:0]. SEXT[6:0] is defined in register address 44h. Writing to registers 44h and 46h enables pre-programming of the required clock mode before the PLL output is selected. w PP Rev 3.0 June 2006 14 Pre-Production WM9713L Figure 2 Clocking Architecture for WM9713L w PP Rev 3.0 June 2006 15 WM9713L Clock mode and division ratios are controlled by register 44h as shown in Table 2. REGISTER ADDRESS 44h BIT 14:12 LABEL SEXT[6:4] DEFAULT 000 (div 1) DESCRIPTION Pre-Production Defines clock division ratio for Hi-fi: DSP, ADCs and DACs 000: f 001: f/2 ... 111: f/8 Defines clock division ratio for PCM interface and voice DAC in external clock mode only: 0000: f 0001: f/2 … 1111: f/16 Selects between PLL clock and External clock 0: PLL clock 1: external clock Sets AUXADC clock divisor 000: f/16 001: f/12 010: f/8 011: f/6 100: f/4 101: f/3 110: f/2 111: f Clock doubler for MCLKB Clock doubler for MCLKA Selects between MCLKA and MCLKB (N.B. On power-up clock must be present on MCLKA and must be active for 2 clock cycles after switching to MCLKB) 0: SYSCLK=MCLKA 1: SYSCLK=MCLKB 11:8 SEXT[3:0] 0000 (div 1) 7 CLKSRC 1 (ext clk) 5:3 PENDIV 000 (div 16) 2 1 0 CLKBX2 CLKAX2 CLKMUX 0 (Off) 0 (Off) 0 (MCLKA) Table 2 Clock Muxing and Division Control INTERNAL CLOCK FREQUENCIES The internal clock frequencies are defined as follows (refer to Figure 2): • • AC97 CLK – nominally 24.576MHz, used to generate AC97 BITCLK at 12.288MHz. HIFI CLK – for HIFI playback at 48ks/s HIFI CLK = 24.576MHz. See Table 3 for voice only playback. • Voice DAC CLK – see Table 3 for sample rate vs clock frequency. w PP Rev 3.0 June 2006 16 Pre-Production WM9713L SAMPLE RATE 8ks/s voice and HIFI 8ks/s voice only (power save) 16ks/s voice and HIFI 16ks/s voice only (power save) 32ks/s voice and HIFI 48ks/s voice and HIFI Table 3 Clock Division Mode Table VOICE DAC CLK FREQUENCY 2.048MHz 2.048MHz 4.096MHz 4.096MHz 8.192MHz 12.288MHz HIFI CLK FREQUENCY 24.576MHz 4.096MHz 24.576MHz 8.192MHz 24.576MHz 24.576MHz PEN ADC The clock for the AUXADC nominally runs at 768kHz and is derived from BITCLK. The divisor for the clock generator is set by PENDIV. This enables the AUXADC clock frequency to be set according to power consumption and conversion rate considerations. PLL MODE The PLL operation is controlled by register 46h (see Table 4) and has two modes of operation: • • Integer N Fractional N The PLL has been optimized for nominal input clock (PLL_IN) frequencies in the range 8.192MHz – 19.661MHz (LF=0) and 2.048MHz – 4.9152MHz (LF=1). Through use of a clock divider (div by 2 / 4) on the input to the PLL frequencies up to 78.6MHz can be accommodated. The input clock divider is enabled by DIVSEL (0=Off) and the division ratio is set by DIVCTL (0=div2, 1=div4). Figure 3 PLL Architecture w PP Rev 3.0 June 2006 17 WM9713L REGISTER ADDRESS 46h BIT 15:12 11 10 9 8 6:4 3:0 LABEL N[3:0] LF SDM DIVSEL DIVCTL PGADDR PGDATA DEFAULT 0000 0 = off 0 = off 0 = off 0 000 0000 DESCRIPTION Pre-Production PLL integer division control (must be set between 05h and 0Ch for integer N mode) Allows PLL operation with low frequency input clocks (< 8.192MHz) Sigma Delta Modulator enable. Allows fractional N division Enables input clock to PLL to be divided by 2 or 4. Use if input clock is above 14.4MHz Controls division mode when DIVSEL is high. 0 = div by 2, 1= div by 4. Pager address bits to access programming of K[21:0] and SPLL[6:0] Pager data bits Table 4 PLL Clock Control INTEGER N MODE The nominal output frequency of the PLL (PLL_OUT) is 98.304MHz which is divided by 4 to achieve a nominal system clock of 24.576MHz. The integer division ratio (N) is determined by: FPLL_out / FPLL_IN , and is set by N[3:0] and must be in the range 5 to 12 for integer N operation (0101 = div by 5, 1100 = div by 12). Note that setting LF=1 enables a further division by 4 required for input frequencies in the range 2.048MHz – 4.096MHz. Integer N mode is selected by setting SDM=0. FRACTIONAL N MODE Fractional N mode provides a divide resolution of 1/2 and is set by K[21:0] (register 46h, see section). The relationship between the required division X, the fractional division K[21:0] and the integer division N[3:0] is: 22 K = 2 22 ( X − N ) where 0 < (X – N) < 1 and K is rounded to the nearest whole number. For example, if the PLL_IN clock is 13MHz and the desired PLL_OUT clock is 98.304MHz then the desired division, X, is 7.5618. So N[3:0] will be 7h and K[21:0] will be 23F488h to produce the desired 98.304MHz clock (see Table 5). INPUT CLOCK (PLL_IN) DESIRED PLL OUTPUT (PLL_OUT) 98.304MHz 98.304MHz 98.304MHz 98.304MHz 98.304MHz DIVISION REQUIRED (X) 48 24 8 7.5618 7.2818 FRACTIONAL DIVISION (K) INTEGER DIVISION (N) 2.048MHz 4.096MHz 12.288MHz 13MHz 27MHz (13.5MHz)** 0 0 0 0.5618 0.2818 12x4* 6x4* 8 7 7 *Divide by 4 enabled in PLL feedback path for low frequency inputs. (LF = 1) **Divide by 2 enabled at PLL input for frequencies > 14.4MHz > 38MHz (DIVSEL = 1, DIVCTL = 0) Table 5 PLL Modes of Operation w PP Rev 3.0 June 2006 18 Pre-Production WM9713L PLL REGISTER PAGE ADDRESS MAPPING The clock division control bits SPLL[6:0] and the PLL fractional N division bits are accessed through register 46h using a sub-page address system. The 3 bit pager address allows 8 blocks of 4 bit data words to be accessed whilst the register address is set to 46h. This means that when register address 46h is selected a further 7 cycles of programming are required to set all of the page data bits. Control bit allocation for these page addresses is described in Table 6. PAGE ADDRESS 111 110 BIT 31:28 27:24 LABEL SPLL[6:4] SPLL[3:0] DEFAULT 0h 0h DESCRIPTION Clock division control bus SPLL[6:0]. Clock divider reads this control word if PLL is enabled. Bits [6:4] and [3:0] have the same functionality as 44h [14:12] and [11:8] respectively Reserved bits Sigma Delta Modulator control word for fractional N division. Division resolution is 1/222 101 100 011 010 001 000 23:22 21:20 19:16 15:12 11:8 7:4 3:0 Reserved K[21:0] 0h 0h 0h 0h 0h 0h 0h Table 6 Pager Control Bit Allocation Powerdown for the PLL and internal clocks is via registers 26h and 3Ch (see Table 7). REGISTER ADDRESS 26h 3Ch 9 BIT 13 LABEL PR5 PLL DEFAULT 1 (Off) 1 (Off) DESCRIPTION Internal clock disable (active high) PLL powerdown (active high) N.B. both PR5 and PLL must be asserted low before PLL is enabled Table 7 PLL Powerdown Control DIGITAL INTERFACES The WM9713L has two interfaces, a data and control AC’97 interface and a data only PCM interface. The AC’97 interface is available through dedicated pins (SDATAOUT, SDATAIN, SYNC, BITCLK and RESETB) and is the sole control interface with access to all data streams on the device except for the Voice DAC. The PCM interface is available through the GPIO pins (PCMCLK, PCMFS, PCMDAC and PCMADC) and provides access to the Voice DAC. It can also transmit the data from the Stereo ADC. This can be useful, for example, to allow both sides of a phone conversation to be recorded by mixing the transmit and receive paths on one of the ADC channels and transmitting it over the PCM interface. AC97 INTERFACE INTERFACE PROTOCOL The WM9713L uses an AC’97 interface for both data transfer and control. The AC-Link has 5 wires: • • • • • SDATAIN (pin 8) carries data from the WM9713L to the controller SDATAOUT (pin 5) carries data from the controller to the WM9713L BITCLK (pin 6) is a clock, derived from either MCLKA or MCLKB inputs and supplied to the controller. SYNC is a synchronization signal generated by the controller and passed to the WM9713L RESETB resets the WM9713L to its default state w PP Rev 3.0 June 2006 19 WM9713L Pre-Production Figure 4 AC-Link Interface (typical case with BITCLK generated by the AC97 codec) The SDATAIN and SDATAOUT signals each carry 13 time-division multiplexed data streams (slots 0 to 12). A complete sequence of slots 0 to 12 is referred to as an AC-Link frame, and contains a total of 256 bits. The frame rate is 48kHz. This makes it possible to simultaneously transmit and receive multiple data streams (e.g. audio, touchpanel, AUXDAC, control) at sample rates up to 48kHz. Detailed information can be found in the AC’97 (Revision 2.2) specification, which can be obtained at www.intel.com/design/chipsets/audio/ Note: SDATAOUT and SYNC must be held low when RESETB is applied. These signals must be held low for the entire duration of the RESETB pulse and especially during the low-to-high transition of RESETB. If SDATAOUT or SYNC is high during reset, the WM9713L may enter test modes. Information relating to this operation is available in the AC'97 specification or in Wolfson applications note WAN-0104 available at www.wolfsonmirco.com. PCM INTERFACE OPERATION W M9713L can implement a PCM voice codec function using the dedicated VXDAC and either one or both of the existing hi-fi ADC’s. In PCM codec mode, VXDAC input and ADC output are interfaced via a PCM style port via GPIO pins. This interface can support one ADC channel, or stereo/dual ADC channels if required, (two channels of data are sent per PCM frame as back to back words). In voice only mode, the AC link is used only for control information, not audio data. Therefore it will generally be shut down (PR4=1), except when control data must be sent. The PCM interface makes use of 4 of the GPIO interface pins, for clock, frame, and data in/out. If the PCM codec function is not enabled then the GPIO pins may be used for other functions. INTERFACE PROTOCOL The WM9713L PCM audio interface is used for the input of data to the Voice DAC and the output of data from the Stereo ADC. When enabled, the PCM audio interface uses four GPIO pins: • • • • GPIO1/PCMCLK: Bit clock GPIO3/PCMFS: Frame Sync GPIO4/PCMDAC: Voice DAC data input GPIO5/PCMADC: Stereo ADC data output Depending on the mode of operation (see “PCM Interface Modes”), at least one of these four pins must be set up as an output by writing to register 4Ch (see Table 62). When not enabled the GPIOs may be used for other functions on the WM9713L. w PP Rev 3.0 June 2006 20 Pre-Production WM9713L PCM INTERFACE MODES The WM9713L PCM audio interface may be configured in one of four modes: • • • • Disabled Mode: The WM9713L disables and tri-states all PCM interface pins. Any clock input is ignored and ADC/DAC data is not transferred. Slave Mode: The WM9713L accepts PCMCLK and PCMFS as inputs from an external source. Master Mode: The WM9713L generates PCMCLK and PCMFS as outputs. Partial Master Mode: The WM9713L generates PCMCLK as an output, and accepts PCMFS as an external input. PCM AUDIO DATA FORMATS Four different audio data formats are supported: • • • • DSP mode Left justified Right justified I 2S All four of these modes are MSB first. They are described below. Refer to the Electrical Characteristic section for timing information. The PCM Interface may be configured for Mono mode, where only one channel of ADC data is output. In this mode the interface should be configured for DSP mode. A short or long frame sync is supported and the MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of VXCLK. Note that when operating in stereo mode the mono Voice DAC always uses the left channel data as its input. 1/fs 1 PCMCLK PCMFS PCMCLK PCMADC/ PCMDAC 1 2 3 n-2 n-1 n MSB Input Word Length (WL) LSB Figure 5 PCM Interface Mono Mode (mode A, FSP=0) w PP Rev 3.0 June 2006 21 WM9713L 1/fs 1 PCMCLK Pre-Production PCMFS PCMCLK PCMADC/ PCMDAC 1 2 3 n-2 n-1 n MSB Input Word Length (WL) LSB Figure 6 PCM Interface Mono Mode (mode B, FSP=1) In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of PCMCLK (selectable by FSP) following a rising edge of PCMFS. Right channel data immediately follows left channel data. Depending on word length, PCMCLK frequency and sample rate, there may be unused PCMCLK cycles between the LSB of the right channel data and the next sample. 1/fs 1 BCLK / VXCLK PCMFS PCMCLK LEFT CHANNEL PCMADC/ PCMDAC 1 2 3 n-2 n-1 n 1 2 RIGHT CHANNEL 3 n-2 n-1 n MSB Input Word Length (WL) LSB Figure 7 DSP Mode Audio Interface (mode A, FSP=0) 1/fs 1 BCLK / VXCLK PCMFS PCMCLK LEFT CHANNEL PCMADC/ PCMDAC 1 2 3 n-2 n-1 n 1 2 RIGHT CHANNEL 3 n-2 n-1 n MSB Input Word Length (WL) LSB Figure 7 DSP Mode Audio Interface (mode B, FSP=1) w PP Rev 3.0 June 2006 22 Pre-Production WM9713L In Left Justified mode, the MSB is available on the first rising edge of PCMCLK following a PCMFS transition. The other bits up to the LSB are then transmitted in order. Depending on word length, PCMCLK frequency and sample rate, there may be unused PCMCLK cycles before each PCMFS transition. 1/fs LEFT CHANNEL PCMFS RIGHT CHANNEL PCMCLK PCMADC/ PCMDAC 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n MSB LSB MSB LSB Figure 8 Left Justified Audio Interface (assuming n-bit word length) In Right Justified mode, the LSB is available on the last rising edge of PCMCLK before a PCMFS transition. All other bits are transmitted before (MSB first). Depending on word length, PCMCLK frequency and sample rate, there may be unused PCMCLK cycles after each PCMFS transition. 1/fs LEFT CHANNEL PCMFS RIGHT CHANNEL PCMCLK PCMADC / PCMDAC 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n MSB LSB MSB LSB Figure 9 Right Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of PCMCLK following a PCMFS transition. The other bits up to the LSB are then transmitted in order. Depending on word length, PCMCLK frequency and sample rate, there may be unused PCMCLK cycles between the LSB of one sample and the MSB of the next. 1/fs LEFT CHANNEL PCMFS RIGHT CHANNEL PCMCLK 1 BCLK 1 BCLK 3 n-2 n-1 n 1 2 3 n-2 n-1 n PCMADC/ PCMDAC 1 2 MSB LSB MSB LSB Figure 10 I2S Justified Audio Interface (assuming n-bit word length) w PP Rev 3.0 June 2006 23 WM9713L CONTROL Pre-Production The register bits controlling PCM audio format, word length and operating modes are summarised below. CTRL must be set to override the normal use of the PCM interface pins as GPIOs, MODE must be set to specify master/slave modes. REGISTER ADDRESS 36h PCM Control BIT 15 LABEL CTRL DEFAULT 0 DESCRIPTION Sets function and control registers for GPIO / PCM interface pins. 0 = GPIO pins as GPIOs 1 = GPIO pins configured as PCM interface and controlled by this register PCM interface mode when CTRL=1 00 = PCM interface disabled [PCMCLK tristated, PCMFS tri-stated] 01 = PCM interface in slave mode [PCMCLK as input, PCMFS as input] 10 = PCM interface in master mode [PCMCLK as output, PCMFS as output] 11 = PCM interface in partial master mode [PCMCLK as output, PCMFS as input] Voice DAC clock to PCMCLK divider. In master mode PCMCLK is derived from Voice DAC clock. 000 : PCMCLK = Voice DAC clock 001 : PCMCLK = Voice DAC clock / 2 010 : PCMCLK = Voice DAC clock / 4 011 : PCMCLK = Voice DAC clock / 8 100 : PCMCLK = Voice DAC clock / 16 VXDAC oversample rate: 0: 128 x fs 1: 64 x fs PCMCLK polarity 1 = invert PCMCLK polarity 0 = normal PCMCLK polarity Right, Left and I2S modes – PCMFS polarity 1 = invert PCMFS polarity 0 = normal PCMFS polarity DSP Mode – mode A/B select 0 = MSB is available on 2nd PCMCLK rising edge after LRC rising edge (mode A) 1 = MSB is available on 1st PCMCLK rising edge after LRC rising edge (mode B) PCM ADC channel select 00 = Output left and right ADC data 01 = Swap and output left and right ADC data 10 = Output left ADC data only 11 = Output right ADC data only 14:13 MODE 10 11:9 DIV 010 8 VDACOS R CP 1 7 0 6 FSP 0 5:4 SEL 10 w PP Rev 3.0 June 2006 24 Pre-Production REGISTER ADDRESS BIT 3:2 LABEL WL DEFAULT 00 WM9713L DESCRIPTION PCM Data Word Length 11 = 32 bits (see Note) 10 = 24 bits 01 = 20 bits 00 = 16 bits PCM Data Format Select 11 = DSP Mode 10 = I2S Format 01 = Left justified 00 = Right justified 1:0 FMT 11 Table 8 PCM Codec Control Note: Right justified does not support 32-bit data. w PP Rev 3.0 June 2006 25 WM9713L AUDIO ADCS STEREO ADC Pre-Production The WM9713L has a stereo sigma-delta ADC to digitize audio signals. The ADC achieves high quality audio recording at low power consumption. The ADC sample rate can be controlled by writing to a control register (see “Variable Rate Audio”). It is independent of the DAC sample rate. To save power, the left and right ADCs can be separately switched off using the Powerdown bits ADCL and ADCR (register 3Ch, bits 5:4), whereas PR0 disables both ADCs (see “Power Management” section). If only one ADC is running, the same ADC data appears on both the left and right AC-Link slots. The output from the ADC can be sent over either the AC link as usual, or output via the PCM interface which may be configured on the GPIO pins. HIGH PASS FILTER The WM9713L audio ADC incorporates a digital high pass filter that eliminates any DC bias from the ADC output data. The filter is enabled by default. For DC measurements, it can be disabled by writing a ‘1’ to the HPF bit (register 5Ch, bit 3). This high pass filter corner frequency can be selected to have different values in WM9713L, to suit applications such as voice where a higher cutoff frequency is required. REGISTER ADDRESS 5Ch BIT 3 LABEL HPF DEFAULT 0 DESCRIPTION High-pass filter disable 0: Filter enabled (for audio) 1: Filter disabled (for DC measurements) HPF corner frequency 00: 7Hz @ Fs=48kHz 01: 82Hz @ Fs=16kHz 10: 82Hz @ Fs=8kHz 11: 170Hz @ Fs=8kHz 5Ah 5:4 HPMODE 00 Note: the filter corner frequency is proportional to the sample rate. Table 9 Controlling the ADC Highpass Filter ADC SLOT MAPPING By default, the output of the left audio ADC appears on slot 3 of the SDATAIN signal (pin 8), and the right ADC data appears on slot 4. However, the ADC output data can also be sent to other slots, by setting the ASS (ADC slot select) control bits as shown below. REGISTER ADDRESS 5Ch Additional Functions (2) BIT 1:0 LABEL ASS DEFAULT 00 DESCRIPTION ADC to slot mapping 00: Left = Slot 3, Right = Slot 4 (default) 01: Left = Slot 7, Right = Slot 8 10: Left = Slot 6, Right = Slot 9 11: Left = Slot 10, Right = Slot 11 Table 10 ADC Slot Mapping w PP Rev 3.0 June 2006 26 Pre-Production WM9713L RECORD SELECTOR The record selector determines which input signals are routed into the audio ADC. The left and right channels can be selected independently. This is useful for recording a phone call: one channel can be used for the RX signal and the other for the TX signal, so that both sides of the conversation are digitized. REGISTER ADDRESS 14h Record Routing / Mux Select BIT 6 LABEL RECBST DEFAULT 0 DESCRIPTION 20dB Boost 1: Boost ADC input signal by 20dB 0 :No boost Note: RECBST gain is in addition to the microphone pre-amps (MPABST and MPBBST bits) and record gain (GRL and GRR / GRL bits). Left ADC signal source 000: MICA (pre-PGA) 001: MICB (pre-PGA) 010: LINEL (pre-PGA) 011: MONOIN (pre-PGA) 100: Headphone Mix (left) 101: Speaker Mix 110: Mono Mix 111: Reserved (do not use this setting) Right ADC signal source 000: MICA (pre-PGA) 001: MICB (pre-PGA) 010: LINER (pre-PGA) 011: MONOIN (pre-PGA) 100: Headphone Mix (right) 101: Speaker Mix 110: Mono Mix 111: Reserved (do not use this setting) 5:3 RECSL 000 2:0 RECSR 000 Table 11 Audio Record Selector w PP Rev 3.0 June 2006 27 WM9713L RECORD GAIN Pre-Production The amplitude of the signal that enters the audio ADC is controlled by the Record PGA (Programmable Gain Amplifier). The PGA gain can be programmed either by writing to the Record Gain register, or by the Automatic Level Control (ALC) circuit (see next section). When the ALC is enabled, any writes to the Record Gain register have no effect. Two different gain ranges can be implemented: the standard gain range defined in the AC’97 standard, or an extended gain range with smaller gain steps. The ALC circuit always uses the extended gain range, as this has been found to result in better sound quality. REGISTER ADDRESS 12h Record Gain BIT 15 LABEL RMU DEFAULT 1 DESCRIPTION Mute Audio ADC (both channels) 1: Mute (OFF) 0: No Mute (ON) Gain range select (left) 0: Standard (0 to 22.5dB, 1.5dB step size) 1: Extended (-17.25 to +30dB, 0.75dB steps) Record Volume (left) Standard (GRL=0) XX0000: 0dB XX0001: +1.5dB … (1.5dB steps) XX1111: +22.5dB 7 ZC 0 Extended (GRL=1) 000000: -17.25dB 000001: -16.5dB … (0.75dB steps) 111111: +30dB 14 GRL 0 13:8 RECVOLL 000000 Zero Cross Enable 0: Record Gain changes immediately 1: Record Gain changes when signal is zero or after time-out Gain range select (right) Similar to GRL Record Volume (right) Similar to RECVOLR 6 5:0 GRR RECVOLR 0 000000 Table 12 Record Gain Register The output of the Record PGA can also be mixed into the phone and/or headphone outputs (see “Audio Mixers”). This makes it possible to use the ALC function for the microphone signal in a smartphone application. REGISTER ADDRESS 14h Record Routing BIT 15:14 LABEL R2H DEFAULT 11 (mute) DESCRIPTION Controls record mux to headphone mixer paths. 00=stereo, 01=left rec mux only, 10=right rec mux only, 11=mute left and right Controls gain of record mux l/r to headphone mixer paths. 000: +6dB 001: +3dB ... (3dBsteps) 111: -15dB Controls record mux to mono mixer path. 00=stereo, 01=left rec mux only, 10=right rec mux only, 11=mute left and right Enables 20dB gain boost for record mux to mono mixer path 13:11 R2HVOL 010 (0dB) 10:9 R2M 11 (mute) 8 R2MBST 0 (OFF) Table 13 Record PGA Routing Control w PP Rev 3.0 June 2006 28 Pre-Production WM9713L AUTOMATIC LEVEL CONTROL The WM9713L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary. input signal PGA gain signal after ALC ALC target level hold time decay time attack time Figure 11 ALC Operation The ALC function is enabled using the ALCSEL control bits. When enabled, the recording volume can be programmed between –6dB and –28.5dB (relative to ADC full scale) using the ALCL register bits. HLD, DCY and ATK control the hold, decay and attack times, respectively. HOLD TIME Hold time is the time delay between the peak level detected being below target and the PGA gain beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. DECAY (GAIN RAMP-UP) TIME Decay time is the time that it takes for the PGA gain to ramp up across 90% of its range (e.g. from –15B up to 27.75dB). The time it takes for the recording level to return to its target value therefore depends on both the decay time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the decay time. The decay time can be programmed in power-of-two (2n) steps, from 24ms, 48ms, 96ms, etc. to 24.58s. w PP Rev 3.0 June 2006 29 WM9713L ATTACK (GAIN RAMP-DOWN) TIME Pre-Production Attack time is the time that it takes for the PGA gain to ramp down across 90% of its range (e.g. from 27.75dB down to –15B gain). The time it takes for the recording level to return to its target value therefore depends on both the attack time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the attack time. The attack time can be programmed in power-of-two (2n) steps, from 6ms, 12ms, 24ms, etc. to 6.14s. When operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved. However, the ALC function can also be enabled on one channel only. In this case, only one PGA is controlled by the ALC mechanism, while the other channel runs independently with its PGA gain set through the control register. When one ADC channel is unused, the peak detector disregards that channel. The ALC function can also operate when the two ADC outputs are mixed to mono in the digital domain, but not if they are mixed to mono in the analogue domain, before entering the ADCs. w PP Rev 3.0 June 2006 30 Pre-Production REGISTER ADDRESS 62h ALC / Noise Gate Control BIT 15:14 LABEL ALCSEL DEFAULT 00 (OFF) WM9713L DESCRIPTION ALC function select 00 = ALC off (PGA gain set by register) 01 = Right channel only 10 = Left channel only 11 = Stereo (PGA registers unused) PGA gain limit for ALC 111 = +30dB 110 = +24dB ….(6dB steps) 001 = -6dB 000 = -12dB Programmable zero cross timeout (delay for 12.288MHz BITCLK): 11: 2^17 * tbitclk (10.67 ms) 10: 2^16 * tbitclk (5.33 ms) 01: 2^15 * tbitclk (2.67 ms) 00: 2^14 * tbitclk (1.33 ms) ALC target – sets signal level at ADC input 0000 = -28.5dB FS 0001 = -27.0dB FS … (1.5dB steps) 1110 = -7.5dB FS 1111 = -6dB FS ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms … (time doubles with every step) 1111 = 43.691s ALC decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms … (time doubles with every step) 1010 or higher = 24.58s ALC attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms … (time doubles with every step) 1010 or higher = 6.14s 13:11 MAXGAIN 111 (+30dB) 10:9 ZCTIMEOUT 11 60h ALC Control 15:12 ALCL 1011 (-12dB) 11:8 HLD 0000 (0ms) 7:4 DCY 0011 (192ms) 3:0 ATK 0010 (24ms) Table 14 ALC Control MAXIMUM GAIN The MAXGAIN register sets the maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled. w PP Rev 3.0 June 2006 31 WM9713L PEAK LIMITER Pre-Production To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. (Note: If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used). NOISE GATE W hen the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM9713L has a noise gate function that prevents noise pumping by comparing the signal level at the input pins (i.e. before the record PGA) against a noise gate threshold, NGTH. Provided that the noise gate function is enabled (NGAT = 1), the noise gate cuts in when: Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dB] < NGTH [dB] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). If the NGG bit is set, the ADC output is also muted when the noise gate cuts in. The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 1.5dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set–up of the function. Note that the noise gate only works in conjunction with the ALC function, and always operates on the same channel(s) as the ALC (left, right, both, or none). REGISTER ADDRESS 62h ALC / Noise Gate Control 7 BIT LABEL NGAT DEFAULT 0 DESCRIPTION Noise gate function enable 1 = enable 0 = disable Noise gate type 0 = PGA gain held constant 1 = mute ADC output Noise gate threshold 00000: -76.5dBFS 00001: -75dBFS … 1.5 dB steps 11110: -31.5dBFS 11111: -30dBFS 5 NGG 0 4:0 NGTH(4:0) 00000 Table 15 Noise Gate Control w PP Rev 3.0 June 2006 32 Pre-Production WM9713L AUDIO DACS STEREO DAC The WM9713L has a stereo sigma-delta DAC that achieves high quality audio playback at low power consumption. Digital tone control, adaptive bass boost and 3-D enhancement functions operate on the digital audio data before it is passed to the stereo DAC. (Contrary to the AC’97 specification, they have no effect on analogue input signals or signals played through the auxiliary DAC. Nevertheless, the ID2 and ID5 bits in the reset register, 00h, are set to ‘1’ to indicate that the WM9713L supports tone control and bass boost.) The DAC output has a PGA for volume control. The DAC sample rate can be controlled by writing to a control register (see “Variable Rate Audio”). It is independent of the ADC sample rate. When not in use the DACs can be separately powered down using the Powerdown register bits DACL and DACR (register 3Ch, bits [7:6]). STEREO DAC VOLUME The volume of the DAC output signal is controlled by a PGA (Programmable Gain Amplifier). Each DAC can be mixed into the headphone, speaker and mono mixer paths (see “Audio Mixers”) controlled by register 0Ch. Each DAC-to-mixer path has an independent mute bit. When all DAC-to-mixer paths are muted the DAC PGA is muted automatically. When not in use the DAC PGAs can be powered down using the Powerdown register bits DACL and DACR (register 3Ch, bits [7:6]). REGISTER ADDRESS 0Ch DAC Volume BIT 15 14 13 12:8 LABEL D2H D2S D2M DACL VOL DEFAULT 1 1 1 01000 (0dB) DESCRIPTION Mute DAC path to headphone mixer 1: Mute, 0: No mute (ON) Mute DAC path to speaker mixer 1: Mute, 0: No mute (ON) Mute DAC path to mono mixer 1: Mute, 0: No mute (ON) Left DAC Volume 00000: +12dB … (1.5dB steps) 11111: -34.5dB Right DAC Volume similar to DACLVOL Read-only bit to indicate auto-muting 1: DAC auto-muted 0: DAC not muted DAC Auto-Mute Enable 1: Automatically mutes analogue output of stereo DAC if digital input is zero 0: Auto-mute OFF 4:0 5Ch Additional Functions (2) 15 DACR VOL AMUTE 01000 (0dB) 0 7 AMEN 0 Table 16 Stereo DAC Volume Control w PP Rev 3.0 June 2006 33 WM9713L TONE CONTROL / BASS BOOST Pre-Production The WM9713L provides separate controls for bass and treble with programmable gains and filter characteristics. This function operates on digital audio data before it is passed to the audio DACs. Bass control can take two different forms: • Linear bass control: bass signals are amplified or attenuated by a user programmable gain. This is independent of signal volume, and very high bass gains on loud signals may lead to signal clipping. Adaptive bass boost: The bass volume is amplified by a variable gain. When the bass volume is low, it is boosted more than when the bass volume is high. This method is recommended because it prevents clipping, and usually sounds more pleasant to the human ear. • Treble control applies a user programmable gain, without any adaptive boost function. Treble, linear bass and 3D enhancement can all produce signals that exceed full-scale. In order to avoid limiting under these conditions, it is recommended to set the DAT bit to attenuate the digital input signal by 6dB. The gain at the outputs should be increased by 6dB to compensate for the attenuation. Cut-only tone adjustment (i.e. bass and treble gains 0) and adaptive bass boost cannot produce signals above full-scale and therefore do not require the DAT bit to be set. REGISTER ADDRESS 20h DAC Tone Control BIT 15 LABEL BB DEFAULT 0 DESCRIPTION Bass Mode 0 = Linear bass control 1 = Adaptive bass boost Bass Cut-off Frequency 0 = Low (130Hz at 48kHz sampling) 1 = High (200Hz at 48kHz sampling) Bass Intensity Code 0000 0001 0010 … 0111 … 1011-1101 1110 1111 6 DAT 0 BB=0 +9dB +9dB +7.5dB (1.5dB steps) 0dB (1.5dB steps) -6dB -6dB Bypass (OFF) BB=1 15 (max) 14 13 … 8 … 4-2 1 (min) 12 BC 0 11:8 BASS 1111 (OFF) -6dB attenuation 0 = Off 1 = On Treble Cut-off Frequency 0 = High (8kHz at 48kHz sampling) 1 = Low (4kHz at 48kHz sampling) Treble Intensity 0000 or 0001 = +9dB 0010 = +7.5dB … (1.5dB steps) 1011 to 1110 = -6dB 1111 = Treble Control Disabled 4 TC 0 3:0 TRBL 1111 (Disabled) Table 17 DAC Tone Control Note: 1. All cut-off frequencies change proportionally with the DAC sample rate. w PP Rev 3.0 June 2006 34 Pre-Production WM9713L 3D STEREO ENHANCEMENT The 3D stereo enhancement function artificially increases the separation between the left and right channels by amplifying the (L-R) difference signal in the frequency range where the human ear is sensitive to directionality. The programmable 3D depth setting controls the degree of stereo expansion introduced by the function. Additionally, the upper and lower limits of the frequency range used for 3D enhancement can be selected using the 3DFILT control bits. REGISTER ADDRESS 40h General Purpose 1Eh DAC 3D Control BIT 13 LABEL 3DE DEFAULT 0 (disabled) 0 DESCRIPTION 3D enhancement enable 5 3DLC Lower Cut-off Frequency 0 = Low (200Hz at 48kHz sampling) 1 = High (500Hz at 48kHz sampling) Upper Cut-off Frequency 0 = High (2.2kHz at 48kHz sampling) 1 = Low (1.5kHz at 48kHz sampling) 3D Depth 0000: 0% (minimum 3D effect) 0001: 6.67% …(6.67% steps) 1110: 93.3% 1111: 100% (maximum) 4 3DUC 0 3:0 3DDEPTH 0000 Table 18 Stereo Enhancement Control Note: 1. All cut-off frequencies change proportionally with the DAC sample rate. VOICE DAC VXDAC is a 16-bit mono DAC intended for playback of Rx voice signals input via the PCM interface. Performance has been optimised for operating at 8ks/s or 16ks/s. The VXDAC will function at other sample rates up to 48ks/s, but this is not recommended. The analogue output of VXDAC is routed directly into the output mixers. The signal gain into each mixer can be adjusted at the mixer inputs using control register 18h. When not in use the VXDAC can be powered down using the Powerdown register bit VXDAC (register 3Ch, bit 12). w PP Rev 3.0 June 2006 35 WM9713L REGISTER ADDRESS 3Ch Powerdown (1) 18h VXDAC Output Control BIT 12 15 LABEL VXDAC V2H DEFAULT 1 1 DESCRIPTION VXDAC powerdown bit 1: OFF, 0: ON Pre-Production Mute VXDAC path to headphone mixer 1: Mute, 0: No mute (ON) VXDAC to headphone mixer gain 000: +6dB … (3dB steps) 111: -15dB Mute VXDAC path to speaker mixer 1: Mute, 0: No mute (ON) VXDAC to speaker mixer gain 000: +6dB … (3dB steps) 111: -15dB Mute VXDAC path to mono mixer 1: Mute, 0: No mute (ON) VXDAC to mono mixer gain 000: +6dB … (3dB steps) 111: -15dB 14:12 V2HVOL 010 (0dB) 11 10:8 V2S V2SVOL 1 010 (0dB) 7 6:4 V2M V2MVOL 1 010 (0dB) Table 19 VXDAC Control AUXILIARY DAC AUXDAC is a simple 12-bit mono DAC. It can be used to generate DC signals (with the numeric input written into a control register), or AC signals such as telephone-quality ring tones or system beeps (with the input signal supplied through an AC-Link slot). In AC mode (XSLE = 1), the input data is binary offset coded; in DC mode (XSLE = 0), there is no offset. The analogue output of AUXDAC is routed directly into the output mixers. The signal gain into each mixer can be adjusted at the mixer inputs using control register 12h. In slot mode (XSLE = 1), the AUXDAC also supports variable sample rates (See “Variable Rate Audio” section). When not in use the auxillary DAC can be powered down using the Powerdown register bit AUXDAC (register 3Ch, bit 11). w PP Rev 3.0 June 2006 36 Pre-Production REGISTER ADDRESS 3Ch Powerdown (1) 64h AUXDAC Input Control BIT 11 15 LABEL AUXDAC XSLE DEFAULT 0 0 WM9713L DESCRIPTION AUXDAC powerdown 1: OFF, 0: ON AUXDAC input selection 0: from AUXDACVAL (for DC signals) 1: from AC-Link slot selected by AUXDACSLT (for AC signals) AUXDAC Input Selection 000 – Slot 5, bits 8-19 (with XSLE=1) 001 – Slot 6, bits 8-19 (with XSLE=1) 010 – Slot 7, bits 8-19 (with XSLE=1) 011 – Slot 8, bits 8-19 (with XSLE=1) 100 – Slot 9, bits 8-19 (with XSLE=1) 101 – Slot 10, bits 8-19 (with XSLE=1) 110 – Slot 11, bits 8-19 (with XSLE=1) 111 – RESERVED (do not use) AUXDAC Digital Input (with XSLE=0) 000h: minimum FFFh: full-scale Mute AUXDAC path to headphone mixer 1: Mute, 0: No mute (ON) AUXDAC to headphone mixer gain 000: +6dB … (3dB steps) 111: -15dB Mute AUXDAC path to speaker mixer 1: Mute, 0: No mute (ON) AUXDAC to speaker mixer gain 000: +6dB … (3dB steps) 111: -15dB Mute AUXDAC path to mono mixer 1: Mute, 0: No mute (ON) AUXDAC to mono mixer gain 000: +6dB … (3dB steps) 111: -15dB 14:12 AUXDAC SLT 000 11:0 AUXDAC VAL A2H 000h 1Ah AUXDAC Output Control 15 1 14:12 A2HVOL 010 (0dB) 11 10:8 A2S A2SVOL 1 010 (0dB) 7 6:4 A2M A2MVOL 1 010 (0dB) Table 20 AUXDAC Control w PP Rev 3.0 June 2006 37 WM9713L VARIABLE RATE AUDIO / SAMPLE RATE CONVERSION Pre-Production By using an AC’97 Rev2.2 compliant audio interface, the WM9713L can record and playback at all commonly used audio sample rates, and offer full split-rate support (i.e. the DAC, ADC and AUXDAC sample rates are completely independent of each other – any combination is possible). The default sample rate is 48kHz. If the VRA bit in register 2Ah is set, then other sample rates can be selected by writing to registers 2Ch, 32h and 2Eh. The AC-Link continues to run at 48k frames per second irrespective of the sample rate selected. However, if the sample rate is less than 48kHz, then some frames do not carry an audio sample. REGISTER ADDRESS 2Ah Extended Audio Stat/Ctrl 2Ch Audio DAC Sample Rate 0 BIT LABEL VRA DEFAULT 0 (OFF) DESCRIPTION Variable Rate Audio 0: OFF (DAC and ADC run at 48kHz) 1: ON (sample rates determined by registers 2Ch and 32h) Audio DAC sample rate 1F40h: 8kHz 2B11h: 11.025kHz 2EE0h: 12kHz 3E80h: 16kHz 5622h: 22.05kHz 5DC0h: 24kHz 7D00h: 32kHz AC44h: 44.1kHz BB80h: 48kHz Any other value defaults to the nearest supported sample rate Audio ADC sample rate similar to DACSR AUXDAC sample rate similar to DACSR 15:0 DACSR BB80h (48kHz) 32h Audio ADC Sample Rate 2Eh AUXDAC Sample Rate 15:0 ADCSR BB80h (48kHz) BB80h (48kHz) 15:0 AUXDA CSR Table 21 Audio Sample Rate Control Note: Changing the ADC and / or DAC sample rate will only be effective if the ADC’s and DAC’s are enabled and powered up before the sample rate is changed. This is done by setting the relevant bits in registers 26h and 3Ch, as well as the VRA bit in register 2Ah. The process is as follows: 1. 2. 3. Enable and power up ADC’s and or DAC’s in registers 26h and 3Ch. Enable VRA bit in 2Ah, bit 0. Change the sample rate in the respective register. w PP Rev 3.0 June 2006 38 Pre-Production WM9713L AUDIO INPUTS The following sections give an overview of the analogue audio input pins and their function. For more information on recommended external components, please refer to the “Applications Information” section. LINE INPUT The LINEL and LINER inputs are designed to record line level signals, and/or to mix into one of the analogue outputs. Both pins are directly connected to the record selector. The record PGA adjusts the recording volume, controlled by register 12h or by the ALC function. For analogue mixing, the line input signals pass through a separate PGA, controlled by register 0Ah. The signals can be mixed into the headphone, speaker and mono mixer paths (see “Audio Mixers”). Each LINE-to-mixer path has an independent mute bit. When all LINE-to-mixer paths are muted the line PGA is muted automatically. When the line inputs are not used, the line PGA can be switched off to save power (see “Power Management” section). LINEL and LINER are biased internally to the reference voltage VREF. Whenever the inputs are muted or the device placed into standby mode, the inputs remain biased to VREF using special antithump circuitry to suppress any audible clicks when changing inputs. REGISTER ADDRESS 0Ah BIT 15 14 13 12:8 LABEL L2H L2S L2M LINEL VOL DEFAULT 1 1 1 01000 (0dB) DESCRIPTION Mute LINE path to headphone mixer 1: Mute, 0: No mute (ON) Mute LINE path to speaker mixer 1: Mute, 0: No mute (ON) Mute LINE path to mono mixer 1: Mute, 0: No mute (ON) LINEL input gain 00000: +12dB … (1.5dB steps) 11111: -34.5dB LINER input gain similar to LINELVOL 4:0 LINER VOL 01000 (0dB) Table 22 Line Input Control Additionally, line inputs can be used as single-ended microphone inputs through the record mux to provide a clickless ALC function by bypassing offset introduced through the microphone pre-amps. Note that the line inputs to the mixers should all be deselected if this is input configuration is used. MICROPHONE INPUT MICROPHONE PRE-AMPS There are two microphone pre-amplifiers, MPA and MPB, which can be configured in a variety of ways to accommodate up to 3 selectable differential microphone inputs or 2 differential microphone inputs operating simultaneously for stereo or noise cancellation. The microphone input circuit is shown in Figure 12. w PP Rev 3.0 June 2006 39 WM9713L Pre-Production Vmid MIC1 Vmid 22h: 13-12 22h:11-10 00 = +12dB 11 = +30dB MIC2A Vmid MICA MICB MIC2B 22h:9-8 00 = +12dB 11 = +30dB MICCM Figure 12 Microphone Input Circuit The input pins used for the microphones are MIC1, MICCM, MIC2A and MIC2B. Note that input pins MIC2A and MIC2B are multi-function inputs and must be configured for use as microphone inputs when required. This is achieved using MICCMPSEL[1:0] in register 22h (see Table 23). The input to microphone pre-amp A can be selected from any of the three microphone inputs MIC1, MIC2A and MIC2B using MPASEL[1:0]. Each pre-amp has independent boost control from +12dB to +30dB in four steps. This is controlled by MPABST[1:0] and MPBBST[1:0]. When not in use each microphone pre-amp can be powered down using the Powerdown register bits MPA and MPB (register 3Eh, bits [1:0]). When disabled the inputs are tied to Vmid (for MIC2A and MIC2B this only applies when they are selected as microphone inputs, otherwise they are left floating). REGISTER ADDRESS 22h BIT 15:14 LABEL MICCMPSEL DEFAULT 00 DESCRIPTION MIC2A and MIC2B pin configuration 00: MIC2A and MIC2B microphone inputs 01: MIC2A only 10: MIC2B only 11: neither MPA pre-amp input select 00 : MIC1 01 : MIC2A 10 : MIC2B 11 : unused (do not select) MPA pre-amp gain control 00 : +12dB 01 : +18dB 10 : +24dB 11 : +30dB MPB pre-amp gain control 00 = +12dB 01 = +18dB 10 = +24dB 11 = +30dB 13:12 MPASEL 00 11:10 MPABST 00 9:8 MPBBST 00 Table 23 Microphone Pre-amp Control w PP Rev 3.0 June 2006 40 Pre-Production WM9713L SINGLE MIC OPERATION Up to three microphones can be connected in a single-ended configuration. Any one of the three MICs can be selected as the input to MPA using MPASEL[1:0] (Register 22h, bits 13:12). Only the microphone on MIC2B can be selected to MPB. Note that MPABST always sets the gain for the selected MPA input microphone. If MIC2B is the selected input for MPA it is recommended that MPB is disabled. DUAL MIC OPERATION Up to two microphones can be connected in a dual differential configuration. This is suitable for stereo microphone or noise cancellation applications. Mic1 is connected between the MIC2A and MICCM inputs and mic2 is connected between the MIC2B and MICCM inputs as shown in Figure 13. Additionally, another microphone can be supported on MIC1 selected through the MPA input mux. Note that the microphones can be connected in a single-ended configuration. Figure 13 Dual Microphone Configuration w PP Rev 3.0 June 2006 41 WM9713L MICROPHONE BIASING CIRCUIT Pre-Production The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via MBVOL in register 22h. MICBIAS=0.75*AVDD. When MBVOL=0, MICBIAS=0.9*AVDD and when MBVOL=1, The microphone bias is driven to a dedicated MICBIAS pin 28 and is enabled by MPOP1EN in register 22h. It can also be configured to drive out on GPIO8 pin 12 enabled by MPOP2EN in register 22h. When not in use the microphone bias can be powered down using the Powerdown register bit MICBIAS (register 3Eh, bit 14). REGISTER ADDRESS 22h BIT 7 6 5 LABEL MBOP2EN MBOP1EN MBVOL DEFAULT 0 (Off) 1 (On) 0 DESCRIPTION Microphone bias enable to GPIO8 (pin 12) Microphone bias enable to MICBIAS (pin 28) Microphone bias voltage control 0: 0.9 * AVDD 1: 0.75 * AVDD Table 24 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 14. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA. Figure 14 Microphone Bias Schematic MICBIAS CURRENT DETECT The WM9713L includes a microphone bias current detect circuit with programmable thresholds for the microphone bias current, above which an interrupt will be triggered. There are two separate interrupt bits, MICDET to e.g. distinguish between one or two microphones connected to the WM9713L, and MICSHT to detect a shorted microphone (mic button press). The microphone current detect threshold is set by MCDTHR[2:0], for MICDET, and MCDSCTHR[1:0] for MICSHT. Thresholds for each code are shown in Table 25 When not in use the microphone bias current detect circuit can be powered down using the Powerdown register bit MCD (register 3Eh, bit 15). See the GPIO and Interrupt Controller sections for details on the interrupt and status readback for these MICBIAS current detection features. w PP Rev 3.0 June 2006 42 Pre-Production REGISTER ADDRESS 22h BIT 4:2 LABEL MCDTHR DEFAULT 000 DESCRIPTION WM9713L Mic current detect threshold 000:100uA 001:200uA ….100uA steps up to 111:800uA These values are for 3.3V supply and scale with supply voltage (AVDD). Mic current detect short circuit threshold 00: 600uA 01: 1200uA 10: 1800uA 11: 2400uA These values are for 3.3V supply and scale with supply voltage (AVDD). 1:0 MCDSCTR 00 Table 25 Microphone Current Detect Control MICROPHONE PGAS The microphone pre-amps MPA and MPB drive into two microphone PGAs whose gain is controlled by register 0Eh. The PGA signals can be routed into the headphone mixers and the mono mixer, but not the speaker mixer (to prevent forming a feedback loop) controlled by register 10h. When the PGA signals are not selected as an input to any of the mixers the outputs of the PGAs are muted automatically. When not in use the microphone PGAs can be powered down using the Powerdown register bits MA and MB (register 3Eh, bits [3:2]). REGISTER ADDRESS 0Eh Mic PGA Volume BIT 12:8 LABEL MICAVOL DEFAULT 01000 (0dB) DESCRIPTION MICA input gain 00000: +12dB … (1.5dB steps) 11111: -34.5dB MICB input gain 00000: +12dB … (1.5dB steps) 11111: -34.5dB 4:0 MICBVOL 01000 (0dB) Table 26 Microphone PGA Volume Control REGISTER ADDRESS 10h MIC Routing 7 6 5 4:3 BIT LABEL MA2M MB2M MIC2MBST MIC2H DEFAULT 1 1 0 11 DESCRIPTION Mute MICA path to mono mixer 1: Mute, 0: No mute (ON) Mute MICB path to mono mixer 1: Mute, 0: No mute (ON) Mic to mono mixer boost 0: 0dB, 1: +20dB Mic to headphone mixers select 00: Stereo (MICA to HPL, MICB to HPR) 01: MICA only (MICA to HPL and HPR) 10: MICB only (MICB to HPL and HPR) 11: none (mutes microphone PGAs) Mic PGA to headphone mixers gain 000: +6dB … (3dB steps) 111: -15dB PP Rev 3.0 June 2006 43 2:0 MIC2HVOL 010 (0dB) Table 27 Microphone PGA Routing Control w WM9713L MONOIN INPUT Pre-Production Pin 20 (MONOIN) is a mono input designed to connect to the receive path of a telephony device. The pin connects directly to the record selector for phone call recording (Note: to record both sides of a phone call, one ADC channel should record the MONOIN signal while the other channel records the MIC signal). The record PGA adjusts the recording volume, and is controlled by register 12h or by the ALC function (see “Record Gain” and “Automatic Level Control” sections). REGISTER ADDRESS 14h Record Routing BIT 15:14 LABEL R2H DEFAULT 11 (mute) DESCRIPTION Controls record mux to headphone mixer paths. 00=stereo 01=left rec mux only 10=right rec mux only 11=mute left and right Controls gain of record mux l/r to headphone mixer paths 000: +6dB … (3dB steps) 111: -15dB Controls record mux to mono mixer path. 00=stereo 01=left rec mux only 10=right rec mux only 11=mute left and right Enables 20dB gain boost for record mux to mono mixer path 13:11 R2HVOL 010 (0dB) 10:9 R2M 11 (mute) 8 R2MBST 0 (OFF) Table 28 Record PGA Routing Control To listen to the MONOIN signal, the signal passes through a separate PGA, controlled by register 08h. The signal can be routed into the headphone mixer (for normal phone call operation) and/or the speaker mixer (for speakerphone operation), but not into the mono mixer (to prevent forming a feedback loop). When the signal is not selected as an input to any of the mixers the output of the PGA is muted automatically. When not in use the MONOIN PGA can be powered down using the Powerdown register bit MOIN (register 3Eh, bit 4). MONOIN is biased internally to the reference voltage VREF. Whenever the input is muted or the device placed into standby mode, the input remains biased to VREF using special anti-thump circuitry to suppress any audible clicks when changing inputs. REGISTER ADDRESS 08h MONOIN PGA Vol / Routing BIT 15 14 12:8 LABEL M2H M2S MONOIN VOL DEFAULT 1 1 01000 (0dB) DESCRIPTION Mute MONIN path to headphone mixer 1: Mute, 0: No mute (ON) Mute MONOIN path to speaker mixer 1: Mute, 0: No mute (ON) MONOIN input gain 00000: +12dB … (1.5dB steps) 11111: -34.5dB Table 29 Mono PGA Control w PP Rev 3.0 June 2006 44 Pre-Production WM9713L PCBEEP INPUT Pin 19 (PCBEEP) is a mono, line level input intended for externally generated signal or warning tones. It is routed directly to the record selector and all three output mixers, without an input amplifier. The signal gain into each mixer can be independently controlled, with a separate mute bit for each signal path. PCBEEP is biased internally to the reference voltage VREF. When the signal is not selected as an input to any of the mixers the input remains biased to VREF using special anti-thump circuitry to suppress any audible clicks when changing inputs. REGISTER ADDRESS 16h PCBEEP input BIT 15 14:12 LABEL B2H B2HVOL DEFAULT 1 010 (0dB) DESCRIPTION Mute PCBEEP path to headphone mixer 1: Mute, 0: No mute (ON) PCBEEP to headphone mixer gain 000: +6dB … (3dB steps) 111: -15dB Mute PCBEEP path to speaker mixer 1: Mute, 0: No mute (ON) PCBEEP to speaker mixer gain 000: +6dB … (3dB steps) 111: -15dB Mute PCBEEP path to mono mixer 1: Mute, 0: No mute (ON) PCBEEP to mono mixer gain 000: +6dB … (3dB steps) 111: -15dB 11 10:8 B2S B2SVOL 1 010 (0dB) 7 6:4 B2M B2MVOL 1 010 (0dB) Table 30 PCBEEP Control DIFFERENTIAL MONO INPUT PCBEEP and MONOIN inputs can be configured to provide a differential mono input. This is achieved by mixing the two inputs together using the headphone mixers or the speaker mixer. Note that the gain of the MONOIN PGA must match the gain of the PCBEEP mixer input to achieve a balanced differential mono input. w PP Rev 3.0 June 2006 45 WM9713L AUDIO MIXERS MIXER OVERVIEW Pre-Production The WM9713L has four separate low-power audio mixers to cover all audio functions required by smartphones, PDAs and handheld computers. These mixers are used to drive the audio outputs HPL, HPR, MONO, SPKL, SPKR, OUT3 and OUT4. There are also two inverters used to provide differential output signals (e.g. for driving BTL loads) HEADPHONE MIXERS There are two headphone mixers, headphone mixer left and headphone mixer right (HPMIXL and HPMIXR). These mixers are the stereo output driver source. They are used to drive the stereo outputs HPL and HPR. They can also be used to drive SPKL and SPKR outputs and, when used in conjunction with OUT3 and OUT4, they can be configured to drive complementary signals through the two output inverters to support bridge-tied load (BTL) stereo loudspeaker outputs. The following signals can be mixed into the headphone path: • • • • • • • • MONOIN (controlled by register 08h, see “Audio Inputs”) LINEL/R (controlled by register 0Ah, see “Audio Inputs”) the output of the Record PGA (controlled by register 14h, see “Audio ADC”, “Record Gain”) the stereo DAC signal (controlled by register 0Ch, see “Audio DACs”) the MIC signal (controlled by register 10h, see “Audio Inputs”) PC_BEEP (controlled by register 16h, see “Audio Inputs”) the VXDAC signal (controlled by register 18h, see “Audio DACs”) the AUXDAC signal (controlled by register 1Ah, see “Auxiliary DAC”) In a typical smartphone application, the headphone signal is a mix of MONOIN / VXDAC and sidetone (for phone calls) and the stereo DAC signal (for music playback). When not in use the headphone mixers can be powered down using the Powerdown register bits HPLX and HPRX (register 3Ch, bits [3:2]). SPEAKER MIXER The speaker mixer (SPKMIX) is a mono source. It is typically used to drive a mono loudspeaker in BTL configuration. The following signals can be mixed into the speaker path: • • • • • • MONOIN (controlled by register 08h, see “Audio Inputs”) LINEL/R (controlled by register 0Ah, see “Audio Inputs”) the stereo DAC signal (controlled by register 0Ch, see “Audio DACs”) PC_BEEP (controlled by register 16h, see “Audio Inputs”) the VXDAC signal (controlled by register 18h, see “Audio DACs”) the AUXDAC signal (controlled by register 1Ah, see “Auxiliary DAC”) In a typical smartphone application, the speaker signal is a mix of AUXDAC (for system alerts or ring tone playback), MONOIN / VXDAC (for speakerphone function), and PC_BEEP (for externally generated ring tones). Note that when selected the stereo input pairs LINEL/R and DACL/R are summed and attenuated by -6dB so that 0dBFS signals on each channel sum to give a 0dBFS mono signal. When not in use the speaker mixer can be powered down using the Powerdown register bit SPKX (register 3Ch, bit 1). w PP Rev 3.0 June 2006 46 Pre-Production WM9713L MONO MIXER The mono mixer drives the MONO pin. The following signals can be mixed into MONO: • • • • • • • LINEL/R (controlled by register 0Ah, see “Audio Inputs”) the output of the Record PGA (controlled by register 14h, see “Audio ADC”, “Record Gain”) the stereo DAC signal (controlled by register 0Ch, see “Audio DACs”) the MIC signal (controlled by register 10h, see “Audio Inputs”) PC_BEEP (controlled by register 16h, see “Audio Inputs”) the VXDAC signal (controlled by register 18h, see “Audio DACs”) the AUXDAC signal (controlled by register 12h, see “Auxiliary DAC”) In a typical smartphone application, the MONO signal is a mix of the amplified microphone signal (possibly with Automatic Gain Control) and (if enabled) an audio playback signal from the stereo DAC or the auxiliary DAC. Note that when selected the stereo input pairs LINEL/R and DACL/R are summed and attenuated by -6dB so that 0dBFS signals on each channel sum to give a 0dBFS mono signal. When not in use the mono mixer can be powered down using the Powerdown register bit MX (register 3Ch, bit 0). MIXER OUTPUT INVERTERS There are two general purpose mixer output inverters, INV1 and INV2. Each inverter can be selected to drive HPMIXL, HPMIXR, SPKMIX, MONOMIX or { ( HPMIXL + HPMIXR ) / 2 }. The outputs of the inverters can be used to generate complimentary signals (to drive BTL configured loads) and to provide greater flexibility in output driver configurations. INV1 can be selected as the source for SPKL, MONO and OUT3 and INV2 as the source for SPKR and OUT4. The input source for each inverter is selected using INV1[2:0] and INV2[2:0] in register 1Eh (see Table 31). When no input is selected the inverter is powered down. REGISTER ADDRESS 1Eh BIT 15:13 LABEL INV1 DEFAULT 000 (OFF) DESCRIPTION INV1 source select 000: ZH (OFF – no source selected) 001: MONOMIX 010: SPKMIX 011: HPMIXL 100: HPMIXR 101: HPMIXMONO 110: unused 111: Vmid INV2 source select Same as INV1 12:10 INV2 000 (OFF) Table 31 Mixer Inverter Source Select w PP Rev 3.0 June 2006 47 WM9713L ANALOGUE AUDIO OUTPUTS Pre-Production The following sections give an overview of the analogue audio output pins. The WM9713L has three outputs capable of driving loads down to 16Ω (headphone / line drivers) – HPL, HPR and MONO and four outputs capable of driving loads down to 8Ω (loudspeaker / line drivers) – SPKL, SPKR, OUT3 and OUT4. The combination of output drivers, mixers and mixer inverters means that many output configurations can be supported. For examples of typical output and mixer configurations please refer to the “Typical Output Configurations” section. For more information on recommended external components, please refer to the “Applications Information” section. Each output is driven by a PGA with a gain range of 0dB to -46.5dB in -1.5dB steps. Each PGA has an input source mux, mute and zero-cross detect circuit (delaying gain changes until a zero-cross is detected, or after time-out). HEADPHONE OUTPUTS – HPL AND HPR The HPL and HPR outputs (pins 39 and 41) are designed to drive a 16Ω or 32Ω headphone load. They can also be used as line outputs. They can be used in and AC coupled or DC coupled (capless) configuration. The available input sources are HPMIXL/R and Vmid (see Table 32). REGISTER ADDRESS 1Ch Output PGA Mux Select BIT 7:6 LABEL HPL DEFAULT 00 (Vmid) DESCRIPTION HPL input source select 00: Vmid 01: no input (tri-stated if HPL=1 in register 3Eh) 10: HPMIXL 11: unused HPR input source select 00: Vmid 01: no input (tri-stated if HPR=1 in register 3Eh) 10: HPMIXR 11: unused 5:4 HPR 00 (Vmid) Table 32 HPL / HPR PGA Input Source The signal volume on HPL and HPR can be independently adjusted under software control by writing to register 04h. When not in use HPL and HPR can be powered down using the Powerdown register bits HPL and HPR (register 3Eh, bits [10:9]). To minimise pops and clicks when the PGA is powered down / up it is recommended that the Vmid input is selected during the power down / up cycle. This ensures the same DC level is maintained on the output pin throughout. w PP Rev 3.0 June 2006 48 Pre-Production REGISTER ADDRESS 04h Headphone Volume BIT 15 LABEL MUL DEFAULT 1 (Mute) WM9713L DESCRIPTION Mute HPL 1: Mute (OFF) 0: No Mute (ON) Left zero cross enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out HPL Volume 000000: 0dB (maximum) 000001: -1.5dB … (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB Mute HPR 1: Mute (OFF) 0: No Mute (ON) Right zero cross enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out HPR Volume Similar to HPLVOL 14 ZCL 0 13:8 HPLVOL 000000 (0dB) 7 MUR 1 (Mute) 6 ZCR 0 5:0 HPRVOL 000000 (0dB) Table 33 HPL / HPR PGA Control MONO OUTPUT The MONO output (pin 31) is designed to drive a 16Ω headphone load and can also be used as a line output. The available input sources are MONOMIX, INV1 and Vmid (see Table 34) REGISTER ADDRESS 1Ch Output PGA Mux Select BIT 15:14 LABEL MONO DEFAULT 00 (Vmid) DESCRIPTION MONO input source select 00: Vmid 01: no input (tri-stated if MONO=1 in register 3Eh) 10: MONOMIX 11: INV1 Table 34 MONO PGA Input Source The signal volume on MONO can be independently adjusted under software control by writing to register 08h. When not in use MONO can be powered down using the Powerdown register bit MONO (register 3Eh, bit 13). To minimise pops and clicks when the PGA is powered down / up it is recommended that the Vmid input is selected during the power down / up cycle. This ensures the same DC level is maintained on the output pin throughout. w PP Rev 3.0 June 2006 49 WM9713L REGISTER ADDRESS 08h MONO Vol BIT 7 MU LABEL DEFAULT 1 (Mute) Pre-Production DESCRIPTION Mute MONO 1: Mute (OFF) 0: No Mute (ON) Right zero cross enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out MONO Volume 000000: 0dB (maximum) 000001: -1.5dB … (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB 6 ZC 0 5:0 MONOVOL 000000 (0dB) Table 35 Mono PGA Control SPEAKER OUTPUTS – SPKL AND SPKR The SPKL and SPKR (pins 35 and 36) are designed to drive a loudspeaker load down to 8Ω and can also be used as line outputs and headphone outputs. They are designed to drive an 8Ω load AC coupled or in a BTL (capless) configuration. The available input sources are HPMIXL/R, SPKMIXL/R, INV1/2 and Vmid (see Table 36). REGISTER ADDRESS 1Ch Output PGA Mux Select BIT 13:11 LABEL SPKL DEFAULT 000 (Vmid) DESCRIPTION SPKL input source select 000: Vmid 001: no input (tri-stated if SPKL=1 in register 3Eh) 010: HPMIXL 011: SPKMIX 100: INV1 101-111: unused SPKR input source select 000: Vmid 001: no input (tri-stated if SPKR=1 in register 3Eh) 010: HPMIXR 011: SPKMIX 100: INV2 101-111: unused 10:8 SPKR 000 (Vmid) Table 36 SPKL / SPKR PGA Input Source The signal volume on SPKL and SPKR can be independently adjusted under software control by writing to register 02h. When not in use SPKL and SPKR can be powered down using the Powerdown register bits SPKL and SPKR (register 3Eh, bits [8:7]). To minimise pops and clicks when the PGA is powered down / up it is recommended that the Vmid input is selected during the power down / up cycle. This ensures the same DC level is maintained on the output pin throughout. w PP Rev 3.0 June 2006 50 Pre-Production REGISTER ADDRESS 02h Speaker Volume BIT 15 LABEL MUL DEFAULT 1 (Mute) WM9713L DESCRIPTION Mute SPKL 1: Mute (OFF) 0: No Mute (ON) Left zero cross enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out SPKL Volume 000000: 0dB (maximum) 000001: -1.5dB … (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB Mute SPKR 1: Mute (OFF) 0: No Mute (ON) Right zero cross enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out SPKR Volume Similar to SPKLVOL 14 ZCL 0 13:8 SPKLVOL 000000 (0dB) 7 MUR 1 (Mute) 6 ZCR 0 5:0 SPKRVOL 000000 (0dB) Table 37 SPKL / SPKR PGA Control Note: 1. For BTL speaker drive, it is recommended that both PGAs have the same gain setting. AUXILIARY OUTPUTS – OUT3 AND OUT4 The OUT3 and OUT4 outputs (pins 37 and 33) are designed to drive a loudspeaker load down to 8Ω and can also be used as line outputs and headphone outputs. They are designed to drive an 8Ω load AC coupled or in a BTL (capless) configuration and can be used as a midrail buffer to drive the headphone outputs in a capless DC configuration. The available input sources are INV1/2 and Vmid (see Table 38). REGISTER ADDRESS 1Ch Output PGA Mux Select BIT 3:2 LABEL OUT3 DEFAULT 00 (Vmid) DESCRIPTION OUT3 input source select 00: Vmid 01: no i/p (ZH if buffer disabled) 10: INV1 11: unused OUT4 input source select 00: Vmid 01: no i/p (ZH if buffer disabled) 10: INV2 11: unused 1:0 OUT4 00 (Vmid) Table 38 OUT3 / OUT4 PGA Input Source The signal volume on OUT3 and OUT4 can be independently adjusted under software control by writing to register 06h. When not in use OUT3 and OUT4 can be powered down using the Powerdown register bits OUT3 and OUT4 (register 3Eh, bits [11:12]). To minimise pops and clicks when the PGA is powered down / up it is recommended that the Vmid input is selected during the power down / up cycle. This ensures the same DC level is maintained on the output pin throughout. w PP Rev 3.0 June 2006 51 WM9713L REGISTER ADDRESS 06h Speaker Volume BIT 15 LABEL MU4 DEFAULT 1 (Mute) Pre-Production DESCRIPTION Mute OUT4 1: Mute (OFF) 0: No Mute (ON) OUT4 zero cross enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out OUT4 Volume 000000: 0dB (maximum) 000001: -1.5dB … (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB Mute OUT3 1: Mute (OFF) 0: No Mute (ON) OUT3 zero cross enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out OUT3 Volume Similar to OUT4VOL 14 ZC4 0 13:8 OUT4VOL 000000 (0dB) 7 MU3 1 (Mute) 6 ZC3 0 5:0 OUT3VOL 000000 (0dB) Table 39 OUT3 / OUT4 PGA Control THERMAL SENSOR The speaker and headphone outputs can drive very large currents. To protect the WM9713L from becoming too hot, a thermal sensor has been built in. If the chip temperature reaches approximately 150°C, and the TI bit is set, the WM9713L deasserts GPIO bit 11 in register 54h, a virtual GPIO that can be set up to generate an interrupt to the CPU (see “GPIO and Interrupt Control” section). REGISTER ADDRESS 3Ch BIT 13 LABEL TSHUT DEFAULT 1 DESCRIPTION Power down thermal sensor 0: Enabled 1: Disabled Thermal sensor (virtual GPIO) 1: Temperature below 150°C 0: Temperature above 150°C See also “GPIO and Interrupt Control” section. 54h 11 TI 0 Table 40 Thermal Cutout Control w PP Rev 3.0 June 2006 52 Pre-Production WM9713L JACK INSERTION AND AUTO-SWITCHING In a phone application, a BTL ear speaker may be connected across MONO and HPL, a stereo headphone on HPL and HPR and stereo speakers on SPKL, SPKR, OUT3 and OUT4 (see Figure 15). Typically, only one of these three output devices is used at any given time: when no headphone is plugged in, the BTL ear speaker or stereo speakers are active, otherwise the headphone is used. Figure 15 Typical Output Configuration The presence of a headphone can be detected using one of GPIO1/6/7/8 (pins 44, 3, 11 & 12) and an external pull-up resistor (see Figure 41, page 103 for a circuit diagram). When the jack is inserted, the GPIO is pulled low by a switch on the socket. When the jack is removed the GPIO is pulled high by a resistor. If the JIEN bit is set, the WM9713L automatically switches between headphone and any other output configuration, typically ear speaker or stereo speaker that has been set up in the Powerdown and Output PGA Mux Select registers. Note: Please refer to WAN_0182 for further information on jack detect configuration. In addition to the typical configuration explained above, the WM9713L can also support automatic switching between the following three configurations set as BTL ear speaker and headphone. REGISTER ADDRESS 24h Output Volume Mapping (Jack Insert) BIT 1:0 LABEL EARSPKSEL DEFAULT 00 DESCRIPTION 00: Default, no ear speaker configuration selected. 01: MONO and HPL driver selected as BTL ear speaker. 10: OUT3 and HPL driver selected as BTL ear speaker. 11: OUT4 and HPL driver selected as BTL ear speaker. Table 41 Ear Speaker Configuration For example if OUT4 and HPL is selected as the BTL ear speaker, the user should select EARSPKSEL = 3h, then OUT4 is tri-stated on jack insert to prevent sound across the ear speaker during headphone operation and HPL volume is set to OUT4 volume on jack out to ensure correct ear speaker operation. It should be noted that all other outputs except HPL, HPR and selected ear speaker driver are disabled and internally connected to VREF on jack insert. This maintains VREF at those outputs and helps prevent pops when the outputs are enabled. w PP Rev 3.0 June 2006 53 WM9713L Pre-Production Finally if the user wishes to DC couple the headphone outputs the user needs to select between OUT3 and OUT4 as the mid-rail output buffer driver. The selected mid-rail output buffer is enabled on jack insert. On jack out it defaults to whatever configuration has been set up in the Powerdown and Output PGA Mux Select registers. REGISTER ADDRESS 24h Output Volume Mapping (Jack Insert) BIT 3:2 LABEL DCDRVSEL DEFAULT 00 DESCRIPTION 00: Default, AC coupled headphone. 01: OUT4 as mid-rail output buffer. 11: OUT3 as mid-rail output buffer. Table 42 DC Coupled Headphone Configuration In summary: JIEN not set: Outputs work as normal as selected in the Powerdown and Output PGA Mux Select registers. JIEN set: On jack insert GPIO1/6/7/8 is pulled low, HPL and HPR are enabled, DCDRVSEL decides if the headphones are DC or AC coupled and configures OUT3 or OUT4 to suit, EARSPKSEL decides if MONO, OUT3 or OUT4 need to be tri-stated to ensure no sound out on the ear-speaker and finally all other outputs are disabled as explained above to prevent pops on re-enabling. On jack out GPIO1/6/7/8 is pulled high, the outputs work as normal as selected in the Powerdown and Output PGA Mux Select registers except that HPL Volume is controlled by EARSPKSEL to ensure correct ear speaker operation. REGISTER ADDRESS 24h Output Volume Mapping (Jack Insert) 5Ah Additional Functions (1) BIT 4 LABEL JIEN DEFAULT 0 (OFF) DESCRIPTION Jack Insert Enable – Takes output of GPIO1 logic 7:6 JSEL 00 (GPIO1) GPIO select for jack insert detection: 00: GPIO1 01: GPIO6 10: GPIO7 11: GPIO8 Table 43 Jack Insertion / Auto-Switching (1) w PP Rev 3.0 June 2006 54 Pre-Production WM9713L HPR VOLUME MONO STATE HPL VOLUME MODE DESCRIPTION GPIO1 User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled HZ HZ HZ HZ HZ User Controlled User Controlled 1 00 00 0 Jack Insert Detection Enabled. Headphone plugged in. No Ear Speaker Selected. AC Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged in. MONO Ear Speaker Selected. AC Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged in. OUT3 Ear Speaker Selected. AC Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged in. OUT4 Ear Speaker Selected. AC Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged in. OUT4 Ear Speaker Selected. OUT3 DC Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged out. No Ear Speaker Selected. Jack Insert Detection Enabled. Headphone plugged out. OUT4 Ear Speaker Selected. HPR Volume HPL Volume Enabled Enabled HZ HZ HZ 1 01 00 0 HPR Volume HPL Volume Tri-Stated Enabled Enabled HZ HZ 1 10 00 0 HPR Volume HPL Volume Tri-Stated Enabled Enabled HZ HZ 1 11 00 0 HPR Volume HPL Volume Tri-Stated Enabled Enabled HZ HZ 1 11 01 0 HPR Volume HPL Volume Tri-Stated Enabled Enabled VMID HZ User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled 1 11 XX 1 User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled Table 44 Jack Insertion / Auto-Switching (2) w PP Rev 3.0 June 2006 55 User Controlled OUT4 Volume User Controlled 1 00 XX 1 HZ HZ HZ HZ HZ User Controlled 0 XX XX X Jack Insert Detection Disabled. SPKR STATE SPKL STATE OUT3 STATE OUT4 STATE EARSPKSEL HPR STATE HPL STATE DCDRVSEL JIEN WM9713L DIGITAL AUDIO (SPDIF) OUTPUT Pre-Production The WM9713L supports the SPDIF standard. Pins 48 & 12 can be used to output the SPDIF data. Note that pins 48 & 12 can also be used as GPIO pins. The GE5 & GE8 bits (register 56h, bit 5 & bit 8) select between GPIO and SPDIF functionality for pins 48 & 12 respectively (see “GPIO and Interrupt control” section). Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or sub-frame in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in register 2Ah is ‘0’). Once the desired values have been written to this register, the contents should be read back to ensure that the sample rate in particular is supported, then SPDIF validity bit SPCV in register 2Ah should be read to ensure the desired configuration is valid. Only then should the SPDIF enable bit in register 2Ah be set. This ensures that control and status information start up correctly at the beginning of SPDIF transmission. REGISTER ADDRESS 2Ah Extended Audio BIT 10 5:4 LABEL SPCV SPSA DEFAULT 0 01 DESCRIPTION SPDIF validity bit (read-only) SPDIF slot assignment (ADCO = 0) 00: Slots 3, 4 01: Slots 6, 9 10: Slots 7, 8 11: Slots 10, 11 SPDIF output enable 1 = enabled, 0 = disabled Validity bit; ‘0’ indicates frame valid, ‘1’ indicates frame not valid Indicates that the WM9713L does not support double rate SPDIF output (read-only) Indicates that the WM9713L only supports 48kHz sampling on the SPDIF output (readonly) Generation level; programmed as required by user Category code; programmed as required by user Pre-emphasis; ‘0’ indicates no pre-emphasis, ‘1’ indicates 50/15us pre-emphasis Copyright; ‘0’ indicates copyright is not asserted, ‘1’ indicates copyright Non-audio; ‘0’ indicates data is PCM, ‘1’ indicates non-PCM format (e.g. DD or DTS) Professional; ‘0’ indicates consumer, ‘1’ indicates professional Source of SPDIF data 0: SPDIF data comes from SDATAOUT (pin 5), slot selected by SPSA 1: SPDIF data comes from audio ADC 2 3Ah SPDIF Control Register 15 14 13:12 SEN V DRS SPSR 0 0 0 10 11 10:4 3 2 1 0 5Ch Additional Function Control 4 L CC PRE COPY AUDIB PRO ADCO 0 0000000 0 0 0 0 0 Table 45 SPDIF Output Control w PP Rev 3.0 June 2006 56 Pre-Production WM9713L TOUCHPANEL INTERFACE The WM9713L includes a touchpanel driver and digitiser circuit for use with 4-wire or 5-wire resistive touchpanels. The following functions are implemented: X co-ordinate measurement Y co-ordinate measurement Pen down detection, with programmable sensitivity Touch pressure measurement (4-wire touchpanel only) Auxiliary measurement from COMP1/AUX1 (pin 29), COMP2/AUX2 (pin 30), or WIPER/AUX4 (pin 12) The touchpanel digitiser uses a very low power, 12-bit successive approximation type ADC. The same ADC can also be used for battery and auxiliary measurements (see the “Battery Alarm and Battery Measurement” and “Auxiliary ADC Inputs” sections). An on-chip switch matrix connects each touchpanel terminal to the supply voltage TPVDD, to ground (TPGND), or to the ADC input, as required. Figure 16 Touchpanel Switch Matrix w PP Rev 3.0 June 2006 57 WM9713L PRINCIPLE OF OPERATION - FOUR-WIRE TOUCHPANEL Four-wire touchpanels are connected to the WM9713L as follows: • • • • Right side contact = X+ (pin 14) Left side contact = X- (pin 16) Top side contact = Y+ (pin 15) Bottom side contact = Y- (pin 17) Pre-Production The principle of operation is illustrated below (Note: the illustrations assume that the top plate is used for X and the bottom plate for Y measurements, although the reverse is also possible). Figure 17 X Co-ordinate Measurement on 4-wire Touchpanel For an X co-ordinate measurement, the X+ pin is internally switched to TPVDD and X- to TPGND. The X plate becomes a potential divider, and the voltage at the point of contact is proportional to its X co-ordinate. This voltage is measured on the Y+ and Y- pins, which carry no current (hence there is no voltage drop in RY+ or RY-). Due to the ratiometric measurement method, the supply voltage does not affect measurement accuracy. The voltage references VREF+ and VREF- are taken from after the matrix switches, so that any voltage drop in these switches has no effect on the ADC measurement. Figure 18 Y Co-ordinate Measurement on 4-wire Touchpanel Y co-ordinate measurements are similar to X co-ordinate measurements, with the X and Y plates interchanged. w PP Rev 3.0 June 2006 58 Pre-Production WM9713L Figure 19 Pen Down Detection on 4-wire Touchpanel Pen down detection uses a zero power comparator (effectively a CMOS logic gate) with an internal, programmable pull-up resistor RPU that controls pen-down sensitivity. Increasing RPU makes the touchpanel less sensitive to touch, while lowering RPU makes it more sensitive. When the touchpanel is not being touched, no current flows in the circuit, and the PENDOWN signal is low. When the panel is touched with a pen or finger, current flows through RPU and the panel, and the comparator output goes high. The PENDOWN signal can be read from bit 15 in register 7Ah (labeled PNDN). It can also be observed on pin 46 (GPIO3 / PENDOWN), if the pin is not used for GPIO (GE3=0). Additionally, PENDOWN is passed to the GPIO logic block (register 54h, bit 13), where it can generate CPU interrupts, and / or to wake up the WM9713L from sleep mode (see “GPIO and Interrupt Control” section). Figure 20 Touch Pressure Measurement on 4-wire Touchpanel Touch pressure can be determined indirectly by measuring the contact resistance RC between the top and bottom plates. RC decreases as the touch pressure on the panel increases. The WM9713L measures RC by sending a constant current IP through the touchpanel and measuring the potential on each plate. The two values are subtracted in the digital domain to obtain the potential difference, which is proportional to RC. To suit different types of touchpanels, the magnitude of IP can be set to either 400µA or 200µA using the PIL control bit. w PP Rev 3.0 June 2006 59 WM9713L PRINCIPLE OF OPERATION - FIVE-WIRE TOUCHPANEL Five-wire touchpanels are connected to the WM9713L as follows: Top sheet contact = WIPER/AUX4 (pin 12) Top left corner of bottom sheet = TL (pin 16) Top right corner of bottom sheet = TR (pin 15) Bottom left corner of bottom sheet = BL (pin 17) Bottom right corner of bottom sheet = BR (pin 14) Pre-Production Figure 21 X Co-ordinate Measurement on 5-wire Touchpanel For an X co-ordinate measurement, the top left and bottom left corners of the touchpanel are grounded internally to the WM9713L, while the top right and bottom right contacts are connected to TPVDD. The bottom plate becomes a potential divider with a voltage gradient in the X direction. The voltage at the point of contact is proportional to its X co-ordinate. This voltage is measured on the WIPER pin and converted to a digital value by the ADC. Due to the ratiometric measurement method, the supply voltage does not affect measurement accuracy. The voltage references VREF+ and VREF- are taken from after the matrix switches, so that any voltage drop in these switches has no effect on the ADC measurement. Figure 22 Y Co-ordinate Measurement on 5-wire Touchpanel w PP Rev 3.0 June 2006 60 Pre-Production WM9713L Y co-ordinate measurements are similar to Y co-ordinate measurements. However, the voltage gradient on the bottom plate is in the Y direction instead of the X direction. This is achieved by grounding the bottom left and bottom right corners of the touchpanel, and connecting the top left and top right contacts to TPVDD. Figure 23 Pen Down Detection on 5-wire Touchpanel Pen down detection works in a similar fashion for both 4-wire and 5-wire touchpanels (see Four-Wire Touchpanel Operation). On a 5-wire touchpanel, all four contacts of the bottom plate are grounded, and the top plate contact is connected to the internal programmable pull-up resistor, RPU. w PP Rev 3.0 June 2006 61 WM9713L CONTROLLING THE TOUCHPANEL DIGITISER All touchpanel functions are accessed and controlled through the AC-Link interface. Pre-Production PHYSICAL CHARACTERISTICS The physical characteristics of the touchpanel interface are controlled through register 78h, as shown below. REGISTER ADDRESS 78h BIT 12 LABEL 45W DEFAULT 0 (4-wire) DESCRIPTION Touchpanel Type Selection 0: 4-wire 1: 5-wire Current used for pressure measurement 0: IP = 200µA 1: IP = 400µA Internal Pull-up resistor for Pen Detection 111111: 64kΩ/63 = 1.02kΩ (least sensitive) 111110: 64KΩ/62 = 1.03KΩ … (pull-up = 64kΩ / binary value of RPU) 000010: 64KΩ/2 = 32KΩ 000001: 64kΩ/1 = 64kΩ (most sensitive) 000000: RESERVED (do not use this setting) 8 PIL 0 (200µA) 0:5 RPU 000001 (64kΩ) Table 46 Touchpanel Digitiser Control (Physical Characteristics) POWER MANAGEMENT To save power, the touchpanel digitiser and the pen-down detector can be independently disabled when they are not used. The power consumption of the pen-down detector is normally negligible, except when the pen is down. The pen ADC is powered-down using PADCPD, register 3Ch bit 15. The state of the digitiser and pen down detector is controlled by the following bits. REGISTER ADDRESS 3Ch 78h BIT 15 15:14 LABEL PADCPD PRP DEFAULT 1 = off 00 DESCRIPTION Pen ADC power down Pen ADC/AUX ADC enable 00 – Pen digitiser off, pen detect off, no wake-up on pen down (default) 01 – Pen digitiser powered off, pen detect enabled, touchpanel digitiser wakes up (changes to state 11) on pen-down 10 – Pen digitiser off, pen detect enabled, no wake-up on pen down 11 – Pen digitiser and pen detect enabled Wake-up on pen-down mode 0: Wake-up the AC-Link only (hold SDATAIN high until controller sends warm reset or cold reset) 1: Wake-up the WM9713L without waiting for a reset signal from the controller 13 RPR 0 Table 47 Touchpanel Digitiser Control (Power Management) w PP Rev 3.0 June 2006 62 Pre-Production WM9713L INITIATION OF MEASUREMENTS The WM9713L touchpanel interface supports both polling routines and DMA (direct memory access) to control the flow of data from the touchpanel ADC to the host CPU. In a polling routine, the CPU starts each measurement individually by writing to the POLL bit (register 74h, bit 9). This bit automatically resets itself when the measurement is completed. REGISTER ADDRESS 74h 9 BIT LABEL POLL DEFAULT 0 DESCRIPTION Writing “1” initiates a measurement. (when CTC is not set) 8 76h 9:8 CTC CR 0 00 0: Polling mode 1: Continuous mode (for DMA) Continuous mode rate (DEL C 1111) 00: 93.75 Hz (every 512 AC-Link frames) 01: 120 Hz (every 400 AC-Link frames) 10: 153.75 Hz (every 312 AC-Link frames) 11: 187.5Hz (every 256 AC-Link frames) Continuous mode “fast rate” (DEL = 1111) 00: 8 kHz (every six AC-Link frames) 01: 12 kHz (every four AC-Link frames) 10: 24 kHz (every other AC-Link frame) 11: 48 kHz (every AC-Link frame) NOTE: PENDIV bits in 44h [5:3] should be set to 111 in 48kHz mode to ensure that samples occur synchronously on the AC97 data channel 78h 11 PDEN 0 0: measure regardless of pen status 1: measure only when pen is down (when CTC=0 and POLL=1, measurement is delayed until pen-down; when CTC=1, measurements are stopped on pen-up) Sets polarity of PENDOWN flag: 0: non-inverted 1: inverted 10 PDPOL 0 Table 48 Touchpanel Digitiser Control (Initiation of Measurements) In continuous mode (CTC = 1), the WM9713L autonomously initiates measurements (or sets of measurements) at the rate set by CR, and supplies the measured data to the CPU on one of the unused AC’97 time slots. DMA-enabled CPUs can write the data directly into a FIFO without any intervention by the CPU core. This reduces CPU loading and speeds up the execution of user programs in handheld systems. Note that the measurement frequency in continuous mode is also affected by the DEL bits (see “Touchpanel Settling Time”). The faster rates achieved when DEL = 1111 may be useful when the ADC is used for auxiliary measurements. w PP Rev 3.0 June 2006 63 WM9713L MEASUREMENT TYPES Pre-Production The ADCSEL control bits determine which type of measurement is performed (see below). REGISTER ADDRESS 74h BIT 9 POLL LABEL DEFAULT 0 DESCRIPTION Writing “1” initiates a measurement. (when CTC is not set) 8 7 6 5 4 3 2 1 0 CTC ADCSEL_AUX4 ADCSEL_AUX3 ADCSEL_AUX2 ADCSEL_AUX1 ADCSEL_PRESSURE ADCSEL_Y ADCSEL_X COO 0 0 0 0 0 0 0 0 0 0: Polling mode 1: Continuous mode (for DMA) Enable AUX4 measurement (pin 12) Enable AUX3 measurement Enable AUX2 measurement (pin 30) Enable AUX1 measurement (pin 29) Enable touchpanel pressure measurement Enable touchpanel Y co-ord measurement Enable touchpanel X co-ord measurement Enable co-ordinate mode 0: Single measurement. A single measurement is made depending on the setting of ADCSEL[7:1]. 1: Co-ordinate measurement. X, then Y, followed by an additional measurement indicated by ADCSEL[7:1]. If more than one ADCSEL[7:1] bit is selected then the third, additional, measurement will alternate sequentially between those selected. Table 49 Touchpanel Digitiser Control (Measurement Types) W hen COO is ‘0’, the WM9713L performs a single measurement – either in polling mode or continuously, as indicated by the CTC bit. The type of measurement is specified by the ADCSEL[7:1] bits. If CTC=0 (polling mode) then only one of the ADCSEL[7:1] bits should be set. If operating in continuous mode (CTC=1), then more than one ADCSEL[7:1] bit may be set and selected conversions will be performed cyclically in the following order => “X,Y,PRESSURE,AUX1,AUX2,AUX3,AUX4…” The co-ordinate mode (COO = ‘1’) makes it easier to obtain co-ordinate pairs rather than single coordinates. In polling-coordinate mode (CTC = ‘0’, COO = ‘1’), the WM9713L performs an X coordinate, then a Y co-ordinate, followed by a single additional measurement determined by ADCSEL[7:1], then stops. In continuous-coordinate mode (CTC = ‘1’, COO = ‘1’), the WM9713L continuously repeats a sequence consisting of an X-co-ordinate,Y co-ordinate, then an additional measurement determined by ADCSEL[7:1]. At least one of the ADCSEL bits must be set in continuous coordinate mode when CTC = COO = 1). Should more than one of the ADCSEL[7:1] bits be set during continuous co-ordinate mode then the additional measurement alternates for every set of three measurements. For example if ADCSEL_AUX1 and ADCSEL_AUX3 were both selected whilst CTC = ‘1’, COO = ‘1’ then the following sequence of conversions would be performed: “X,Y,AUX1,X,Y,AUX3,X,Y,AUX1,X,Y,AUX3…” w PP Rev 3.0 June 2006 64 Pre-Production WM9713L CONVERSION RATE As stated previously the conversion rate is specified by the CR bits (reg 76h). CR may be set to 93.75Hz (every 512 AC-Link Frames), 120Hz (every 400 AC-Link Frames), 153.75Hz (every 312 AC-Link frames) or 187.5Hz (every 256 AC-Link frames). If only one ADRSEL[7:1] bit is set then each individual conversion occurs at the rate specified by CR. If multiple ADRSEL[7:1] bits are set then the complete set of conversions requested is completed at the rate specified by CR. DATA READBACK This data is stored in register 7Ah, and can be retrieved by reading the register in the usual manner (see AC-Link Interface section). Additionally, the data can also be passed to the controller on one of the AC-Link time slots not used for audio functions. The output data word of the touchpanel interface consists of three parts: • Pen Status (1 bit) – this is also passed to the GPIO logic block, which can be programmed to generate an interrupt and/or wake up the WM9713L on pen down (see GPIO and Interrupt Control). Output data from the touchpanel ADC (12 bits) ADCSRC: 3 additional bits that indicate the source of the ADC data. In co-ordinate mode (COO = ‘1’), the WM9713L schedules different types of measurements autonomously and so these register bits may be required. • • If the data is being read back using the polling method, there are several ways to determine when a measurement has finished: • • Reading back the POLL bit. If it has been reset to ‘0’, then the measurement has finished. Monitoring the ADA signal, see GPIO and interrupt section. ADA goes high after every single conversion. If operating in co-ordinate mode (COO=1) then ADA goes high after every group of 3 conversions. Reading back 7Ah until the new data appears • w PP Rev 3.0 June 2006 65 WM9713L REGISTER ADDRESS 7Ah or AC-Link slot selected by SLT BIT 15 LABEL PNDN DEFAULT 0 DESCRIPTION Pen status (read-only) 0: Pen Up 1: Pen Down Pre-Production 14:12 ADCSRC 000 Touchpanel ADC Source 000: No measurement 001: X co-ordinate measurement 010: Y co-ordinate measurement 011: Pressure measurement (4-wire only) 100: COMP1/AUX1 measurement (pin 29) 101: COMP2/AUX2 measurement (pin 30) 110: AUX3 measurement (SPKVDD pin) 111: WIPER/AUX4 measurement (pin 12) Touchpanel ADC Data (read-only) Bit 11 = MSB Bit 0 = LSB 0: No effect (new ADC data overwrites unread data in register 7Ah) 1: New data is held back, and measurements delayed, until register 7Ah is read) 11:0 ADCD 000h 78h 9 WAIT 0 Table 50 Touchpanel Digitiser Data W hen operating in co-ordinate mode (COO=1) there will be 3 results to read back from each set of measurements – namely X,Y and the third additional measurement. After the co-ordinate set has finished the X result will be present in register 7Ah. Once this has been read back by the user the Y result will overwrite register 7Ah, as indicated by ADCSRC. Finally, after the Y result has been read back, the result of the third, additional, measurement will become present in 7Ah, again indicated by ADCSRC. To avoid losing data that has not yet been read, the WM9713L can delay overwriting register 7Ah with new conversions until the old data has been read. This function is enabled using the WAIT bit, and applies to both single and co-ordinate conversion mode. The flow diagram in Figure 24 shows the timing of touchpanel conversions, and data readback from register 7Ah - dependent on the individual settings of the CO, POLL,ADCSEL and CTC bits. w PP Rev 3.0 June 2006 66 Pre-Production WM9713L POLL (74h) CTC (74h) COO (74h) ADCSEL (74H) Starts a single measurement Starts a co-ordinate measurement at specified conversion rate Enables Co-Ordinate mode Specifies the type of measurement to be made Figure 24 Touchpanel Conversion Flow Diagram If the SLEN bit is set to ‘1’, then the touchpanel data appears on the AC-Link slot selected by the SLT control bits, as shown below. The Slot 0 ‘tag’ bit corresponding to the selected time slot is asserted whenever there is new data on that slot. REGISTER ADDRESS 76h BIT 3 LABEL SLEN DEFAULT 0 DESCRIPTION Slot Readback Enable 0: Disabled (readback through register only) 1: Enable (readback slot selected by SLT) AC’97 Slot Selection for Touchpanel Data 000: Slot 5 001: Slot 6 … 101: Slot 10 110: Slot 11 111: RESERVED 2:0 SLT 110 Table 51 Returning Touchpanel Data Through an AC-Link Time Slot w PP Rev 3.0 June 2006 67 WM9713L TOUCHPANEL SETTLING TIME Pre-Production For accurate touchpanel measurements, some settling time may be required between the switch matrix applying a voltage across the touchpanel plate and the ADC sampling the signal. This time delay function is built into the WM9713L and can be programmed as shown below. REGISTER ADDRESS 76h BIT 7:4 LABEL DEL DEFAULT 0000 (1 frame) DESCRIPTION Touchpanel ADC Settling Time Table 52 Touchpanel Settling Time Control (1) DEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DELAY (AC-LINK FRAMES) 1 2 4 8 16 32 48 64 96 128 160 192 224 256 288 DELAY (TIME) 20.8µs 41.7µs 83.3µs 167µs 333µs 667µs 1ms 1.33ms 2ms 2.67ms 3.33ms 4ms 4.67ms 5.33ms 6ms No delay, switch matrix always on Table 53 Touchpanel Settling Time Control (2) The total time for co-ordinate or auxiliary measurements to complete is the delay time DEL, plus one AC-Link frame (20.8µs). For a pressure measurement, the time taken is DEL plus two AC-Link frames (41.6µs). Although the DELAY is variable the maximum value that may be programmed depends on the number of ADCSEL[7:1] bits set, as shown in the following table. Setting multiple ADCSEL[7:1] bits leaves less spare AC_Link frames for the DELAY. w PP Rev 3.0 June 2006 68 Pre-Production WM9713L NUMBERS OF ADCSEL[1:7] BITS SET 1 1 1 1 2 2 2 2 3, 4 3, 4 3, 4 3, 4 5,6,7 5,6,7 5,6,7 5,6,7 1 (if COO=1) 1 (if COO=1) 1 (if COO=1) 1 (if COO=1) 2,3,4,5,6,7 (if COO=1) 2,3,4,5,6,7 (if COO=1) 2,3,4,5,6,7,8 (if COO=1) 2,3,4,5,6,7,8 (if COO=1) CR SETTING MAX DELAY SETTING 00 (93.75Hz) 01 (120Hz) 10 (153.75Hz) 11 (187.5Hz) 00 (93.75Hz) 01 (120Hz) 10 (153.75Hz) 11 (187.5Hz) 00 (93.75Hz) 01 (120Hz) 10 (153.75Hz) 11 (187.5Hz) 00 (93.75Hz) 01 (120Hz) 10 (153.75Hz) 11 (187.5Hz) 00 (93.75Hz) 01 (120Hz) 10 (153.75Hz) 11 (187.5Hz) 00 (93.75Hz) 01 (120Hz) 288 288 288 256 256 192 128 128 96 96 64 48 48 48 32 16 224 192 128 96 160 128 10 (153.75Hz) 11 (187.5Hz) 96 64 Table 54 Maximum Delay Values Setting DEL to ‘1111’ reduces the settling time to zero, i.e. measurements begin immediately. This mode is intended for fast sampling on AUX inputs. It is NOT intended for touchpanel digitisation. There are several side-effects when DEL is set to ‘1111’: • • Co-ordinate mode does not work, i.e. the WM9713L behaves as if COO = 0, even if COO = 1 (see “Measurement Types”) If X / Y co-ordinate or touch pressure measurements are selected (ADCSEL = 001, 010 or 011), then the switch matrix is constantly on, and current constantly flows in the touchpanel. This increases power consumption in the system, and is therefore not recommended for battery powered systems In continuous mode (CTC = 1), setting DEL = 1111 increases the sampling rate of the touchpanel ADC (see “Initiation of Measurements”) • w PP Rev 3.0 June 2006 69 WM9713L MASK INPUT CONTROL Pre-Production Sources of glitch noise, such as the signals driving an LCD display, may feed through to the touchscreen plates and affect measurement accuracy. In order to minimise this effect, a signal may be applied to MASK (pin 47 / pin 3) to delay or synchronise the sampling of any input to the ADC. The effect of the MASK signal depends on the the MSK bits of register 78h (bits [7:6]), as described below. REGISTER ADDRESS 78h BIT 7:6 LABEL MSK DEFAULT 00 DESCRIPTION MASK input control (see Table 56) Table 55 MASK Input Control MSK[1-0] 00 01 10 EFFECT OF SIGNAL ON MASK PIN Mask has no effect on conversions GPIO input disabled (default) Static; ‘hi’ on MASK pin stops conversions, ‘lo’ has no effect. Edge triggered; rising or falling edge on MASK pin delays conversions by an amount set in the DEL[3-0] register. Conversions are asynchronous to the MASK signal. Synchronous mode; conversions wait until rising or falling edge on MASK initiates cycle; screen starts to be driven when the edge arrives, the conversion sample being taken a period set by DEL[3-0] after the edge. 11 Table 56 Controlling the MASK Feature Note that pin 47 / pin 3 can also be used as a GPIO(see “GPIO and Interrupt Control” section), or to output the ADA signal (see below). THE ADA SIGNAL W henever data becomes available from the touchpanel ADC, the internal ADA (ADC Data Available) signal goes high and remains high until the data has been read from register 7Ah (if SLEN = 0) or until it has been sent out on an AC-Link slot (if SLEN = 1). ADA goes high either• • After every touchpannel ADC conversion (in normal mode, COO=0) After every set of 3 conversions (co-ordinate mode, COO=1) ADA can be used to generate an interrupt, if the AW bit (register 52h, bit 12) is set (see “GPIO and interrupt control” section) It is also possible to output the ADA signal on pin 47 / pin 3, if this pin is not used as a GPIO. The GE4/6 bit must be set to ‘0’ to achieve this (see “GPIO and interrupt control” section). Alternatively, ADA can be read from bit 12 in register 54h. w PP Rev 3.0 June 2006 70 Pre-Production WM9713L ADDITIONAL FEATURES AUXILIARY ADC INPUTS The ADC used for touchpanel digitisation can also be used for the sole purpose of auxiliary measurements, provided that it is enabled (register 78h, PRP = 11). The WM9713L has three pins that can be used as auxiliary ADC inputs: • • • MIC2A / COMP1 / AUX1 (pin 29) MIC2B / COMP2 / AUX2 (pin 30) W IPER / AUX4 (pin 12) Additionally, the speaker supply (SPKVDD) can be used as an auxillary ADC input through an onchip potential divider giving an input to the auxillary ADC of SPKVDD/3. This input is referred to as the AUX3 input (see Figure 16). Note that pin 12 connects to the wiper of a 5-wire touchpanel wiper function. Auxiliary measurements taken on pin 12 are only meaningful when it is not connected to a touchpanel (i.e. a 4-wire touchpanel, or no touchpanel at all, is used). Pins 29 and 30 are also used as comparator inputs (see Battery Alarm and Battery Measurement), but auxiliary measurements can still be taken on these pins at any time. The ADCSEL control bits select between different ADC inputs, as shown in Table 57. The ADCSEL control bits determine which type of measurement is performed (see below). When performing auxiliary conversions the co-ordinate mode bit, COO, should be off (0). If CTC=0 then only one of the ADCSEL[7:1] bits should be set. If operating in continuous mode (CTC=1), then more than one ADCSEL[7:1] bit may be set, and conversions will be performed cyclically in the following order => “AUX1,AUX2,AUX3,AUX4…” – dependent on which bits are set. BIT REGISTER ADDRESS 74h 7 6 5 4 0 ADCSEL_AUX4 ADCSEL_AUX3 ADCSEL_AUX2 ADCSEL_AUX1 COO 0 0 0 0 0 Enable AUX4 measurement (pin12) Enable AUX3 measurement (SPKVDD) Enable AUX2 measurement (pin30) Enable AUX1 measurement (pin29) Enable co-ordinate mode – for touchpanel conversions only (see “Controlling the Touchpanel Interface”) LABEL DEFAULT DESCRIPTION Table 57 Auxiliary ADC Measurements Auxiliary ADC measurements are initiated in the same way as touchpanel measurements, and the data is returned in the same manner. Please refer to the “Controlling the Touchpanel Interface” section. w PP Rev 3.0 June 2006 71 WM9713L BATTERY ALARM AND ANALOGUE COMPARATORS Pre-Production The battery alarm function differs from battery measurement in that it does not actually measure the battery voltage. Battery alarm only indicates “OK”, “Low” or “Dead”. The advantage of the battery alarm function is that it does not require a clock and can therefore be used in low-power sleep or standby modes. Figure 25 Battery Alarm Example Schematic The typical schematic for a dual threshold battery alarm is shown above. This alarm has two thresholds, “dead battery” (COMP1) and “low battery” (COMP2). R1, R2 and R3 set the threshold voltages. Their values can be up to about 1MΩ in order to keep the battery current [IALARM = VBATT / (R1+R2+R3)] to a minimum (higher resistor values may affect the accuracy of the system as leakage currents into the input pins become significant). Dead battery alarm: COMP1 triggers when VBATT < VREF × (R1+R2+R3) / (R2+R3) A dead battery alarm is the highest priority of interrupt in the system. It should immediately save all unsaved data and shut down the system. The GP15, GS15 and GW15 bits must be set to generate this interrupt. Low battery alarm: COMP2 triggers when VBATT < VREF × (R1+R2+R3) / R3 A low battery alarm has a lower priority than a dead battery alarm. Since the threshold voltage is higher than for a dead battery alarm, there is enough power left in the battery to give the user a warning and/or shut down “gracefully”. When VBATT gets close to the low battery threshold, spurious alarms are filtered out by the COMP2 delay function. The purpose of the capacitor C is to remove from the comparator inputs any high frequency noise or glitches that may be present on the battery (for example, noise generated by a charge pump). It forms a low pass filter with R1, R2 and R3. Low pass cutoff fc [Hz] = 1/ (2π C × (R1 || (R2+R3))) Provided that the cutoff frequency is several orders of magnitude lower than the noise frequency fn, this simple circuit can achieve excellent noise rejection. Noise rejection [dB] = 20 log (fn / fc) The circuit shown above also allows for measuring the battery voltage VBATT. This is achieved simply by setting the touchpanel ADC input to be either COMP1 (ADCSEL = 100) or COMP2 (ADCSEL = 101) (see also Auxiliary ADC Inputs). w PP Rev 3.0 June 2006 72 Pre-Production WM9713L The WM9713L has two on-chip comparators that can be used to implement a battery alarm function, or other functions such as a window comparator. Each comparator has one of its inputs tied to COMP1 (pin 29) or COMP2 (pin 30), and the other tied to a voltage reference. The voltage reference can be either internally generated (VREF = AVDD/2) or externally connected on AUX4 (pin 12). The comparator output signals are passed to the GPIO logic block (see “GPIO and Interrupt Control” section), where they can be used to send an interrupt to the CPU via the AC-Link or via the IRQ pin, and / or to wake up the WM9713L from sleep mode. COMP1/AUX1 (pin 29) corresponds to GPIO bit 15 and COMP2/AUX2 (pin30) to bit 14. REGISTER ADDRESS 4Eh BIT 15 LABEL CP1 DEFAULT 1 DESCRIPTION COMP1 Polarity (see also “GPIO and Interrupt Control”) 0: Alarm when COMP1 voltage is below VREF 1: Alarm when COMP1 voltage is above VREF COMP2 Polarity (see also “GPIO and Interrupt Control”) 0: Alarm when COMP2 voltage is below VREF 1: Alarm when COMP2 voltage is above VREF Low Battery Alarm Delay 000: No delay 001: 0.17s (213 = 8192 AC-Link frames) 010: 0.34s (214 = 16384 AC-Link frames) 011: 0.68s (215 = 32768 AC-Link frames) 100: 1.4s (216 = 65536 AC-Link frames) 17 101: 2.7s (2 = 131072 AC-Link frames) 110: 5.5s (218 = 262144 AC-Link frames) 111: 10.9s (219 = 524288 AC-Link frames) 14 CP2 1 5Ah 15:13 COMP2 DEL 000 Table 58 Comparator Control REGISTER ADDRESS 5Ch Additional Analogue Functions BIT 14 LABEL C1REF DEFAULT 0 DESCRIPTION Comparator 1 Reference Voltage 0 1 13:12 C1SRC 00 00 01 10 11 11 C2REF 0 0 1 10:9 C2SRC 00 00 01 10 11 Table 59 Comparator Reference and Source Control VREF = AVDD/2 WIPER/AUX4 (pin 12) AVDD/2 when C1REF=’1’. Otherwise comparator 1 is powered down COMP1/AUX1 (pin 29) COMP2/AUX2 (pin 30) Reserved VREF = AVDD/2 WIPER/AUX4 (pin 12) AVDD/2 when C2REF=’1’. Otherwise comparator 2 is powered down COMP1/AUX1 (pin 29) COMP2/AUX2 (pin 30) Reserved Comparator 1 Signal Source Comparator 2 Reference Voltage Comparator 2 Signal Source w PP Rev 3.0 June 2006 73 WM9713L COMP2 DELAY FUNCTION Pre-Production COMP2 has an optional delay function for use when the input signal is noisy. When COMP2 triggers and the delay is enabled (i.e. COMP2DEL is non-zero), then GPIO bit 14 does not change state immediately, and no interrupt is generated. Instead, the WM9713L starts a delay timer and checks COMP2 again after the delay time has passed. If COMP2 is still active, then the GPIO bit is set and an interrupt may be generated (depending on the state of the GW14 bit). If COMP2 is no longer active, the GPIO bit is not set, i.e. all register bits are as if COMP2 had never triggered. COMP2 TRIGGERS C2W? 0 END 1 COMP2 DEL? non-zero START TIMER WAIT time=COMP2DEL 000 SHUT DOWN TIMER COMP2? Inactive END [FALSE ALARM] Active SET GI14 END Figure 26 COMP2 Delay Flow Chart w PP Rev 3.0 June 2006 74 Pre-Production WM9713L GPIO AND INTERRUPT CONTROL The WM9713L has eight GPIO pins that operate as defined in the AC’97 Revision 2.2 specification. Each GPIO pin can be set up as an input or as an output, and has corresponding bits in register 54h and in slot 12. The state of a GPIO output is determined by sending data through slot 12 of outgoing frames (SDATAOUT). Data can be returned from a GPIO input by reading the register bit, or examining slot 12 of incoming frames (SDATAIN). GPIO inputs can be made sticky, and can be programmed to generate an interrupt, transmitted either through the AC-Link or through a dedicated, level-mode interrupt pin (GPIO2/IRQ, pin 45). In addition, the GPIO pins 1, 3, 4 and 5 can be used for the PCM interface by setting bit 15 of register 36h (see “PCM Codec” section). Setting this bit disables any GPIO functions selected on these pins. REGISTER ADDRESS 36h PCM Codec Control BIT 15 LABEL CTRL DEFAULT 0 DESCRIPTION Enables PCM interface on GPIO pins 1, 3, 4 and 5. 0: Normal GPIO functions 1: PCM interface enabled Note: For PCM interface, one or more of these pins (depending on master/slave/partial master mode) must be set up as an output by writing to register 4Ch (see Table 62) Toggle GPIO pin function: 0: secondary function enabled 1: GPIO enabled 56h GPIO Pin Sharing 8:2 GE# 1 (GPIO) Table 60 GPIO Additional Function Control GPIO pins 2 to 8 are multi-purpose pins that can also be used for other (non-GPIO / -PCM) purposes, e.g. as a SPDIF output or to signal pendown. This is controlled by register 56h (see Table 63) Note that GPIO6/7/8 each have an additional function independent of the GPIO / auxillary functions discussed above. If these pins are to be used as GPIO then the independent function needs to be disabled using its own control registers, e.g. to use pin 11 as a GPIO then the RESETB function needs to be disabled (RSTDIS, register 5Ah, bit 8). Independently of the GPIO pins, the WM9713L also has seven virtual GPIOs. These are signals from inside the WM9713L, which are treated as if they were GPIO input signals. From a software perspective, virtual GPIOs are the same as GPIO pins, but they cannot be set up as outputs, and are not tied to an actual pin. This allows for simple, uniform processing of different types of signals that may generate interrupts (e.g. pen down, battery warnings, jack insertion, high-temperature warning, or GPIO signals). w PP Rev 3.0 June 2006 75 WM9713L Pre-Production Figure 27 GPIO Logic GPIO BIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLOT 12 BIT 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 TYPE GPIO Pin GPIO Pin GPIO Pin GPIO Pin GPIO Pin GPIO Pin GPIO Pin GPIO Pin Virtual GPIO Virtual GPIO Virtual GPIO Virtual GPIO Virtual GPIO Virtual GPIO Virtual GPIO PIN NO. 44 45 46 47 48 3 11 12 [MICDET] [MICSHT] [Thermal Cutout] [ADA] [PEN DOWN] [COMP2] [COMP1] GPIO1 GPIO2 / IRQ enabled only when pin not used as IRQ GPIO3 / PENDOWN enabled only when pin not used as PENDOWN GPIO4 / ADA / MASK enabled only when pin not used as ADA GPIO5 / SPDIF_OUT enabled only when pin not used as SPDIF_OUT GPIO6 / ADA / MASK Enabled only when pin not used as ADA GPIO7 / PENDOWN enabled only when pin not used as PENDOWN GPIO8 / SPDIF_OUT enabled only when pin not used as SPDIF_OUT Internal microphone bias current detect, generates an interrupt above a threshold (see MICBIAS Current Detect) Internal shorted microphone detect, generates an interrupt above a threshold (see MICBIAS Current Detect) Internal thermal cutout signal, indicates when internal temperature reaches approximately 150°C (see “Thermal Sensor”) Internal ADA (ADC Data Available) Signal enabled only when touchpanel ADC is active Internal PENDOWN Signal enabled only when pen-down detection is active Internal COMP2 output (Low Battery Alarm) enabled only when COMP2 is on Internal COMP1 output (Dead Battery Alarm) enabled only when COMP1 is on DESCRIPTION Table 61 GPIO Bits and Pins w PP Rev 3.0 June 2006 76 Pre-Production WM9713L Note: GPIO7 (Pin 11) has an independent RESETB function. This must be disabled using RSTDIS (Register 5Ah, bit 8) before using Pin 11 as a GPIO / PENDOWN. The properties of the GPIOs are controlled through registers 4Ch to 52h, as shown below. REGISTER ADDRESS 4Ch BIT n LABEL GCn DEFAULT 1 DESCRIPTION GPIO Pin Configuration 0: Output 1: Input GC9-15 are always ‘1’ GPIO Pin Polarity / Type Input (GCn=1) 0: Active Low 1: Active High [GIn = pin level XNOR GPn] 50h n GSn 0 GPIO Pin Sticky 1: Sticky 0: Not Sticky GPIO Pin Wake-up 1: Wake Up (generate interrupts from this pin) 0: No wake-up (no interrupts generated) GPIO Pin Status Read: Returns status of each GPIO pin Write: Writing ‘0’ clears sticky bit Output (GCn=0) 0: Active High 1: Active low 4Eh n GPn 1 52h n GWn 0 54h n GIn N/A Table 62 GPIO Control The following procedure is recommended for handling interrupts: When the controller receives an interrupt, check register 54h. For each GPIO bit in descending order of priority, check if the bit is ‘1’. If yes, execute corresponding interrupt routine, then write ‘0’ to corresponding bit in 54h. If no, continue to next lower priority GPIO. After all GPIOs have been checked, check if interrupt still present or no. If yes, repeat procedure. If no, then jump back to process that ran before the interrupt. If the system CPU cannot execute such an interrupt routine, it may be preferable to switch internal signals (such as PENDOWN) directly onto the GPIO pins. However, in this case the interrupt signals cannot be made sticky, and more GPIO pins are tied up both on the WM9713L and on the CPU. w PP Rev 3.0 June 2006 77 WM9713L REGISTER ADDRESS 56h GPIO pins function select BIT 2 LABEL GE2 DEFAULT 1 DESCRIPTION Pre-Production GPIO2 / IRQ output select 0: Pin 45 disconnected from GPIO logic set 4Ch, bit 2 to ‘0’ to output IRQ signal 1: Pin 45 connected to GPIO logic (IRQ disabled) GPIO3 / PENDOWN output select 0: Pin 46 disconnected from GPIO logic set 4Ch, bit 3 to ‘0’ to output PENDOWN signal 1: Pin 46 connected to GPIO logic GPIO4 / ADA / MASK output select 0: Pin 47 disconnected from GPIO logic set 4Ch, bit 4 to ‘0’ to output ADA signal set 4Ch, bit 4 to ‘1’ to input MASK signal 1: Pin 47 connected to GPIO logic GPIO5 / SPDIF output select 0: Pin 48 = SPDIF (disconnected from GPIO logic) set 4Ch, bit 5 to ‘0’ to output SPDIF signal 1: Pin 48 connected to GPIO logic (SPDIF disabled) GPIO6 / ADA / MASK output select 0: Pin 3 disconnected from GPIO logic set 4Ch, bit 6 to ‘0’ to output ADA signal set 4Ch, bit 6 to ‘1’ to input MASK signal 1: Pin 3 connected to GPIO logic GPIO7 / PENDOWN output select 0: Pin 11 disconnected from GPIO logic set 4Ch, bit 7 to ‘0’ to output PENDOWN signal 1: Pin 11 connected to GPIO logic GPIO8 / SPDIF output select 0: Pin 12 = SPDIF (disconnected from GPIO logic) set 4Ch, bit 8 to ‘0’ to output SPDIF signal 1: Pin 12 connected to GPIO logic (SPDIF disabled) 3 GE3 1 4 GE4 1 5 GE5 1 6 GE6 1 7 GE7 1 8 GE8 1 Table 63 Using GPIO Pins for Non-GPIO Functions w PP Rev 3.0 June 2006 78 Pre-Production WM9713L POWER MANAGEMENT INTRODUCTION The WM9713L includes the standard power down control register defined by the AC’97 specification (register 26h). Additionally, it also allows more specific control over the individual blocks of the device through register Powerdown registers 3Ch and 3Eh. Each particular circuit block is active when both the relevant bit in register 26h AND the relevant bit in the Powerdown registers 3Ch and 3Eh are set to ‘0’. Note that the default power-up condition is all OFF. AC97 CONTROL REGISTER REGISTER ADDRESS 26h Powerdown/ Status register BIT 14 13 12 11 10 9 8 3 2 1 0 LABEL PR6 PR5 PR4 PR3 PR2 PR1 PR0 REF ANL DAC ADC DEFAULT 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 0 0 0 0 DESCRIPTION Disables all output PGAS Disables internal clock Disables AC-link interface (external clock off) Disables VREF, input PGAs, DACs, ADCs, mixers and outputs Disables input PGAs and mixers Disables stereo DAC Disables stereo ADCs and record mux PGA Read-only bit, indicates VREF is ready (inverse of PR3) Read-only bit, indicates analogue mixers are ready (inverse of PR2) Read-only bit, indicates stereo DAC is ready (inverse of PR1) Read-only bit, indicates stereo ADC is ready (inverse of PR0) Table 64 Powerdown and Status Register (Conforms to AC’97 Rev 2.2) EXTENDED POWERDOWN REGISTERS REGISTER ADDRESS 3Ch Powerdown (1) BIT 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 LABEL PADCPD VMID1M TSHUT VXDAC AUXDAC VREF PLL DACL DACR ADCL ADCR HPLX HPRX SPKX MX DEFAULT 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) DESCRIPTION Disables touchpanel/aux ADC Disables 1Meg Vmid resistor string Disables thermal shutdown Disables VXDAC Disables AUXDAC Disables master bias reference generator Disables PLL Disables left DAC (see Note 1) Disables right DAC (see Note 1) Disables left ADC Disables right ADC Disables left headphone mixer Disables right headphone mixer Disables speaker mixer Disables mono mixer Note: W hen analogue inputs or outputs are disabled, they are internally connected to VREF through a large resistor (VREF=AVDD/2 except when VREF and VMID1M are both OFF). This maintains the potential at that node and helps to eliminate pops when the pins are re-enabled. Table 65 Extended Power Down Register (1) (Additional to AC’97 Rev 2.2) Note: 1. When disabling a PGA, always ensure that it is muted first. PP Rev 3.0 June 2006 79 w WM9713L REGISTER ADDRESS 3Eh Powerdown (2) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LABEL MCD MICBIA S MONO OUT4 OUT3 HPL HPR SPKL SPKR LL LR MOIN MA MB MPA MPB DEFAULT 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) DESCRIPTION Pre-Production Disables microphone current detect Disables microphone bias Disables MONO output PGA (see Note 1) Disables OUT4 output PGA Disables OUT3 output PGA Disables HPL output PGA Disables HPR output PGA Disables SPKL output PGA Disables SPKR output PGA Disables LINEL PGA Disables LINER PGA Disables MONOIN PGA Disables mic PGA MA Disables mic PGA MB Disables mic pre-amp MPA Disables mic pre-amp MPB (“ (“ (“ (“ (“ (“ (“ (“ (“ (“ (“ “) “) “) “) “) “) “) “) “) “) “) Note: W hen analogue inputs or outputs are disabled, they are internally connected to VREF through a large resistor (VREF=AVDD/2 except when VREF and VMID1M are both OFF). This maintains the potential at that node and helps to eliminate pops when the pins are re-enabled. Table 66 Extended Power Down Register (2) (Additional to AC’97 Rev 2.2) Note: 1. When disabling a PGA, always ensure that it is muted first. ADDITIONAL POWER MANAGEMENT Mixer output inverters: see “Mixer output Inverters” section. Inverters are OFF by default. Touchpanel Interface: see “Controlling the Touchpanel Digitiser / Power Management”. The touchpanel digitiser is OFF by default. SLEEP MODE W henever the PR4 bit (reg. 26h) is set, the AC-Link interface is disabled, and the WM9713L is in sleep mode. There is in fact a very large number of different sleep modes, depending on the other control bits. For example, the low-power standby mode described below is a sleep mode. It is desirable to use sleep modes whenever possible, as this will save power. The following functions do not require a clock and can therefore operate in sleep mode: • • • • Analogue-to-analogue audio (DACs and ADCs unused), e.g. phone call mode Pen-down detection GPIO and interrupts Battery alarm / analogue comparators The WM9713L can awake from sleep mode as a result of • • • A warm reset on the AC-Link (according to the AC’97 specification) A signal on a GPIO pin (if the pin is configured as an input, with wake-up enabled – see “GPIO and Interrupt Control” section) A virtual GPIO event such as pen-down, battery alarm, etc. (see “GPIO and Interrupt Control” section) w PP Rev 3.0 June 2006 80 Pre-Production WM9713L LOW POWER STANDBY MODE If all the bits in registers 26h, 3Ch and 3Eh are set except VMID1M (register 3Ch, bit 14), then the WM9713L is in low-power standby mode and consumes very little current. A 1MΩ resistor string remains connected across AVDD to generate VREF. This is necessary if the on-chip analogue comparators are used (see “Battery Alarm and Battery Measurement” section), and helps shorten the delay between wake-up and playback readiness. If VREF is not required, the 1MΩ resistor string can be disabled by setting the VMID1M bit, reducing current consumption further. SAVING POWER AT LOW SUPPLY VOLTAGES The analogue supplies to the WM9713L can run from 1.8V to 3.6V. By default, all analogue circuitry on the IC is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to 1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias currents used in the analogue circuitry. This is controlled as shown below. REGISTER ADDRESS 5Ch BIT 6:5 LABEL VBIAS DEFAULT 00 DESCRIPTION Analogue Bias optimization 11 : Lowest bias current, optimized for 1.8V 10 : Low bias current, optimized for 2.5V 01, 00 : Default bias current, optimized for 3.3V Table 67 Analogue Bias Selection POWER ON RESET (POR) The WM9713L has an internal power on reset (PORB) which ensures that a reset is applied to all registers until a supply threshold has been exceeded. The POR circuitry monitors the voltage for both AVDD and DCVDD and will release the internal reset signal once these supplies are both nominally greater than 1.36V. The internal reset signal is an AND of the PORB and RESETB input signal. It is recommended that for operation of the WM9713L, all device power rails should be stable before configuring the device for operation. AC97 INTERFACE TIMING Test Characteristics: DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25°C to +85°C, unless otherwise stated. CLOCK SPECIFICATIONS tCLK_HIGH BITCLK tCLK_LOW tCLK_PERIOD tSYNC_HIGH tSYNC_LOW SYNC tSYNC_PERIOD Figure 28 Clock Specifications (50pF External Load) w PP Rev 3.0 June 2006 81 WM9713L PARAMETER BITCLK frequency BITCLK period BITCLK output jitter BITCLK high pulse width (Note 1) BITCLK low pulse width (Note 1) SYNC frequency SYNC period SYNC high pulse width SYNC low pulse width Note: 1. Worst case duty cycle restricted to 45/55 tSYNC_PERIOD tSYNC_HIGH tSYNC_LOW tCLK_HIGH tCLK_LOW 36 36 40.7 40.7 48 20.8 1.3 19.5 tCLK_PERIOD SYMBOL MIN TYP 12.288 81.4 Pre-Production MAX UNIT MHz ns 750 45 45 ps ns ns kHz µs µs µs DATA SETUP AND HOLD Figure 29 Data Setup and Hold (50pF External Load) Note: Setup and hold times for SDATAIN are with respect to the AC’97 controller, not the WM9713L. PARAMETER Setup to falling edge of BITCLK Hold from falling edge of BITCLK Output valid delay from rising edge of BITCLK SYMBOL tSETUP tHOLD tCO MIN 10 10 15 TYP MAX UNIT ns Ns ns w PP Rev 3.0 June 2006 82 Pre-Production WM9713L SIGNAL RISE AND FALL TIMES triseCLK BITCLK triseSYNC SYNC triseDIN SDATAIN triseDOUT SDATAOUT tfallDOUT tfallDIN tfallSYNC tfallCLK Figure 30 Signal Rise and Fall Times (50pF External Load) PARAMETER BITCLK rise time BITCLK fall time SYNC rise time SYNC fall time SDATAIN rise time SDATAIN fall time SDATAOUT rise time SDATAOUT fall time SYMBOL triseCLK tfallCLK triseSYNC tfallSYNC triseDIN tfallDIN triseDOUT tfallDOUT MIN 2 2 2 2 2 2 2 2 TYP MAX 6 6 6 6 6 6 6 6 UNIT ns ns ns ns ns ns ns ns AC-LINK POWERDOWN SLOT 1 SYNC SLOT 2 BITCLK SDATAOUT WRITE TO 0X20 DATA PR4 DON'T CARE tS2_PDOWN SDATAIN Figure 31 AC-Link Powerdown Timing AC-Link powerdown occurs when PR4 (register 26h, bit 12) is set (see “Power Management” section). PARAMETER End of Slot 2 to BITCLK and SDATAIN low SYMBOL tS2_PDOWN MIN TYP MAX 1.0 UNIT µs w PP Rev 3.0 June 2006 83 WM9713L COLD RESET (ASYNCHRONOUS, RESETS REGISTER SETTINGS) Pre-Production tRST_LOW RESETB tRST2CLK BITCLK Figure 32 Cold Reset Timing Note: For correct operation SDATAOUT and SYNC must be held LOW for entire RESETB active low period otherwise the device may enter test mode. See AC'97 specification or Wolfson applications note WAN104 for more details. PARAMETER RESETB active low pulse width RESETB inactive to BITCLK startup delay SYMBOL tRST_LOW tRST2CLK MIN 1.0 162.8 TYP MAX UNIT µs ns WARM RESET (ASYNCHRONOUS, PRESERVES REGISTER SETTINGS) Figure 33 Warm Reset Timing PARAMETER SYNC active high pulse width SYNC inactive to BITCLK startup delay SYMBOL tSYNC_HIGH tRST2CLK MIN 162.4 TYP 1.3 MAX UNIT µs ns w PP Rev 3.0 June 2006 84 Pre-Production WM9713L 15 0 M UL M UL M U4 M 2H L2H D2H 0 0 RM U R2H B2H V2H A2H M ONO INVA BB 0 0 BC M PA BST 0 PR3 REV1 0 0 PR2 REV0 SPCV B2HV OL V2HV OL A2HV OL SPKL INV B BA SS M PBBST 0 PR1 AM AP 0 0 PR0 LDAC 0 REGISTER MAP R eg 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1A h 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 32h 36h 3Ah 3Ch 3Eh 40h 42h 44h 46h 4Ch 4Eh 50h 52h 54h 56h 58h 5A h 5Ch 60h 62h 64h 74h 76h 78h 7A h 7Ch 7Eh Reset Speaker Volume Headphone V olume OUT3/ 4 Volume M ONO V ol & M ONOIN PGA Vol / Routing LINEIN PGA Volume / Rout ing DAC PGA Volume / Rout ing M IC PGA V olume M IC Rout ing Record PGA Volume Record Rout ing / M ux Select PCBEEP Volume / Rout ing VxDAC Volume / Rout ing AUXDAC V olume / Routing Output PGA M ux Select DAC 3D Control & INV M ux Select DAC Tone Cont rol M IC Input Select & Bias / Det ect Ctrl Output Volume M apping (Jack Insert ) Powerdown Ct rl/ Stat Ext ended Audio ID Ext 'd Audio St at / Ct rl Audio DACs Sample Rate AUXDAC Sample Rat e Audio ADCs Sample Rate PCM codec control SPDIF cont rol Powerdown (1) Powerdown (2) General Purpose Fast Power-Up Control M CLK / PLL Cont rol M CLK / PLL Cont rol GPIO Pin Configurat ion GPIO Pin Polarit y / Type GPIO Pin Sticky GPIO Pin Wake-Up GPIO Pin Stat us GPIO Pin Sharing GPIO Pull UP/ DOWN Ct rl Addit ional Funct ions (1) Addit ional Funct ions (2) ALC Cont rol ALC / Noise Gat e Cont rol AUXDAC input cont rol Digitiser Reg 1 Digitiser Reg 2 Digitiser Reg 3 Digitiser Read Back Vendor ID1 Vendor ID2 1 C1P C1S C1W C1I 1 PU8 1 C2P C2S C2W C2I 1 PU7 COM P2DEL AMUTE C1REF N ame 14 SE4 ZCL ZCL ZC4 M 2S L2S D2S 0 0 GRL 13 SE3 12 SE2 11 SE1 10 SE0 9 ID9 8 ID8 7 ID7 M UR M UR M U3 MU 0 0 0 6 ID6 ZCR ZCR ZC3 ZC 0 0 0 5 ID5 4 ID4 3 ID3 2 ID2 1 ID1 0 ID0 D e f a ult 6174h 8080h 8080h 8080h C880h E808h E808h 0808h 00DAh 8000h D600h SPKLVOL HPLVOL OUT4VOL 0 L2M D2M 0 0 0 0 M ONOINVOL LINELV OL DACLV OL M ICAV OL 0 0 0 SPKRVOL HPRV OL OUT3VOL M ONOV OL 0 0 0 LINERVOL DACRVOL M ICBV OL M IC2HVOL RECVOLR RECSR 0 0 0 OUT3 3DDEPTH TRBL M CDTHR JIEN 0 0 SPSA DCDRVSEL REF VRM 0 ANL SPDIF SEN M CDSCTHR EARSPKSEL DA C DRA 0 ADC VRA VRA 0 0 0 0 0 0 OUT4 0 0 0 M A2M ZC (Ext ended) R2HVOL B2S V2S A2S RECVOLL R2M B2SVOL V2SVOL A2SVOL SPKR 0 0 R2M BST M B 2M M IC2M M IC2H BST GRR (Ext ended) REC BST B2M VOL V2M VOL A2M VOL RECSL 0 B 2M V 2M A 2M HPL 0 0 A AA0h A AA0h A AA0h 0000h 0000h 0F0Fh 0040h 0000h 7F00h 0405h 0410h B B80h B B80h B B80h HPR 0 DAT 3DLC 0 3DUC TC M ICCM PSEL 0 0 ID1 0 0 PR6 ID0 0 M PA SEL 0 PR5 0 0 0 PR4 0 0 M B OP M BOP1 M B VO 2EN EN L 0 0 0 0 SDAC 0 0 CDA C 0 0 0 DA CSR (Audio DA Cs Sample Rat e) AUXDACSR (Auxiliary DAC Sample Rate) ADCSR (Audio ADCs Sample Rat e) CTRL V PA DCP D M CD 0 0 0 M ODE DRS VM ID 1M M IC B IAS 0 0 SPSR TSHUT M ONO 3DE 0 SEXT[6:4] N[3:0] 1 PP PS PW PI 1 PU6 1 AP AS AW AI 1 PU5 0 C1SRC LF 1 TP TS TW TI 1 PU4 0 C2 REF 0 L AUXD AC OUT3 0 0 DIV VDAC CP FSP OSR CC (Cat egory Code) PLL HPR 0 0 1 SPKL 0 0 DACL SPKR LB 0 DACR LL 0 M ONO 0 SEL PRE ADCL LR 0 SPKL ADCR M OIN 0 SPKR PENDIV PGADDR HPLX MA 0 HPL WL COPY HPRX MB 0 HPR CLKBX 2 FM T AUD IB SPKX M PA 0 OUT3 PRO MX M PB 0 OUT4 4523h 2000h FDFFh FFFFh 0000h 0000h 0080h 0000h FFFEh FFFFh 0000h 0000h GPIO pins FFFEh 4000h 0000h 0000h B032h 3E00h 0000h VX DA C OUT4 0 0 VREF HPL 0 0 SEXT[3:0] SDM 1 SP SS SW SI 1 PU3 0 C2SRC CLKSR C DIVSEL DIVCTL 0 1 MP MS MW MI 1 PU2 0 GC8 GP8 GS8 GW8 GI8 GE8 PU1 RSTDIS 0 GC7 GP7 GS7 GW7 GI7 GE7 PD8 JSEL AM EN CLKA X CLKM U 2 X PGDA TA GC1 GP1 GS1 GW1 GI1 1 PD2 0 1 0 0 0 0 PD1 GC6 GP6 GS6 GW6 GI6 GE6 PD7 GC5 GP5 GS5 GW5 GI5 GE5 PD6 GC4 GP4 GS4 GW4 GI4 GE4 PD5 GC3 GP3 GS3 GW3 GI3 GE3 PD4 GC2 GP2 GS2 GW2 GI2 GE2 PD3 HPM ODE V BIA S ADCO Die Revision HPF 0 WAKEE IRQ N INV ASS ALCL (t arget level) ALCSEL XSLE 0 0 PRP PNDN HLD (hold t ime) ZCTIM EOUT 0 NGA T DCY (decay time) 0 NGG ATK (at tack t ime) NGTH (threshold) M AX GAIN AUXDA CSLT AUXDA C VA L 0 0 45W 0 0 PDEN 0 0 PDPOL WAIT POLL CR PIL M SK A DCD (TOUCHPA NEL ADC Y DA TA) A SCII charact er “ M ” Device Identifier CTC DEL ADCSEL SLEN RPU SLT COO 0 0 0 0 RPR ADCSRC 0000h 0006h 0001h 0000h 574Dh 4C13h A SCII charact er “ W ” ASCII charact er “ L” Table 68 WM9713L Register Map Note: Register 46h provides access to a sub-page address system to set the SPLL[6:0] and K[21:0] register bits (see Table 6). PP Rev 3.0 June 2006 85 w WM9713L REGISTER BITS BY ADDRESS REGISTER ADDRESS 00h BIT 14:10 9:6 5 4 3 2 1 0 LABEL SE [4:0] ID9:6 ID5 ID4 ID3 ID2 ID1 ID0 DEFAULT 11000 0101 1 1 0 1 0 0 DESCRIPTION Indicates a codec from Wolfson Microelectronics Indicates 18 bits resolution for ADCs and DACs Indicates that the WM9713L supports bass boost Indicates that the WM9713L has a headphone output Indicates that the WM9713L does not support simulated stereo Indicates that the WM9713L supports bass and treble control Indicates that the WM9713L does not support modem functions Indicates that the WM9713L does not have a dedicated microphone ADC Pre-Production REFER TO Intel’s AC’97 Component Specification, Revision 2.2, page 50 Register 00h is a read-only register. Writing any value to this register resets all registers to their default, but does not change the contents of reg. 00h. Reading the register reveals information about the codec to the driver, as required by the AC’97 Specification, Revision 2.2 REGISTER ADDRESS 02h 15 14 BIT LABEL MUL ZCL SPKLVOL MUR ZCR SPKRVOL DEFAULT 1 (mute) 0 (OFF) 000000 (0dB) 1 (mute) 0 (OFF) 000000 (0dB) Mutes SPKL DESCRIPTION REFER TO Analogue Audio Outputs Enables zero-cross detector on SPKL SPKL volume Mutes SPKR Enables zero-cross detector on SPKR SPKR volume 13:8 7 6 5:0 Register 02h controls the output pins SPKL and SPKR. REGISTER ADDRESS 04h 15 14 BIT LABEL MUL ZCL HPL VOL MUR ZCR HPR VOL DEFAULT 1 (mute) 0 (OFF) 000000 (0dB) 1 (mute) 0 (OFF) 000000 (0dB) Mutes HPL DESCRIPTION REFER TO Analogue Audio Outputs Enables zero-cross detector on HPL HPL volume Mutes HPR Enables zero-cross detector on HPR HPR volume 13:8 7 6 5:0 Register 04h controls the headphone output pins, HPL and HPR. REGISTER ADDRESS 06h 15 14 BIT LABEL MU4 ZC4 OUT4VOL MU3 ZC3 OUT3VOL DEFAULT 1 (mute) 0 (OFF) 000000 (0dB) 1 (mute) 0 (OFF) 000000 (0dB) Mutes OUT4 DESCRIPTION REFER TO Analogue Audio Outputs Enables zero-cross detector OUT4 volume Mutes OUT3 Enables zero-cross detector OUT3 volume 13:8 7 6 5:0 Register 06h controls the analogue output pins OUT3 and OUT4. w PP Rev 3.0 June 2006 86 Pre-Production REGISTER ADDRESS 08h 15 14 12:8 7 6 5:0 BIT LABEL M2H M2S MONOINVOL MU ZC MONOVOL DEFAULT 1 (mute) 1 (mute) 01000 (0dB) 1 (mute) 0 (OFF) 000000 (0dB) DESCRIPTION Mutes MONOIN to headphone mixer paths Mutes MONOIN to speaker mixer path Controls MONOIN input gain to all mixers (but not to ADC) Mutes MONO. Enables zero-cross detector MONO volume WM9713L REFER TO Analogue Inputs; Analogue Audio Outputs Register 08h controls the analogue output pin MONO and the analogue input pin MONOIN. REGISTER ADDRESS 0Ah 15 14 13 BIT LABEL L2H L2S L2M LINELVOL LINERVOL DEFAULT 1 (mute) 1 (mute) 1 (mute) 01000 (0dB) 01000 (0dB) DESCRIPTION Mutes LINE to headphone mixer paths Mutes LINE to speaker mixer path Mutes LINE to mono mixer path Controls LINEL input gain to all mixers (but not to ADC) Controls LINER input gain to all mixers (but not to ADC) REFER TO Analogue Inputs, Line Input 12:8 4:0 Register 0Ah controls the analogue input pins LINEL and LINER. REGISTER ADDRESS 0Ch 15 14 13 BIT LABEL D2H D2S D2M DACLVOL DACRVOL DEFAULT 1 (mute) 1 (mute) 1 (mute) 01000 (0dB) 01000 (0dB) DESCRIPTION Mutes DAC to headphone mixer path Mutes DAC to speaker mixer path Mutes DAC to mono mixer path Controls left DAC input gain to all mixers Controls right DAC input gain to all mixers REFER TO Audio DACs 12:8 4:0 Register 0Ch controls the audio DACs (but not AUXDAC). REGISTER ADDRESS 0Eh BIT 12:8 4:0 LABEL MICAVOL MICBVOL DEFAULT 01000 (0dB) 01000 (0dB) DESCRIPTION Controls MICA PGA volume Controls MICB PGA volume REFER TO Analogue Inputs, Microphone Input Register 0Eh controls the microphone PGA volume (MICA and MICB). REGISTER ADDRESS 10h 7 6 5 BIT LABEL MA2M MB2M MIC2MBST MIC2H DEFAULT 1 (mute) 1 (mute) 0 (OFF) 11 (mute) DESCRIPTION Mutes MICA to mono mixer path Mutes MICB to mono mixer path Enables 20dB gain boost at mono mixer for MICA and MICB Controls microphone to headphone mixer paths. 00=stereo, 01=MICA only, 10=MICB only, 11=mute MICA and MICB Controls gain of microphone to headphone mixer path REFER TO Analogue Inputs, Microphone Input 4:3 2:0 MIC2HVOL 010 (0dB) Register 10h controls the microphone routing (MICA and MICB). w PP Rev 3.0 June 2006 87 WM9713L REGISTER ADDRESS 12h 15 14 BIT LABEL RMU GRL DEFAULT 1 (mute) 0 (standard) DESCRIPTION Mutes audio ADC input Selects gain range for PGA of left ADC. 0=0...+22.5dB in 1.5dB steps, 1=-17.25...+30dB in 0.75dB steps Controls left ADC recording volume Enables zero-cross detector Selects gain range for PGA of right ADC. 0=0...+22.5dB in 1.5dB steps, 1=-17.25...+30dB in 0.75dB steps Controls right ADC recording volume Pre-Production REFER TO Audio ADC, Record Gain 13:8 7 6 RECVOLL ZC GRR 000000 (0dB) 0 (OFF) 0 (standard) 5:0 RECVOLR 000000 (0dB) Register 12h controls the record volume. REGISTER ADDRESS 14h BIT 15:14 LABEL R2H DEFAULT 11 (mute) DESCRIPTION Controls record mux to headphone mixer paths. 00=stereo, 01=left ADC only, 10=right ADC only, 11=mute left and right Controls gain of record mux l/r to headphone mixer paths Controls record mux to mono mixer path. 00=stereo, 01=left rec mux only, 10=right rec mux only, 11=mute left and right Enables 20dB gain boost for record mux to mono mixer path Enables 20dB gain boost for ADC record path Selects left record mux signal source: 000=MICA, 001=MICB, 010=LINEL, 011=MONOIN, 100=HPMIXL, 101=SPKMIC, 110=MONOMIX, 111=Reserved (Do not use) Selects right record mux signal source: 000=MICA, 001=MICB, 010=LINER, 011=MONOIN, 100=HPMIXR, 101=SPKMIC, 110=MONOMIX, 111=Reserved (Do not use) REFER TO Audio ADC, Record Selector 13:11 10:9 R2HVOL R2M 010 (0dB) 11 (mute) 8 6 5:3 R2MBST RECBST RECSL 0 (OFF) 0 (OFF) 000 (mic) 2:0 RECSR 000 (mic) Register 14h controls the.record selector and the ADC to mono mixer path. REGISTER ADDRESS 16h 15 BIT LABEL B2H B2HVOL B2S B2SVOL B2M B2MVOL DEFAULT 1 (mute) 010 (0dB) 1 (mute) 010 (0dB) 1 (mute) 010 (0dB) DESCRIPTION Mutes PCBEEP to headphone mixer paths Controls gain of PCBEEP to headphone mixer paths Mutes PCBEEP to speaker mixer path Controls gain of PCBEEP to speaker mixer path Mutes PCBEEP to mono mixer path Controls gain of PCBEEP to mono mixer path REFER TO Analogue Inputs, PCBEEP Input 14:12 11 10:8 7 6:4 Register 16h controls the analogue input pin PCBEEP. w PP Rev 3.0 June 2006 88 Pre-Production REGISTER ADDRESS 18h 15 14:12 11 10:8 7 6:4 BIT LABEL V2H V2HVOL V2S V2SVOL V2M V2MVOL DEFAULT 1 (mute) 010 (0dB) 1 (mute) 010 (0dB) 1 (mute) 010 (0dB) DESCRIPTION Mutes VXDAC to headphone mixer paths Controls gain of VXDAC to headphone mixer paths Mutes VXDAC to speaker mixer path Controls gain of VXDAC to speaker mixer path Mutes VXDAC to mono mixer path Controls gain of VXDAC to mono mixer path WM9713L REFER TO Audio Mixers, Side Tone Control Register 18h controls the output signal of the Voice DAC. REGISTER ADDRESS 1Ah 15 BIT LABEL A2H A2HVOL A2S A2SVOL A2M A2MVOL DEFAULT 1 (mute) 010 (0dB) 1 (mute) 010 (0dB) 1 (mute) 010 (0dB) DESCRIPTION Mutes AUXDAC to headphone mixer paths Controls gain of AUXDAC to headphone mixer paths Mutes AUXDAC to speaker mixer path Controls gain of AUXDAC to speaker mixer path Mutes AUXDAC to mono mixer path Controls gain of AUXDAC to mono mixer path REFER TO Auxiliary DAC 14:12 11 10:8 7 6:4 Register 1Ah controls the output signal of the auxiliary DAC. REGISTER ADDRESS 1Ch BIT 15:14 13:11 LABEL MONO SPKL DEFAULT 00 (VMID) 000 (VMID) DESCRIPTION MONO PGA input select: 00=Vmid; 01=no i/p (ZH if buffer disabled); 10=MONOMIX; 11=INV1 SPKL PGA input select: 000=Vmid; 001=no i/p (ZH if buffer disabled); 010=HPMIXL; 011=SPKMIX; 100=INV1; 101-111=unused SPKR PGA input select: 000=Vmid; 001=no i/p (ZH if buffer disabled); 010=HPMIXR; 011=SPKMIX; 100=INV2; 101-111=unused HPL PGA input select: 00=Vmid; 01=no i/p (ZH if buffer disabled); 10=HPMIXL; 11=unused HPR PGA input select: 00=Vmid; 01=no i/p (ZH if buffer disabled); 10=HPMIXR; 11=unused OUT3 PGA input select: 00=Vmid; 01=no i/p (ZH if buffer disabled); 10=INV1; 11=unused OUT4 PGA input select: 00=Vmid; 01=no i/p (ZH if buffer disabled); 10=INV2; 11=unused REFER TO Analogue Audio Outputs 10:8 SPKR 000 (VMID) 7:6 5:4 3:2 1:0 HPL HPR OUT3 OUT4 00 (VMID) 00 (VMID) 00 (VMID) 00 (VMID) Register 1Ch controls the inputs to the output PGAs. REGISTER ADDRESS 1Eh BIT 15:13 LABEL INV1 DEFAULT 000 (ZH) DESCRIPTION INV1 input select: 000=ZH (OFF – no source selected); 001=MONOMIX; 010=SPKMIX; 011=HPMIXL; 100=HPMIXR; 101=HPMIXMONO; 110=unused; 111=Vmid INV2 input select: 000=ZH (OFF – no source selected); 001=MONOMIX; 010=SPKMIX; 011=HPMIXL; 100=HPMIXR; 101=HPMIXMONO; 110=unused; 111=Vmid Selects lower cut-off frequency Selects upper cut-off frequency Controls depth of 3D effect REFER TO Audio DACs, 3D Stereo Enhancement; Analogue Audio Outputs 12:10 INV2 000 (ZH) 5 4 3:0 3DLC 3DUC 3DDEPTH 0 (low) 0 (high) 0000 (0%) Register 1Eh controls 3D stereo enhancement for the audio DACs and input muxes to the output inverters INV1 and INV2. w PP Rev 3.0 June 2006 89 WM9713L REGISTER ADDRESS 20h 15 12 11:8 6 4 3:0 BIT LABEL BB BC BASS DAT TC TRBL DEFAULT 0 (linear) 0 (low) 1111 (OFF) 0 (OFF) 0 (high) 1111 (OFF) DESCRIPTION Selects linear bass control or adaptive bass boost Selects bass cut-off frequency Controls bass intensity Enables 6dB pre-DAC attenuation Selects treble cut-off frequency Controls treble intensity Pre-Production REFER TO Audio DACs, Tone Control / Bass Boost Register 20h controls the bass and treble response of the left and right audio DAC (but not AUXDAC). REGISTER ADDRESS 22h BIT 15:14 13:12 11:10 9:8 7 6 5 4:2 1:0 LABEL MICCMPSEL MPASEL MPABST MPBBST MBOP2EN MBOP1EN MBVOL MCDTHR MCDSCTHR DEFAULT 00 (mics) 00 (MIC1) 00 (12dB) 00 (12dB) 0 (Off) 1 (On) 0 (0.9xAVDD) 000 (100uA) 00 (600uA) DESCRIPTION Selects input function for MIC2A/COMP1 and MIC2B/COMP2 Selects input to MICA preamp (from MIC1, MIC2A, MIC2B) Controls MICA preamp gain boost Controls MICB preamp gain boost Enables microphone bias output path to pin 12 Enables microphone bias output path to MICBIAS Selects microphone bias voltage Controls microphone current detect threshold Controls microphone short-circuit detect threshold REFER TO Analogue Inputs, Microphone Input Register 22h controls the microphone input configuration and microphone bias and detect configuration. REGISTER ADDRESS 24h 4 BIT LABEL JIEN DCDRVSEL EARSPKSEL DEFAULT 0 (OFF) 00 (AC) 00 DESCRIPTION Jack insert detect enable Output PGA source for headphone DC reference (default is AC coupled – no source selected) Ear speaker source select (default is no source selected) REFER TO Analogue Audio Outputs 3:2 1:0 Register 24h controls the output volume mapping on headphone jack insertion. REGISTER ADDRESS 26h 14 13 12 11 10 9 8 3 2 1 0 BIT LABEL PR6 PR5 PR4 PR3 PR2 PR1 PR0 REF ANL DAC ADC DEFAULT 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 0 0 0 0 DESCRIPTION Disables all output PGAS Disables internal clock Disables AC-link interface (external clock off) Disables VREF, input PGAs, DACs, ADCs, mixers and outputs Disables input PGAs and mixers Disables stereo DAC Disables stereo ADCs and record mux PGA Read-only bit, indicates VREF is ready (inverse of PR3) Read-only bit, indicates analogue mixers are ready (inverse of PR2) Read-only bit, indicates stereo DAC is ready (inverse of PR1) Read-only bit, indicates stereo ADC is ready (inverse of PR0) REFER TO Power Management Register 26h is for power management according to the AC’97 specification. Note that the actual state of many circuit blocks depends on both register 26h AND registers 3Ch and 3Eh. w PP Rev 3.0 June 2006 90 Pre-Production REGISTER ADDRESS 28h BIT 15:14 11:10 9 8 7 6 3 2 1 0 ID REV AMAP LDAC SDAC CDAC VRM SPDIF DRA VRA LABEL DEFAULT 00 01 0 0 0 0 0 1 0 1 DESCRIPTION Indicates that the WM9713L is configured as the primary codec in the system. Indicates that the WM9713L conforms to AC’97 Rev2.2 Indicates that the WM9713L does not support slot mapping Indicates that the WM9713L does not have an LFE DAC Indicates that the WM9713L does not have Surround DACs Indicates that the WM9713L does not have a Centre DAC Indicates that the WM9713L does not have a dedicated, variable rate microphone ADC Indicates that the WM9713L supports SPDIF output Indicates that the WM9713L does not support double rate audio Indicates that the WM9713L supports variable rate audio WM9713L REFER TO Intel’s AC’97 Component Specification, Revision 2.2, page 59 Register 28h is a read-only register that indicates to the driver which advanced AC’97 features the WM9713L supports. REGISTER ADDRESS 2Ah 10 BIT LABEL SPCV SPSA SEN VRA DEFAULT 1 (valid) 01 (slots 6, 9) 0 (OFF) 0 (OFF) DESCRIPTION SPDIF validity bit (read-only) Controls SPDIF slot assignment. 00=slots 3 and 4, 01=6/9, 10=7/8, 11=10/11 Enables SPDIF output enable Enables variable rate audio REFER TO Digital Audio (SPDIF) Output 5:4 2 0 Register 2Ah controls the SPDIF output and variable rate audio. REGISTER ADDRESS 2Ch 2Eh 32h all all all BIT LABEL DACSR AUXDACSR ADCSR DEFAULT BB80h BB80h BB80h DESCRIPTION Controls stereo DAC sample rate Controls auxiliary DAC sample rate Controls audio ADC sample rate REFER TO Variable Rate Audio / Sample Rate Conversion Note: The VRA bit in register 2Ah must be set first to obtain sample rates other than 48kHz Registers 2Ch, 2Eh 32h and control the sample rates for the stereo DAC, auxiliary DAC and audio ADC, respectively. w PP Rev 3.0 June 2006 91 WM9713L REGISTER ADDRESS 36h 15 14:13 11:9 7 6 5:4 3:2 1:0 BIT LABEL CTRL MODE DIV CP FSP SEL WL FMT DEFAULT 0 (GPIO reg) 10 (master mode) 010 (1/4) 0 (normal) 0 00 (LandR data) 10 (24 bits) 10 (I2S) DESCRIPTION Specifies how the PCM interface pins are controlled. PCM interface mode when PCMCTRL=1 Voice DAC clock to PCMCLK divider reserved PCMCLK polarity right, left and I2S modes – PCMFS polarity DSP Mode – mode A/B select PCM ADC channel select PCM Data Word Length PCM Data Format Select Pre-Production REFER TO PCM Codec Register 36h controls the PCM codec. REGISTER ADDRESS 3Ah 15 14 BIT V LABEL 0 0 DEFAULT DESCRIPTION Validity bit; ‘0’ indicates frame valid, ‘1’ indicates frame not valid Indicates that the WM9713L does not support double rate SPDIF output (read-only) Indicates that the WM9713L only supports 48kHz sampling on the SPDIF output (read-only) Generation level; programmed as required by user Category code; programmed as required by user Pre-emphasis; ‘0’ indicates no pre-emphasis, ‘1’ indicates 50/15us pre-emphasis Copyright; ‘0’ indicates copyright is not asserted, ‘1’ indicates copyright Non-audio; ‘0’ indicates data is PCM, ‘1’ indicates non-PCM format (e.g. DD or DTS) Professional; ‘0’ indicates consumer, ‘1’ indicates professional REFER TO Digital Audio (SPDIF) Output DRS SPSR L CC PRE COPY AUDIB PRO 13:12 11 10:4 3 2 1 0 10 0 0000000 0 0 0 0 Register 3Ah Read/Write. Controls the SPDIF output. w PP Rev 3.0 June 2006 92 Pre-Production REGISTER ADDRESS 3Ch BIT 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 LABEL PD15 VMID1M TSHUT VXDAC AUXDAC VREF PLL DACL DACR ADCL ADCR HPLX HPRX SPKX MX DEFAULT 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) DESCRIPTION Touchpanel / PenADC power down Disables 1Meg Vmid resistor string Disables thermal shutdown Disables VXDAC Disables AUXDAC Disables reference generator Disables PLL Disables left DAC Disables right DAC Disables left ADC Disables right ADC Disables left headphone mixer Disables right headphone mixer Disables speaker mixer Disables mono mixer WM9713L REFER TO Power Management * “0” corresponds to “ON”, if and only if the corresponding bit in register 26h is also 0. Register 3Ch is for power management additional to the AC’97 specification. Note that the actual state of each circuit block depends on both register 3Ch AND register 26h. REGISTER ADDRESS 3Eh BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LABEL MCD MICBIAS MONO OUT4 OUT3 HPL HPR SPKL SPKR LL LR MOIN MA MB MPA MPB DEFAULT 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) DESCRIPTION Disables microphone current detect Disables microphone bias Disables MONO output PGA Disables OUT4 output PGA Disables OUT3 output PGA Disables HPL output PGA Disables HPR output PGA Disables SPKL output PGA Disables SPKR output PGA Disables LINEL PGA Disables LINER PGA Disables MONOIN PGA Disables mic PGA MA Disables mic PGA MB Disables mic pre-amp MPA Disables mic pre-amp MPB REFER TO Power Management * “0” corresponds to “ON”, if and only if the corresponding bit in register 26h is also 0. Register 3Eh is for power management additional to the AC’97 specification. Note that the actual state of each circuit block depends on both register 3Eh AND register 26h. REGISTER ADDRESS 40h BIT 13 7 LABEL 3DE LB DEFAULT 0 (OFF) 0 (OFF) DESCRIPTION Enables 3D enhancement Enables loopback (i.e. feed ADC output data directly into DAC) REFER TO Audio DACs, 3D Stereo Enhancement Intel’s AC’97 Component Specification, Revision 2.2, page 55 Register 40h is a “general purpose” register as defined by the AC’97 specification. Only two bits are implemented in the WM9713L. w PP Rev 3.0 June 2006 93 WM9713L REGISTER ADDRESS 42h BIT 6 5 4 3 2 1 0 LABEL MONO SPKL SPKR HPL HPR OUT3 OUT4 DEFAULT 0 (Off) 0 (Off) 0 (Off) 0 (Off) 0 (Off) 0 (Off) 0 (Off) DESCRIPTION Enables fast power for MONO output Enables fast power for SPKL output Enables fast power for SPKR output Enables fast power for HPL output Enables fast power for HPR output Enables fast power for OUT3 output Enables fast power for OUT4 output Pre-Production REFER TO Analogue Audio Outputs, Power-Up Register 42h controls power-up conditions for output PGAs. REGISTER ADDRESS 44h BIT 14:1 2 11:8 7 5:3 2 1 0 LABEL SEXT[6:4] SEXT[3:0] CLKSRC PENDIV CLKBX2 CLKAX2 CLKMUX DEFAULT 000 (div 1) 0000 (div 1) 1 (ext clk) 000 (div 16) 0 (Off) 0 (Off) 0 (MCLKA) DESCRIPTION Defines clock division ratio for Hi-fi block: 000=f; 001=f/2; ... ; 111=f/8 Defines clock division ratio for voice DAC clock: 0000=f; 0001=f/2; … ; 1111=f/16 Selects between PLL clock and External clock Sets AUXADC clock divisor: 000=f/16; 001=f/12; 010=f/8; 011=f/6; 100=f/4; 101=f/3; 110=f/2; 111=f Clock doubler for MCLKB Clock doubler for MCLKA Selects between MCLKA and MCLKB (N.B. On power-up clock must be present on MCLKA and must be active for 2 clock cycles after switching to MCLKB) REFER TO Clock Generation Register 44h controls clock division and muxing. REGISTER ADDRESS 46h BIT 15:1 2 11 10 9 8 6:4 3:0 LABEL N[3:0] LF SDM DIVSEL DIVCTL PGADDR PGDATA DEFAULT 0000 0 = off 0 0 = off 0 000 0000 DESCRIPTION PLL integer division control (must be set between 512 for integer N mode) Allows PLL operation with low frequency input clocks (< 8.192MHz) Sigma Delta Modulator enable. Allows fractional N division Enables input clock to PLL to be divided by 2 or 4. Use if input clock is above 14.4MHz Controls division mode when DIVSEL is high. 0 = div by 2, 1= div by 4. Pager address bits to access programming of K[21:0] and SPLL[6:0] Pager data bits REFER TO Analogue Audio Outputs, Power-Up Register 46h controls PLL clock generation. w PP Rev 3.0 June 2006 94 Pre-Production REGISTER ADDRESS 4Ch BIT LABEL DEFAULT all 1 (all inputs) except unused bits all 1 all 0 (not sticky) all 0 (OFF) = status of GPIO inputs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 please refer to the register map DESCRIPTION Controls GPIO configuration as inputs or as outputs (note: virtual GPIOs can only be inputs) Controls GPIO polarity (actual polarity depends on register 4Ch AND register 4Eh) Makes GPIO signals sticky Enables wake-up for each GPIO signal GPIO pin status (read from inputs, write ‘0’ to clear sticky bits) Controls Comparator 1 signal (virtual GPIO) Controls Comparator 2 signal (virtual GPIO) Controls Pen-Down Detector signal (virtual GPIO) Controls ADA signal (virtual GPIO) Controls Thermal sensor signal (virtual GPIO) Controls Microphone short detect (virtual GPIO) Controls Microphone insert detect (virtual GPIO) Controls GPIO8 (pin 3) Controls GPIO7 (pin 11) Controls GPIO6 (pin 12) Controls GPIO5 (pin 48) Controls GPIO4 (pin 47) Controls GPIO3 (pin 46) Controls GPIO2 (pin 45) Controls GPIO1 (pin 44) WM9713L REFER TO GPIO and Interrupt Control 4Eh 50h 52h 54h Register 4Ch to 54h control the GPIO pins and virtual GPIO signals. REGISTER ADDRESS 56h BIT 8 7 6 5 4 3 2 LABEL GE8 GE7 GE6 GE5 GE4 GE3 GE2 DEFAULT 1 (GPIO) 1 (GPIO) 1 (GPIO) 1 (GPIO) 1 (GPIO) 1 (GPIO) 1 (GPIO) DESCRIPTION Selects between GPIO8 and SPDIF_OUT function for pin 12 Selects between GPIO7 and PENDOWN function for pin 11 Selects between GPIO6 and ADA/MASK functions for pin 3 Selects between GPIO5 and SPDIF_OUT function for pin 48 Selects between GPIO4 and ADA/MASK functions for pin 47 Selects between GPIO3 and PENDOWN function for pin 46 Selects between GPIO2 and IRQ function for pin 45 REFER TO GPIO and Interrupt Control Register 56h controls the use of GPIO pins for non-GPIO functions. REGISTER ADDRESS 58h BIT 15:8 7:0 LABEL PU PD DEFAULT 01000000 00000000 DESCRIPTION Enables weak pull-up on GPIO pins (1=On) Enables weak pull-down on GPIO pins (1=On) REFER TO GPIO and Interrupt Control Register 56h controls GPIO pull-up/down. w PP Rev 3.0 June 2006 95 WM9713L REGISTER ADDRESS 5Ah 8 7:6 BIT 15:13 LABEL COMP2DEL RSTDIS JSEL DEFAULT 000 (no delay) 0 (RESETB enabled) 00 (GPIO1) DESCRIPTION Selects Comparator 2 delay Disables RESETB pin to enable use as a GPIO Selects GPIO for jack insert detect: 00: GPIO1 01: GPIO6 10: GPIO7 11: GPIO8 HPF corner frequency 00: 7Hz @ Fs=48kHz 01: 82Hz @ Fs=16kHz 10: 82Hz @ Fs=8kHz 11: 170Hz @ Fs=8kHz Pre-Production REFER TO Battery Alarm GPIO Interrupt and Control Jack Insertion & AutoSwitching 5:4 HPMODE 00 Audio ADCs 3:2 1 0 DIE REV W AKEEN IRQ INV Indicates device revision. 00=Rev.A, 01=Rev.B, 10=Rev.C 0 (no wake-up) 0 (not inverted) Enables GPIO wake-up Inverts the IRQ signal (pin 45) N/A GPIO and Interrupt Control Register 5Ah controls several additional functions. REGISTER ADDRESS 5Ch BIT 15 14 13:12 11 10:9 7 6:5 LABEL AMUTE C1REF C1SRC C2REF C2SRC AMEN VBIAS 0 DEFAULT DESCRIPTION Read-only bit to indicate DAC automuting Selects Comparator 1 Reference Voltage Selects Comparator 1 Signal Source Selects Comparator 1 Reference Voltage Selects Comparator 1 Signal Source Enables DAC Auto-Mute Selects analogue bias for lowest power, depending on AVDD supply. 0X=3.3V, 10=2.5V, 11=1.8V Selects source of SPDIF data. 0=from SDATAOUT, 1= from audio ADC Disables ADC high-pass filter Selects time slots for stereo ADC data. 00=slots 3 and 4, 01=7/8, 10=6/9, 11=10/11 REFER TO Audio DACs, Stereo DACs Battery Alarm 0 (AVDD/2) 00 (OFF) 0 (AVDD/2) 00 (OFF) 0 (OFF) 00 Power Management 4 3 1:0 ADCO HPF ASS 0 0 00 Digital Audio (SPDIF) Output Audio ADC Audio ADC, ADC Slot Mapping Register 5Ch controls several additional functions. w PP Rev 3.0 June 2006 96 Pre-Production REGISTER ADDRESS 60h BIT 15:12 11:8 7:4 3:0 62h 15:14 13:11 10:9 7 5 4:0 LABEL ALCL HLD DCY ATK ALCSEL MAXGAIN ZC TIMEOUT NGAT NGG NGTH DEFAULT 1011 (-12dB) 0000 (0 ms) 0011 (192 ms) 0010 (24 ms) 00 (OFF) 111 (+30dB) 11 (slowest) 0 (OFF) 0 (hold gain) 00000 (-76.5dB) DESCRIPTION Controls ALC threshold Controls ALC hold time Controls ALC decay time Controls ALC attack time Controls which channel ALC operates on. 00=none, 01=right only, 10=left only, 11=both Controls upper gain limit for ALC Controls time-out for zero-cross detection Enables noise gate function Selects noise gate type. 0=hold gain, 1=mute Controls noise gate threshold WM9713L REFER TO Audio ADC, Automatic Level Control Registers 60h and 62h control the ALC and Noise Gate functions. REGISTER ADDRESS 64h BIT 15 LABEL XSLE 0 DEFAULT DESCRIPTION Selects input for AUXDAC. 0=from AUXDACVAL (for DC signals), 1=from AC-Link slot (for AC signals) Selects input slot for AUXDAC (with XSLE=1) AUXDAC Digital Input for AUXDAC (with XSLE=0). 000h= minimum, FFFh=full-scale REFER TO Auxiliary DAC 14:12 11:0 AUXDACSLT AUXDACVAL 000 (Slot 5) 000000000 Register 64h controls the input signal of the auxiliary DAC. w PP Rev 3.0 June 2006 97 WM9713L REGISTER ADDRESS 74h 9 8 7 6 5 4 3 2 1 0 76h 9:8 7:4 3 2:0 78h 15:14 BIT LABEL POLL CTC ADCSEL_AUX4 ADCSEL_AUX3 ADCSEL_AUX2 ADCSEL_AUX1 ADCSEL_PRES SURE ADCSEL_Y ADCSEL_X COO CR DEL SLEN SLT PRP 0 0 0 0 0 0 0 0 0 0 (OFF) 00 (93.75Hz) 0000 (20.8µs) 1 110 (slot 11) 00 DEFAULT DESCRIPTION Writing “1” initiates a measurement (when CTC is not set) 0=Polling mode; 1=Continuous mode (for DMA) Enable COMP1/AUX4 measurement (pin32) Enable COMP1/AUX3 measurement (pin31) Enable COMP1/AUX2 measurement (pin30) Enable COMP1/AUX1 measurement (pin29) Enable touchpanel pressure measurement Enable touchpanel Y co-ord measurement Enable touchpanel X co-ord measurement Enables co-ordinate mode Controls conversion rate in continuous mode Controls touchpanel settling time Enables slot readback of touchpanel data Selects time slot for readback of touchpanel data Selects mode of operation. 00=OFF, 01=pen detect with wake-up, 10=pen detect without wake-up, 11=running Selects wake-up mode. 0=AC-Link only, 1=AC-Link and WM9713L auto-wake-up Selects 4-wire or 5-wire touchpanel Selects when touchpanel measurements take place. 0=always, 1=only when pen is down PENDOWN polarity: 0=non-inverted; 1=inverted Controls data readback from register 7Ah. 0=overwrite old data with new, 1=wait until old data has been read Controls current used for pressure measurement. 1=400µA Controls MASK feature Controls internal pull-up resistor for pen-down detection Indicates pen status. Indicates measurement type Returns data from touchpanel / AUXADC Pre-Production REFER TO Touchpanel Interface 13 12 11 10 9 RPR 45W PDEN PDPOL W AIT 0 0 (4-wire) 0 (always) 0 0 8 7:6 5:0 7Ah read only 15 14:12 11:0 PIL MSK RPU PNDN ADCSRC ADCD 0 (200µA) 00 (OFF) 000001 (64kΩ) 0 (pen up) 000 (none) 000h Registers 76h, 78h and 7Ah control the touchpanel interface. REGISTER ADDRESS 7Ch 7Eh BIT 15:8 7:0 15:8 7:0 LABEL F7:0 S7:0 T7:0 REV7:0 DEFAULT 57h 4Dh 4Ch 13h DESCRIPTION ASCII character “W ” for Wolfson ASCII character “M” ASCII character “L” Device identifier REFER TO Intel’s AC’97 Component Specification, Revision 2.2, page 50 Register 7Ch and 7Eh are read-only registers that indicate to the driver that the codec is a WM9713L. w PP Rev 3.0 June 2006 98 Pre-Production WM9713L APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 34 Recommended External Component Diagram w PP Rev 3.0 June 2006 99 WM9713L LINE OUTPUT Pre-Production The headphone outputs, HPL and HPR, can be used as stereo line outputs. The speaker outputs, SPKL and SPKR, can also be used as line outputs. Recommended external components are shown below. Figure 35 Recommended Circuit for Line Output The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, fc. Assuming a 10 kΩ load and C1, C2 = 10µF: fc = 1 / 2π (RL+R1) C1 = 1 / (2π x 10.1kΩ x 1µF) = 16 Hz Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 and C2 will diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage when used improperly. AC-COUPLED HEADPHONE OUTPUT The circuit diagram below shows how to connect a stereo headphone to the WM9713L. Figure 36 Simple Headphone Output Circuit Diagram The DC blocking capacitors C1 and C2 together with the load resistance determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. For example, with a 16Ω load and C1 = 220µF: fc = 1 / 2π RLC1 = 1 / (2π x 16Ω x 220µF) = 45 Hz w PP Rev 3.0 June 2006 100 Pre-Production WM9713L DC COUPLED (CAPLESS) HEADPHONE OUTPUT In the interest of saving board space and cost, it may be desirable to eliminate the 220µF DC blocking capacitors. This can be achieved by using OUT3 as a headphone pseudo-ground, as shown below. Figure 37 Capless Headphone Output Circuit Diagram As the OUT3 pin produces a DC voltage of AVDD/2, there is no DC offset between HPL/HPR and OUT3, and therefore no DC blocking capacitors are required. However, this configuration has some drawbacks: The power consumption of the WM9713L is increased, due to the additional power consumed in the OUT3 output buffer. If the DC coupled output is connected to the line-in of a grounded piece of equipment, then OUT3 becomes short-circuited. Although the built-in short circuit protection will prevent any damage to the WM9713L, the audio signal will not be transmitted properly. OUT3 cannot be used for another purpose BTL LOUDSPEAKER OUTPUT SPKL and SPKR can differentially drive a mono 8Ω loudspeaker as shown below. Figure 38 Speaker Output Connection (INV = 1) To drive out differentially one of the speaker outputs must be inverted using INV1 or INV2. w PP Rev 3.0 June 2006 101 WM9713L COMBINED HEADSET / BTL EAR SPEAKER Pre-Production In smartphone applications with a loudspeaker and separate ear speaker (receiver), a BTL ear speaker can be connected at the OUT3 pin, as shown below. Figure 39 Combined Headset / BTL Ear Speaker The ear speaker and the headset play the same signal. Whenever the headset is plugged in, the headphone outputs are enabled and OUT3 disabled. When the headset is not plugged in, OUT3 is enabled (see “Jack Insertion and Auto-Switching”) COMBINED HEADSET / SINGLE-ENDED EAR SPEAKER Instead of a BTL ear speaker, a single-ended ear speaker can also be used, as shown below. Figure 40 Combined Headset / Single-ended Ear Speaker w PP Rev 3.0 June 2006 102 Pre-Production WM9713L JACK INSERT DETECTION The circuit diagram below shows how to detect when a headphone or headset has been plugged into the headphone socket. It generates an interrupt, instructing the controller to enable HPL and HPR and disable OUT3. Figure 41 Jack Insert Detection Circuit The circuit requires a headphone socket with a switch that closes on insertion (for using sockets with a switch that opens on insertion, please refer to Application Note WAN0182). It detects both headphones and phone headsets. Any GPIO pin can be used, provided that it is configured as an input. HOOKSWITCH DETECTION Alternatively a headphone socket with a switch that opens on insertion can be used. For this mode of operation the GPIO input must be inverted. The circuit diagram below shows how to detect when the “hookswitch” of a phone headset is pressed (pressing the hookswitch is equivalent to lifting the receiver in a stationary telephone). Figure 42 Hookswitch Detection Circuit The circuit uses a GPIO pin as a sense input. The impedance of the microphone and the resistor in the MICBIAS path must be such that the potential at the GPIO pin is above 0.7×DBVDD when the hookswitch is open, and below 0.3×DBVDD when it is closed. w PP Rev 3.0 June 2006 103 WM9713L TYPICAL OUTPUT CONFIGURATIONS Pre-Production The WM9713L has three outputs capable of driving loads down to 16Ω (headphone / line drivers) – HPL, HPR and MONO - and four outputs capable of driving loads down to 8Ω (loudspeaker / line drivers) – SPKL, SPKR, OUT3 and OUT4. The combination of output drivers, mixers and mixer inverters means that many output configurations can be supported. Below are some examples of typical output configurations for smartphone applications. STEREO SPEAKER Figure 43 shows a typical output configuration for stereo speakers with headphones, ear speaker and hands-free operation. The table shows suggested mixer outputs to select for each output PGA for a given operating scenario. (Note the inverted mixer outputs can be achieved using the mixer output inverters INV1 and INV2). Figure 43 Stereo Speaker Output Configuration w PP Rev 3.0 June 2006 104 Pre-Production WM9713L MONO SPEAKER Figure 44 shows a typical output configuration for mono speaker with headphones, ear speaker and hands-free operation. The table shows suggested mixer outputs to select for each output PGA for a given operating scenario. (Note the inverted mixer outputs can be achieved using the mixer output inverters INV1 and INV2). Figure 44 Mono Speaker Output Configuration w PP Rev 3.0 June 2006 105 WM9713L WM9713L MONO SPEAKER Pre-Production Figure 45 shows a typical output configuration compatible with the WM9712 for mono speaker with headphones, ear speaker and hands-free operation. The table shows suggested mixer outputs to select for each output PGA for a given operating scenario. (Note the inverted mixer outputs can be achieved using the mixer output inverters INV1 and INV2). When using this configuration note that AVDD, HPVDD and SPKVDD must all be at the same voltage to achieve the best performance. Figure 45 WM9713L Mono Speaker Configuration w PP Rev 3.0 June 2006 106 Pre-Production WM9713L PACKAGE DIMENSIONS FL: 48 PIN QFN PLASTIC PACKAGE 7 X 7 X 0.9 mm BODY, 0.50 mm LEAD PITCH D2 D2/2 37 48 L 36 1 INDEX AREA (D/2 X E/2) DM029.E SEE DETAIL 1 D EXPOSED GROUND 6 PADDLE E2/2 E2 SEE DETAIL 2 E 25 12 2X b 2X aaa C aaa C 24 e 13 BOTTOM VIEW ccc C TOP VIEW (A3) A 0.08 C C SEATING PLANE SIDE VIEW A1 DETAIL 1 R = 0.3MM DETAIL 2 1 DETAIL 3 W T (A3) H b Exposed lead G Datum Terminal tip e/2 EXPOSED GROUND PADDLE R e Half etch tie bar DETAIL 3 Symbols A A1 A3 b D D2 E E2 e G H L T W aaa bbb ccc REF Dimensions (mm) NOM MAX 0.90 1.00 0.05 0.02 0.20 REF 0.18 0.25 0.30 7.00 BSC 5.00 5.15 5.25 7.00 BSC 5.00 5.15 5.25 0.5 BSC 0.213 0.1 0.50 0.30 0.4 0.1 0.2 Tolerances of Form and Position 0.15 0.10 0.10 MIN 0.80 0 NOTE 1 JEDEC, MO-220, VARIATION VKKD-2 NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. ALL DIMENSIONS ARE IN MILLIMETRES 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002. 4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. w PP Rev 3.0 June 2006 107 WM9713L IMPORTANT NOTICE Pre-Production W olfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. 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Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: W olfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PP Rev 3.0 June 2006 108